Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391261584	2598125	0	0
DepthKnown_A	391261584	391131242	0	0
RvalidKnown_A	391261584	391131242	0	0
WreadyKnown_A	391261584	391131242	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	2598125	0	0
T2	745777	10811	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	0	0	0
T6	150515	832	0	0
T7	1594	0	0	0
T8	364032	832	0	0
T9	142610	1663	0	0
T10	873	0	0	0
T11	212903	1669	0	0
T12	0	14984	0	0
T13	0	832	0	0
T14	0	2495	0	0
T21	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391261584	2967856	0	0
DepthKnown_A	391261584	391131242	0	0
RvalidKnown_A	391261584	391131242	0	0
WreadyKnown_A	391261584	391131242	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	2967856	0	0
T2	745777	6656	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	0	0	0
T6	150515	2512	0	0
T7	1594	0	0	0
T8	364032	3881	0	0
T9	142610	832	0	0
T10	873	0	0	0
T11	212903	839	0	0
T12	0	20748	0	0
T13	0	832	0	0
T14	0	1664	0	0
T21	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391261584	157701	0	0
DepthKnown_A	391261584	391131242	0	0
RvalidKnown_A	391261584	391131242	0	0
WreadyKnown_A	391261584	391131242	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	157701	0	0
T2	745777	320	0	0
T3	70777	0	0	0
T4	183520	0	0	0
T5	284770	423	0	0
T6	150515	533	0	0
T7	1594	0	0	0
T8	364032	0	0	0
T9	142610	0	0	0
T10	873	0	0	0
T11	212903	0	0	0
T12	0	586	0	0
T15	0	500	0	0
T16	0	761	0	0
T17	0	4	0	0
T21	0	100	0	0
T25	0	100	0	0
T27	0	319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391261584	383889	0	0
DepthKnown_A	391261584	391131242	0	0
RvalidKnown_A	391261584	391131242	0	0
WreadyKnown_A	391261584	391131242	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	383889	0	0
T2	745777	320	0	0
T3	70777	0	0	0
T4	183520	0	0	0
T5	284770	423	0	0
T6	150515	1576	0	0
T7	1594	0	0	0
T8	364032	0	0	0
T9	142610	0	0	0
T10	873	0	0	0
T11	212903	0	0	0
T12	0	1752	0	0
T15	0	2339	0	0
T16	0	761	0	0
T17	0	4	0	0
T21	0	100	0	0
T25	0	100	0	0
T27	0	1490	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391261584	6293889	0	0
DepthKnown_A	391261584	391131242	0	0
RvalidKnown_A	391261584	391131242	0	0
WreadyKnown_A	391261584	391131242	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	6293889	0	0
T1	3628	32	0	0
T2	745777	1617	0	0
T3	70777	299	0	0
T4	183520	257	0	0
T5	284770	5386	0	0
T6	150515	4105	0	0
T7	1594	77	0	0
T8	364032	495	0	0
T9	142610	5682	0	0
T10	873	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391261584	15152098	0	0
DepthKnown_A	391261584	391131242	0	0
RvalidKnown_A	391261584	391131242	0	0
WreadyKnown_A	391261584	391131242	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	15152098	0	0
T1	3628	32	0	0
T2	745777	1614	0	0
T3	70777	299	0	0
T4	183520	257	0	0
T5	284770	5377	0	0
T6	150515	12193	0	0
T7	1594	77	0	0
T8	364032	2185	0	0
T9	142610	5682	0	0
T10	873	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391261584	391131242	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0