Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T12
1	0	Covered	T5,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T5,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T49

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T49
1	0	Covered	T2,T12,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T2,T12,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	657657815	521747525	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	657657815	3175815	0	0
GntImpliesValid_A	657657815	3175815	0	0
GrantKnown_A	657657815	521747525	0	0
IdxKnown_A	657657815	521747525	0	0
IndexIsCorrect_A	657657815	3175815	0	0
LockArbDecision_A	657657815	0	0	0
NoReadyValidNoGrant_A	657657815	0	0	0
ReadyAndValidImplyGrant_A	657657815	3175815	0	0
ReqAndReadyImplyGrant_A	657657815	3175815	0	0
ReqImpliesValid_A	657657815	3175815	0	0
ReqStaysHighUntilGranted0_M	657657815	0	0	0
RoundRobin_A	657657815	6	0	926
ValidKnown_A	657657815	521747525	0	0
gen_data_port_assertion.DataFlow_A	657657815	3175815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	521747525	0	0
T1	4412	4264	0	0
T2	1427543	1084166	0	0
T3	282871	172035	0	0
T4	271436	227422	0	0
T5	416204	347366	0	0
T6	438941	292939	0	0
T7	1594	1540	0	0
T8	465266	414269	0	0
T9	420798	281600	0	0
T10	873	774	0	0
T11	104632	52316	0	0
T12	962966	475046	0	0
T13	8208	8208	0	0
T14	0	61717	0	0
T15	0	36784	0	0
T16	0	74720	0	0
T17	0	2400	0	0
T19	0	72	0	0
T20	0	27406	0	0
T42	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	3175815	0	0
T2	1086660	10762	0	0
T3	176824	0	0	0
T4	227478	832	0	0
T5	416204	3796	0	0
T6	438941	5144	0	0
T7	1594	0	0	0
T8	465266	832	0	0
T9	420798	832	0	0
T10	873	0	0	0
T11	317535	832	0	0
T12	962966	18563	0	0
T13	16416	832	0	0
T14	61717	2	0	0
T15	0	5260	0	0
T16	0	7515	0	0
T17	0	62	0	0
T20	27406	0	0	0
T21	0	200	0	0
T27	0	4335	0	0
T28	0	552	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	6284	0	0
T45	15002	0	0	0
T49	0	8	0	0
T50	0	3504	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	3175815	0	0
T2	1086660	10762	0	0
T3	176824	0	0	0
T4	227478	832	0	0
T5	416204	3796	0	0
T6	438941	5144	0	0
T7	1594	0	0	0
T8	465266	832	0	0
T9	420798	832	0	0
T10	873	0	0	0
T11	317535	832	0	0
T12	962966	18563	0	0
T13	16416	832	0	0
T14	61717	2	0	0
T15	0	5260	0	0
T16	0	7515	0	0
T17	0	62	0	0
T20	27406	0	0	0
T21	0	200	0	0
T27	0	4335	0	0
T28	0	552	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	6284	0	0
T45	15002	0	0	0
T49	0	8	0	0
T50	0	3504	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	521747525	0	0
T1	4412	4264	0	0
T2	1427543	1084166	0	0
T3	282871	172035	0	0
T4	271436	227422	0	0
T5	416204	347366	0	0
T6	438941	292939	0	0
T7	1594	1540	0	0
T8	465266	414269	0	0
T9	420798	281600	0	0
T10	873	774	0	0
T11	104632	52316	0	0
T12	962966	475046	0	0
T13	8208	8208	0	0
T14	0	61717	0	0
T15	0	36784	0	0
T16	0	74720	0	0
T17	0	2400	0	0
T19	0	72	0	0
T20	0	27406	0	0
T42	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	521747525	0	0
T1	4412	4264	0	0
T2	1427543	1084166	0	0
T3	282871	172035	0	0
T4	271436	227422	0	0
T5	416204	347366	0	0
T6	438941	292939	0	0
T7	1594	1540	0	0
T8	465266	414269	0	0
T9	420798	281600	0	0
T10	873	774	0	0
T11	104632	52316	0	0
T12	962966	475046	0	0
T13	8208	8208	0	0
T14	0	61717	0	0
T15	0	36784	0	0
T16	0	74720	0	0
T17	0	2400	0	0
T19	0	72	0	0
T20	0	27406	0	0
T42	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	3175815	0	0
T2	1086660	10762	0	0
T3	176824	0	0	0
T4	227478	832	0	0
T5	416204	3796	0	0
T6	438941	5144	0	0
T7	1594	0	0	0
T8	465266	832	0	0
T9	420798	832	0	0
T10	873	0	0	0
T11	317535	832	0	0
T12	962966	18563	0	0
T13	16416	832	0	0
T14	61717	2	0	0
T15	0	5260	0	0
T16	0	7515	0	0
T17	0	62	0	0
T20	27406	0	0	0
T21	0	200	0	0
T27	0	4335	0	0
T28	0	552	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	6284	0	0
T45	15002	0	0	0
T49	0	8	0	0
T50	0	3504	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	3175815	0	0
T2	1086660	10762	0	0
T3	176824	0	0	0
T4	227478	832	0	0
T5	416204	3796	0	0
T6	438941	5144	0	0
T7	1594	0	0	0
T8	465266	832	0	0
T9	420798	832	0	0
T10	873	0	0	0
T11	317535	832	0	0
T12	962966	18563	0	0
T13	16416	832	0	0
T14	61717	2	0	0
T15	0	5260	0	0
T16	0	7515	0	0
T17	0	62	0	0
T20	27406	0	0	0
T21	0	200	0	0
T27	0	4335	0	0
T28	0	552	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	6284	0	0
T45	15002	0	0	0
T49	0	8	0	0
T50	0	3504	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	3175815	0	0
T2	1086660	10762	0	0
T3	176824	0	0	0
T4	227478	832	0	0
T5	416204	3796	0	0
T6	438941	5144	0	0
T7	1594	0	0	0
T8	465266	832	0	0
T9	420798	832	0	0
T10	873	0	0	0
T11	317535	832	0	0
T12	962966	18563	0	0
T13	16416	832	0	0
T14	61717	2	0	0
T15	0	5260	0	0
T16	0	7515	0	0
T17	0	62	0	0
T20	27406	0	0	0
T21	0	200	0	0
T27	0	4335	0	0
T28	0	552	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	6284	0	0
T45	15002	0	0	0
T49	0	8	0	0
T50	0	3504	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	3175815	0	0
T2	1086660	10762	0	0
T3	176824	0	0	0
T4	227478	832	0	0
T5	416204	3796	0	0
T6	438941	5144	0	0
T7	1594	0	0	0
T8	465266	832	0	0
T9	420798	832	0	0
T10	873	0	0	0
T11	317535	832	0	0
T12	962966	18563	0	0
T13	16416	832	0	0
T14	61717	2	0	0
T15	0	5260	0	0
T16	0	7515	0	0
T17	0	62	0	0
T20	27406	0	0	0
T21	0	200	0	0
T27	0	4335	0	0
T28	0	552	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	6284	0	0
T45	15002	0	0	0
T49	0	8	0	0
T50	0	3504	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	6	0	926
T51	202525	1	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	235088	0	0	1
T58	53012	0	0	1
T59	177062	0	0	1
T60	594067	0	0	1
T61	58977	0	0	1
T62	107724	0	0	1
T63	16024	0	0	1
T64	29649	0	0	1
T65	46401	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	521747525	0	0
T1	4412	4264	0	0
T2	1427543	1084166	0	0
T3	282871	172035	0	0
T4	271436	227422	0	0
T5	416204	347366	0	0
T6	438941	292939	0	0
T7	1594	1540	0	0
T8	465266	414269	0	0
T9	420798	281600	0	0
T10	873	774	0	0
T11	104632	52316	0	0
T12	962966	475046	0	0
T13	8208	8208	0	0
T14	0	61717	0	0
T15	0	36784	0	0
T16	0	74720	0	0
T17	0	2400	0	0
T19	0	72	0	0
T20	0	27406	0	0
T42	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657657815	3175815	0	0
T2	1086660	10762	0	0
T3	176824	0	0	0
T4	227478	832	0	0
T5	416204	3796	0	0
T6	438941	5144	0	0
T7	1594	0	0	0
T8	465266	832	0	0
T9	420798	832	0	0
T10	873	0	0	0
T11	317535	832	0	0
T12	962966	18563	0	0
T13	16416	832	0	0
T14	61717	2	0	0
T15	0	5260	0	0
T16	0	7515	0	0
T17	0	62	0	0
T20	27406	0	0	0
T21	0	200	0	0
T27	0	4335	0	0
T28	0	552	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	6284	0	0
T45	15002	0	0	0
T49	0	8	0	0
T50	0	3504	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T12
1	0	Covered	T5,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T5,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	134525927	27365677	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	134525927	619136	0	0
GntImpliesValid_A	134525927	619136	0	0
GrantKnown_A	134525927	27365677	0	0
IdxKnown_A	134525927	27365677	0	0
IndexIsCorrect_A	134525927	619136	0	0
LockArbDecision_A	134525927	0	0	0
NoReadyValidNoGrant_A	134525927	0	0	0
ReadyAndValidImplyGrant_A	134525927	619136	0	0
ReqAndReadyImplyGrant_A	134525927	619136	0	0
ReqImpliesValid_A	134525927	619136	0	0
ReqStaysHighUntilGranted0_M	134525927	0	0	0
RoundRobin_A	134525927	0	0	0
ValidKnown_A	134525927	27365677	0	0
gen_data_port_assertion.DataFlow_A	134525927	619136	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	27365677	0	0
T1	784	720	0	0
T2	340883	0	0	0
T3	106047	101336	0	0
T4	43958	0	0	0
T5	65717	62664	0	0
T6	144213	104336	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	45008	0	0
T15	0	36784	0	0
T16	0	74720	0	0
T17	0	2400	0	0
T19	0	72	0	0
T42	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	619136	0	0
T5	65717	2550	0	0
T6	144213	2965	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	2192	0	0
T13	8208	0	0	0
T14	61717	0	0	0
T15	0	1577	0	0
T16	0	2384	0	0
T17	0	62	0	0
T20	27406	0	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	5766	0	0
T45	15002	0	0	0
T50	0	3504	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	619136	0	0
T5	65717	2550	0	0
T6	144213	2965	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	2192	0	0
T13	8208	0	0	0
T14	61717	0	0	0
T15	0	1577	0	0
T16	0	2384	0	0
T17	0	62	0	0
T20	27406	0	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	5766	0	0
T45	15002	0	0	0
T50	0	3504	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	27365677	0	0
T1	784	720	0	0
T2	340883	0	0	0
T3	106047	101336	0	0
T4	43958	0	0	0
T5	65717	62664	0	0
T6	144213	104336	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	45008	0	0
T15	0	36784	0	0
T16	0	74720	0	0
T17	0	2400	0	0
T19	0	72	0	0
T42	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	27365677	0	0
T1	784	720	0	0
T2	340883	0	0	0
T3	106047	101336	0	0
T4	43958	0	0	0
T5	65717	62664	0	0
T6	144213	104336	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	45008	0	0
T15	0	36784	0	0
T16	0	74720	0	0
T17	0	2400	0	0
T19	0	72	0	0
T42	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	619136	0	0
T5	65717	2550	0	0
T6	144213	2965	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	2192	0	0
T13	8208	0	0	0
T14	61717	0	0	0
T15	0	1577	0	0
T16	0	2384	0	0
T17	0	62	0	0
T20	27406	0	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	5766	0	0
T45	15002	0	0	0
T50	0	3504	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	619136	0	0
T5	65717	2550	0	0
T6	144213	2965	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	2192	0	0
T13	8208	0	0	0
T14	61717	0	0	0
T15	0	1577	0	0
T16	0	2384	0	0
T17	0	62	0	0
T20	27406	0	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	5766	0	0
T45	15002	0	0	0
T50	0	3504	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	619136	0	0
T5	65717	2550	0	0
T6	144213	2965	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	2192	0	0
T13	8208	0	0	0
T14	61717	0	0	0
T15	0	1577	0	0
T16	0	2384	0	0
T17	0	62	0	0
T20	27406	0	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	5766	0	0
T45	15002	0	0	0
T50	0	3504	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	619136	0	0
T5	65717	2550	0	0
T6	144213	2965	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	2192	0	0
T13	8208	0	0	0
T14	61717	0	0	0
T15	0	1577	0	0
T16	0	2384	0	0
T17	0	62	0	0
T20	27406	0	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	5766	0	0
T45	15002	0	0	0
T50	0	3504	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	27365677	0	0
T1	784	720	0	0
T2	340883	0	0	0
T3	106047	101336	0	0
T4	43958	0	0	0
T5	65717	62664	0	0
T6	144213	104336	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	45008	0	0
T15	0	36784	0	0
T16	0	74720	0	0
T17	0	2400	0	0
T19	0	72	0	0
T42	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	619136	0	0
T5	65717	2550	0	0
T6	144213	2965	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	2192	0	0
T13	8208	0	0	0
T14	61717	0	0	0
T15	0	1577	0	0
T16	0	2384	0	0
T17	0	62	0	0
T20	27406	0	0	0
T31	0	1380	0	0
T32	0	4402	0	0
T43	0	5766	0	0
T45	15002	0	0	0
T50	0	3504	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T49

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T49
1	0	Covered	T2,T12,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T2,T12,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T49
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T12,T14
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	134525927	105860955	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	134525927	521357	0	0
GntImpliesValid_A	134525927	521357	0	0
GrantKnown_A	134525927	105860955	0	0
IdxKnown_A	134525927	105860955	0	0
IndexIsCorrect_A	134525927	521357	0	0
LockArbDecision_A	134525927	0	0	0
NoReadyValidNoGrant_A	134525927	0	0	0
ReadyAndValidImplyGrant_A	134525927	521357	0	0
ReqAndReadyImplyGrant_A	134525927	521357	0	0
ReqImpliesValid_A	134525927	521357	0	0
ReqStaysHighUntilGranted0_M	134525927	0	0	0
RoundRobin_A	134525927	0	0	0
ValidKnown_A	134525927	105860955	0	0
gen_data_port_assertion.DataFlow_A	134525927	521357	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	105860955	0	0
T2	340883	338450	0	0
T3	106047	0	0	0
T4	43958	43958	0	0
T5	65717	0	0	0
T6	144213	38180	0	0
T8	50617	50320	0	0
T9	139094	139088	0	0
T11	52316	52316	0	0
T12	481483	430038	0	0
T13	8208	8208	0	0
T14	0	61717	0	0
T20	0	27406	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	521357	0	0
T2	340883	3767	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	5292	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	0	3683	0	0
T16	0	5131	0	0
T27	0	4335	0	0
T28	0	552	0	0
T30	0	2154	0	0
T43	0	518	0	0
T49	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	521357	0	0
T2	340883	3767	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	5292	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	0	3683	0	0
T16	0	5131	0	0
T27	0	4335	0	0
T28	0	552	0	0
T30	0	2154	0	0
T43	0	518	0	0
T49	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	105860955	0	0
T2	340883	338450	0	0
T3	106047	0	0	0
T4	43958	43958	0	0
T5	65717	0	0	0
T6	144213	38180	0	0
T8	50617	50320	0	0
T9	139094	139088	0	0
T11	52316	52316	0	0
T12	481483	430038	0	0
T13	8208	8208	0	0
T14	0	61717	0	0
T20	0	27406	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	105860955	0	0
T2	340883	338450	0	0
T3	106047	0	0	0
T4	43958	43958	0	0
T5	65717	0	0	0
T6	144213	38180	0	0
T8	50617	50320	0	0
T9	139094	139088	0	0
T11	52316	52316	0	0
T12	481483	430038	0	0
T13	8208	8208	0	0
T14	0	61717	0	0
T20	0	27406	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	521357	0	0
T2	340883	3767	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	5292	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	0	3683	0	0
T16	0	5131	0	0
T27	0	4335	0	0
T28	0	552	0	0
T30	0	2154	0	0
T43	0	518	0	0
T49	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	521357	0	0
T2	340883	3767	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	5292	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	0	3683	0	0
T16	0	5131	0	0
T27	0	4335	0	0
T28	0	552	0	0
T30	0	2154	0	0
T43	0	518	0	0
T49	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	521357	0	0
T2	340883	3767	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	5292	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	0	3683	0	0
T16	0	5131	0	0
T27	0	4335	0	0
T28	0	552	0	0
T30	0	2154	0	0
T43	0	518	0	0
T49	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	521357	0	0
T2	340883	3767	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	5292	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	0	3683	0	0
T16	0	5131	0	0
T27	0	4335	0	0
T28	0	552	0	0
T30	0	2154	0	0
T43	0	518	0	0
T49	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	105860955	0	0
T2	340883	338450	0	0
T3	106047	0	0	0
T4	43958	43958	0	0
T5	65717	0	0	0
T6	144213	38180	0	0
T8	50617	50320	0	0
T9	139094	139088	0	0
T11	52316	52316	0	0
T12	481483	430038	0	0
T13	8208	8208	0	0
T14	0	61717	0	0
T20	0	27406	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	521357	0	0
T2	340883	3767	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	5292	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	0	3683	0	0
T16	0	5131	0	0
T27	0	4335	0	0
T28	0	552	0	0
T30	0	2154	0	0
T43	0	518	0	0
T49	0	8	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	388605961	388520893	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	388605961	2035322	0	0
GntImpliesValid_A	388605961	2035322	0	0
GrantKnown_A	388605961	388520893	0	0
IdxKnown_A	388605961	388520893	0	0
IndexIsCorrect_A	388605961	2035322	0	0
LockArbDecision_A	388605961	0	0	0
NoReadyValidNoGrant_A	388605961	0	0	0
ReadyAndValidImplyGrant_A	388605961	2035322	0	0
ReqAndReadyImplyGrant_A	388605961	2035322	0	0
ReqImpliesValid_A	388605961	2035322	0	0
ReqStaysHighUntilGranted0_M	388605961	0	0	0
RoundRobin_A	388605961	6	0	926
ValidKnown_A	388605961	388520893	0	0
gen_data_port_assertion.DataFlow_A	388605961	2035322	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	388520893	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	2035322	0	0
T2	745777	6995	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	1246	0	0
T6	150515	2179	0	0
T7	1594	0	0	0
T8	364032	832	0	0
T9	142610	832	0	0
T10	873	0	0	0
T11	212903	832	0	0
T12	0	11079	0	0
T13	0	832	0	0
T21	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	2035322	0	0
T2	745777	6995	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	1246	0	0
T6	150515	2179	0	0
T7	1594	0	0	0
T8	364032	832	0	0
T9	142610	832	0	0
T10	873	0	0	0
T11	212903	832	0	0
T12	0	11079	0	0
T13	0	832	0	0
T21	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	388520893	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	388520893	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	2035322	0	0
T2	745777	6995	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	1246	0	0
T6	150515	2179	0	0
T7	1594	0	0	0
T8	364032	832	0	0
T9	142610	832	0	0
T10	873	0	0	0
T11	212903	832	0	0
T12	0	11079	0	0
T13	0	832	0	0
T21	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	2035322	0	0
T2	745777	6995	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	1246	0	0
T6	150515	2179	0	0
T7	1594	0	0	0
T8	364032	832	0	0
T9	142610	832	0	0
T10	873	0	0	0
T11	212903	832	0	0
T12	0	11079	0	0
T13	0	832	0	0
T21	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	2035322	0	0
T2	745777	6995	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	1246	0	0
T6	150515	2179	0	0
T7	1594	0	0	0
T8	364032	832	0	0
T9	142610	832	0	0
T10	873	0	0	0
T11	212903	832	0	0
T12	0	11079	0	0
T13	0	832	0	0
T21	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	2035322	0	0
T2	745777	6995	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	1246	0	0
T6	150515	2179	0	0
T7	1594	0	0	0
T8	364032	832	0	0
T9	142610	832	0	0
T10	873	0	0	0
T11	212903	832	0	0
T12	0	11079	0	0
T13	0	832	0	0
T21	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	6	0	926
T51	202525	1	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	235088	0	0	1
T58	53012	0	0	1
T59	177062	0	0	1
T60	594067	0	0	1
T61	58977	0	0	1
T62	107724	0	0	1
T63	16024	0	0	1
T64	29649	0	0	1
T65	46401	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	388520893	0	0
T1	3628	3544	0	0
T2	745777	745716	0	0
T3	70777	70699	0	0
T4	183520	183464	0	0
T5	284770	284702	0	0
T6	150515	150423	0	0
T7	1594	1540	0	0
T8	364032	363949	0	0
T9	142610	142512	0	0
T10	873	774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	2035322	0	0
T2	745777	6995	0	0
T3	70777	0	0	0
T4	183520	832	0	0
T5	284770	1246	0	0
T6	150515	2179	0	0
T7	1594	0	0	0
T8	364032	832	0	0
T9	142610	832	0	0
T10	873	0	0	0
T11	212903	832	0	0
T12	0	11079	0	0
T13	0	832	0	0
T21	0	200	0	0