Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
4015 |
0 |
0 |
T99 |
53435 |
3 |
0 |
0 |
T100 |
4466 |
206 |
0 |
0 |
T101 |
3591 |
2 |
0 |
0 |
T102 |
14826 |
283 |
0 |
0 |
T103 |
67081 |
3 |
0 |
0 |
T104 |
35038 |
3 |
0 |
0 |
T105 |
4344 |
177 |
0 |
0 |
T106 |
2739 |
124 |
0 |
0 |
T108 |
3687 |
223 |
0 |
0 |
T111 |
9359 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2523 |
0 |
0 |
T103 |
67081 |
75 |
0 |
0 |
T104 |
35038 |
40 |
0 |
0 |
T111 |
9359 |
17 |
0 |
0 |
T113 |
35718 |
47 |
0 |
0 |
T118 |
10853 |
4 |
0 |
0 |
T146 |
70701 |
67 |
0 |
0 |
T147 |
14467 |
66 |
0 |
0 |
T148 |
14421 |
39 |
0 |
0 |
T149 |
14914 |
30 |
0 |
0 |
T150 |
31045 |
11 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2697 |
0 |
0 |
T88 |
2827 |
2 |
0 |
0 |
T103 |
67081 |
103 |
0 |
0 |
T104 |
35038 |
33 |
0 |
0 |
T111 |
9359 |
13 |
0 |
0 |
T113 |
35718 |
37 |
0 |
0 |
T118 |
10853 |
8 |
0 |
0 |
T146 |
70701 |
85 |
0 |
0 |
T147 |
14467 |
41 |
0 |
0 |
T148 |
14421 |
98 |
0 |
0 |
T149 |
14914 |
16 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
3422 |
0 |
0 |
T88 |
2827 |
8 |
0 |
0 |
T103 |
67081 |
151 |
0 |
0 |
T104 |
35038 |
81 |
0 |
0 |
T111 |
9359 |
15 |
0 |
0 |
T113 |
35718 |
55 |
0 |
0 |
T118 |
10853 |
25 |
0 |
0 |
T146 |
70701 |
124 |
0 |
0 |
T147 |
14467 |
36 |
0 |
0 |
T148 |
14421 |
13 |
0 |
0 |
T149 |
14914 |
26 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
14008 |
0 |
0 |
T88 |
2827 |
8 |
0 |
0 |
T103 |
67081 |
914 |
0 |
0 |
T104 |
35038 |
622 |
0 |
0 |
T111 |
9359 |
165 |
0 |
0 |
T113 |
35718 |
355 |
0 |
0 |
T118 |
10853 |
127 |
0 |
0 |
T146 |
70701 |
1158 |
0 |
0 |
T147 |
14467 |
37 |
0 |
0 |
T148 |
14421 |
12 |
0 |
0 |
T149 |
14914 |
129 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
13874 |
0 |
0 |
T88 |
2827 |
6 |
0 |
0 |
T103 |
67081 |
819 |
0 |
0 |
T104 |
35038 |
419 |
0 |
0 |
T111 |
9359 |
146 |
0 |
0 |
T113 |
35718 |
346 |
0 |
0 |
T118 |
10853 |
130 |
0 |
0 |
T146 |
70701 |
942 |
0 |
0 |
T147 |
14467 |
31 |
0 |
0 |
T148 |
14421 |
34 |
0 |
0 |
T149 |
14914 |
265 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
14685 |
0 |
0 |
T88 |
2827 |
1 |
0 |
0 |
T103 |
67081 |
1352 |
0 |
0 |
T104 |
35038 |
673 |
0 |
0 |
T111 |
9359 |
13 |
0 |
0 |
T113 |
35718 |
604 |
0 |
0 |
T118 |
10853 |
140 |
0 |
0 |
T146 |
70701 |
1279 |
0 |
0 |
T147 |
14467 |
58 |
0 |
0 |
T148 |
14421 |
48 |
0 |
0 |
T149 |
14914 |
139 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
15283 |
0 |
0 |
T88 |
2827 |
5 |
0 |
0 |
T103 |
67081 |
1147 |
0 |
0 |
T104 |
35038 |
640 |
0 |
0 |
T111 |
9359 |
220 |
0 |
0 |
T113 |
35718 |
739 |
0 |
0 |
T118 |
10853 |
125 |
0 |
0 |
T146 |
70701 |
838 |
0 |
0 |
T147 |
14467 |
75 |
0 |
0 |
T148 |
14421 |
49 |
0 |
0 |
T149 |
14914 |
418 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
15158 |
0 |
0 |
T88 |
2827 |
1 |
0 |
0 |
T103 |
67081 |
1415 |
0 |
0 |
T104 |
35038 |
514 |
0 |
0 |
T111 |
9359 |
18 |
0 |
0 |
T113 |
35718 |
805 |
0 |
0 |
T118 |
10853 |
150 |
0 |
0 |
T146 |
70701 |
1117 |
0 |
0 |
T147 |
14467 |
40 |
0 |
0 |
T148 |
14421 |
81 |
0 |
0 |
T149 |
14914 |
344 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
13625 |
0 |
0 |
T103 |
67081 |
1499 |
0 |
0 |
T104 |
35038 |
773 |
0 |
0 |
T111 |
9359 |
11 |
0 |
0 |
T113 |
35718 |
505 |
0 |
0 |
T118 |
10853 |
105 |
0 |
0 |
T146 |
70701 |
1191 |
0 |
0 |
T147 |
14467 |
52 |
0 |
0 |
T148 |
14421 |
32 |
0 |
0 |
T149 |
14914 |
227 |
0 |
0 |
T150 |
31045 |
384 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
14903 |
0 |
0 |
T88 |
2827 |
5 |
0 |
0 |
T103 |
67081 |
1308 |
0 |
0 |
T104 |
35038 |
531 |
0 |
0 |
T111 |
9359 |
27 |
0 |
0 |
T113 |
35718 |
657 |
0 |
0 |
T118 |
10853 |
69 |
0 |
0 |
T146 |
70701 |
1150 |
0 |
0 |
T147 |
14467 |
83 |
0 |
0 |
T148 |
14421 |
34 |
0 |
0 |
T149 |
14914 |
238 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
14979 |
0 |
0 |
T88 |
2827 |
13 |
0 |
0 |
T103 |
67081 |
993 |
0 |
0 |
T104 |
35038 |
483 |
0 |
0 |
T111 |
9359 |
136 |
0 |
0 |
T113 |
35718 |
1059 |
0 |
0 |
T118 |
10853 |
74 |
0 |
0 |
T146 |
70701 |
1698 |
0 |
0 |
T147 |
14467 |
32 |
0 |
0 |
T148 |
14421 |
51 |
0 |
0 |
T149 |
14914 |
18 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7032 |
0 |
0 |
T88 |
2827 |
6 |
0 |
0 |
T103 |
67081 |
427 |
0 |
0 |
T104 |
35038 |
199 |
0 |
0 |
T111 |
9359 |
63 |
0 |
0 |
T113 |
35718 |
307 |
0 |
0 |
T118 |
10853 |
28 |
0 |
0 |
T146 |
70701 |
648 |
0 |
0 |
T147 |
14467 |
39 |
0 |
0 |
T148 |
14421 |
20 |
0 |
0 |
T149 |
14914 |
70 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7596 |
0 |
0 |
T88 |
2827 |
4 |
0 |
0 |
T103 |
67081 |
620 |
0 |
0 |
T104 |
35038 |
110 |
0 |
0 |
T111 |
9359 |
62 |
0 |
0 |
T113 |
35718 |
397 |
0 |
0 |
T118 |
10853 |
47 |
0 |
0 |
T146 |
70701 |
473 |
0 |
0 |
T147 |
14467 |
60 |
0 |
0 |
T148 |
14421 |
44 |
0 |
0 |
T149 |
14914 |
16 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7040 |
0 |
0 |
T103 |
67081 |
451 |
0 |
0 |
T104 |
35038 |
272 |
0 |
0 |
T111 |
9359 |
57 |
0 |
0 |
T113 |
35718 |
354 |
0 |
0 |
T118 |
10853 |
17 |
0 |
0 |
T146 |
70701 |
399 |
0 |
0 |
T147 |
14467 |
36 |
0 |
0 |
T148 |
14421 |
43 |
0 |
0 |
T149 |
14914 |
121 |
0 |
0 |
T150 |
31045 |
142 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7144 |
0 |
0 |
T88 |
2827 |
5 |
0 |
0 |
T103 |
67081 |
442 |
0 |
0 |
T104 |
35038 |
362 |
0 |
0 |
T111 |
9359 |
21 |
0 |
0 |
T113 |
35718 |
248 |
0 |
0 |
T118 |
10853 |
32 |
0 |
0 |
T146 |
70701 |
707 |
0 |
0 |
T147 |
14467 |
23 |
0 |
0 |
T148 |
14421 |
44 |
0 |
0 |
T149 |
14914 |
15 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
6614 |
0 |
0 |
T88 |
2827 |
3 |
0 |
0 |
T103 |
67081 |
499 |
0 |
0 |
T104 |
35038 |
175 |
0 |
0 |
T111 |
9359 |
84 |
0 |
0 |
T113 |
35718 |
231 |
0 |
0 |
T118 |
10853 |
56 |
0 |
0 |
T146 |
70701 |
446 |
0 |
0 |
T147 |
14467 |
9 |
0 |
0 |
T148 |
14421 |
64 |
0 |
0 |
T149 |
14914 |
33 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7524 |
0 |
0 |
T88 |
2827 |
9 |
0 |
0 |
T103 |
67081 |
357 |
0 |
0 |
T104 |
35038 |
118 |
0 |
0 |
T111 |
9359 |
133 |
0 |
0 |
T113 |
35718 |
199 |
0 |
0 |
T118 |
10853 |
32 |
0 |
0 |
T146 |
70701 |
732 |
0 |
0 |
T147 |
14467 |
51 |
0 |
0 |
T148 |
14421 |
23 |
0 |
0 |
T149 |
14914 |
152 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7231 |
0 |
0 |
T88 |
2827 |
7 |
0 |
0 |
T103 |
67081 |
532 |
0 |
0 |
T104 |
35038 |
196 |
0 |
0 |
T111 |
9359 |
66 |
0 |
0 |
T113 |
35718 |
134 |
0 |
0 |
T118 |
10853 |
67 |
0 |
0 |
T146 |
70701 |
460 |
0 |
0 |
T147 |
14467 |
19 |
0 |
0 |
T148 |
14421 |
29 |
0 |
0 |
T149 |
14914 |
17 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7339 |
0 |
0 |
T103 |
67081 |
502 |
0 |
0 |
T104 |
35038 |
431 |
0 |
0 |
T111 |
9359 |
44 |
0 |
0 |
T113 |
35718 |
84 |
0 |
0 |
T118 |
10853 |
8 |
0 |
0 |
T146 |
70701 |
404 |
0 |
0 |
T147 |
14467 |
24 |
0 |
0 |
T148 |
14421 |
46 |
0 |
0 |
T149 |
14914 |
131 |
0 |
0 |
T150 |
31045 |
145 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7096 |
0 |
0 |
T88 |
2827 |
5 |
0 |
0 |
T103 |
67081 |
620 |
0 |
0 |
T104 |
35038 |
256 |
0 |
0 |
T111 |
9359 |
90 |
0 |
0 |
T113 |
35718 |
214 |
0 |
0 |
T118 |
10853 |
18 |
0 |
0 |
T146 |
70701 |
518 |
0 |
0 |
T147 |
14467 |
59 |
0 |
0 |
T148 |
14421 |
12 |
0 |
0 |
T149 |
14914 |
26 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7352 |
0 |
0 |
T88 |
2827 |
3 |
0 |
0 |
T103 |
67081 |
436 |
0 |
0 |
T104 |
35038 |
259 |
0 |
0 |
T111 |
9359 |
60 |
0 |
0 |
T113 |
35718 |
239 |
0 |
0 |
T118 |
10853 |
56 |
0 |
0 |
T146 |
70701 |
509 |
0 |
0 |
T147 |
14467 |
22 |
0 |
0 |
T148 |
14421 |
41 |
0 |
0 |
T149 |
14914 |
106 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7270 |
0 |
0 |
T103 |
67081 |
491 |
0 |
0 |
T104 |
35038 |
340 |
0 |
0 |
T111 |
9359 |
127 |
0 |
0 |
T113 |
35718 |
173 |
0 |
0 |
T118 |
10853 |
51 |
0 |
0 |
T146 |
70701 |
532 |
0 |
0 |
T147 |
14467 |
57 |
0 |
0 |
T148 |
14421 |
33 |
0 |
0 |
T149 |
14914 |
22 |
0 |
0 |
T150 |
31045 |
157 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
8019 |
0 |
0 |
T88 |
2827 |
6 |
0 |
0 |
T103 |
67081 |
636 |
0 |
0 |
T104 |
35038 |
418 |
0 |
0 |
T111 |
9359 |
69 |
0 |
0 |
T113 |
35718 |
379 |
0 |
0 |
T118 |
10853 |
19 |
0 |
0 |
T146 |
70701 |
757 |
0 |
0 |
T147 |
14467 |
28 |
0 |
0 |
T148 |
14421 |
35 |
0 |
0 |
T149 |
14914 |
78 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7207 |
0 |
0 |
T88 |
2827 |
1 |
0 |
0 |
T103 |
67081 |
705 |
0 |
0 |
T104 |
35038 |
280 |
0 |
0 |
T111 |
9359 |
18 |
0 |
0 |
T113 |
35718 |
262 |
0 |
0 |
T118 |
10853 |
90 |
0 |
0 |
T146 |
70701 |
533 |
0 |
0 |
T147 |
14467 |
38 |
0 |
0 |
T148 |
14421 |
56 |
0 |
0 |
T149 |
14914 |
105 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
6741 |
0 |
0 |
T103 |
67081 |
654 |
0 |
0 |
T104 |
35038 |
251 |
0 |
0 |
T111 |
9359 |
65 |
0 |
0 |
T113 |
35718 |
158 |
0 |
0 |
T118 |
10853 |
4 |
0 |
0 |
T146 |
70701 |
374 |
0 |
0 |
T147 |
14467 |
51 |
0 |
0 |
T148 |
14421 |
42 |
0 |
0 |
T149 |
14914 |
89 |
0 |
0 |
T150 |
31045 |
97 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7490 |
0 |
0 |
T88 |
2827 |
4 |
0 |
0 |
T103 |
67081 |
487 |
0 |
0 |
T104 |
35038 |
194 |
0 |
0 |
T111 |
9359 |
102 |
0 |
0 |
T113 |
35718 |
422 |
0 |
0 |
T118 |
10853 |
61 |
0 |
0 |
T146 |
70701 |
654 |
0 |
0 |
T147 |
14467 |
71 |
0 |
0 |
T148 |
14421 |
37 |
0 |
0 |
T149 |
14914 |
115 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7012 |
0 |
0 |
T88 |
2827 |
1 |
0 |
0 |
T103 |
67081 |
624 |
0 |
0 |
T104 |
35038 |
247 |
0 |
0 |
T111 |
9359 |
72 |
0 |
0 |
T113 |
35718 |
276 |
0 |
0 |
T118 |
10853 |
55 |
0 |
0 |
T146 |
70701 |
465 |
0 |
0 |
T147 |
14467 |
71 |
0 |
0 |
T148 |
14421 |
83 |
0 |
0 |
T149 |
14914 |
66 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7532 |
0 |
0 |
T103 |
67081 |
629 |
0 |
0 |
T104 |
35038 |
309 |
0 |
0 |
T111 |
9359 |
81 |
0 |
0 |
T113 |
35718 |
212 |
0 |
0 |
T118 |
10853 |
54 |
0 |
0 |
T146 |
70701 |
701 |
0 |
0 |
T147 |
14467 |
57 |
0 |
0 |
T148 |
14421 |
29 |
0 |
0 |
T149 |
14914 |
140 |
0 |
0 |
T150 |
31045 |
108 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7390 |
0 |
0 |
T88 |
2827 |
2 |
0 |
0 |
T103 |
67081 |
504 |
0 |
0 |
T104 |
35038 |
335 |
0 |
0 |
T111 |
9359 |
52 |
0 |
0 |
T113 |
35718 |
248 |
0 |
0 |
T118 |
10853 |
57 |
0 |
0 |
T146 |
70701 |
472 |
0 |
0 |
T147 |
14467 |
17 |
0 |
0 |
T148 |
14421 |
24 |
0 |
0 |
T149 |
14914 |
110 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7190 |
0 |
0 |
T88 |
2827 |
4 |
0 |
0 |
T103 |
67081 |
640 |
0 |
0 |
T104 |
35038 |
309 |
0 |
0 |
T111 |
9359 |
78 |
0 |
0 |
T113 |
35718 |
328 |
0 |
0 |
T118 |
10853 |
51 |
0 |
0 |
T146 |
70701 |
553 |
0 |
0 |
T147 |
14467 |
82 |
0 |
0 |
T148 |
14421 |
43 |
0 |
0 |
T149 |
14914 |
93 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7252 |
0 |
0 |
T88 |
2827 |
2 |
0 |
0 |
T103 |
67081 |
559 |
0 |
0 |
T104 |
35038 |
268 |
0 |
0 |
T111 |
9359 |
67 |
0 |
0 |
T113 |
35718 |
357 |
0 |
0 |
T118 |
10853 |
43 |
0 |
0 |
T146 |
70701 |
476 |
0 |
0 |
T147 |
14467 |
96 |
0 |
0 |
T148 |
14421 |
28 |
0 |
0 |
T149 |
14914 |
111 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7196 |
0 |
0 |
T88 |
2827 |
1 |
0 |
0 |
T103 |
67081 |
651 |
0 |
0 |
T104 |
35038 |
294 |
0 |
0 |
T111 |
9359 |
112 |
0 |
0 |
T113 |
35718 |
320 |
0 |
0 |
T118 |
10853 |
74 |
0 |
0 |
T146 |
70701 |
449 |
0 |
0 |
T147 |
14467 |
37 |
0 |
0 |
T148 |
14421 |
30 |
0 |
0 |
T149 |
14914 |
50 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7937 |
0 |
0 |
T88 |
2827 |
7 |
0 |
0 |
T103 |
67081 |
785 |
0 |
0 |
T104 |
35038 |
144 |
0 |
0 |
T111 |
9359 |
97 |
0 |
0 |
T113 |
35718 |
290 |
0 |
0 |
T118 |
10853 |
20 |
0 |
0 |
T146 |
70701 |
481 |
0 |
0 |
T147 |
14467 |
72 |
0 |
0 |
T148 |
14421 |
42 |
0 |
0 |
T149 |
14914 |
130 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
7301 |
0 |
0 |
T88 |
2827 |
9 |
0 |
0 |
T103 |
67081 |
756 |
0 |
0 |
T104 |
35038 |
232 |
0 |
0 |
T111 |
9359 |
11 |
0 |
0 |
T113 |
35718 |
219 |
0 |
0 |
T146 |
70701 |
646 |
0 |
0 |
T147 |
14467 |
36 |
0 |
0 |
T148 |
14421 |
35 |
0 |
0 |
T149 |
14914 |
161 |
0 |
0 |
T150 |
31045 |
204 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
6712 |
0 |
0 |
T88 |
2827 |
10 |
0 |
0 |
T103 |
67081 |
718 |
0 |
0 |
T104 |
35038 |
147 |
0 |
0 |
T111 |
9359 |
23 |
0 |
0 |
T113 |
35718 |
195 |
0 |
0 |
T118 |
10853 |
56 |
0 |
0 |
T146 |
70701 |
548 |
0 |
0 |
T147 |
14467 |
71 |
0 |
0 |
T148 |
14421 |
28 |
0 |
0 |
T149 |
14914 |
101 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
3025 |
0 |
0 |
T88 |
2827 |
2 |
0 |
0 |
T103 |
67081 |
92 |
0 |
0 |
T104 |
35038 |
83 |
0 |
0 |
T111 |
9359 |
16 |
0 |
0 |
T113 |
35718 |
53 |
0 |
0 |
T118 |
10853 |
9 |
0 |
0 |
T146 |
70701 |
101 |
0 |
0 |
T147 |
14467 |
49 |
0 |
0 |
T148 |
14421 |
61 |
0 |
0 |
T149 |
14914 |
12 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
3012 |
0 |
0 |
T88 |
2827 |
5 |
0 |
0 |
T103 |
67081 |
108 |
0 |
0 |
T104 |
35038 |
58 |
0 |
0 |
T111 |
9359 |
25 |
0 |
0 |
T113 |
35718 |
67 |
0 |
0 |
T118 |
10853 |
10 |
0 |
0 |
T146 |
70701 |
92 |
0 |
0 |
T147 |
14467 |
65 |
0 |
0 |
T148 |
14421 |
52 |
0 |
0 |
T149 |
14914 |
23 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2924 |
0 |
0 |
T88 |
2827 |
8 |
0 |
0 |
T103 |
67081 |
111 |
0 |
0 |
T104 |
35038 |
61 |
0 |
0 |
T111 |
9359 |
22 |
0 |
0 |
T113 |
35718 |
51 |
0 |
0 |
T118 |
10853 |
9 |
0 |
0 |
T146 |
70701 |
102 |
0 |
0 |
T147 |
14467 |
35 |
0 |
0 |
T148 |
14421 |
66 |
0 |
0 |
T149 |
14914 |
16 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2938 |
0 |
0 |
T88 |
2827 |
7 |
0 |
0 |
T103 |
67081 |
111 |
0 |
0 |
T104 |
35038 |
50 |
0 |
0 |
T111 |
9359 |
21 |
0 |
0 |
T113 |
35718 |
70 |
0 |
0 |
T146 |
70701 |
136 |
0 |
0 |
T147 |
14467 |
33 |
0 |
0 |
T148 |
14421 |
41 |
0 |
0 |
T149 |
14914 |
37 |
0 |
0 |
T150 |
31045 |
38 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
3938 |
0 |
0 |
T88 |
2827 |
4 |
0 |
0 |
T103 |
67081 |
225 |
0 |
0 |
T104 |
35038 |
149 |
0 |
0 |
T111 |
9359 |
40 |
0 |
0 |
T113 |
35718 |
117 |
0 |
0 |
T118 |
10853 |
24 |
0 |
0 |
T146 |
70701 |
208 |
0 |
0 |
T147 |
14467 |
28 |
0 |
0 |
T148 |
14421 |
38 |
0 |
0 |
T149 |
14914 |
47 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
6137 |
0 |
0 |
T34 |
569601 |
0 |
0 |
0 |
T35 |
152839 |
18 |
0 |
0 |
T72 |
0 |
46 |
0 |
0 |
T142 |
15859 |
0 |
0 |
0 |
T143 |
182983 |
0 |
0 |
0 |
T151 |
0 |
21 |
0 |
0 |
T152 |
0 |
14 |
0 |
0 |
T153 |
0 |
11 |
0 |
0 |
T154 |
0 |
28 |
0 |
0 |
T155 |
0 |
21 |
0 |
0 |
T156 |
0 |
39 |
0 |
0 |
T157 |
0 |
7 |
0 |
0 |
T158 |
0 |
36 |
0 |
0 |
T159 |
2943 |
0 |
0 |
0 |
T160 |
265964 |
0 |
0 |
0 |
T161 |
343338 |
0 |
0 |
0 |
T162 |
7901 |
0 |
0 |
0 |
T163 |
1075 |
0 |
0 |
0 |
T164 |
1770 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
3200 |
0 |
0 |
T88 |
2827 |
4 |
0 |
0 |
T103 |
67081 |
115 |
0 |
0 |
T104 |
35038 |
73 |
0 |
0 |
T111 |
9359 |
24 |
0 |
0 |
T113 |
35718 |
43 |
0 |
0 |
T118 |
10853 |
14 |
0 |
0 |
T146 |
70701 |
127 |
0 |
0 |
T147 |
14467 |
27 |
0 |
0 |
T148 |
14421 |
31 |
0 |
0 |
T149 |
14914 |
28 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
3042 |
0 |
0 |
T88 |
2827 |
9 |
0 |
0 |
T103 |
67081 |
116 |
0 |
0 |
T104 |
35038 |
55 |
0 |
0 |
T111 |
9359 |
15 |
0 |
0 |
T113 |
35718 |
24 |
0 |
0 |
T118 |
10853 |
7 |
0 |
0 |
T146 |
70701 |
109 |
0 |
0 |
T147 |
14467 |
104 |
0 |
0 |
T148 |
14421 |
17 |
0 |
0 |
T149 |
14914 |
36 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2693 |
0 |
0 |
T103 |
67081 |
63 |
0 |
0 |
T104 |
35038 |
32 |
0 |
0 |
T111 |
9359 |
15 |
0 |
0 |
T113 |
35718 |
28 |
0 |
0 |
T118 |
10853 |
3 |
0 |
0 |
T146 |
70701 |
82 |
0 |
0 |
T147 |
14467 |
33 |
0 |
0 |
T148 |
14421 |
47 |
0 |
0 |
T149 |
14914 |
33 |
0 |
0 |
T150 |
31045 |
4 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2659 |
0 |
0 |
T88 |
2827 |
8 |
0 |
0 |
T103 |
67081 |
78 |
0 |
0 |
T104 |
35038 |
46 |
0 |
0 |
T111 |
9359 |
8 |
0 |
0 |
T113 |
35718 |
29 |
0 |
0 |
T118 |
10853 |
10 |
0 |
0 |
T146 |
70701 |
82 |
0 |
0 |
T147 |
14467 |
40 |
0 |
0 |
T148 |
14421 |
14 |
0 |
0 |
T149 |
14914 |
15 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2588 |
0 |
0 |
T88 |
2827 |
2 |
0 |
0 |
T103 |
67081 |
101 |
0 |
0 |
T104 |
35038 |
48 |
0 |
0 |
T111 |
9359 |
14 |
0 |
0 |
T113 |
35718 |
31 |
0 |
0 |
T118 |
10853 |
8 |
0 |
0 |
T146 |
70701 |
70 |
0 |
0 |
T147 |
14467 |
20 |
0 |
0 |
T148 |
14421 |
49 |
0 |
0 |
T149 |
14914 |
22 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2779 |
0 |
0 |
T88 |
2827 |
9 |
0 |
0 |
T103 |
67081 |
72 |
0 |
0 |
T104 |
35038 |
40 |
0 |
0 |
T111 |
9359 |
24 |
0 |
0 |
T113 |
35718 |
34 |
0 |
0 |
T118 |
10853 |
16 |
0 |
0 |
T146 |
70701 |
86 |
0 |
0 |
T147 |
14467 |
42 |
0 |
0 |
T148 |
14421 |
58 |
0 |
0 |
T149 |
14914 |
26 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
3673 |
0 |
0 |
T88 |
2827 |
9 |
0 |
0 |
T103 |
67081 |
157 |
0 |
0 |
T104 |
35038 |
98 |
0 |
0 |
T111 |
9359 |
45 |
0 |
0 |
T113 |
35718 |
107 |
0 |
0 |
T118 |
10853 |
31 |
0 |
0 |
T146 |
70701 |
133 |
0 |
0 |
T147 |
14467 |
49 |
0 |
0 |
T148 |
14421 |
46 |
0 |
0 |
T149 |
14914 |
31 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2713 |
0 |
0 |
T88 |
2827 |
1 |
0 |
0 |
T103 |
67081 |
90 |
0 |
0 |
T104 |
35038 |
23 |
0 |
0 |
T111 |
9359 |
10 |
0 |
0 |
T113 |
35718 |
19 |
0 |
0 |
T118 |
10853 |
7 |
0 |
0 |
T146 |
70701 |
92 |
0 |
0 |
T147 |
14467 |
75 |
0 |
0 |
T148 |
14421 |
45 |
0 |
0 |
T149 |
14914 |
15 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
4397 |
0 |
0 |
T88 |
2827 |
5 |
0 |
0 |
T103 |
67081 |
253 |
0 |
0 |
T104 |
35038 |
75 |
0 |
0 |
T111 |
9359 |
35 |
0 |
0 |
T113 |
35718 |
132 |
0 |
0 |
T118 |
10853 |
11 |
0 |
0 |
T146 |
70701 |
275 |
0 |
0 |
T147 |
14467 |
33 |
0 |
0 |
T148 |
14421 |
52 |
0 |
0 |
T149 |
14914 |
64 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
3055 |
0 |
0 |
T88 |
2827 |
8 |
0 |
0 |
T103 |
67081 |
103 |
0 |
0 |
T104 |
35038 |
42 |
0 |
0 |
T111 |
9359 |
25 |
0 |
0 |
T113 |
35718 |
56 |
0 |
0 |
T118 |
10853 |
4 |
0 |
0 |
T146 |
70701 |
101 |
0 |
0 |
T147 |
14467 |
14 |
0 |
0 |
T148 |
14421 |
49 |
0 |
0 |
T149 |
14914 |
26 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2704 |
0 |
0 |
T88 |
2827 |
3 |
0 |
0 |
T103 |
67081 |
91 |
0 |
0 |
T104 |
35038 |
24 |
0 |
0 |
T111 |
9359 |
15 |
0 |
0 |
T113 |
35718 |
20 |
0 |
0 |
T118 |
10853 |
6 |
0 |
0 |
T146 |
70701 |
64 |
0 |
0 |
T147 |
14467 |
62 |
0 |
0 |
T148 |
14421 |
45 |
0 |
0 |
T149 |
14914 |
5 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2840 |
0 |
0 |
T88 |
2827 |
9 |
0 |
0 |
T103 |
67081 |
106 |
0 |
0 |
T104 |
35038 |
18 |
0 |
0 |
T111 |
9359 |
20 |
0 |
0 |
T113 |
35718 |
38 |
0 |
0 |
T118 |
10853 |
6 |
0 |
0 |
T146 |
70701 |
84 |
0 |
0 |
T147 |
14467 |
59 |
0 |
0 |
T148 |
14421 |
68 |
0 |
0 |
T149 |
14914 |
25 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2670 |
0 |
0 |
T88 |
2827 |
13 |
0 |
0 |
T103 |
67081 |
79 |
0 |
0 |
T104 |
35038 |
21 |
0 |
0 |
T111 |
9359 |
8 |
0 |
0 |
T113 |
35718 |
25 |
0 |
0 |
T118 |
10853 |
10 |
0 |
0 |
T146 |
70701 |
44 |
0 |
0 |
T147 |
14467 |
67 |
0 |
0 |
T148 |
14421 |
56 |
0 |
0 |
T149 |
14914 |
12 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2562 |
0 |
0 |
T88 |
2827 |
10 |
0 |
0 |
T103 |
67081 |
92 |
0 |
0 |
T104 |
35038 |
40 |
0 |
0 |
T111 |
9359 |
16 |
0 |
0 |
T113 |
35718 |
46 |
0 |
0 |
T118 |
10853 |
12 |
0 |
0 |
T146 |
70701 |
60 |
0 |
0 |
T147 |
14467 |
33 |
0 |
0 |
T148 |
14421 |
49 |
0 |
0 |
T149 |
14914 |
13 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2759 |
0 |
0 |
T88 |
2827 |
9 |
0 |
0 |
T103 |
67081 |
92 |
0 |
0 |
T104 |
35038 |
26 |
0 |
0 |
T111 |
9359 |
28 |
0 |
0 |
T113 |
35718 |
39 |
0 |
0 |
T118 |
10853 |
5 |
0 |
0 |
T146 |
70701 |
80 |
0 |
0 |
T147 |
14467 |
75 |
0 |
0 |
T148 |
14421 |
41 |
0 |
0 |
T149 |
14914 |
22 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
391261584 |
2606 |
0 |
0 |
T103 |
67081 |
83 |
0 |
0 |
T104 |
35038 |
33 |
0 |
0 |
T111 |
9359 |
26 |
0 |
0 |
T113 |
35718 |
32 |
0 |
0 |
T118 |
10853 |
9 |
0 |
0 |
T146 |
70701 |
64 |
0 |
0 |
T147 |
14467 |
61 |
0 |
0 |
T148 |
14421 |
39 |
0 |
0 |
T149 |
14914 |
30 |
0 |
0 |
T150 |
31045 |
4 |
0 |
0 |