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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 98.35 94.20 98.61 89.36 97.23 95.82 99.10


Total test records in report: 1101
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T1010 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.633747515 May 26 01:01:47 PM PDT 24 May 26 01:01:49 PM PDT 24 328131951 ps
T1011 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1646597586 May 26 01:01:47 PM PDT 24 May 26 01:01:51 PM PDT 24 171189828 ps
T1012 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4152227835 May 26 01:01:48 PM PDT 24 May 26 01:01:50 PM PDT 24 26164971 ps
T121 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.379524627 May 26 01:02:03 PM PDT 24 May 26 01:02:08 PM PDT 24 784758856 ps
T1013 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4173101622 May 26 01:01:58 PM PDT 24 May 26 01:02:03 PM PDT 24 208764590 ps
T1014 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1120989605 May 26 01:02:01 PM PDT 24 May 26 01:02:04 PM PDT 24 101936735 ps
T1015 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2503379455 May 26 01:01:40 PM PDT 24 May 26 01:01:42 PM PDT 24 12234709 ps
T1016 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2416523559 May 26 01:02:01 PM PDT 24 May 26 01:02:05 PM PDT 24 29242847 ps
T1017 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3935519067 May 26 01:01:57 PM PDT 24 May 26 01:02:03 PM PDT 24 59771800 ps
T1018 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.151977602 May 26 01:01:59 PM PDT 24 May 26 01:02:02 PM PDT 24 33049067 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3350662165 May 26 01:01:40 PM PDT 24 May 26 01:01:43 PM PDT 24 144278944 ps
T1019 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1046459947 May 26 01:01:51 PM PDT 24 May 26 01:01:54 PM PDT 24 31250340 ps
T1020 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1976962841 May 26 01:01:56 PM PDT 24 May 26 01:02:00 PM PDT 24 96034894 ps
T1021 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3247382385 May 26 01:02:00 PM PDT 24 May 26 01:02:04 PM PDT 24 19782541 ps
T1022 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3871411104 May 26 01:01:50 PM PDT 24 May 26 01:01:54 PM PDT 24 1089466033 ps
T1023 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2479345728 May 26 01:02:04 PM PDT 24 May 26 01:02:08 PM PDT 24 15020547 ps
T1024 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.918906624 May 26 01:02:04 PM PDT 24 May 26 01:02:11 PM PDT 24 178163356 ps
T1025 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2035539719 May 26 01:02:01 PM PDT 24 May 26 01:02:05 PM PDT 24 10526699 ps
T1026 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1277277580 May 26 01:01:35 PM PDT 24 May 26 01:01:37 PM PDT 24 23785445 ps
T1027 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.502819125 May 26 01:01:59 PM PDT 24 May 26 01:02:03 PM PDT 24 27249748 ps
T1028 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1200662844 May 26 01:01:51 PM PDT 24 May 26 01:01:53 PM PDT 24 21291870 ps
T1029 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1935782529 May 26 01:01:58 PM PDT 24 May 26 01:02:02 PM PDT 24 82726244 ps
T1030 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1908643550 May 26 01:02:04 PM PDT 24 May 26 01:02:09 PM PDT 24 263771620 ps
T1031 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.858942683 May 26 01:02:00 PM PDT 24 May 26 01:02:11 PM PDT 24 968039952 ps
T123 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2654546523 May 26 01:01:40 PM PDT 24 May 26 01:02:03 PM PDT 24 1657617137 ps
T1032 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.229072633 May 26 01:01:54 PM PDT 24 May 26 01:01:59 PM PDT 24 142322874 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2673716945 May 26 01:01:55 PM PDT 24 May 26 01:02:11 PM PDT 24 918732040 ps
T1033 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2565949999 May 26 01:01:40 PM PDT 24 May 26 01:01:55 PM PDT 24 4697127879 ps
T1034 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4157140656 May 26 01:01:49 PM PDT 24 May 26 01:01:54 PM PDT 24 262115720 ps
T1035 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2577115823 May 26 01:01:40 PM PDT 24 May 26 01:01:49 PM PDT 24 418842362 ps
T1036 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.778567950 May 26 01:01:57 PM PDT 24 May 26 01:02:02 PM PDT 24 214051320 ps
T1037 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1601737168 May 26 01:01:54 PM PDT 24 May 26 01:01:57 PM PDT 24 11810223 ps
T1038 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4240388318 May 26 01:01:57 PM PDT 24 May 26 01:02:02 PM PDT 24 187318273 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2656197064 May 26 01:01:57 PM PDT 24 May 26 01:02:01 PM PDT 24 72861634 ps
T1040 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3429955308 May 26 01:01:55 PM PDT 24 May 26 01:01:57 PM PDT 24 16100770 ps
T1041 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1181939422 May 26 01:01:38 PM PDT 24 May 26 01:01:42 PM PDT 24 121504684 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3995224426 May 26 01:01:38 PM PDT 24 May 26 01:01:40 PM PDT 24 14067935 ps
T1043 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2633289261 May 26 01:01:56 PM PDT 24 May 26 01:01:58 PM PDT 24 14801694 ps
T1044 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2950139909 May 26 01:01:52 PM PDT 24 May 26 01:01:56 PM PDT 24 123117331 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2959990073 May 26 01:01:40 PM PDT 24 May 26 01:01:44 PM PDT 24 91786212 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2896279246 May 26 01:01:48 PM PDT 24 May 26 01:01:52 PM PDT 24 176089341 ps
T1047 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.79782136 May 26 01:01:54 PM PDT 24 May 26 01:01:57 PM PDT 24 123790954 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3247928568 May 26 01:01:40 PM PDT 24 May 26 01:01:44 PM PDT 24 425025465 ps
T1049 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.409604720 May 26 01:01:54 PM PDT 24 May 26 01:02:00 PM PDT 24 360955103 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1024567767 May 26 01:01:26 PM PDT 24 May 26 01:01:31 PM PDT 24 54512641 ps
T1051 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2242220165 May 26 01:02:00 PM PDT 24 May 26 01:02:04 PM PDT 24 86377491 ps
T1052 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2369444187 May 26 01:02:01 PM PDT 24 May 26 01:02:05 PM PDT 24 43360426 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3344803422 May 26 01:01:40 PM PDT 24 May 26 01:02:07 PM PDT 24 1820933344 ps
T1054 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1377730899 May 26 01:01:58 PM PDT 24 May 26 01:02:01 PM PDT 24 76634073 ps
T1055 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2740120299 May 26 01:01:53 PM PDT 24 May 26 01:01:58 PM PDT 24 35547894 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.245963159 May 26 01:01:38 PM PDT 24 May 26 01:01:39 PM PDT 24 44207103 ps
T1057 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3610900572 May 26 01:01:54 PM PDT 24 May 26 01:01:59 PM PDT 24 553118091 ps
T1058 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.190521134 May 26 01:01:58 PM PDT 24 May 26 01:02:03 PM PDT 24 63666333 ps
T1059 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1888017799 May 26 01:01:39 PM PDT 24 May 26 01:02:04 PM PDT 24 1196954401 ps
T1060 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3511744482 May 26 01:02:03 PM PDT 24 May 26 01:02:07 PM PDT 24 143039392 ps
T1061 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1928840275 May 26 01:02:03 PM PDT 24 May 26 01:02:07 PM PDT 24 14967497 ps
T1062 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.758443482 May 26 01:01:54 PM PDT 24 May 26 01:01:58 PM PDT 24 143448709 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3989133238 May 26 01:01:58 PM PDT 24 May 26 01:02:01 PM PDT 24 67709131 ps
T1064 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3562421822 May 26 01:01:58 PM PDT 24 May 26 01:02:02 PM PDT 24 13330364 ps
T1065 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1561816120 May 26 01:01:56 PM PDT 24 May 26 01:01:59 PM PDT 24 26011724 ps
T1066 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4230420262 May 26 01:02:05 PM PDT 24 May 26 01:02:09 PM PDT 24 15003050 ps
T1067 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3483424126 May 26 01:01:57 PM PDT 24 May 26 01:01:59 PM PDT 24 36214008 ps
T1068 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.31582803 May 26 01:02:03 PM PDT 24 May 26 01:02:08 PM PDT 24 229711052 ps
T1069 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1324996055 May 26 01:01:40 PM PDT 24 May 26 01:01:42 PM PDT 24 10910503 ps
T1070 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1307104442 May 26 01:01:46 PM PDT 24 May 26 01:01:49 PM PDT 24 36298580 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.42598282 May 26 01:01:37 PM PDT 24 May 26 01:02:02 PM PDT 24 2075961501 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.183697084 May 26 01:01:53 PM PDT 24 May 26 01:02:20 PM PDT 24 4591772841 ps
T167 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.610433707 May 26 01:01:48 PM PDT 24 May 26 01:02:05 PM PDT 24 2586097929 ps
T1073 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.281987845 May 26 01:01:54 PM PDT 24 May 26 01:01:59 PM PDT 24 60220205 ps
T1074 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.929346462 May 26 01:01:50 PM PDT 24 May 26 01:01:54 PM PDT 24 729205164 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2061589442 May 26 01:01:39 PM PDT 24 May 26 01:01:42 PM PDT 24 222250696 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1832420825 May 26 01:01:52 PM PDT 24 May 26 01:01:56 PM PDT 24 474731707 ps
T1077 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2428597161 May 26 01:01:39 PM PDT 24 May 26 01:01:47 PM PDT 24 437925960 ps
T1078 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1161457627 May 26 01:01:58 PM PDT 24 May 26 01:02:03 PM PDT 24 97611556 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.266485852 May 26 01:01:36 PM PDT 24 May 26 01:02:14 PM PDT 24 1956751480 ps
T168 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2929537817 May 26 01:01:38 PM PDT 24 May 26 01:01:54 PM PDT 24 659010410 ps
T1080 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3641726145 May 26 01:02:04 PM PDT 24 May 26 01:02:09 PM PDT 24 455369404 ps
T169 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1325190748 May 26 01:01:52 PM PDT 24 May 26 01:02:13 PM PDT 24 884149794 ps
T166 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2667989361 May 26 01:01:54 PM PDT 24 May 26 01:02:03 PM PDT 24 218736593 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1454051785 May 26 01:01:38 PM PDT 24 May 26 01:01:47 PM PDT 24 321090299 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.538110318 May 26 01:01:57 PM PDT 24 May 26 01:02:15 PM PDT 24 1504269272 ps
T1083 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.687103911 May 26 01:01:58 PM PDT 24 May 26 01:02:05 PM PDT 24 154395666 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.59910714 May 26 01:01:37 PM PDT 24 May 26 01:01:41 PM PDT 24 473200259 ps
T1085 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2665968152 May 26 01:01:59 PM PDT 24 May 26 01:02:03 PM PDT 24 14422386 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4161327061 May 26 01:01:37 PM PDT 24 May 26 01:01:51 PM PDT 24 4556723567 ps
T1087 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3706122478 May 26 01:01:55 PM PDT 24 May 26 01:02:09 PM PDT 24 804986731 ps
T1088 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1722800266 May 26 01:01:55 PM PDT 24 May 26 01:02:20 PM PDT 24 3788475418 ps
T1089 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2550829271 May 26 01:02:02 PM PDT 24 May 26 01:02:06 PM PDT 24 52260494 ps
T1090 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3386719169 May 26 01:02:00 PM PDT 24 May 26 01:02:06 PM PDT 24 54077902 ps
T1091 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2457744200 May 26 01:01:59 PM PDT 24 May 26 01:02:03 PM PDT 24 33189070 ps
T270 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4131175892 May 26 01:01:49 PM PDT 24 May 26 01:01:54 PM PDT 24 747619923 ps
T1092 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4170811240 May 26 01:01:58 PM PDT 24 May 26 01:02:02 PM PDT 24 384643321 ps
T1093 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3989873314 May 26 01:02:00 PM PDT 24 May 26 01:02:06 PM PDT 24 1106086005 ps
T1094 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3368443084 May 26 01:02:00 PM PDT 24 May 26 01:02:04 PM PDT 24 17793292 ps
T1095 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.594361652 May 26 01:01:58 PM PDT 24 May 26 01:02:02 PM PDT 24 13128896 ps
T1096 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3507491762 May 26 01:02:03 PM PDT 24 May 26 01:02:07 PM PDT 24 100764858 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2993158359 May 26 01:01:37 PM PDT 24 May 26 01:01:40 PM PDT 24 48251617 ps
T1098 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.191834652 May 26 01:02:01 PM PDT 24 May 26 01:02:05 PM PDT 24 69702341 ps
T1099 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1076918801 May 26 01:02:00 PM PDT 24 May 26 01:02:05 PM PDT 24 201857138 ps
T1100 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3597544836 May 26 01:02:00 PM PDT 24 May 26 01:02:03 PM PDT 24 12960702 ps
T1101 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3679430904 May 26 01:01:54 PM PDT 24 May 26 01:01:59 PM PDT 24 109424021 ps

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2528418873
Short name T6
Test name
Test status
Simulation time 21502301504 ps
CPU time 20.09 seconds
Started May 26 02:40:36 PM PDT 24
Finished May 26 02:40:59 PM PDT 24
Peak memory 224336 kb
Host smart-c49e17f0-2dc8-4de5-92b8-0a9c81fcd80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528418873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2528418873
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3888431451
Short name T15
Test name
Test status
Simulation time 205609354068 ps
CPU time 505.08 seconds
Started May 26 02:40:55 PM PDT 24
Finished May 26 02:49:22 PM PDT 24
Peak memory 264632 kb
Host smart-7fdcee7e-2628-4365-ae3a-002661df23a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888431451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3888431451
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.550716291
Short name T16
Test name
Test status
Simulation time 12246773109 ps
CPU time 144.81 seconds
Started May 26 02:42:02 PM PDT 24
Finished May 26 02:44:28 PM PDT 24
Peak memory 257076 kb
Host smart-9e410d8d-7e09-4d7b-80a7-c7bd2fad7532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550716291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.550716291
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1289462697
Short name T32
Test name
Test status
Simulation time 170149726289 ps
CPU time 427.28 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:46:58 PM PDT 24
Peak memory 248916 kb
Host smart-2a64ce0b-5278-4a43-8c55-14355fe81029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289462697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1289462697
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1359707686
Short name T103
Test name
Test status
Simulation time 2795119497 ps
CPU time 14.82 seconds
Started May 26 01:01:52 PM PDT 24
Finished May 26 01:02:07 PM PDT 24
Peak memory 215480 kb
Host smart-369bea42-618f-4e9b-8f95-ff3cf8ace929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359707686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1359707686
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2075059513
Short name T160
Test name
Test status
Simulation time 106385774780 ps
CPU time 259.9 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:46:00 PM PDT 24
Peak memory 249132 kb
Host smart-673cbf66-38f4-4f60-b6ea-41706bb09174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075059513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2075059513
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.4159007075
Short name T175
Test name
Test status
Simulation time 23090568380 ps
CPU time 224.57 seconds
Started May 26 02:39:46 PM PDT 24
Finished May 26 02:43:33 PM PDT 24
Peak memory 260444 kb
Host smart-831cd2ad-329e-4db0-9ba6-9e08036d7d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159007075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4159007075
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.811579967
Short name T74
Test name
Test status
Simulation time 39900305 ps
CPU time 0.71 seconds
Started May 26 02:39:00 PM PDT 24
Finished May 26 02:39:01 PM PDT 24
Peak memory 215760 kb
Host smart-4f0225b7-55f2-48e5-b1e0-d9a309054dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811579967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.811579967
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2222910331
Short name T152
Test name
Test status
Simulation time 109061206771 ps
CPU time 603.86 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:51:28 PM PDT 24
Peak memory 273404 kb
Host smart-0553cef8-6f9e-4533-b240-23660546cc27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222910331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2222910331
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.429841245
Short name T174
Test name
Test status
Simulation time 186300833731 ps
CPU time 484.83 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:48:02 PM PDT 24
Peak memory 253808 kb
Host smart-6ea296cf-b15c-4718-83b1-0926e5c3af2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429841245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.429841245
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.236141200
Short name T105
Test name
Test status
Simulation time 94463120 ps
CPU time 3.34 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:59 PM PDT 24
Peak memory 215408 kb
Host smart-45587dc1-93ee-49a0-929f-162d90be8679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236141200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.236141200
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.660776194
Short name T243
Test name
Test status
Simulation time 72846318200 ps
CPU time 477.2 seconds
Started May 26 02:39:13 PM PDT 24
Finished May 26 02:47:11 PM PDT 24
Peak memory 273472 kb
Host smart-2dad7ac9-8e53-4b45-b265-16fa01e2a896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660776194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.660776194
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1992898929
Short name T71
Test name
Test status
Simulation time 855619685 ps
CPU time 1.11 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 234744 kb
Host smart-31159d42-ff0f-463a-9ad9-5bcbf4ebfe6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992898929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1992898929
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3641399179
Short name T186
Test name
Test status
Simulation time 103558133469 ps
CPU time 290.53 seconds
Started May 26 02:41:31 PM PDT 24
Finished May 26 02:46:23 PM PDT 24
Peak memory 273384 kb
Host smart-6680beb3-3e0c-4736-9deb-6d463ddb6ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641399179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3641399179
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.650435269
Short name T86
Test name
Test status
Simulation time 19213492426 ps
CPU time 32.96 seconds
Started May 26 02:40:06 PM PDT 24
Finished May 26 02:40:39 PM PDT 24
Peak memory 240544 kb
Host smart-a181ad15-2bac-4ccf-b626-e78253d706fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650435269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.650435269
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3514360831
Short name T60
Test name
Test status
Simulation time 6061883411 ps
CPU time 152.55 seconds
Started May 26 02:40:13 PM PDT 24
Finished May 26 02:42:47 PM PDT 24
Peak memory 268524 kb
Host smart-1f7ae2e9-a8b2-4e37-93c5-b4cd60cab62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514360831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3514360831
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4077549237
Short name T120
Test name
Test status
Simulation time 93060628 ps
CPU time 1.74 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:01:58 PM PDT 24
Peak memory 207132 kb
Host smart-643992e8-470a-45e1-968e-a84aa5b5fb22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077549237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
077549237
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.582147281
Short name T34
Test name
Test status
Simulation time 219080250577 ps
CPU time 440.94 seconds
Started May 26 02:41:12 PM PDT 24
Finished May 26 02:48:35 PM PDT 24
Peak memory 265400 kb
Host smart-7ca7810a-cdcf-4011-b91b-9eea08631ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582147281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.582147281
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2716172872
Short name T12
Test name
Test status
Simulation time 40562534038 ps
CPU time 339.61 seconds
Started May 26 02:41:55 PM PDT 24
Finished May 26 02:47:35 PM PDT 24
Peak memory 253632 kb
Host smart-27568d68-1afa-482f-9522-2c59152e7d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716172872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2716172872
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2675858263
Short name T158
Test name
Test status
Simulation time 46770488626 ps
CPU time 505.17 seconds
Started May 26 02:40:40 PM PDT 24
Finished May 26 02:49:06 PM PDT 24
Peak memory 264756 kb
Host smart-9f21057f-e5b6-4cbe-954f-790ddfaf2162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675858263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2675858263
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2135602707
Short name T21
Test name
Test status
Simulation time 15066636 ps
CPU time 1.03 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:39:43 PM PDT 24
Peak memory 217460 kb
Host smart-2ea0a10b-a776-4004-9105-85e00edb5fb5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135602707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2135602707
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3249087801
Short name T232
Test name
Test status
Simulation time 419245384237 ps
CPU time 577.98 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:51:36 PM PDT 24
Peak memory 252676 kb
Host smart-b2e3bd79-ba38-4d42-bf48-95f64a7464c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249087801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3249087801
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4114454547
Short name T156
Test name
Test status
Simulation time 28063087771 ps
CPU time 117.48 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 267856 kb
Host smart-2f028cc5-7737-4476-874a-a88182a42db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114454547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4114454547
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2541417214
Short name T37
Test name
Test status
Simulation time 25071389015 ps
CPU time 210.36 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:43:58 PM PDT 24
Peak memory 256228 kb
Host smart-8e27abb1-0c31-4d3b-9ea5-be28c442cb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541417214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2541417214
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1731092036
Short name T68
Test name
Test status
Simulation time 21295060 ps
CPU time 0.7 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:05 PM PDT 24
Peak memory 204260 kb
Host smart-0b60cc85-47be-4be1-be4c-1432f38231c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731092036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1731092036
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1430778178
Short name T81
Test name
Test status
Simulation time 18592953386 ps
CPU time 47.15 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:55 PM PDT 24
Peak memory 215868 kb
Host smart-d0cf598b-f6ad-4ca0-8fb5-d7c6ab35ae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430778178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1430778178
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.132840990
Short name T226
Test name
Test status
Simulation time 3543776140 ps
CPU time 22.11 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:40:03 PM PDT 24
Peak memory 248816 kb
Host smart-32e3621a-99b8-4c23-9cb2-7d85c082571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132840990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.132840990
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.287142789
Short name T242
Test name
Test status
Simulation time 261608885837 ps
CPU time 677.98 seconds
Started May 26 02:41:47 PM PDT 24
Finished May 26 02:53:05 PM PDT 24
Peak memory 261820 kb
Host smart-6493f47e-5fbe-42cb-aaaf-e3a402cfbf57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287142789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.287142789
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2314734629
Short name T150
Test name
Test status
Simulation time 1411201800 ps
CPU time 7.48 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:09 PM PDT 24
Peak memory 223344 kb
Host smart-eeeeecee-8f77-4fc7-8d09-e72c8ae3a78a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314734629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2314734629
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2969865438
Short name T260
Test name
Test status
Simulation time 4938771705 ps
CPU time 54.4 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:42:10 PM PDT 24
Peak memory 251768 kb
Host smart-9123df20-626c-48d8-ac93-47f7cbe454eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969865438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2969865438
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.517788373
Short name T202
Test name
Test status
Simulation time 27404269225 ps
CPU time 284.72 seconds
Started May 26 02:41:33 PM PDT 24
Finished May 26 02:46:19 PM PDT 24
Peak memory 262568 kb
Host smart-8e7ebeb7-b16a-4d04-bed6-b54b101e7eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517788373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.517788373
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3117185081
Short name T54
Test name
Test status
Simulation time 31032737949 ps
CPU time 120.37 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:41:56 PM PDT 24
Peak memory 256896 kb
Host smart-26de836c-97df-4b20-b9a2-cdfca4e32b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117185081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3117185081
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3458972595
Short name T227
Test name
Test status
Simulation time 8416390211 ps
CPU time 48.59 seconds
Started May 26 02:39:46 PM PDT 24
Finished May 26 02:40:37 PM PDT 24
Peak memory 252116 kb
Host smart-f9879146-e757-44c5-9e18-808520a44cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458972595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3458972595
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1744221461
Short name T92
Test name
Test status
Simulation time 240665759884 ps
CPU time 397.5 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 265324 kb
Host smart-b34ceeb3-e834-4415-8ba3-c141c30bbb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744221461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1744221461
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3108711376
Short name T241
Test name
Test status
Simulation time 230050911330 ps
CPU time 379.18 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:45:59 PM PDT 24
Peak memory 249876 kb
Host smart-8efebf46-fa63-47ba-bcba-d9092236db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108711376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3108711376
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1527613023
Short name T9
Test name
Test status
Simulation time 2852240482 ps
CPU time 19.22 seconds
Started May 26 02:39:21 PM PDT 24
Finished May 26 02:39:42 PM PDT 24
Peak memory 237528 kb
Host smart-2ef7bcc1-cdff-4728-832d-76b88c2474a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527613023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1527613023
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1321302660
Short name T100
Test name
Test status
Simulation time 58026038 ps
CPU time 3.07 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:06 PM PDT 24
Peak memory 215564 kb
Host smart-e691f7f1-5ac0-41fe-b2db-737ec7b25682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321302660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1321302660
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1325190748
Short name T169
Test name
Test status
Simulation time 884149794 ps
CPU time 20.44 seconds
Started May 26 01:01:52 PM PDT 24
Finished May 26 01:02:13 PM PDT 24
Peak memory 215460 kb
Host smart-b2ca148a-b5f2-4695-8dd8-08d791eb8c57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325190748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1325190748
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1548881228
Short name T73
Test name
Test status
Simulation time 105871541682 ps
CPU time 233.61 seconds
Started May 26 02:40:49 PM PDT 24
Finished May 26 02:44:44 PM PDT 24
Peak memory 254008 kb
Host smart-6b3af2d2-f0de-4efe-89dd-48db0d6dccd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548881228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1548881228
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.850480845
Short name T309
Test name
Test status
Simulation time 763381553 ps
CPU time 8.43 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:40:57 PM PDT 24
Peak memory 232380 kb
Host smart-2bf664db-96de-407f-bd52-4310be0d3b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850480845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.850480845
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2012822382
Short name T238
Test name
Test status
Simulation time 16310883010 ps
CPU time 117.31 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:42:56 PM PDT 24
Peak memory 271244 kb
Host smart-7515451b-2725-4020-a96d-67b2da615deb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012822382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2012822382
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4187923925
Short name T235
Test name
Test status
Simulation time 38098088860 ps
CPU time 177.68 seconds
Started May 26 02:41:12 PM PDT 24
Finished May 26 02:44:11 PM PDT 24
Peak memory 248920 kb
Host smart-fdfb0841-0a35-4517-bbd2-49d6f0735870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187923925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4187923925
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1498660364
Short name T173
Test name
Test status
Simulation time 35581929073 ps
CPU time 80.72 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:40:45 PM PDT 24
Peak memory 252488 kb
Host smart-ad33fec1-d41d-41d4-bd06-c739db5472d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498660364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1498660364
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2548592925
Short name T95
Test name
Test status
Simulation time 1251289752 ps
CPU time 4.43 seconds
Started May 26 02:39:38 PM PDT 24
Finished May 26 02:39:45 PM PDT 24
Peak memory 233676 kb
Host smart-9e35b720-be54-45e4-a02f-cf96d2d33001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548592925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2548592925
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3739849024
Short name T245
Test name
Test status
Simulation time 65368835154 ps
CPU time 527.06 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:49:15 PM PDT 24
Peak memory 267240 kb
Host smart-40bb2741-4f67-4711-b41e-f02c61db3b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739849024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3739849024
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1285948619
Short name T165
Test name
Test status
Simulation time 2035541839 ps
CPU time 21.28 seconds
Started May 26 01:01:29 PM PDT 24
Finished May 26 01:01:51 PM PDT 24
Peak memory 215552 kb
Host smart-d98a67f3-6bb6-48fd-9182-ca780e3317e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285948619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1285948619
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4131175892
Short name T270
Test name
Test status
Simulation time 747619923 ps
CPU time 4.51 seconds
Started May 26 01:01:49 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 215812 kb
Host smart-3bbae238-66bc-4d70-b97e-3809a16379db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131175892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
131175892
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3231080211
Short name T252
Test name
Test status
Simulation time 257854440446 ps
CPU time 637.32 seconds
Started May 26 02:38:59 PM PDT 24
Finished May 26 02:49:37 PM PDT 24
Peak memory 257088 kb
Host smart-07c556e1-9bf0-4a26-87a9-247ac02e6674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231080211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3231080211
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3153825861
Short name T203
Test name
Test status
Simulation time 55956597292 ps
CPU time 169.27 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:43:47 PM PDT 24
Peak memory 239040 kb
Host smart-c99dcb40-7529-442f-a762-f2afd58070da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153825861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3153825861
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2567267284
Short name T230
Test name
Test status
Simulation time 4746692659 ps
CPU time 60.11 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:42:03 PM PDT 24
Peak memory 250368 kb
Host smart-7866dc2b-7865-464e-a9f1-fddc630d96cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567267284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2567267284
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3999798821
Short name T258
Test name
Test status
Simulation time 63798529224 ps
CPU time 601.47 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:49:26 PM PDT 24
Peak memory 264700 kb
Host smart-2246241e-baf8-4a4c-9ea6-a5780a391261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999798821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3999798821
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1547673902
Short name T268
Test name
Test status
Simulation time 17053396750 ps
CPU time 62.71 seconds
Started May 26 02:39:24 PM PDT 24
Finished May 26 02:40:29 PM PDT 24
Peak memory 240640 kb
Host smart-445d880c-f0dd-441d-b65b-2adb5060905e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547673902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1547673902
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3592096527
Short name T48
Test name
Test status
Simulation time 575437561 ps
CPU time 4.3 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:43 PM PDT 24
Peak memory 224168 kb
Host smart-22b61dcd-c8ee-4790-b8d7-c2cec5e9fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592096527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3592096527
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2445607874
Short name T90
Test name
Test status
Simulation time 80688204 ps
CPU time 1.43 seconds
Started May 26 01:01:37 PM PDT 24
Finished May 26 01:01:39 PM PDT 24
Peak memory 207288 kb
Host smart-360f3544-28cb-41b5-af26-d0d281924298
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445607874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2445607874
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2654546523
Short name T123
Test name
Test status
Simulation time 1657617137 ps
CPU time 21.57 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 215412 kb
Host smart-d3375be2-d2b1-490f-8a04-a20ebaa7835f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654546523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2654546523
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2565949999
Short name T1033
Test name
Test status
Simulation time 4697127879 ps
CPU time 14.13 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:55 PM PDT 24
Peak memory 207220 kb
Host smart-02e46ebd-f201-467d-9084-d2c4dd37caf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565949999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2565949999
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1181939422
Short name T1041
Test name
Test status
Simulation time 121504684 ps
CPU time 3.51 seconds
Started May 26 01:01:38 PM PDT 24
Finished May 26 01:01:42 PM PDT 24
Peak memory 218104 kb
Host smart-dbd045e8-494c-44b3-a82f-6ad05500294e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181939422 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1181939422
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3247928568
Short name T1048
Test name
Test status
Simulation time 425025465 ps
CPU time 2.76 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:44 PM PDT 24
Peak memory 215552 kb
Host smart-906eecee-f703-44b0-b0e4-303a376fb679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247928568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
247928568
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.245963159
Short name T1056
Test name
Test status
Simulation time 44207103 ps
CPU time 0.76 seconds
Started May 26 01:01:38 PM PDT 24
Finished May 26 01:01:39 PM PDT 24
Peak memory 203724 kb
Host smart-947e4c34-246b-496c-bd8a-3aa050b82d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245963159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.245963159
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1201798624
Short name T990
Test name
Test status
Simulation time 118503829 ps
CPU time 1.35 seconds
Started May 26 01:01:37 PM PDT 24
Finished May 26 01:01:39 PM PDT 24
Peak memory 215516 kb
Host smart-735d9a40-d71f-471e-b7f1-6c3ed4ecb26f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201798624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1201798624
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3995224426
Short name T1042
Test name
Test status
Simulation time 14067935 ps
CPU time 0.65 seconds
Started May 26 01:01:38 PM PDT 24
Finished May 26 01:01:40 PM PDT 24
Peak memory 203524 kb
Host smart-bfdd243f-86f9-4c3f-a50a-f87e3fdaa26d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995224426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3995224426
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3967663229
Short name T138
Test name
Test status
Simulation time 234208864 ps
CPU time 1.85 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:43 PM PDT 24
Peak memory 207208 kb
Host smart-67fd2984-9a59-407f-9f09-8d89afa14ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967663229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3967663229
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1024567767
Short name T1050
Test name
Test status
Simulation time 54512641 ps
CPU time 3.28 seconds
Started May 26 01:01:26 PM PDT 24
Finished May 26 01:01:31 PM PDT 24
Peak memory 220348 kb
Host smart-5073889b-ee84-4f91-b2da-2bf7d25819a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024567767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
024567767
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1888017799
Short name T1059
Test name
Test status
Simulation time 1196954401 ps
CPU time 24.13 seconds
Started May 26 01:01:39 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 207036 kb
Host smart-d0c2c818-c08b-4083-9577-2d051654eb2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888017799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1888017799
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3344803422
Short name T1053
Test name
Test status
Simulation time 1820933344 ps
CPU time 26.46 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:02:07 PM PDT 24
Peak memory 207064 kb
Host smart-5a37bd76-b599-44ca-98a6-5589e4b7eefd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344803422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3344803422
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.786632758
Short name T89
Test name
Test status
Simulation time 42244302 ps
CPU time 1.37 seconds
Started May 26 01:01:39 PM PDT 24
Finished May 26 01:01:41 PM PDT 24
Peak memory 207204 kb
Host smart-7596fe88-d755-4eb9-8a78-190091a80c7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786632758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.786632758
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2959990073
Short name T1045
Test name
Test status
Simulation time 91786212 ps
CPU time 2.83 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:44 PM PDT 24
Peak memory 216540 kb
Host smart-1d657ab0-8a31-43a8-bdc0-6d6b96ea3b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959990073 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2959990073
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3819629282
Short name T118
Test name
Test status
Simulation time 434228232 ps
CPU time 2.63 seconds
Started May 26 01:01:38 PM PDT 24
Finished May 26 01:01:41 PM PDT 24
Peak memory 215472 kb
Host smart-9f65bc9b-0d01-42b8-848e-be8fd6c26b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819629282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
819629282
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.243516826
Short name T992
Test name
Test status
Simulation time 45051594 ps
CPU time 0.81 seconds
Started May 26 01:01:39 PM PDT 24
Finished May 26 01:01:41 PM PDT 24
Peak memory 203584 kb
Host smart-286fd78d-c800-4d97-a7f2-d43ccabf5d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243516826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.243516826
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.852603415
Short name T115
Test name
Test status
Simulation time 23004671 ps
CPU time 2.04 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:43 PM PDT 24
Peak memory 215416 kb
Host smart-b178fade-6521-4eeb-ae89-e9b1f9e3d8b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852603415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.852603415
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2503379455
Short name T1015
Test name
Test status
Simulation time 12234709 ps
CPU time 0.72 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:42 PM PDT 24
Peak memory 203436 kb
Host smart-5af19fad-5e06-481c-83b7-b6ef554be0d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503379455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2503379455
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3307939591
Short name T994
Test name
Test status
Simulation time 28600560 ps
CPU time 1.89 seconds
Started May 26 01:01:36 PM PDT 24
Finished May 26 01:01:38 PM PDT 24
Peak memory 215376 kb
Host smart-945be953-0b10-4b9c-88e4-8f61493b4652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307939591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3307939591
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2970199048
Short name T1009
Test name
Test status
Simulation time 611675955 ps
CPU time 3.72 seconds
Started May 26 01:01:44 PM PDT 24
Finished May 26 01:01:48 PM PDT 24
Peak memory 215560 kb
Host smart-48272500-0116-4288-8f4f-a34a1aa103b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970199048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
970199048
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2428597161
Short name T1077
Test name
Test status
Simulation time 437925960 ps
CPU time 7.37 seconds
Started May 26 01:01:39 PM PDT 24
Finished May 26 01:01:47 PM PDT 24
Peak memory 215412 kb
Host smart-2e9b7c33-5b89-42ab-a9bb-e6f8fc48ebcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428597161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2428597161
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4157140656
Short name T1034
Test name
Test status
Simulation time 262115720 ps
CPU time 3.99 seconds
Started May 26 01:01:49 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 217912 kb
Host smart-49bc9262-d1c9-4745-b002-e4ee8c000e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157140656 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4157140656
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3247382385
Short name T1021
Test name
Test status
Simulation time 19782541 ps
CPU time 1.29 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 207188 kb
Host smart-fbed17b7-e2a4-4389-a642-e60181f82c1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247382385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3247382385
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1200662844
Short name T1028
Test name
Test status
Simulation time 21291870 ps
CPU time 0.8 seconds
Started May 26 01:01:51 PM PDT 24
Finished May 26 01:01:53 PM PDT 24
Peak memory 203620 kb
Host smart-965b4794-fd58-4b64-8354-f113387cd0ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200662844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1200662844
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1832420825
Short name T1076
Test name
Test status
Simulation time 474731707 ps
CPU time 3.2 seconds
Started May 26 01:01:52 PM PDT 24
Finished May 26 01:01:56 PM PDT 24
Peak memory 215416 kb
Host smart-9baac49b-274b-4676-b033-7239708395c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832420825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1832420825
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3610900572
Short name T1057
Test name
Test status
Simulation time 553118091 ps
CPU time 3.4 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:59 PM PDT 24
Peak memory 216944 kb
Host smart-5e34730b-127d-4886-bbde-ff8362b89a70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610900572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3610900572
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3706122478
Short name T1087
Test name
Test status
Simulation time 804986731 ps
CPU time 12.92 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:02:09 PM PDT 24
Peak memory 215368 kb
Host smart-c83b6d3a-3d97-4e68-b543-a78abc642488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706122478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3706122478
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1046459947
Short name T1019
Test name
Test status
Simulation time 31250340 ps
CPU time 1.8 seconds
Started May 26 01:01:51 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 215456 kb
Host smart-b0cb0de8-bb4c-4d3c-8546-9e8f73017ccc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046459947 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1046459947
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.79782136
Short name T1047
Test name
Test status
Simulation time 123790954 ps
CPU time 2.02 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:57 PM PDT 24
Peak memory 215648 kb
Host smart-a1a4c77e-7e9d-4351-b4fa-8e775b5bfe2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79782136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.79782136
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2197756446
Short name T977
Test name
Test status
Simulation time 14861992 ps
CPU time 0.83 seconds
Started May 26 01:01:52 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 203920 kb
Host smart-97086884-30fa-43c9-9eed-83303ea3c09a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197756446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2197756446
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1935782529
Short name T1029
Test name
Test status
Simulation time 82726244 ps
CPU time 2.54 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 216564 kb
Host smart-292f3d67-8ba3-4240-8d0f-79446c00757e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935782529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1935782529
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1255148759
Short name T107
Test name
Test status
Simulation time 56855057 ps
CPU time 3.82 seconds
Started May 26 01:01:56 PM PDT 24
Finished May 26 01:02:01 PM PDT 24
Peak memory 216512 kb
Host smart-bb12fd27-bbd5-4a1e-908a-cfd89a4c3278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255148759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1255148759
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.55260643
Short name T149
Test name
Test status
Simulation time 150668957 ps
CPU time 4.01 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:02:00 PM PDT 24
Peak memory 217168 kb
Host smart-69711b10-953b-4590-99a4-43a7af0be70b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55260643 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.55260643
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1561816120
Short name T1065
Test name
Test status
Simulation time 26011724 ps
CPU time 1.85 seconds
Started May 26 01:01:56 PM PDT 24
Finished May 26 01:01:59 PM PDT 24
Peak memory 215420 kb
Host smart-16ceadda-5a80-4326-ae53-f56039ee6e3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561816120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1561816120
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3035792174
Short name T1004
Test name
Test status
Simulation time 160418536 ps
CPU time 0.7 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 203928 kb
Host smart-f4e0bd5b-cdb3-409b-8a35-08888dea0f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035792174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3035792174
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3891583843
Short name T137
Test name
Test status
Simulation time 397332612 ps
CPU time 2.75 seconds
Started May 26 01:01:56 PM PDT 24
Finished May 26 01:02:00 PM PDT 24
Peak memory 215408 kb
Host smart-694f5eff-7f9e-4a1f-bf37-f97f8a8af10f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891583843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3891583843
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3871411104
Short name T1022
Test name
Test status
Simulation time 1089466033 ps
CPU time 3.25 seconds
Started May 26 01:01:50 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 215760 kb
Host smart-b37818b8-9f8b-472e-8eb8-27f20c1cd8ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871411104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3871411104
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3394143983
Short name T111
Test name
Test status
Simulation time 390069961 ps
CPU time 2.83 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 216660 kb
Host smart-a39e4584-0f50-4590-bc28-16f6d56b7da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394143983 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3394143983
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2740120299
Short name T1055
Test name
Test status
Simulation time 35547894 ps
CPU time 2.59 seconds
Started May 26 01:01:53 PM PDT 24
Finished May 26 01:01:58 PM PDT 24
Peak memory 215448 kb
Host smart-9dc2d41a-f936-4fca-bf07-a5e0b217c390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740120299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2740120299
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1597401404
Short name T982
Test name
Test status
Simulation time 14528971 ps
CPU time 0.73 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:57 PM PDT 24
Peak memory 203972 kb
Host smart-e2982300-5cd3-49bb-bbf7-c779296cfa88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597401404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1597401404
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4170811240
Short name T1092
Test name
Test status
Simulation time 384643321 ps
CPU time 2.06 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 215524 kb
Host smart-fdf5a206-d197-42be-b506-b38a21c87ad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170811240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4170811240
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3935519067
Short name T1017
Test name
Test status
Simulation time 59771800 ps
CPU time 3.56 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 215500 kb
Host smart-81cffaae-9448-464a-af93-76c0c484aa84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935519067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3935519067
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2047278696
Short name T113
Test name
Test status
Simulation time 1984486201 ps
CPU time 9.26 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 215276 kb
Host smart-18ab2b74-e989-4530-97f2-45c0922d02d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047278696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2047278696
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1161457627
Short name T1078
Test name
Test status
Simulation time 97611556 ps
CPU time 3.47 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 218024 kb
Host smart-1e873a0c-2c03-4006-9b67-97b75c586e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161457627 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1161457627
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4173101622
Short name T1013
Test name
Test status
Simulation time 208764590 ps
CPU time 2.67 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 215460 kb
Host smart-81c00aad-a507-4f25-a278-9b47c98ab5ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173101622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4173101622
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3153257804
Short name T976
Test name
Test status
Simulation time 37577008 ps
CPU time 0.72 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:01:57 PM PDT 24
Peak memory 203980 kb
Host smart-edf6bfd7-c1b0-4c70-be7b-ff6d5e3004cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153257804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3153257804
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2150046008
Short name T148
Test name
Test status
Simulation time 151813821 ps
CPU time 3.49 seconds
Started May 26 01:01:51 PM PDT 24
Finished May 26 01:01:55 PM PDT 24
Peak memory 215376 kb
Host smart-7460cb0d-1134-4bf1-a577-7792ca28baa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150046008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2150046008
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3101088344
Short name T101
Test name
Test status
Simulation time 156172780 ps
CPU time 2.34 seconds
Started May 26 01:01:51 PM PDT 24
Finished May 26 01:01:55 PM PDT 24
Peak memory 216584 kb
Host smart-0d8159b3-39e5-4dec-9486-4c24bdc69d97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101088344 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3101088344
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3023942967
Short name T997
Test name
Test status
Simulation time 46300219 ps
CPU time 1.41 seconds
Started May 26 01:01:50 PM PDT 24
Finished May 26 01:01:52 PM PDT 24
Peak memory 207192 kb
Host smart-c2a74a47-9ed1-4751-aabc-2251a7e57ba4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023942967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3023942967
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2312978818
Short name T974
Test name
Test status
Simulation time 59540029 ps
CPU time 0.75 seconds
Started May 26 01:01:51 PM PDT 24
Finished May 26 01:01:53 PM PDT 24
Peak memory 203920 kb
Host smart-1c3fc76d-9920-494e-b5b9-d987cfa8d58b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312978818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2312978818
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.687103911
Short name T1083
Test name
Test status
Simulation time 154395666 ps
CPU time 4.29 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 215424 kb
Host smart-5ddacbdc-2b1d-4a99-ba69-bd9b0b867015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687103911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.687103911
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.432178593
Short name T108
Test name
Test status
Simulation time 73785638 ps
CPU time 2.84 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:58 PM PDT 24
Peak memory 215480 kb
Host smart-30bd78c7-4dad-451b-b8ff-ddb28b254b62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432178593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.432178593
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2396337791
Short name T112
Test name
Test status
Simulation time 1738587000 ps
CPU time 21.53 seconds
Started May 26 01:01:53 PM PDT 24
Finished May 26 01:02:15 PM PDT 24
Peak memory 215460 kb
Host smart-bd495875-e98a-4aaf-aa17-f47b4eb42dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396337791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2396337791
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3386719169
Short name T1090
Test name
Test status
Simulation time 54077902 ps
CPU time 3.43 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:06 PM PDT 24
Peak memory 217884 kb
Host smart-29bcbf32-f436-4252-b1f7-eac47d71252e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386719169 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3386719169
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.191834652
Short name T1098
Test name
Test status
Simulation time 69702341 ps
CPU time 1.25 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 207232 kb
Host smart-5549f415-9bef-4a6f-b913-782e064da2e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191834652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.191834652
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1120989605
Short name T1014
Test name
Test status
Simulation time 101936735 ps
CPU time 0.7 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 203748 kb
Host smart-d5c5aee5-8046-4692-b24c-d3829ec41389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120989605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1120989605
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3641726145
Short name T1080
Test name
Test status
Simulation time 455369404 ps
CPU time 3.11 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:09 PM PDT 24
Peak memory 215524 kb
Host smart-c2b43a8a-388d-4abe-889d-96a15aa86614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641726145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3641726145
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2998396112
Short name T110
Test name
Test status
Simulation time 47912054 ps
CPU time 2.67 seconds
Started May 26 01:01:51 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 215652 kb
Host smart-b9e27c46-7eba-4110-8d95-68903a3dc74a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998396112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2998396112
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1535742393
Short name T146
Test name
Test status
Simulation time 736518459 ps
CPU time 16 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:02:13 PM PDT 24
Peak memory 215956 kb
Host smart-da8a338c-d9bf-4656-baa8-8e0207da4852
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535742393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1535742393
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3989873314
Short name T1093
Test name
Test status
Simulation time 1106086005 ps
CPU time 2.49 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:06 PM PDT 24
Peak memory 216720 kb
Host smart-33f0e339-a73e-46bf-a631-110c016f6815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989873314 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3989873314
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2656197064
Short name T1039
Test name
Test status
Simulation time 72861634 ps
CPU time 1.94 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:01 PM PDT 24
Peak memory 215452 kb
Host smart-4980ffde-5b76-491b-a08e-4ed2a0bd15f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656197064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2656197064
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3835028376
Short name T1006
Test name
Test status
Simulation time 34198655 ps
CPU time 0.72 seconds
Started May 26 01:02:02 PM PDT 24
Finished May 26 01:02:06 PM PDT 24
Peak memory 203616 kb
Host smart-1c03017d-7799-4784-b4f8-293222216f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835028376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3835028376
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.918906624
Short name T1024
Test name
Test status
Simulation time 178163356 ps
CPU time 3.83 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:11 PM PDT 24
Peak memory 215508 kb
Host smart-68bf731c-3323-4eac-8bd0-362298c60dca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918906624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.918906624
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1908643550
Short name T1030
Test name
Test status
Simulation time 263771620 ps
CPU time 2.45 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:09 PM PDT 24
Peak memory 215660 kb
Host smart-1696bde6-038d-4d01-8795-90ecdd6313a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908643550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1908643550
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.858942683
Short name T1031
Test name
Test status
Simulation time 968039952 ps
CPU time 7.12 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:11 PM PDT 24
Peak memory 215544 kb
Host smart-1f7a5eb6-6a8e-4c3a-b251-98f3f5b6589b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858942683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.858942683
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.197852550
Short name T1002
Test name
Test status
Simulation time 82327346 ps
CPU time 1.63 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:00 PM PDT 24
Peak memory 215568 kb
Host smart-0133cc05-61f6-49e8-b817-f9f6bcc6dc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197852550 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.197852550
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2369444187
Short name T1052
Test name
Test status
Simulation time 43360426 ps
CPU time 1.29 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 215392 kb
Host smart-4d0d38a4-e6b5-43fe-bd36-2d699a59d9e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369444187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2369444187
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.594361652
Short name T1095
Test name
Test status
Simulation time 13128896 ps
CPU time 0.75 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 203596 kb
Host smart-850f95ed-181c-4a64-b157-d6f4cf345eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594361652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.594361652
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2220329945
Short name T147
Test name
Test status
Simulation time 144704137 ps
CPU time 3.25 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 215436 kb
Host smart-db79c27d-17cc-4f12-8435-2c04ce2aca60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220329945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2220329945
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3936982117
Short name T272
Test name
Test status
Simulation time 2190123190 ps
CPU time 14.28 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:15 PM PDT 24
Peak memory 216216 kb
Host smart-acd92a69-fcb9-4b25-a8be-cb51722cc767
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936982117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3936982117
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1076918801
Short name T1099
Test name
Test status
Simulation time 201857138 ps
CPU time 2.73 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 216840 kb
Host smart-f7142d57-9bbe-4930-9e69-365ea4d98db7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076918801 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1076918801
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3507491762
Short name T1096
Test name
Test status
Simulation time 100764858 ps
CPU time 1.78 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:02:07 PM PDT 24
Peak memory 215432 kb
Host smart-6775586e-8658-44fe-b46b-9c62998ff539
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507491762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3507491762
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1928840275
Short name T1061
Test name
Test status
Simulation time 14967497 ps
CPU time 0.76 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:02:07 PM PDT 24
Peak memory 203648 kb
Host smart-1d6b3070-38b0-450c-8765-b0b9d3c30f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928840275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1928840275
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.190521134
Short name T1058
Test name
Test status
Simulation time 63666333 ps
CPU time 2.07 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 215404 kb
Host smart-1f3c58c7-0859-46cc-9167-70b19baea5d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190521134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.190521134
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3682896388
Short name T109
Test name
Test status
Simulation time 59989468 ps
CPU time 3.82 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:06 PM PDT 24
Peak memory 215368 kb
Host smart-3b594644-a435-4d1e-ad2a-6f1c62ebbea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682896388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3682896388
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4133340207
Short name T104
Test name
Test status
Simulation time 729972333 ps
CPU time 8.19 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:07 PM PDT 24
Peak memory 215740 kb
Host smart-9ee2d80b-e0c8-4101-be43-9380e9e5b21d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133340207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4133340207
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2577115823
Short name T1035
Test name
Test status
Simulation time 418842362 ps
CPU time 8.39 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:49 PM PDT 24
Peak memory 215452 kb
Host smart-673fe169-f5b2-4762-a2fb-d5a77515eb85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577115823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2577115823
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.266485852
Short name T1079
Test name
Test status
Simulation time 1956751480 ps
CPU time 37.7 seconds
Started May 26 01:01:36 PM PDT 24
Finished May 26 01:02:14 PM PDT 24
Peak memory 216576 kb
Host smart-ff294136-2eb6-45a0-a223-84dbe4e86f92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266485852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.266485852
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3350662165
Short name T122
Test name
Test status
Simulation time 144278944 ps
CPU time 1.5 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:43 PM PDT 24
Peak memory 207240 kb
Host smart-516e5986-e5c9-4ab4-a108-82e593043912
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350662165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3350662165
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.59910714
Short name T1084
Test name
Test status
Simulation time 473200259 ps
CPU time 3.57 seconds
Started May 26 01:01:37 PM PDT 24
Finished May 26 01:01:41 PM PDT 24
Peak memory 216500 kb
Host smart-b9d733c9-510c-4e9d-ac3a-f86f4cd12dbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59910714 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.59910714
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2235891124
Short name T114
Test name
Test status
Simulation time 143044036 ps
CPU time 2.42 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:43 PM PDT 24
Peak memory 207152 kb
Host smart-c85c06f7-d228-46a4-b9dc-1cd21ef3e383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235891124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
235891124
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.842091085
Short name T988
Test name
Test status
Simulation time 32142042 ps
CPU time 0.81 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:42 PM PDT 24
Peak memory 203916 kb
Host smart-d781cd72-6485-4e10-93a0-0f9b8ca9faf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842091085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.842091085
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2061589442
Short name T1075
Test name
Test status
Simulation time 222250696 ps
CPU time 2.04 seconds
Started May 26 01:01:39 PM PDT 24
Finished May 26 01:01:42 PM PDT 24
Peak memory 215548 kb
Host smart-62556f30-2ca8-4386-a27c-f36aeefcadd5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061589442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2061589442
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1324996055
Short name T1069
Test name
Test status
Simulation time 10910503 ps
CPU time 0.66 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:42 PM PDT 24
Peak memory 203928 kb
Host smart-599ddb82-56a3-4541-811e-c371835822e0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324996055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1324996055
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2993158359
Short name T1097
Test name
Test status
Simulation time 48251617 ps
CPU time 2.68 seconds
Started May 26 01:01:37 PM PDT 24
Finished May 26 01:01:40 PM PDT 24
Peak memory 215396 kb
Host smart-1e8265f9-184e-4a2b-aee9-e46843dec156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993158359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2993158359
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1307104442
Short name T1070
Test name
Test status
Simulation time 36298580 ps
CPU time 2.25 seconds
Started May 26 01:01:46 PM PDT 24
Finished May 26 01:01:49 PM PDT 24
Peak memory 215640 kb
Host smart-bdafef3f-e999-410f-9089-766a7c6e90ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307104442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
307104442
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2929537817
Short name T168
Test name
Test status
Simulation time 659010410 ps
CPU time 15.78 seconds
Started May 26 01:01:38 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 223592 kb
Host smart-2978fb61-8107-44c1-a3af-0e955d454701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929537817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2929537817
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1740068112
Short name T979
Test name
Test status
Simulation time 111057656 ps
CPU time 0.74 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 203664 kb
Host smart-b50e0499-1bfa-4724-b6aa-5b8bb944af8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740068112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1740068112
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2471766388
Short name T985
Test name
Test status
Simulation time 25330077 ps
CPU time 0.72 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 203712 kb
Host smart-e273cb93-3f9f-422b-8587-cb564e24d161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471766388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2471766388
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3562421822
Short name T1064
Test name
Test status
Simulation time 13330364 ps
CPU time 0.71 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 203588 kb
Host smart-8c0cd34e-9554-4c4b-95d3-eb7898a678be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562421822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3562421822
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2903443078
Short name T981
Test name
Test status
Simulation time 45939014 ps
CPU time 0.74 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:09 PM PDT 24
Peak memory 203580 kb
Host smart-cd9bda3c-de42-4718-8e47-2fe53180f915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903443078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2903443078
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4230420262
Short name T1066
Test name
Test status
Simulation time 15003050 ps
CPU time 0.68 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:09 PM PDT 24
Peak memory 203604 kb
Host smart-bd6599b9-e694-4de7-bd34-6c39145b1908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230420262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4230420262
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3483424126
Short name T1067
Test name
Test status
Simulation time 36214008 ps
CPU time 0.7 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:01:59 PM PDT 24
Peak memory 203592 kb
Host smart-1426f561-905d-4032-8284-36984636e11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483424126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3483424126
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.151977602
Short name T1018
Test name
Test status
Simulation time 33049067 ps
CPU time 0.72 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 203516 kb
Host smart-fde09cd6-b985-48f7-8159-f6cdf5a8d9a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151977602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.151977602
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.502819125
Short name T1027
Test name
Test status
Simulation time 27249748 ps
CPU time 0.79 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 203664 kb
Host smart-c1141a64-c61f-4596-bade-b821ef68bb1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502819125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.502819125
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.844349774
Short name T991
Test name
Test status
Simulation time 54327691 ps
CPU time 0.73 seconds
Started May 26 01:02:02 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 203868 kb
Host smart-b5ab7fed-af70-4d31-9f21-75d24947143a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844349774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.844349774
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3517574355
Short name T980
Test name
Test status
Simulation time 16044098 ps
CPU time 0.71 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:02:07 PM PDT 24
Peak memory 203480 kb
Host smart-ff2bd7f1-c3e7-46cc-b637-52778e8c0aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517574355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3517574355
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1454051785
Short name T1081
Test name
Test status
Simulation time 321090299 ps
CPU time 8.06 seconds
Started May 26 01:01:38 PM PDT 24
Finished May 26 01:01:47 PM PDT 24
Peak memory 207368 kb
Host smart-6f08c2c2-eb86-4250-b082-850d881563f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454051785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1454051785
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4161327061
Short name T1086
Test name
Test status
Simulation time 4556723567 ps
CPU time 13.36 seconds
Started May 26 01:01:37 PM PDT 24
Finished May 26 01:01:51 PM PDT 24
Peak memory 215456 kb
Host smart-f6191f14-56e4-4f52-8b13-5e51e90089bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161327061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4161327061
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2527585842
Short name T88
Test name
Test status
Simulation time 117858278 ps
CPU time 1.19 seconds
Started May 26 01:01:38 PM PDT 24
Finished May 26 01:01:40 PM PDT 24
Peak memory 207492 kb
Host smart-061356d2-6082-42e7-851a-2f9a4d3710ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527585842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2527585842
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4240388318
Short name T1038
Test name
Test status
Simulation time 187318273 ps
CPU time 3.46 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 217740 kb
Host smart-22c46343-3f59-4373-bc57-4b7326007df4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240388318 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4240388318
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1365430171
Short name T139
Test name
Test status
Simulation time 92649459 ps
CPU time 1.74 seconds
Started May 26 01:01:44 PM PDT 24
Finished May 26 01:01:46 PM PDT 24
Peak memory 207112 kb
Host smart-d832d931-3c08-4f91-9097-2fff766af518
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365430171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
365430171
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1277277580
Short name T1026
Test name
Test status
Simulation time 23785445 ps
CPU time 0.71 seconds
Started May 26 01:01:35 PM PDT 24
Finished May 26 01:01:37 PM PDT 24
Peak memory 203584 kb
Host smart-77468abf-3a44-4de9-b57f-de0620b0e024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277277580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
277277580
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.727859028
Short name T117
Test name
Test status
Simulation time 182516972 ps
CPU time 1.46 seconds
Started May 26 01:01:39 PM PDT 24
Finished May 26 01:01:41 PM PDT 24
Peak memory 215392 kb
Host smart-c2e2684a-409e-4b45-b385-390bcf71fe35
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727859028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.727859028
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2580439450
Short name T987
Test name
Test status
Simulation time 17763411 ps
CPU time 0.72 seconds
Started May 26 01:01:40 PM PDT 24
Finished May 26 01:01:42 PM PDT 24
Peak memory 203512 kb
Host smart-596728bb-8f65-4b4e-81bc-acf9e9460c52
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580439450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2580439450
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.778567950
Short name T1036
Test name
Test status
Simulation time 214051320 ps
CPU time 3.17 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 215384 kb
Host smart-bbc1511a-5341-4c4a-a054-98490e1d3475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778567950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.778567950
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.40260047
Short name T106
Test name
Test status
Simulation time 114223549 ps
CPU time 2.2 seconds
Started May 26 01:01:39 PM PDT 24
Finished May 26 01:01:42 PM PDT 24
Peak memory 215504 kb
Host smart-3a99f72f-bd1c-4523-b2ac-8fb423782c35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40260047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.40260047
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.42598282
Short name T1071
Test name
Test status
Simulation time 2075961501 ps
CPU time 24.18 seconds
Started May 26 01:01:37 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 215496 kb
Host smart-c5bf050a-9424-456c-a454-cb66b7f35ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42598282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_t
l_intg_err.42598282
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1990870838
Short name T1008
Test name
Test status
Simulation time 59639980 ps
CPU time 0.72 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 203708 kb
Host smart-ed2dc297-1440-4c43-9b5f-f0951d0197fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990870838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1990870838
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2169474342
Short name T1005
Test name
Test status
Simulation time 105944587 ps
CPU time 0.72 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:02:06 PM PDT 24
Peak memory 203604 kb
Host smart-7b30a2ce-0b57-4cd0-9b1a-c6868161a173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169474342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2169474342
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1679157546
Short name T1003
Test name
Test status
Simulation time 45067208 ps
CPU time 0.81 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 203668 kb
Host smart-4f3b9e81-bf50-4302-8035-9713f282257d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679157546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1679157546
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2479345728
Short name T1023
Test name
Test status
Simulation time 15020547 ps
CPU time 0.78 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:08 PM PDT 24
Peak memory 203908 kb
Host smart-22aae60b-4ede-4ffb-8aca-322621d59538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479345728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2479345728
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2035539719
Short name T1025
Test name
Test status
Simulation time 10526699 ps
CPU time 0.68 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 203932 kb
Host smart-f15f9b5a-0165-4387-b97b-9ffe12a2adab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035539719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2035539719
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3597544836
Short name T1100
Test name
Test status
Simulation time 12960702 ps
CPU time 0.68 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 203640 kb
Host smart-c4ca4e23-e455-4e2c-8b73-a37991c53b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597544836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3597544836
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2550829271
Short name T1089
Test name
Test status
Simulation time 52260494 ps
CPU time 0.76 seconds
Started May 26 01:02:02 PM PDT 24
Finished May 26 01:02:06 PM PDT 24
Peak memory 203664 kb
Host smart-caeae25b-997e-4528-8f1d-17d19ed3da66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550829271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2550829271
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3377629035
Short name T1001
Test name
Test status
Simulation time 41381250 ps
CPU time 0.79 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 203608 kb
Host smart-bef366b7-fe76-433d-8f2b-7c0ee0c74d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377629035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3377629035
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3511744482
Short name T1060
Test name
Test status
Simulation time 143039392 ps
CPU time 0.71 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:02:07 PM PDT 24
Peak memory 203532 kb
Host smart-0891931e-c864-4554-87d7-e3bedfcfc914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511744482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3511744482
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2242220165
Short name T1051
Test name
Test status
Simulation time 86377491 ps
CPU time 0.69 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 204020 kb
Host smart-c4951b76-9884-40ed-bafc-9494b59d8aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242220165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2242220165
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2673716945
Short name T124
Test name
Test status
Simulation time 918732040 ps
CPU time 15.07 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:02:11 PM PDT 24
Peak memory 215408 kb
Host smart-a95ace11-84cf-428c-8524-31d9d38fe0bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673716945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2673716945
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.183697084
Short name T1072
Test name
Test status
Simulation time 4591772841 ps
CPU time 26.49 seconds
Started May 26 01:01:53 PM PDT 24
Finished May 26 01:02:20 PM PDT 24
Peak memory 207288 kb
Host smart-62e4e1d8-6614-4908-a3fa-6fe255a2f675
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183697084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.183697084
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3989133238
Short name T1063
Test name
Test status
Simulation time 67709131 ps
CPU time 1.14 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:01 PM PDT 24
Peak memory 207112 kb
Host smart-85cade08-cfb3-45e7-be51-e7fe61a09aa5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989133238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3989133238
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2896279246
Short name T1046
Test name
Test status
Simulation time 176089341 ps
CPU time 4.04 seconds
Started May 26 01:01:48 PM PDT 24
Finished May 26 01:01:52 PM PDT 24
Peak memory 217064 kb
Host smart-d0adda96-a6d7-43b8-aa94-57cacaa98377
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896279246 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2896279246
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1248429320
Short name T975
Test name
Test status
Simulation time 25120946 ps
CPU time 0.77 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:01 PM PDT 24
Peak memory 203988 kb
Host smart-d5b38179-bd13-44bb-996b-74caa67a9aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248429320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
248429320
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2226586522
Short name T119
Test name
Test status
Simulation time 51283683 ps
CPU time 1.73 seconds
Started May 26 01:01:50 PM PDT 24
Finished May 26 01:01:52 PM PDT 24
Peak memory 215540 kb
Host smart-844adbc6-9bd5-4a41-8e31-d248c89c6fc5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226586522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2226586522
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3370356472
Short name T999
Test name
Test status
Simulation time 21939414 ps
CPU time 0.67 seconds
Started May 26 01:01:48 PM PDT 24
Finished May 26 01:01:49 PM PDT 24
Peak memory 203556 kb
Host smart-82b4dccb-9d26-4eb9-a638-6e19808a6b7a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370356472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3370356472
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1646597586
Short name T1011
Test name
Test status
Simulation time 171189828 ps
CPU time 2.68 seconds
Started May 26 01:01:47 PM PDT 24
Finished May 26 01:01:51 PM PDT 24
Peak memory 215404 kb
Host smart-1a4b5ff9-563b-4129-a862-ee03086a0951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646597586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1646597586
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.538110318
Short name T1082
Test name
Test status
Simulation time 1504269272 ps
CPU time 16.01 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:15 PM PDT 24
Peak memory 215712 kb
Host smart-fa0cccae-f883-4f68-8afd-26c71619d0d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538110318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.538110318
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2457744200
Short name T1091
Test name
Test status
Simulation time 33189070 ps
CPU time 0.76 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 203664 kb
Host smart-ee50bf96-0baf-494e-8529-f28d7b20e89c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457744200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2457744200
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1484348488
Short name T984
Test name
Test status
Simulation time 15818393 ps
CPU time 0.73 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:01 PM PDT 24
Peak memory 203888 kb
Host smart-44f7a225-20ec-4bc9-93fa-396f4b496c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484348488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1484348488
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2416523559
Short name T1016
Test name
Test status
Simulation time 29242847 ps
CPU time 0.76 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 203616 kb
Host smart-000f68f2-a81c-4230-b86d-b63770f411ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416523559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2416523559
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2665968152
Short name T1085
Test name
Test status
Simulation time 14422386 ps
CPU time 0.78 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 203588 kb
Host smart-212bcaac-0236-40ff-8687-90555935ecaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665968152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2665968152
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2633289261
Short name T1043
Test name
Test status
Simulation time 14801694 ps
CPU time 0.78 seconds
Started May 26 01:01:56 PM PDT 24
Finished May 26 01:01:58 PM PDT 24
Peak memory 203712 kb
Host smart-5881285b-792f-4db3-8f58-f51085c7a0f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633289261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2633289261
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3207508134
Short name T1007
Test name
Test status
Simulation time 19057461 ps
CPU time 0.72 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:01:59 PM PDT 24
Peak memory 203884 kb
Host smart-e58e5b05-4a9b-4c1d-bc7c-45e21c7ee0eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207508134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3207508134
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2157866169
Short name T983
Test name
Test status
Simulation time 15156944 ps
CPU time 0.74 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:08 PM PDT 24
Peak memory 203672 kb
Host smart-94070a58-3724-409c-b67d-a9d9768631e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157866169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2157866169
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3368443084
Short name T1094
Test name
Test status
Simulation time 17793292 ps
CPU time 0.74 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 203756 kb
Host smart-81f96fb2-da65-4001-888b-f416dc9b2ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368443084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3368443084
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3291286807
Short name T986
Test name
Test status
Simulation time 34604383 ps
CPU time 0.77 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:01 PM PDT 24
Peak memory 203664 kb
Host smart-7653efeb-ebf3-416c-9707-6ea35b3736bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291286807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3291286807
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3788400262
Short name T973
Test name
Test status
Simulation time 63521826 ps
CPU time 0.8 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:08 PM PDT 24
Peak memory 203596 kb
Host smart-19060016-73ef-4242-b47c-cf1eed0696ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788400262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3788400262
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.229072633
Short name T1032
Test name
Test status
Simulation time 142322874 ps
CPU time 3.61 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:59 PM PDT 24
Peak memory 217992 kb
Host smart-ed369f78-c1a4-4a6d-974c-7ce97735a400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229072633 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.229072633
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.758443482
Short name T1062
Test name
Test status
Simulation time 143448709 ps
CPU time 2.15 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:58 PM PDT 24
Peak memory 215532 kb
Host smart-20bea420-2481-404a-96a6-d185a670ad39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758443482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.758443482
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3429955308
Short name T1040
Test name
Test status
Simulation time 16100770 ps
CPU time 0.75 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:01:57 PM PDT 24
Peak memory 203868 kb
Host smart-baafe594-d076-4f2d-9d5e-e2382e04547f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429955308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
429955308
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3679430904
Short name T1101
Test name
Test status
Simulation time 109424021 ps
CPU time 4.03 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:59 PM PDT 24
Peak memory 215376 kb
Host smart-50d83866-839e-425c-ada4-d01bd2c60b9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679430904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3679430904
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.409604720
Short name T1049
Test name
Test status
Simulation time 360955103 ps
CPU time 4.67 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:02:00 PM PDT 24
Peak memory 216504 kb
Host smart-c4ad3add-273f-4994-8c9a-72a428d92f48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409604720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.409604720
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1722800266
Short name T1088
Test name
Test status
Simulation time 3788475418 ps
CPU time 23.24 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:02:20 PM PDT 24
Peak memory 215476 kb
Host smart-d5457827-5783-4b19-8d6d-ee62762aee90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722800266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1722800266
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.929346462
Short name T1074
Test name
Test status
Simulation time 729205164 ps
CPU time 3.78 seconds
Started May 26 01:01:50 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 217340 kb
Host smart-41e83479-deaf-4f9e-8aa5-023700ceb79d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929346462 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.929346462
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3126610985
Short name T136
Test name
Test status
Simulation time 42690294 ps
CPU time 1.48 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:57 PM PDT 24
Peak memory 215352 kb
Host smart-ac8fcb5d-8a7a-4713-b079-9ef96bc8cb5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126610985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
126610985
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3572639540
Short name T978
Test name
Test status
Simulation time 59080879 ps
CPU time 0.78 seconds
Started May 26 01:01:56 PM PDT 24
Finished May 26 01:01:58 PM PDT 24
Peak memory 203640 kb
Host smart-dc170f40-df81-4b81-9689-c8f76795682d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572639540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
572639540
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.31582803
Short name T1068
Test name
Test status
Simulation time 229711052 ps
CPU time 1.75 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:02:08 PM PDT 24
Peak memory 215268 kb
Host smart-efdc41aa-bd81-4ff5-98b0-dad0e668b5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi
_device_same_csr_outstanding.31582803
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1976962841
Short name T1020
Test name
Test status
Simulation time 96034894 ps
CPU time 2.66 seconds
Started May 26 01:01:56 PM PDT 24
Finished May 26 01:02:00 PM PDT 24
Peak memory 215592 kb
Host smart-0c289024-e55d-4573-a512-c1debac3342c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976962841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
976962841
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2667989361
Short name T166
Test name
Test status
Simulation time 218736593 ps
CPU time 6.89 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:02:03 PM PDT 24
Peak memory 215384 kb
Host smart-1d4a6c46-13a0-48f2-be75-ca3d1d771077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667989361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2667989361
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.891978916
Short name T1000
Test name
Test status
Simulation time 88340860 ps
CPU time 1.81 seconds
Started May 26 01:01:53 PM PDT 24
Finished May 26 01:01:57 PM PDT 24
Peak memory 216568 kb
Host smart-d697df3b-9605-4110-bb07-5f0b36984e15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891978916 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.891978916
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.379524627
Short name T121
Test name
Test status
Simulation time 784758856 ps
CPU time 2.53 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:02:08 PM PDT 24
Peak memory 215552 kb
Host smart-10115536-58e9-4179-b71a-2cd18e138f06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379524627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.379524627
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1241554277
Short name T998
Test name
Test status
Simulation time 42020247 ps
CPU time 0.72 seconds
Started May 26 01:01:56 PM PDT 24
Finished May 26 01:01:58 PM PDT 24
Peak memory 203568 kb
Host smart-503ff48d-f15f-4f78-b4b9-b17985149e6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241554277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
241554277
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1270864992
Short name T995
Test name
Test status
Simulation time 301506766 ps
CPU time 3.84 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:02:00 PM PDT 24
Peak memory 215384 kb
Host smart-b5b1b1d3-b2e0-4fa3-8fab-365f7d34be1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270864992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1270864992
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3270968657
Short name T102
Test name
Test status
Simulation time 302590618 ps
CPU time 4.16 seconds
Started May 26 01:01:55 PM PDT 24
Finished May 26 01:02:00 PM PDT 24
Peak memory 215608 kb
Host smart-8a28e4f8-72c9-4b8d-b514-a5e8b9b41700
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270968657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
270968657
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.69149291
Short name T271
Test name
Test status
Simulation time 1369264779 ps
CPU time 19.11 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:18 PM PDT 24
Peak memory 215372 kb
Host smart-5fb755b0-60e4-46ab-ad45-3bb24d50fca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69149291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_t
l_intg_err.69149291
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2950139909
Short name T1044
Test name
Test status
Simulation time 123117331 ps
CPU time 2.7 seconds
Started May 26 01:01:52 PM PDT 24
Finished May 26 01:01:56 PM PDT 24
Peak memory 216532 kb
Host smart-99c460db-d152-48e3-b485-90967043e7b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950139909 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2950139909
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.633747515
Short name T1010
Test name
Test status
Simulation time 328131951 ps
CPU time 1.81 seconds
Started May 26 01:01:47 PM PDT 24
Finished May 26 01:01:49 PM PDT 24
Peak memory 207176 kb
Host smart-4b3952c7-c2b1-438a-8128-42055c0f9f9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633747515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.633747515
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1377730899
Short name T1054
Test name
Test status
Simulation time 76634073 ps
CPU time 0.69 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:01 PM PDT 24
Peak memory 203876 kb
Host smart-ddfa4220-47fd-42eb-b532-ee437bf3a8fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377730899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
377730899
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4152227835
Short name T1012
Test name
Test status
Simulation time 26164971 ps
CPU time 1.78 seconds
Started May 26 01:01:48 PM PDT 24
Finished May 26 01:01:50 PM PDT 24
Peak memory 215504 kb
Host smart-dd2d9b71-d78c-4077-b671-44bb4058e082
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152227835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4152227835
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3966959312
Short name T996
Test name
Test status
Simulation time 135090436 ps
CPU time 1.95 seconds
Started May 26 01:01:51 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 215404 kb
Host smart-1598a3ca-1118-466f-b362-63241675045b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966959312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
966959312
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.610433707
Short name T167
Test name
Test status
Simulation time 2586097929 ps
CPU time 15.6 seconds
Started May 26 01:01:48 PM PDT 24
Finished May 26 01:02:05 PM PDT 24
Peak memory 215720 kb
Host smart-d6410e19-c3f9-4a8f-99d1-2b9efcb76a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610433707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.610433707
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3499753384
Short name T989
Test name
Test status
Simulation time 83013077 ps
CPU time 2.87 seconds
Started May 26 01:01:51 PM PDT 24
Finished May 26 01:01:54 PM PDT 24
Peak memory 217288 kb
Host smart-6feda76b-89a6-4bdd-8f50-6a4bc6775090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499753384 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3499753384
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2326159990
Short name T116
Test name
Test status
Simulation time 39709413 ps
CPU time 1.87 seconds
Started May 26 01:01:57 PM PDT 24
Finished May 26 01:02:01 PM PDT 24
Peak memory 215476 kb
Host smart-9befa04f-aa36-4134-a035-6349b7bef233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326159990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
326159990
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1601737168
Short name T1037
Test name
Test status
Simulation time 11810223 ps
CPU time 0.71 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:57 PM PDT 24
Peak memory 203732 kb
Host smart-40bc5d40-bde5-4376-8d7a-3d474bcd41da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601737168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
601737168
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1208939455
Short name T993
Test name
Test status
Simulation time 226903556 ps
CPU time 1.93 seconds
Started May 26 01:01:52 PM PDT 24
Finished May 26 01:01:55 PM PDT 24
Peak memory 215416 kb
Host smart-32ec2637-5c1a-4380-ac68-6af954378113
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208939455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1208939455
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.281987845
Short name T1073
Test name
Test status
Simulation time 60220205 ps
CPU time 4.03 seconds
Started May 26 01:01:54 PM PDT 24
Finished May 26 01:01:59 PM PDT 24
Peak memory 215568 kb
Host smart-cd6cec3c-c79d-4470-9d7e-043f57e08633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281987845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.281987845
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1186559546
Short name T99
Test name
Test status
Simulation time 1571714355 ps
CPU time 13.81 seconds
Started May 26 01:01:48 PM PDT 24
Finished May 26 01:02:02 PM PDT 24
Peak memory 215368 kb
Host smart-7078195b-a53f-4b74-8df9-70f97832c867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186559546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1186559546
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4077061880
Short name T353
Test name
Test status
Simulation time 83876564 ps
CPU time 0.77 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:08 PM PDT 24
Peak memory 205284 kb
Host smart-0be12f2c-3d79-475e-970a-186b33bcb3f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077061880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
077061880
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2088132849
Short name T196
Test name
Test status
Simulation time 6381180974 ps
CPU time 13.95 seconds
Started May 26 02:38:58 PM PDT 24
Finished May 26 02:39:13 PM PDT 24
Peak memory 233624 kb
Host smart-fafe9c92-40f9-49fa-ac2c-8407217093cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088132849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2088132849
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2308523116
Short name T929
Test name
Test status
Simulation time 30161291 ps
CPU time 0.72 seconds
Started May 26 02:38:57 PM PDT 24
Finished May 26 02:38:58 PM PDT 24
Peak memory 205260 kb
Host smart-4e2a411a-90ef-4749-94f0-50e4ec9c7a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308523116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2308523116
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1204295493
Short name T607
Test name
Test status
Simulation time 32964216825 ps
CPU time 61.03 seconds
Started May 26 02:39:00 PM PDT 24
Finished May 26 02:40:02 PM PDT 24
Peak memory 249652 kb
Host smart-127ff72b-bd36-4d16-b496-40a1c0668878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204295493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1204295493
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.873469466
Short name T650
Test name
Test status
Simulation time 3057238964 ps
CPU time 58.44 seconds
Started May 26 02:38:58 PM PDT 24
Finished May 26 02:39:57 PM PDT 24
Peak memory 255104 kb
Host smart-02cc8809-ff0b-48e3-894e-b57960651b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873469466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.873469466
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.315169240
Short name T379
Test name
Test status
Simulation time 749153144 ps
CPU time 6.17 seconds
Started May 26 02:38:59 PM PDT 24
Finished May 26 02:39:06 PM PDT 24
Peak memory 240356 kb
Host smart-b681d993-c60e-4317-b37f-34ea7cdf4a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315169240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.315169240
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.354317230
Short name T959
Test name
Test status
Simulation time 4318783638 ps
CPU time 11.62 seconds
Started May 26 02:39:00 PM PDT 24
Finished May 26 02:39:12 PM PDT 24
Peak memory 233616 kb
Host smart-86b3cdca-0aa1-44f1-90bb-a4515422bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354317230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.354317230
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4128735738
Short name T800
Test name
Test status
Simulation time 1585304743 ps
CPU time 8.98 seconds
Started May 26 02:39:00 PM PDT 24
Finished May 26 02:39:10 PM PDT 24
Peak memory 218120 kb
Host smart-a5c446ab-ed6a-4e2a-bbe7-a0e386a1e575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128735738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4128735738
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3842866890
Short name T870
Test name
Test status
Simulation time 90132669 ps
CPU time 1.11 seconds
Started May 26 02:38:58 PM PDT 24
Finished May 26 02:39:00 PM PDT 24
Peak memory 216220 kb
Host smart-8c6e137a-5208-4ce8-a8cb-7c9f8f02073f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842866890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3842866890
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.834104321
Short name T631
Test name
Test status
Simulation time 451826967 ps
CPU time 2.75 seconds
Started May 26 02:38:58 PM PDT 24
Finished May 26 02:39:02 PM PDT 24
Peak memory 234480 kb
Host smart-da58c5df-5926-4ed2-b3f8-6f7181083693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834104321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
834104321
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2148638629
Short name T846
Test name
Test status
Simulation time 169449871 ps
CPU time 2.58 seconds
Started May 26 02:38:58 PM PDT 24
Finished May 26 02:39:02 PM PDT 24
Peak memory 218164 kb
Host smart-2f53aa8a-f341-4c68-9c36-3f7145c8f4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148638629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2148638629
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1347770103
Short name T765
Test name
Test status
Simulation time 4873658857 ps
CPU time 11.07 seconds
Started May 26 02:38:57 PM PDT 24
Finished May 26 02:39:10 PM PDT 24
Peak memory 218888 kb
Host smart-731a890b-2bc5-4fcf-b9e3-af61d8e300ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1347770103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1347770103
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.851360796
Short name T77
Test name
Test status
Simulation time 46941704 ps
CPU time 0.97 seconds
Started May 26 02:39:05 PM PDT 24
Finished May 26 02:39:07 PM PDT 24
Peak memory 234700 kb
Host smart-7feda229-af3d-4ac4-8362-763427c63626
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851360796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.851360796
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3119419417
Short name T822
Test name
Test status
Simulation time 1609500508 ps
CPU time 22.56 seconds
Started May 26 02:38:59 PM PDT 24
Finished May 26 02:39:23 PM PDT 24
Peak memory 218572 kb
Host smart-d95732f9-c605-48f7-ab52-eeae1e5257fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119419417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3119419417
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.291449349
Short name T737
Test name
Test status
Simulation time 8183186046 ps
CPU time 13.41 seconds
Started May 26 02:38:57 PM PDT 24
Finished May 26 02:39:12 PM PDT 24
Peak memory 215944 kb
Host smart-5f042ce1-6ddc-43c5-b9e3-79aca88e7166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291449349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.291449349
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1328544338
Short name T560
Test name
Test status
Simulation time 186060670 ps
CPU time 2.8 seconds
Started May 26 02:38:57 PM PDT 24
Finished May 26 02:39:01 PM PDT 24
Peak memory 215916 kb
Host smart-ad57bb5b-2004-4d14-b2f8-3f599e6b2e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328544338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1328544338
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.42679094
Short name T372
Test name
Test status
Simulation time 119026478 ps
CPU time 0.84 seconds
Started May 26 02:38:59 PM PDT 24
Finished May 26 02:39:01 PM PDT 24
Peak memory 205324 kb
Host smart-258a5ed4-eefe-4210-a255-cd45859e1e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42679094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.42679094
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3375715556
Short name T8
Test name
Test status
Simulation time 24269018440 ps
CPU time 12.6 seconds
Started May 26 02:38:58 PM PDT 24
Finished May 26 02:39:11 PM PDT 24
Peak memory 217140 kb
Host smart-673451eb-8c8f-4b91-b3a9-94e1cb3fab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375715556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3375715556
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4116138073
Short name T462
Test name
Test status
Simulation time 31612289 ps
CPU time 0.69 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 204872 kb
Host smart-8a496e95-219a-4b55-a37f-6692b7ee4746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116138073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
116138073
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4264017917
Short name T826
Test name
Test status
Simulation time 379234769 ps
CPU time 4.87 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:39:13 PM PDT 24
Peak memory 220160 kb
Host smart-6c4175b9-c8c5-4fd6-8da7-b276ed94ef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264017917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4264017917
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.494361928
Short name T430
Test name
Test status
Simulation time 93762188 ps
CPU time 0.79 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 205944 kb
Host smart-7f20fed8-32d3-48ce-8640-875280d73d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494361928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.494361928
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3488078030
Short name T920
Test name
Test status
Simulation time 13109341712 ps
CPU time 18.38 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 234048 kb
Host smart-a08729a3-3c43-41c0-9191-246b3acefae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488078030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3488078030
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.643972756
Short name T2
Test name
Test status
Simulation time 7457797079 ps
CPU time 78.26 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:40:27 PM PDT 24
Peak memory 256672 kb
Host smart-6ffa90a6-f960-453b-a889-5bf0773598b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643972756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.643972756
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1596750365
Short name T788
Test name
Test status
Simulation time 16659099142 ps
CPU time 25.55 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:34 PM PDT 24
Peak memory 248940 kb
Host smart-0ba2934c-61b5-4ae7-9e85-7857bfba23ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596750365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1596750365
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3197726296
Short name T595
Test name
Test status
Simulation time 168021204 ps
CPU time 2.91 seconds
Started May 26 02:39:04 PM PDT 24
Finished May 26 02:39:08 PM PDT 24
Peak memory 232388 kb
Host smart-512e1d23-e832-464c-84cc-2a818d34430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197726296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3197726296
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3566366328
Short name T667
Test name
Test status
Simulation time 503503943 ps
CPU time 3.6 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:11 PM PDT 24
Peak memory 233212 kb
Host smart-dd559b03-89a5-4e11-860b-098eb83fc65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566366328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3566366328
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.553785315
Short name T966
Test name
Test status
Simulation time 583310610 ps
CPU time 7.09 seconds
Started May 26 02:39:05 PM PDT 24
Finished May 26 02:39:14 PM PDT 24
Peak memory 229744 kb
Host smart-6a4eda77-88ed-49e8-9740-c6772f06ac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553785315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.553785315
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.99491992
Short name T680
Test name
Test status
Simulation time 32458469 ps
CPU time 1.06 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 217504 kb
Host smart-6c46eaeb-589e-4c30-a67d-a385ef8689e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99491992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.99491992
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3972770171
Short name T222
Test name
Test status
Simulation time 24882918098 ps
CPU time 18.42 seconds
Started May 26 02:39:04 PM PDT 24
Finished May 26 02:39:23 PM PDT 24
Peak memory 227288 kb
Host smart-6f62d0bd-6773-406f-b00a-8959964cdf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972770171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3972770171
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1691761972
Short name T540
Test name
Test status
Simulation time 2138458850 ps
CPU time 11.18 seconds
Started May 26 02:39:09 PM PDT 24
Finished May 26 02:39:21 PM PDT 24
Peak memory 233468 kb
Host smart-ca169b84-1bba-4c14-999f-2d455d0454ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691761972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1691761972
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3040227972
Short name T349
Test name
Test status
Simulation time 328244217 ps
CPU time 3.2 seconds
Started May 26 02:39:10 PM PDT 24
Finished May 26 02:39:13 PM PDT 24
Peak memory 218816 kb
Host smart-a597fb9b-905d-434c-88d8-6c5bbd8da41b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3040227972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3040227972
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.821140382
Short name T75
Test name
Test status
Simulation time 161489198 ps
CPU time 0.95 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 234656 kb
Host smart-35a8ec84-ca9e-4251-9d56-6568e5ddc575
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821140382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.821140382
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4110105656
Short name T780
Test name
Test status
Simulation time 106960246684 ps
CPU time 303.91 seconds
Started May 26 02:39:05 PM PDT 24
Finished May 26 02:44:10 PM PDT 24
Peak memory 268100 kb
Host smart-fc0d7f88-817e-4d92-8429-7f9f51c33344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110105656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4110105656
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.433468460
Short name T895
Test name
Test status
Simulation time 10591850793 ps
CPU time 9.73 seconds
Started May 26 02:39:08 PM PDT 24
Finished May 26 02:39:19 PM PDT 24
Peak memory 215876 kb
Host smart-209e1efd-a3da-460f-8bbe-8e8239c13884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433468460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.433468460
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2453073651
Short name T829
Test name
Test status
Simulation time 28412566 ps
CPU time 1.22 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 207664 kb
Host smart-4a39d392-c1f2-4739-b819-d9eda58c415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453073651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2453073651
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.641776918
Short name T554
Test name
Test status
Simulation time 91142905 ps
CPU time 0.81 seconds
Started May 26 02:39:05 PM PDT 24
Finished May 26 02:39:07 PM PDT 24
Peak memory 205308 kb
Host smart-5d513922-a331-4edd-9a16-75864b9b19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641776918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.641776918
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.71909722
Short name T475
Test name
Test status
Simulation time 976999898 ps
CPU time 4.24 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:39:13 PM PDT 24
Peak memory 233908 kb
Host smart-3faec545-7ad4-40d8-a17d-1cf2339bbd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71909722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.71909722
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.751469109
Short name T461
Test name
Test status
Simulation time 11705462 ps
CPU time 0.68 seconds
Started May 26 02:39:41 PM PDT 24
Finished May 26 02:39:44 PM PDT 24
Peak memory 205252 kb
Host smart-99531466-24ee-43d5-8236-9f634aa8f586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751469109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.751469109
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3468721314
Short name T531
Test name
Test status
Simulation time 13268152 ps
CPU time 0.79 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:39:42 PM PDT 24
Peak memory 205956 kb
Host smart-fa26414f-3a8d-4019-b4dd-1714411a4e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468721314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3468721314
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.149794482
Short name T553
Test name
Test status
Simulation time 3116291106 ps
CPU time 63.1 seconds
Started May 26 02:39:49 PM PDT 24
Finished May 26 02:40:54 PM PDT 24
Peak memory 253964 kb
Host smart-42029b4f-d0b3-413d-b5b9-50bd4dbed1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149794482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.149794482
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2008440258
Short name T759
Test name
Test status
Simulation time 8824648946 ps
CPU time 59.32 seconds
Started May 26 02:39:41 PM PDT 24
Finished May 26 02:40:42 PM PDT 24
Peak memory 255460 kb
Host smart-fb05e9f3-c372-47a8-8514-5a1bc2f5ac41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008440258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2008440258
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4119439830
Short name T176
Test name
Test status
Simulation time 11328536175 ps
CPU time 54.09 seconds
Started May 26 02:39:50 PM PDT 24
Finished May 26 02:40:46 PM PDT 24
Peak memory 253856 kb
Host smart-0e976f57-49ec-4648-bc05-e56c176def4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119439830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4119439830
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2548002712
Short name T302
Test name
Test status
Simulation time 8695056820 ps
CPU time 64.68 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:40:43 PM PDT 24
Peak memory 232428 kb
Host smart-64e12ae6-f96c-4375-9d99-a6f786c7f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548002712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2548002712
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3968649038
Short name T697
Test name
Test status
Simulation time 79035619 ps
CPU time 2.72 seconds
Started May 26 02:39:47 PM PDT 24
Finished May 26 02:39:52 PM PDT 24
Peak memory 233384 kb
Host smart-d9fce972-4691-475a-80f8-0251c6850d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968649038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3968649038
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1748664049
Short name T189
Test name
Test status
Simulation time 6726076140 ps
CPU time 16.24 seconds
Started May 26 02:39:47 PM PDT 24
Finished May 26 02:40:05 PM PDT 24
Peak memory 218248 kb
Host smart-c83fd327-344d-41d2-90d3-f6e5bcd2b3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748664049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1748664049
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3315933783
Short name T225
Test name
Test status
Simulation time 365095705 ps
CPU time 3.41 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:39:45 PM PDT 24
Peak memory 232408 kb
Host smart-1f936bc3-ae29-4831-ac0f-91fde1ac30d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315933783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3315933783
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.113785569
Short name T491
Test name
Test status
Simulation time 3829014955 ps
CPU time 10.65 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:50 PM PDT 24
Peak memory 238336 kb
Host smart-9e23f3e3-4b68-433e-823c-5cb7ad9f89c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113785569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.113785569
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1098818154
Short name T695
Test name
Test status
Simulation time 712158318 ps
CPU time 4.85 seconds
Started May 26 02:39:38 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 221728 kb
Host smart-499fa40a-1e7a-4c8a-a297-ac9555a79339
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1098818154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1098818154
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2058387292
Short name T70
Test name
Test status
Simulation time 16452559592 ps
CPU time 164.58 seconds
Started May 26 02:39:46 PM PDT 24
Finished May 26 02:42:33 PM PDT 24
Peak memory 250292 kb
Host smart-30b6ce6e-d9fe-4656-8612-185492404f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058387292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2058387292
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2608962429
Short name T471
Test name
Test status
Simulation time 4378733284 ps
CPU time 25.62 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:40:05 PM PDT 24
Peak memory 215976 kb
Host smart-0c47145b-f254-4812-8fe6-7ffac3cb9084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608962429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2608962429
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2739947406
Short name T364
Test name
Test status
Simulation time 8846567463 ps
CPU time 26.87 seconds
Started May 26 02:39:45 PM PDT 24
Finished May 26 02:40:13 PM PDT 24
Peak memory 215900 kb
Host smart-e3d167fc-165b-4278-9bb5-d147ad9dd762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739947406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2739947406
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3218108134
Short name T472
Test name
Test status
Simulation time 21107445 ps
CPU time 1.02 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:40 PM PDT 24
Peak memory 207424 kb
Host smart-ef006958-c84f-4395-8b1e-4440d39a9825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218108134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3218108134
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2502074609
Short name T933
Test name
Test status
Simulation time 75113746 ps
CPU time 0.8 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:39 PM PDT 24
Peak memory 205480 kb
Host smart-004b1b27-d402-476a-99ee-193903845948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502074609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2502074609
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.620643601
Short name T198
Test name
Test status
Simulation time 906780045 ps
CPU time 3.63 seconds
Started May 26 02:39:38 PM PDT 24
Finished May 26 02:39:44 PM PDT 24
Peak memory 218944 kb
Host smart-eb063028-165b-4592-9908-11d7e9225cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620643601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.620643601
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.226507113
Short name T332
Test name
Test status
Simulation time 19632617 ps
CPU time 0.71 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:39:42 PM PDT 24
Peak memory 204944 kb
Host smart-87d89bd2-5e5c-4f8d-a988-c2fa35544a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226507113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.226507113
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.368769436
Short name T833
Test name
Test status
Simulation time 305912288 ps
CPU time 4.26 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 219736 kb
Host smart-b91a31bf-f5c1-4a3b-8ade-8ecc1abb578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368769436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.368769436
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3267161330
Short name T828
Test name
Test status
Simulation time 19148804 ps
CPU time 0.77 seconds
Started May 26 02:39:42 PM PDT 24
Finished May 26 02:39:44 PM PDT 24
Peak memory 205968 kb
Host smart-51ee1232-0806-4e69-b165-fddedeecc094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267161330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3267161330
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1697847261
Short name T898
Test name
Test status
Simulation time 5108196257 ps
CPU time 25.81 seconds
Started May 26 02:39:40 PM PDT 24
Finished May 26 02:40:08 PM PDT 24
Peak memory 248248 kb
Host smart-920fb197-29fc-4b0d-98bd-e5b278af4c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697847261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1697847261
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1166054974
Short name T207
Test name
Test status
Simulation time 103316732659 ps
CPU time 679.26 seconds
Started May 26 02:39:47 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 254860 kb
Host smart-7720a25d-84d2-4ae6-a582-292956542315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166054974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1166054974
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1159141733
Short name T301
Test name
Test status
Simulation time 4195360280 ps
CPU time 52.47 seconds
Started May 26 02:39:43 PM PDT 24
Finished May 26 02:40:37 PM PDT 24
Peak memory 239236 kb
Host smart-89f1e218-4b25-445f-a6a5-623695e7d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159141733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1159141733
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1624491230
Short name T199
Test name
Test status
Simulation time 774491209 ps
CPU time 6 seconds
Started May 26 02:39:43 PM PDT 24
Finished May 26 02:39:50 PM PDT 24
Peak memory 238072 kb
Host smart-db6aacfd-8100-4677-b63b-08effe906976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624491230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1624491230
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1451085806
Short name T490
Test name
Test status
Simulation time 2553745055 ps
CPU time 30.54 seconds
Started May 26 02:39:49 PM PDT 24
Finished May 26 02:40:22 PM PDT 24
Peak memory 243888 kb
Host smart-62366147-b220-4926-b169-8f1d7f906044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451085806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1451085806
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2576688652
Short name T449
Test name
Test status
Simulation time 57019498 ps
CPU time 1.03 seconds
Started May 26 02:39:46 PM PDT 24
Finished May 26 02:39:49 PM PDT 24
Peak memory 217440 kb
Host smart-44ae8c93-2265-409f-bcb4-9716bdfd4bbd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576688652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2576688652
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1561486270
Short name T393
Test name
Test status
Simulation time 1919967234 ps
CPU time 8.22 seconds
Started May 26 02:39:47 PM PDT 24
Finished May 26 02:39:57 PM PDT 24
Peak memory 216752 kb
Host smart-b0519d0d-b7ad-442f-8f03-3b4f7f6f7c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561486270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1561486270
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1664392974
Short name T216
Test name
Test status
Simulation time 16274044526 ps
CPU time 40.26 seconds
Started May 26 02:39:38 PM PDT 24
Finished May 26 02:40:21 PM PDT 24
Peak memory 230084 kb
Host smart-6aa380ec-549f-424d-8162-d0faf803a43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664392974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1664392974
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2501870901
Short name T144
Test name
Test status
Simulation time 391538042 ps
CPU time 5.06 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 222528 kb
Host smart-21bd921e-daea-4708-8375-5bd36d587311
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2501870901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2501870901
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2202466139
Short name T549
Test name
Test status
Simulation time 2961365303 ps
CPU time 15.12 seconds
Started May 26 02:39:40 PM PDT 24
Finished May 26 02:39:57 PM PDT 24
Peak memory 215956 kb
Host smart-c9171c2c-b942-41ec-baaa-59cfa982d874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202466139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2202466139
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2079522218
Short name T807
Test name
Test status
Simulation time 5113331180 ps
CPU time 15.82 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:40:06 PM PDT 24
Peak memory 215960 kb
Host smart-c3ce6ed1-1724-495d-a161-8244cb990292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079522218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2079522218
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1094466944
Short name T791
Test name
Test status
Simulation time 583715585 ps
CPU time 7.52 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:39:58 PM PDT 24
Peak memory 215920 kb
Host smart-6c9df5a8-da93-4b28-bae6-bd86cb8d7749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094466944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1094466944
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3414746487
Short name T481
Test name
Test status
Simulation time 22124499 ps
CPU time 0.76 seconds
Started May 26 02:39:45 PM PDT 24
Finished May 26 02:39:48 PM PDT 24
Peak memory 205268 kb
Host smart-cd920f0a-5480-46a1-8d9a-e9c85ff811c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414746487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3414746487
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3556686188
Short name T681
Test name
Test status
Simulation time 1380435254 ps
CPU time 5.96 seconds
Started May 26 02:39:49 PM PDT 24
Finished May 26 02:39:57 PM PDT 24
Peak memory 238936 kb
Host smart-56791588-b6a0-404d-a09e-41d1b2975ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556686188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3556686188
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3474207930
Short name T346
Test name
Test status
Simulation time 48589786 ps
CPU time 0.72 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:39:56 PM PDT 24
Peak memory 204256 kb
Host smart-cda3cf26-2b66-4b1b-bfd2-30eae34af684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474207930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3474207930
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3329630483
Short name T396
Test name
Test status
Simulation time 60027728 ps
CPU time 2.44 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:39:53 PM PDT 24
Peak memory 221200 kb
Host smart-f19e2786-d158-4d0d-8535-3a3f96e1e4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329630483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3329630483
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4214583544
Short name T164
Test name
Test status
Simulation time 27698980 ps
CPU time 0.83 seconds
Started May 26 02:39:43 PM PDT 24
Finished May 26 02:39:45 PM PDT 24
Peak memory 205932 kb
Host smart-4ecce947-b1d7-4f57-9f25-8504be1ac38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214583544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4214583544
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2806783511
Short name T432
Test name
Test status
Simulation time 53504542055 ps
CPU time 111.61 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:41:42 PM PDT 24
Peak memory 251356 kb
Host smart-1675fa05-a755-4d5b-b9c4-44851dda680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806783511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2806783511
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2320675588
Short name T521
Test name
Test status
Simulation time 496496647 ps
CPU time 3.27 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:39:59 PM PDT 24
Peak memory 223984 kb
Host smart-2e63232f-9972-4f9e-8121-db756c536485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320675588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2320675588
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1825805107
Short name T279
Test name
Test status
Simulation time 357198473 ps
CPU time 7.85 seconds
Started May 26 02:39:43 PM PDT 24
Finished May 26 02:39:52 PM PDT 24
Peak memory 219392 kb
Host smart-17172cb8-8f06-4fe2-a6a8-2aa0d4951df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825805107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1825805107
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1753634132
Short name T732
Test name
Test status
Simulation time 48399956693 ps
CPU time 33.4 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:40:24 PM PDT 24
Peak memory 229604 kb
Host smart-301353a4-883d-42cb-9232-0dd49c1f0bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753634132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1753634132
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1161637704
Short name T675
Test name
Test status
Simulation time 23149314 ps
CPU time 0.97 seconds
Started May 26 02:39:44 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 217476 kb
Host smart-45955804-5ec1-441e-beb4-63e8c99d9157
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161637704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1161637704
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.69494797
Short name T40
Test name
Test status
Simulation time 3126626863 ps
CPU time 5.67 seconds
Started May 26 02:39:38 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 218608 kb
Host smart-31401679-4676-45e1-ad9e-6dc5fbd8fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69494797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.69494797
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.469248385
Short name T190
Test name
Test status
Simulation time 334954053 ps
CPU time 3 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:39:53 PM PDT 24
Peak memory 233024 kb
Host smart-9eee359a-e90d-4408-a172-3c2c25465196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469248385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.469248385
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1692036662
Short name T437
Test name
Test status
Simulation time 2379996070 ps
CPU time 10.37 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:40:01 PM PDT 24
Peak memory 221908 kb
Host smart-26ebd885-da66-4e7b-b2e9-b8bd8ed3ae6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692036662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1692036662
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3478827079
Short name T365
Test name
Test status
Simulation time 881280177 ps
CPU time 3.75 seconds
Started May 26 02:39:45 PM PDT 24
Finished May 26 02:39:51 PM PDT 24
Peak memory 215996 kb
Host smart-6deac256-7edb-4648-9235-ed56748d84aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478827079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3478827079
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.267425814
Short name T541
Test name
Test status
Simulation time 2822445298 ps
CPU time 9.18 seconds
Started May 26 02:39:41 PM PDT 24
Finished May 26 02:39:52 PM PDT 24
Peak memory 215904 kb
Host smart-a8f40837-a6d1-48aa-b94b-03e6c4284e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267425814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.267425814
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1360371149
Short name T761
Test name
Test status
Simulation time 104982932 ps
CPU time 1.76 seconds
Started May 26 02:39:46 PM PDT 24
Finished May 26 02:39:51 PM PDT 24
Peak memory 215904 kb
Host smart-15e4dabb-92e6-4c52-a44a-8f584d3d8bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360371149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1360371149
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1292042046
Short name T411
Test name
Test status
Simulation time 185255084 ps
CPU time 0.83 seconds
Started May 26 02:39:46 PM PDT 24
Finished May 26 02:39:49 PM PDT 24
Peak memory 205292 kb
Host smart-340f28bd-9838-4d1d-afd8-29ebe19f4bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292042046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1292042046
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3556453627
Short name T858
Test name
Test status
Simulation time 1644334886 ps
CPU time 3.14 seconds
Started May 26 02:39:47 PM PDT 24
Finished May 26 02:39:53 PM PDT 24
Peak memory 234620 kb
Host smart-3a70e66f-ffe0-474e-8dc1-bc73c8716dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556453627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3556453627
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3357063990
Short name T947
Test name
Test status
Simulation time 11233552 ps
CPU time 0.72 seconds
Started May 26 02:39:52 PM PDT 24
Finished May 26 02:39:54 PM PDT 24
Peak memory 204892 kb
Host smart-6e3df91e-6586-4e91-984b-7fe7ec7be256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357063990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3357063990
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3949190141
Short name T290
Test name
Test status
Simulation time 261798874 ps
CPU time 5.91 seconds
Started May 26 02:39:52 PM PDT 24
Finished May 26 02:40:00 PM PDT 24
Peak memory 233532 kb
Host smart-36e828bd-18c8-448d-84d4-177e2cafe02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949190141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3949190141
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4138120482
Short name T525
Test name
Test status
Simulation time 68288464 ps
CPU time 0.78 seconds
Started May 26 02:39:50 PM PDT 24
Finished May 26 02:39:53 PM PDT 24
Peak memory 206268 kb
Host smart-a6ab1f94-e2a8-41f7-b35d-59ad12d52019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138120482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4138120482
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1281568123
Short name T188
Test name
Test status
Simulation time 95398619148 ps
CPU time 88.65 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:41:25 PM PDT 24
Peak memory 248792 kb
Host smart-c330649a-8981-4fc0-9440-40d9b06ac010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281568123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1281568123
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4005584215
Short name T251
Test name
Test status
Simulation time 8450100667 ps
CPU time 101.28 seconds
Started May 26 02:39:52 PM PDT 24
Finished May 26 02:41:34 PM PDT 24
Peak memory 248908 kb
Host smart-c438f50d-f683-4e2c-add5-61f5c2472dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005584215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4005584215
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1207444292
Short name T38
Test name
Test status
Simulation time 25343175893 ps
CPU time 171.71 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:42:42 PM PDT 24
Peak memory 248908 kb
Host smart-f41015ca-b015-495a-89fa-dd88124890cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207444292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1207444292
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1430014566
Short name T307
Test name
Test status
Simulation time 1092661000 ps
CPU time 7.38 seconds
Started May 26 02:39:50 PM PDT 24
Finished May 26 02:39:59 PM PDT 24
Peak memory 224216 kb
Host smart-737f7b45-172f-4841-b401-774b883b9791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430014566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1430014566
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.300371721
Short name T208
Test name
Test status
Simulation time 3475426374 ps
CPU time 17.24 seconds
Started May 26 02:39:52 PM PDT 24
Finished May 26 02:40:10 PM PDT 24
Peak memory 234244 kb
Host smart-2d0d06ad-3576-424c-81a9-1f126598262d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300371721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.300371721
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1039137672
Short name T736
Test name
Test status
Simulation time 1231904925 ps
CPU time 16.45 seconds
Started May 26 02:39:46 PM PDT 24
Finished May 26 02:40:05 PM PDT 24
Peak memory 233424 kb
Host smart-abde58b3-157c-4a4b-842a-ce003e2bebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039137672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1039137672
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3576394935
Short name T407
Test name
Test status
Simulation time 85724646 ps
CPU time 1.1 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:39:57 PM PDT 24
Peak memory 216184 kb
Host smart-bc4c52b4-dc64-499a-8425-e931a20258da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576394935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3576394935
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.956679765
Short name T612
Test name
Test status
Simulation time 152050600 ps
CPU time 2.75 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:39:58 PM PDT 24
Peak memory 224140 kb
Host smart-67c57be8-5dfe-4161-89ca-72c3b3bf890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956679765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.956679765
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2212526904
Short name T572
Test name
Test status
Simulation time 1162343944 ps
CPU time 5.22 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:39:55 PM PDT 24
Peak memory 229064 kb
Host smart-296d761a-4d9b-4357-b6f0-da905a54faaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212526904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2212526904
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.384835188
Short name T145
Test name
Test status
Simulation time 1689103996 ps
CPU time 3.81 seconds
Started May 26 02:39:47 PM PDT 24
Finished May 26 02:39:53 PM PDT 24
Peak memory 222100 kb
Host smart-ce5d4e8c-5f38-46a7-9fbc-d0de08ac8d4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=384835188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.384835188
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2145153196
Short name T817
Test name
Test status
Simulation time 1121580493 ps
CPU time 13.31 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:40:04 PM PDT 24
Peak memory 235148 kb
Host smart-2131a5f8-36b5-4983-8968-382ebeb296a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145153196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2145153196
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1237116158
Short name T5
Test name
Test status
Simulation time 2966483304 ps
CPU time 18.45 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:40:09 PM PDT 24
Peak memory 216012 kb
Host smart-c1000885-3480-45c7-aebc-a2c417d2ef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237116158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1237116158
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2348118392
Short name T773
Test name
Test status
Simulation time 715536527 ps
CPU time 4.5 seconds
Started May 26 02:39:48 PM PDT 24
Finished May 26 02:39:55 PM PDT 24
Peak memory 215740 kb
Host smart-53f75d63-8cb6-49c9-8b8e-3691bbf8cc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348118392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2348118392
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4004647697
Short name T82
Test name
Test status
Simulation time 91210970 ps
CPU time 1.9 seconds
Started May 26 02:39:50 PM PDT 24
Finished May 26 02:39:54 PM PDT 24
Peak memory 215928 kb
Host smart-c6e96bf8-2111-419f-8a66-acc9dee58a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004647697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4004647697
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2537718559
Short name T939
Test name
Test status
Simulation time 25983690 ps
CPU time 0.83 seconds
Started May 26 02:39:51 PM PDT 24
Finished May 26 02:39:53 PM PDT 24
Peak memory 205268 kb
Host smart-4610e4cb-bb7f-4d3b-b699-7c26eab16f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537718559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2537718559
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2004455955
Short name T197
Test name
Test status
Simulation time 1079225599 ps
CPU time 8.77 seconds
Started May 26 02:39:52 PM PDT 24
Finished May 26 02:40:02 PM PDT 24
Peak memory 242628 kb
Host smart-2dc2fed9-c30e-4803-bb66-6fe59985958f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004455955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2004455955
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2388132575
Short name T513
Test name
Test status
Simulation time 15233972 ps
CPU time 0.72 seconds
Started May 26 02:39:57 PM PDT 24
Finished May 26 02:39:59 PM PDT 24
Peak memory 204924 kb
Host smart-c6d21e95-ec82-4989-9e87-04ee4d64006a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388132575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2388132575
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4065696619
Short name T613
Test name
Test status
Simulation time 156518686 ps
CPU time 2.39 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:39:58 PM PDT 24
Peak memory 232420 kb
Host smart-c1c2c9c8-3919-429b-9edd-931463315c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065696619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4065696619
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2177162943
Short name T67
Test name
Test status
Simulation time 23310461 ps
CPU time 0.74 seconds
Started May 26 02:39:52 PM PDT 24
Finished May 26 02:39:54 PM PDT 24
Peak memory 204800 kb
Host smart-978d6204-d6a1-4f48-b0fa-4bef77b2894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177162943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2177162943
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.253658221
Short name T280
Test name
Test status
Simulation time 63032592634 ps
CPU time 217.95 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:43:36 PM PDT 24
Peak memory 254756 kb
Host smart-615f5f53-cda2-41ac-8c29-c7d2580293ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253658221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.253658221
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.630671203
Short name T567
Test name
Test status
Simulation time 4855121015 ps
CPU time 31.57 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:40:30 PM PDT 24
Peak memory 239064 kb
Host smart-73e2d57d-c5ba-4cdd-9fe9-fca865b1d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630671203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.630671203
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1795634652
Short name T330
Test name
Test status
Simulation time 407913006 ps
CPU time 2.48 seconds
Started May 26 02:39:58 PM PDT 24
Finished May 26 02:40:01 PM PDT 24
Peak memory 232408 kb
Host smart-dec86080-0b25-4b9c-a04e-744b4a60e00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795634652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1795634652
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3921137672
Short name T375
Test name
Test status
Simulation time 30983185 ps
CPU time 1.99 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:07 PM PDT 24
Peak memory 215732 kb
Host smart-5c17df76-d17b-46c3-a648-61d304d0ea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921137672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3921137672
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4026308716
Short name T215
Test name
Test status
Simulation time 105521451 ps
CPU time 2.15 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:39:59 PM PDT 24
Peak memory 218108 kb
Host smart-0f5296d3-6758-46aa-b62b-80654f91139c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026308716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4026308716
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1090805578
Short name T853
Test name
Test status
Simulation time 28229733 ps
CPU time 1.11 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:39:59 PM PDT 24
Peak memory 216092 kb
Host smart-a3c22bc2-73ef-48b3-ba10-954236bf3353
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090805578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1090805578
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2610116609
Short name T489
Test name
Test status
Simulation time 68742445550 ps
CPU time 13.55 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:40:10 PM PDT 24
Peak memory 226760 kb
Host smart-ecf84d06-ca6a-46fa-b798-7f6bfd249ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610116609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2610116609
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3856071290
Short name T172
Test name
Test status
Simulation time 8625796794 ps
CPU time 12.35 seconds
Started May 26 02:39:57 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 232428 kb
Host smart-a3b6e2b3-c4a4-4674-963b-b1391d37b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856071290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3856071290
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1207645822
Short name T767
Test name
Test status
Simulation time 175032218 ps
CPU time 4.16 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:10 PM PDT 24
Peak memory 219308 kb
Host smart-16e67e3b-76f1-47fb-8098-f43fd78cc228
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1207645822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1207645822
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1679834349
Short name T133
Test name
Test status
Simulation time 61989990243 ps
CPU time 186.17 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:43:04 PM PDT 24
Peak memory 272528 kb
Host smart-bc85d26f-402c-4442-837a-181aa060abbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679834349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1679834349
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2322057238
Short name T315
Test name
Test status
Simulation time 769024945 ps
CPU time 10.22 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:40:08 PM PDT 24
Peak memory 215920 kb
Host smart-56244065-e3c0-4db8-b74d-75c51e32201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322057238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2322057238
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.493653988
Short name T968
Test name
Test status
Simulation time 2504122692 ps
CPU time 10.94 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:16 PM PDT 24
Peak memory 215924 kb
Host smart-057b176a-35a2-4894-8d51-6db5a31a32cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493653988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.493653988
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2654672708
Short name T404
Test name
Test status
Simulation time 31581905 ps
CPU time 0.83 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:39:59 PM PDT 24
Peak memory 205392 kb
Host smart-169fb628-114e-489c-a376-2e13a03614cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654672708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2654672708
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3609160401
Short name T445
Test name
Test status
Simulation time 118078065 ps
CPU time 0.92 seconds
Started May 26 02:39:58 PM PDT 24
Finished May 26 02:40:00 PM PDT 24
Peak memory 206320 kb
Host smart-3ba4575c-3020-42fa-bdd0-ea19983d0a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609160401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3609160401
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1410724613
Short name T590
Test name
Test status
Simulation time 2887252312 ps
CPU time 7.15 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:13 PM PDT 24
Peak memory 219864 kb
Host smart-b1c309d6-4b23-4e06-a04f-69e9d00032de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410724613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1410724613
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1263794441
Short name T334
Test name
Test status
Simulation time 11371826 ps
CPU time 0.75 seconds
Started May 26 02:40:02 PM PDT 24
Finished May 26 02:40:04 PM PDT 24
Peak memory 205264 kb
Host smart-c51fae66-8a09-4fa6-981c-835fc004f82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263794441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1263794441
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.628974724
Short name T438
Test name
Test status
Simulation time 126905498 ps
CPU time 2.45 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:40:01 PM PDT 24
Peak memory 233328 kb
Host smart-96d8f10c-ec4e-4a12-bf06-e383975b1810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628974724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.628974724
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.221449521
Short name T368
Test name
Test status
Simulation time 31016938 ps
CPU time 0.75 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:39:58 PM PDT 24
Peak memory 205940 kb
Host smart-c8b7c16c-6449-43ad-8fb4-018d1cddfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221449521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.221449521
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.162791452
Short name T548
Test name
Test status
Simulation time 77662649400 ps
CPU time 194.17 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:43:12 PM PDT 24
Peak memory 250868 kb
Host smart-f9f0b16a-47ee-4f40-82f8-9a6351b5a35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162791452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.162791452
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2637121510
Short name T756
Test name
Test status
Simulation time 3384521092 ps
CPU time 66.34 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:41:04 PM PDT 24
Peak memory 253312 kb
Host smart-df0b702b-58d1-4732-8189-b5d874b5db20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637121510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2637121510
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3605871355
Short name T179
Test name
Test status
Simulation time 98909592329 ps
CPU time 184.35 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:43:02 PM PDT 24
Peak memory 257072 kb
Host smart-8e06f939-2527-4990-985f-f25d7fd4d01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605871355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3605871355
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3814779348
Short name T712
Test name
Test status
Simulation time 772775534 ps
CPU time 17.4 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:40:14 PM PDT 24
Peak memory 232424 kb
Host smart-ea487e14-4d91-49a6-927d-e0974eac6fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814779348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3814779348
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3209551750
Short name T558
Test name
Test status
Simulation time 2725121561 ps
CPU time 4.76 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:40:02 PM PDT 24
Peak memory 218436 kb
Host smart-5b67aeb3-4f3d-431e-ad22-6ac99fd8eaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209551750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3209551750
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3246571674
Short name T699
Test name
Test status
Simulation time 1107208725 ps
CPU time 10.83 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:16 PM PDT 24
Peak memory 218100 kb
Host smart-30eac174-b301-4831-bfe1-3cb02772b605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246571674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3246571674
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2666663587
Short name T628
Test name
Test status
Simulation time 32646758 ps
CPU time 1.14 seconds
Started May 26 02:39:58 PM PDT 24
Finished May 26 02:40:00 PM PDT 24
Peak memory 216224 kb
Host smart-5f45a720-6aa2-4925-ae89-52f4b1060aea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666663587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2666663587
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2677982927
Short name T855
Test name
Test status
Simulation time 30625724 ps
CPU time 2.03 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:40:00 PM PDT 24
Peak memory 215712 kb
Host smart-8393f298-504b-4aa3-a249-153492257f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677982927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2677982927
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3937759431
Short name T282
Test name
Test status
Simulation time 249710738 ps
CPU time 5.94 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:40:04 PM PDT 24
Peak memory 239480 kb
Host smart-756fe031-01ed-4835-9c4b-f708d5248c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937759431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3937759431
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3880736142
Short name T417
Test name
Test status
Simulation time 549338445 ps
CPU time 2.99 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:40:00 PM PDT 24
Peak memory 219900 kb
Host smart-af40ed25-f9fd-4a74-80e8-d1f0ca621840
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3880736142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3880736142
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.429734158
Short name T153
Test name
Test status
Simulation time 43518858014 ps
CPU time 90.94 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:41:29 PM PDT 24
Peak memory 240672 kb
Host smart-d3d321e0-e519-4fd3-90c5-97247d677e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429734158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.429734158
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1679044252
Short name T657
Test name
Test status
Simulation time 2101874747 ps
CPU time 16.76 seconds
Started May 26 02:39:55 PM PDT 24
Finished May 26 02:40:14 PM PDT 24
Peak memory 215980 kb
Host smart-aa2bdb2b-9fd5-47ff-b7b8-ab93827ff6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679044252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1679044252
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2473180250
Short name T948
Test name
Test status
Simulation time 241725163 ps
CPU time 2.15 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:07 PM PDT 24
Peak memory 215644 kb
Host smart-3cc988ce-cae4-434f-b4dd-27178d840978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473180250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2473180250
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2650771933
Short name T627
Test name
Test status
Simulation time 1326936051 ps
CPU time 12.63 seconds
Started May 26 02:39:56 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 215972 kb
Host smart-22d44fe5-f92f-4e71-8999-8a217a8686b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650771933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2650771933
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1533489390
Short name T538
Test name
Test status
Simulation time 49757525 ps
CPU time 0.75 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:39:57 PM PDT 24
Peak memory 205316 kb
Host smart-bad10447-9657-4cdf-9673-70d763b1ecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533489390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1533489390
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2760563350
Short name T625
Test name
Test status
Simulation time 1325237112 ps
CPU time 10.99 seconds
Started May 26 02:39:54 PM PDT 24
Finished May 26 02:40:06 PM PDT 24
Peak memory 229684 kb
Host smart-c18372c0-6fae-4c83-af04-69e66e8b5977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760563350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2760563350
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2597419184
Short name T520
Test name
Test status
Simulation time 139006968 ps
CPU time 0.69 seconds
Started May 26 02:40:09 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 204924 kb
Host smart-5cf1d2b2-1b92-44fa-b2e8-5887b57d6dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597419184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2597419184
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1079612950
Short name T961
Test name
Test status
Simulation time 123279569 ps
CPU time 3.21 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:07 PM PDT 24
Peak memory 233508 kb
Host smart-f4302e46-62f2-443f-a242-b94ae131740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079612950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1079612950
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2089813824
Short name T909
Test name
Test status
Simulation time 31594368 ps
CPU time 0.78 seconds
Started May 26 02:40:06 PM PDT 24
Finished May 26 02:40:07 PM PDT 24
Peak memory 205856 kb
Host smart-d0e79c1d-3280-4f32-a227-8689ce28a49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089813824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2089813824
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2999003854
Short name T884
Test name
Test status
Simulation time 42508561888 ps
CPU time 83.96 seconds
Started May 26 02:40:02 PM PDT 24
Finished May 26 02:41:27 PM PDT 24
Peak memory 240608 kb
Host smart-c88205b5-271b-4a04-a560-bb9b01e95963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999003854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2999003854
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1008213852
Short name T314
Test name
Test status
Simulation time 8062621810 ps
CPU time 14.23 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:19 PM PDT 24
Peak memory 224348 kb
Host smart-61dccde4-10b1-41d1-b035-9b3dc7f9f388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008213852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1008213852
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2286716859
Short name T178
Test name
Test status
Simulation time 6150379426 ps
CPU time 85.11 seconds
Started May 26 02:40:05 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 249184 kb
Host smart-a492b2f0-1a3f-4e13-8301-81093fc2c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286716859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2286716859
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1100903243
Short name T342
Test name
Test status
Simulation time 576673881 ps
CPU time 6.83 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 233360 kb
Host smart-4e524ebe-0701-4294-9717-77ee4c3f1992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100903243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1100903243
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3691775363
Short name T872
Test name
Test status
Simulation time 4587185983 ps
CPU time 39.55 seconds
Started May 26 02:40:02 PM PDT 24
Finished May 26 02:40:42 PM PDT 24
Peak memory 248508 kb
Host smart-3e527012-38a2-43c4-b0c6-ebf6a1445e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691775363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3691775363
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.604834162
Short name T534
Test name
Test status
Simulation time 24026518 ps
CPU time 1.13 seconds
Started May 26 02:40:01 PM PDT 24
Finished May 26 02:40:03 PM PDT 24
Peak memory 216204 kb
Host smart-7ff2c7c3-33fd-4e2c-9023-0d9fe285229d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604834162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.604834162
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2130364986
Short name T644
Test name
Test status
Simulation time 807543790 ps
CPU time 2.4 seconds
Started May 26 02:40:06 PM PDT 24
Finished May 26 02:40:09 PM PDT 24
Peak memory 216544 kb
Host smart-024fe583-4c8c-4dd3-a2c5-5dd39c7e6afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130364986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2130364986
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3719577938
Short name T624
Test name
Test status
Simulation time 287175194 ps
CPU time 2.25 seconds
Started May 26 02:40:09 PM PDT 24
Finished May 26 02:40:12 PM PDT 24
Peak memory 218348 kb
Host smart-a1cb654a-5d30-4ff0-bcc9-a80c4bbbfb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719577938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3719577938
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.390148795
Short name T621
Test name
Test status
Simulation time 131829496 ps
CPU time 4.15 seconds
Started May 26 02:40:06 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 222576 kb
Host smart-2ba38086-ae61-40b5-beb7-70aec5e074a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=390148795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.390148795
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1532671467
Short name T246
Test name
Test status
Simulation time 13090828569 ps
CPU time 249.96 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:44:14 PM PDT 24
Peak memory 273460 kb
Host smart-60cefbd5-73ae-46a8-b4ca-e1325cd5579b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532671467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1532671467
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1001309064
Short name T868
Test name
Test status
Simulation time 1603834618 ps
CPU time 8.26 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:12 PM PDT 24
Peak memory 215968 kb
Host smart-3980f7c2-c4de-49ea-aece-993e744b301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001309064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1001309064
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1864690618
Short name T313
Test name
Test status
Simulation time 1595832616 ps
CPU time 8.45 seconds
Started May 26 02:40:02 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 215832 kb
Host smart-e079b955-7327-4307-815f-04c11ca7a9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864690618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1864690618
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2436593049
Short name T782
Test name
Test status
Simulation time 320199438 ps
CPU time 3.15 seconds
Started May 26 02:40:07 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 216104 kb
Host smart-7b2739b2-a9ee-40e3-93ab-0e052d6af5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436593049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2436593049
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.408040730
Short name T354
Test name
Test status
Simulation time 34116473 ps
CPU time 0.91 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:06 PM PDT 24
Peak memory 205276 kb
Host smart-7f5b04a3-f163-41a9-adb0-4eeda0bcc5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408040730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.408040730
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1184123724
Short name T515
Test name
Test status
Simulation time 5116179552 ps
CPU time 4.39 seconds
Started May 26 02:40:02 PM PDT 24
Finished May 26 02:40:08 PM PDT 24
Peak memory 218960 kb
Host smart-f6a5ca71-1d62-46cd-b37b-d57ae1c1583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184123724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1184123724
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1125119786
Short name T674
Test name
Test status
Simulation time 1093222112 ps
CPU time 2.46 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:06 PM PDT 24
Peak memory 218424 kb
Host smart-d74c3aae-a096-4430-bad6-dcdadf509db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125119786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1125119786
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1958874532
Short name T337
Test name
Test status
Simulation time 23152258 ps
CPU time 0.85 seconds
Started May 26 02:40:07 PM PDT 24
Finished May 26 02:40:09 PM PDT 24
Peak memory 205944 kb
Host smart-12423095-7ddf-4f92-9fe8-0dd2e16557c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958874532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1958874532
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3182257024
Short name T533
Test name
Test status
Simulation time 1507383870 ps
CPU time 20.44 seconds
Started May 26 02:40:09 PM PDT 24
Finished May 26 02:40:30 PM PDT 24
Peak memory 235216 kb
Host smart-8e414e68-4b09-4dd6-a673-fa105bdbeb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182257024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3182257024
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2388720963
Short name T56
Test name
Test status
Simulation time 32836028571 ps
CPU time 140.23 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:42:24 PM PDT 24
Peak memory 254056 kb
Host smart-7f0f615d-3358-4645-a4e9-fd25614884f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388720963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2388720963
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1161707720
Short name T249
Test name
Test status
Simulation time 6934045655 ps
CPU time 128.62 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:42:13 PM PDT 24
Peak memory 256072 kb
Host smart-b22054a9-aca2-40fd-8431-993da15e5b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161707720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1161707720
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2094078460
Short name T803
Test name
Test status
Simulation time 335201801 ps
CPU time 7.75 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:12 PM PDT 24
Peak memory 232400 kb
Host smart-046f4cb0-5a2b-44e1-b273-8038256be8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094078460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2094078460
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4029628627
Short name T195
Test name
Test status
Simulation time 221390155 ps
CPU time 4.14 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:09 PM PDT 24
Peak memory 234128 kb
Host smart-1bee4112-fcfd-4b54-8c89-216925d56ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029628627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4029628627
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2416627270
Short name T11
Test name
Test status
Simulation time 7096763489 ps
CPU time 17.44 seconds
Started May 26 02:40:06 PM PDT 24
Finished May 26 02:40:24 PM PDT 24
Peak memory 234332 kb
Host smart-73b9d4c3-2815-4db6-b7da-076ee5aae7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416627270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2416627270
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1960279924
Short name T25
Test name
Test status
Simulation time 90678211 ps
CPU time 1.03 seconds
Started May 26 02:40:02 PM PDT 24
Finished May 26 02:40:04 PM PDT 24
Peak memory 217480 kb
Host smart-e9609224-1f89-462b-b73f-3363416ecd13
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960279924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1960279924
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4153192403
Short name T911
Test name
Test status
Simulation time 493039410 ps
CPU time 4.97 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:09 PM PDT 24
Peak memory 218172 kb
Host smart-951d0dbf-7622-476d-a381-6237c7e5e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153192403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4153192403
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3173115075
Short name T893
Test name
Test status
Simulation time 1106449918 ps
CPU time 3.75 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:07 PM PDT 24
Peak memory 233340 kb
Host smart-81780a88-3638-4f3a-8dc2-153033af7438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173115075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3173115075
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2341200252
Short name T350
Test name
Test status
Simulation time 230401410 ps
CPU time 4.6 seconds
Started May 26 02:40:09 PM PDT 24
Finished May 26 02:40:14 PM PDT 24
Peak memory 220144 kb
Host smart-940f1afd-5672-4b56-b693-96493cf7c07d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341200252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2341200252
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2572547254
Short name T125
Test name
Test status
Simulation time 128008862040 ps
CPU time 376.11 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:46:21 PM PDT 24
Peak memory 257084 kb
Host smart-28b27023-a9f9-43bd-ba47-12fe2eb8b00e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572547254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2572547254
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2093350307
Short name T577
Test name
Test status
Simulation time 1588103573 ps
CPU time 21.97 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:27 PM PDT 24
Peak memory 219008 kb
Host smart-ea01e4f0-a374-4a00-81c8-6663892b07bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093350307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2093350307
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4196493400
Short name T808
Test name
Test status
Simulation time 2018239268 ps
CPU time 6.35 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:11 PM PDT 24
Peak memory 215804 kb
Host smart-68f43077-61e9-4e90-a649-1a0c1c1b3fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196493400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4196493400
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1092675159
Short name T163
Test name
Test status
Simulation time 10781140 ps
CPU time 0.66 seconds
Started May 26 02:40:04 PM PDT 24
Finished May 26 02:40:06 PM PDT 24
Peak memory 205124 kb
Host smart-8950176f-c2ac-4817-a31f-0098be738014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092675159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1092675159
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1585216099
Short name T338
Test name
Test status
Simulation time 245113104 ps
CPU time 0.94 seconds
Started May 26 02:40:02 PM PDT 24
Finished May 26 02:40:04 PM PDT 24
Peak memory 205316 kb
Host smart-76cd85c2-6474-4bf0-b1d4-74b3b0ff9df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585216099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1585216099
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2631647992
Short name T201
Test name
Test status
Simulation time 1592311378 ps
CPU time 7.85 seconds
Started May 26 02:40:03 PM PDT 24
Finished May 26 02:40:12 PM PDT 24
Peak memory 222108 kb
Host smart-207da7a0-56b7-48ab-a4d4-82e85082bda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631647992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2631647992
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.317176551
Short name T766
Test name
Test status
Simulation time 13678139 ps
CPU time 0.71 seconds
Started May 26 02:40:11 PM PDT 24
Finished May 26 02:40:13 PM PDT 24
Peak memory 204892 kb
Host smart-acd03e98-235d-4bfb-8bc0-415c94242501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317176551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.317176551
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.242414488
Short name T649
Test name
Test status
Simulation time 381239948 ps
CPU time 5.14 seconds
Started May 26 02:40:14 PM PDT 24
Finished May 26 02:40:20 PM PDT 24
Peak memory 232564 kb
Host smart-b4565d15-7d8d-4033-853c-d666e8c079fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242414488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.242414488
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3635129482
Short name T953
Test name
Test status
Simulation time 62716233 ps
CPU time 0.78 seconds
Started May 26 02:40:12 PM PDT 24
Finished May 26 02:40:14 PM PDT 24
Peak memory 206252 kb
Host smart-6fb0a8a9-5df8-4c9c-8a79-791dd97f09e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635129482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3635129482
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2566495687
Short name T835
Test name
Test status
Simulation time 2105910243 ps
CPU time 40.07 seconds
Started May 26 02:40:12 PM PDT 24
Finished May 26 02:40:53 PM PDT 24
Peak memory 248784 kb
Host smart-78bb932b-73cc-494a-9e8b-1cdea916c9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566495687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2566495687
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.665042698
Short name T651
Test name
Test status
Simulation time 31141879853 ps
CPU time 191.29 seconds
Started May 26 02:40:13 PM PDT 24
Finished May 26 02:43:26 PM PDT 24
Peak memory 252400 kb
Host smart-00378bea-72c7-4036-bee3-12a190928f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665042698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.665042698
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.183767248
Short name T39
Test name
Test status
Simulation time 66266153871 ps
CPU time 266.18 seconds
Started May 26 02:40:12 PM PDT 24
Finished May 26 02:44:40 PM PDT 24
Peak memory 254752 kb
Host smart-9648daf4-b45e-47a5-ad2a-13bfde4035bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183767248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.183767248
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2382512678
Short name T529
Test name
Test status
Simulation time 760768200 ps
CPU time 7.54 seconds
Started May 26 02:40:12 PM PDT 24
Finished May 26 02:40:21 PM PDT 24
Peak memory 224216 kb
Host smart-9f67568b-1829-42b1-b34e-3cda4da27cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382512678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2382512678
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2101821144
Short name T213
Test name
Test status
Simulation time 217958934 ps
CPU time 3.98 seconds
Started May 26 02:40:11 PM PDT 24
Finished May 26 02:40:16 PM PDT 24
Peak memory 218432 kb
Host smart-e654cb59-a884-4362-be7f-6abff18a050d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101821144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2101821144
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1794843015
Short name T869
Test name
Test status
Simulation time 594897509 ps
CPU time 8.9 seconds
Started May 26 02:40:10 PM PDT 24
Finished May 26 02:40:20 PM PDT 24
Peak memory 234732 kb
Host smart-49a7505c-1eca-42ef-9295-1d196dc12f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794843015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1794843015
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3690424472
Short name T669
Test name
Test status
Simulation time 30889998 ps
CPU time 1.02 seconds
Started May 26 02:40:12 PM PDT 24
Finished May 26 02:40:15 PM PDT 24
Peak memory 217476 kb
Host smart-dfdc1996-bf5c-47f9-8938-2b72e894ae01
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690424472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3690424472
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3041799291
Short name T517
Test name
Test status
Simulation time 10708089456 ps
CPU time 30.86 seconds
Started May 26 02:40:11 PM PDT 24
Finished May 26 02:40:44 PM PDT 24
Peak memory 232776 kb
Host smart-0dae1c27-9e1b-4004-96fd-4c9846e745d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041799291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3041799291
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3939651865
Short name T854
Test name
Test status
Simulation time 909131818 ps
CPU time 8 seconds
Started May 26 02:40:10 PM PDT 24
Finished May 26 02:40:20 PM PDT 24
Peak memory 235076 kb
Host smart-7cc237ea-71ea-45df-9b32-fb497731315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939651865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3939651865
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3385588325
Short name T65
Test name
Test status
Simulation time 5800320014 ps
CPU time 7.25 seconds
Started May 26 02:40:13 PM PDT 24
Finished May 26 02:40:22 PM PDT 24
Peak memory 219720 kb
Host smart-2516d954-0e8c-4102-9248-21566274c948
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3385588325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3385588325
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3828341419
Short name T821
Test name
Test status
Simulation time 6248648589 ps
CPU time 9.34 seconds
Started May 26 02:40:12 PM PDT 24
Finished May 26 02:40:23 PM PDT 24
Peak memory 216012 kb
Host smart-5db03589-0972-4082-8b01-7d9fab941344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828341419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3828341419
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2615586339
Short name T336
Test name
Test status
Simulation time 843485082 ps
CPU time 3.17 seconds
Started May 26 02:40:11 PM PDT 24
Finished May 26 02:40:16 PM PDT 24
Peak memory 215636 kb
Host smart-627de39e-566c-4d5a-a801-059bcf54cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615586339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2615586339
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2082267237
Short name T384
Test name
Test status
Simulation time 3634886594 ps
CPU time 3.11 seconds
Started May 26 02:40:13 PM PDT 24
Finished May 26 02:40:18 PM PDT 24
Peak memory 216044 kb
Host smart-7c1431b5-c960-4f59-9f7f-56924eabf5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082267237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2082267237
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1051973967
Short name T1
Test name
Test status
Simulation time 36313017 ps
CPU time 0.85 seconds
Started May 26 02:40:11 PM PDT 24
Finished May 26 02:40:13 PM PDT 24
Peak memory 205300 kb
Host smart-3133faf9-df4c-4157-9092-d7b9f06318c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051973967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1051973967
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1602713412
Short name T277
Test name
Test status
Simulation time 327686415 ps
CPU time 4.55 seconds
Started May 26 02:40:12 PM PDT 24
Finished May 26 02:40:18 PM PDT 24
Peak memory 224168 kb
Host smart-b5963a42-d2ef-4e84-9a6f-6afcd0df16dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602713412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1602713412
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1389440057
Short name T10
Test name
Test status
Simulation time 36466399 ps
CPU time 0.72 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:22 PM PDT 24
Peak memory 204928 kb
Host smart-f1b02809-a526-4c02-9863-ba017835ab69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389440057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1389440057
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.626761780
Short name T294
Test name
Test status
Simulation time 783713354 ps
CPU time 9.61 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:31 PM PDT 24
Peak memory 218316 kb
Host smart-b848028a-ee8c-4b1c-ae12-de53d6512515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626761780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.626761780
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1570663884
Short name T638
Test name
Test status
Simulation time 37487105 ps
CPU time 0.8 seconds
Started May 26 02:40:13 PM PDT 24
Finished May 26 02:40:15 PM PDT 24
Peak memory 204900 kb
Host smart-99f3af94-81fc-4ab8-b94e-7137220456e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570663884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1570663884
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3815449948
Short name T259
Test name
Test status
Simulation time 2252911837 ps
CPU time 22.5 seconds
Started May 26 02:40:19 PM PDT 24
Finished May 26 02:40:43 PM PDT 24
Peak memory 249412 kb
Host smart-cac0e10f-6fce-408d-9a63-ae86cda4645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815449948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3815449948
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.700497199
Short name T55
Test name
Test status
Simulation time 84776224611 ps
CPU time 201.6 seconds
Started May 26 02:40:18 PM PDT 24
Finished May 26 02:43:40 PM PDT 24
Peak memory 250936 kb
Host smart-7dc93098-7fa8-4174-a183-9be261649350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700497199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.700497199
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1636417028
Short name T610
Test name
Test status
Simulation time 96430204312 ps
CPU time 186.05 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:43:28 PM PDT 24
Peak memory 248740 kb
Host smart-e6fcc843-d6d9-4b53-9f61-4c91e66139a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636417028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1636417028
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1761560535
Short name T873
Test name
Test status
Simulation time 1252714064 ps
CPU time 7.9 seconds
Started May 26 02:40:19 PM PDT 24
Finished May 26 02:40:28 PM PDT 24
Peak memory 248980 kb
Host smart-b30186c2-33bb-4dbe-9e65-78dbffb288f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761560535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1761560535
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.619879579
Short name T561
Test name
Test status
Simulation time 823642656 ps
CPU time 4.92 seconds
Started May 26 02:40:25 PM PDT 24
Finished May 26 02:40:31 PM PDT 24
Peak memory 236676 kb
Host smart-1040ee5e-49e0-4d08-8bdc-960f13f48f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619879579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.619879579
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1582433445
Short name T711
Test name
Test status
Simulation time 14415974132 ps
CPU time 127.8 seconds
Started May 26 02:40:19 PM PDT 24
Finished May 26 02:42:28 PM PDT 24
Peak memory 248224 kb
Host smart-2e6e4ce6-dda5-4c77-977a-01e47a84618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582433445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1582433445
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1600301860
Short name T557
Test name
Test status
Simulation time 48584106 ps
CPU time 1.04 seconds
Started May 26 02:40:14 PM PDT 24
Finished May 26 02:40:16 PM PDT 24
Peak memory 217464 kb
Host smart-a1290b61-5fbb-4e9c-add8-85856661b94d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600301860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1600301860
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4007814477
Short name T687
Test name
Test status
Simulation time 19433811949 ps
CPU time 14.2 seconds
Started May 26 02:40:21 PM PDT 24
Finished May 26 02:40:36 PM PDT 24
Peak memory 233992 kb
Host smart-6a24e54b-91ea-4cb8-88d5-a695ee4ccaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007814477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4007814477
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1970296081
Short name T97
Test name
Test status
Simulation time 929765375 ps
CPU time 5.27 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:27 PM PDT 24
Peak memory 233460 kb
Host smart-3d74fc29-3418-42de-9f3c-b2b2c32913bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970296081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1970296081
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2824676211
Short name T662
Test name
Test status
Simulation time 1762957554 ps
CPU time 7.38 seconds
Started May 26 02:40:25 PM PDT 24
Finished May 26 02:40:33 PM PDT 24
Peak memory 219980 kb
Host smart-b158b2bd-5257-41fb-a00e-96718549fa8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2824676211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2824676211
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3140058604
Short name T154
Test name
Test status
Simulation time 3765681512 ps
CPU time 39.96 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:41:02 PM PDT 24
Peak memory 224280 kb
Host smart-9c0eb2bb-e191-45f8-8725-1152ca011738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140058604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3140058604
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.204757541
Short name T450
Test name
Test status
Simulation time 10648307 ps
CPU time 0.68 seconds
Started May 26 02:40:19 PM PDT 24
Finished May 26 02:40:21 PM PDT 24
Peak memory 205064 kb
Host smart-e5234193-7068-4f92-9b8a-e6ffa9b566a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204757541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.204757541
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1253401393
Short name T3
Test name
Test status
Simulation time 2949149370 ps
CPU time 6.18 seconds
Started May 26 02:40:18 PM PDT 24
Finished May 26 02:40:26 PM PDT 24
Peak memory 215916 kb
Host smart-93e63f88-20d8-4c66-89af-25f5e615e789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253401393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1253401393
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3044090486
Short name T478
Test name
Test status
Simulation time 145489432 ps
CPU time 2.57 seconds
Started May 26 02:40:21 PM PDT 24
Finished May 26 02:40:25 PM PDT 24
Peak memory 215892 kb
Host smart-0192c6e7-2cde-4352-8123-1931e96cd1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044090486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3044090486
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.745216802
Short name T684
Test name
Test status
Simulation time 17892936 ps
CPU time 0.73 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:28 PM PDT 24
Peak memory 205324 kb
Host smart-b23313fd-5eea-4f62-9d0f-2b860258a2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745216802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.745216802
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1663914527
Short name T274
Test name
Test status
Simulation time 1729164134 ps
CPU time 5.22 seconds
Started May 26 02:40:17 PM PDT 24
Finished May 26 02:40:23 PM PDT 24
Peak memory 232400 kb
Host smart-64c6b2bf-a6a5-4be3-8d29-2200f7e62631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663914527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1663914527
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2508502809
Short name T392
Test name
Test status
Simulation time 13765693 ps
CPU time 0.73 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 205240 kb
Host smart-5db0b3e5-df9e-4491-9df1-2a22b11a0426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508502809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
508502809
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1476790296
Short name T689
Test name
Test status
Simulation time 494769494 ps
CPU time 5.07 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:13 PM PDT 24
Peak memory 234120 kb
Host smart-4ee85472-30a7-4439-b298-b745acdf9920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476790296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1476790296
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1869556193
Short name T793
Test name
Test status
Simulation time 26975401 ps
CPU time 0.78 seconds
Started May 26 02:39:05 PM PDT 24
Finished May 26 02:39:06 PM PDT 24
Peak memory 206260 kb
Host smart-50bfb223-75ff-469d-8c2f-9c8927ce758a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869556193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1869556193
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.4007774007
Short name T177
Test name
Test status
Simulation time 95120917907 ps
CPU time 175.34 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 257020 kb
Host smart-96d04bdc-990d-47f9-87d1-d6fc6ce80ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007774007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.4007774007
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3492435639
Short name T642
Test name
Test status
Simulation time 1583198333 ps
CPU time 15.34 seconds
Started May 26 02:39:08 PM PDT 24
Finished May 26 02:39:24 PM PDT 24
Peak memory 217220 kb
Host smart-82b59db0-cf9e-41a7-89d2-868de141fcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492435639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3492435639
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.980746935
Short name T247
Test name
Test status
Simulation time 10721884324 ps
CPU time 108.84 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:40:57 PM PDT 24
Peak memory 249092 kb
Host smart-d440b130-042f-48a9-b60c-58ae4e5e8790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980746935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
980746935
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4155423568
Short name T941
Test name
Test status
Simulation time 3516900239 ps
CPU time 14.98 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:23 PM PDT 24
Peak memory 224224 kb
Host smart-74ebace2-bb09-49cb-ac19-5ccb39353de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155423568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4155423568
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2420458590
Short name T934
Test name
Test status
Simulation time 49717253 ps
CPU time 2.56 seconds
Started May 26 02:39:05 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 233548 kb
Host smart-e43ce86c-0d21-4887-9a1e-69cb1117152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420458590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2420458590
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3904154827
Short name T594
Test name
Test status
Simulation time 1020155581 ps
CPU time 12.07 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:39:21 PM PDT 24
Peak memory 238820 kb
Host smart-70a9974b-b0b9-4ef6-97c2-3c547ded9ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904154827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3904154827
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2484254598
Short name T714
Test name
Test status
Simulation time 25907867 ps
CPU time 1.01 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:08 PM PDT 24
Peak memory 217456 kb
Host smart-3ffcb4dc-e59e-4cba-9696-91414bb83654
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484254598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2484254598
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1541206364
Short name T668
Test name
Test status
Simulation time 489388231 ps
CPU time 4.94 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:39:14 PM PDT 24
Peak memory 233064 kb
Host smart-aeab36e1-e7f3-4ae0-848c-57cbbcdf18da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541206364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1541206364
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2106670378
Short name T652
Test name
Test status
Simulation time 534864927 ps
CPU time 5.97 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:39:15 PM PDT 24
Peak memory 233396 kb
Host smart-960beaa4-44cd-40b6-8ab3-43095ab16ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106670378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2106670378
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.302772528
Short name T605
Test name
Test status
Simulation time 1453179643 ps
CPU time 10.29 seconds
Started May 26 02:39:09 PM PDT 24
Finished May 26 02:39:20 PM PDT 24
Peak memory 221844 kb
Host smart-8a2ad4a3-f620-4ae9-a50e-495143b31af6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=302772528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.302772528
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2531424986
Short name T283
Test name
Test status
Simulation time 244367226173 ps
CPU time 228.68 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:42:57 PM PDT 24
Peak memory 255072 kb
Host smart-c84f96c3-3572-49c1-9661-71851aeb7913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531424986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2531424986
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1763289767
Short name T388
Test name
Test status
Simulation time 24214731588 ps
CPU time 19.69 seconds
Started May 26 02:39:06 PM PDT 24
Finished May 26 02:39:28 PM PDT 24
Peak memory 216032 kb
Host smart-469efb9c-aa6c-43f0-ae4f-2ca0924c725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763289767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1763289767
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.389259299
Short name T497
Test name
Test status
Simulation time 3757039959 ps
CPU time 5.6 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:39:14 PM PDT 24
Peak memory 215920 kb
Host smart-2ca8ddf6-b5b2-4ca2-ae8d-bdec2872504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389259299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.389259299
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1290798877
Short name T269
Test name
Test status
Simulation time 117066525 ps
CPU time 2.75 seconds
Started May 26 02:39:05 PM PDT 24
Finished May 26 02:39:08 PM PDT 24
Peak memory 215948 kb
Host smart-6a3c546f-9fd8-4b77-9ee6-862bad0d51c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290798877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1290798877
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1911735616
Short name T790
Test name
Test status
Simulation time 97904258 ps
CPU time 0.99 seconds
Started May 26 02:39:07 PM PDT 24
Finished May 26 02:39:10 PM PDT 24
Peak memory 205300 kb
Host smart-eac2ed15-239a-480c-be00-328e6e30f598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911735616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1911735616
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3483337040
Short name T836
Test name
Test status
Simulation time 5853517232 ps
CPU time 9.85 seconds
Started May 26 02:39:05 PM PDT 24
Finished May 26 02:39:17 PM PDT 24
Peak memory 230280 kb
Host smart-86a0f353-2d1d-4920-8186-8b31a9a5d53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483337040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3483337040
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.641139598
Short name T446
Test name
Test status
Simulation time 79170484 ps
CPU time 0.69 seconds
Started May 26 02:40:21 PM PDT 24
Finished May 26 02:40:23 PM PDT 24
Peak memory 204296 kb
Host smart-b6076ccd-52fa-43e8-b10f-efeb123b8164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641139598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.641139598
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3399083484
Short name T779
Test name
Test status
Simulation time 57537365 ps
CPU time 2 seconds
Started May 26 02:40:25 PM PDT 24
Finished May 26 02:40:28 PM PDT 24
Peak memory 215724 kb
Host smart-e20682bb-f187-48cf-bae3-901b2f51a433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399083484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3399083484
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1673609345
Short name T742
Test name
Test status
Simulation time 21891785 ps
CPU time 0.75 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:23 PM PDT 24
Peak memory 204908 kb
Host smart-a4b5e633-6283-40b9-8174-7eeaf019cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673609345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1673609345
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2896305154
Short name T686
Test name
Test status
Simulation time 10687555 ps
CPU time 0.74 seconds
Started May 26 02:40:18 PM PDT 24
Finished May 26 02:40:19 PM PDT 24
Peak memory 215448 kb
Host smart-16ab0ede-a6e7-43f7-bc3f-299c67f98114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896305154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2896305154
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1798209439
Short name T231
Test name
Test status
Simulation time 5325040262 ps
CPU time 103.83 seconds
Started May 26 02:40:25 PM PDT 24
Finished May 26 02:42:09 PM PDT 24
Peak memory 273520 kb
Host smart-3643b2bc-3250-40cf-90f3-04a4c225b5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798209439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1798209439
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4279364516
Short name T571
Test name
Test status
Simulation time 6742714774 ps
CPU time 34.74 seconds
Started May 26 02:40:25 PM PDT 24
Finished May 26 02:41:01 PM PDT 24
Peak memory 248312 kb
Host smart-a68dd04b-1862-4423-af31-144230a0b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279364516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4279364516
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1867222985
Short name T704
Test name
Test status
Simulation time 1101770402 ps
CPU time 19.08 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:46 PM PDT 24
Peak memory 224216 kb
Host smart-b6b2824d-4e4d-4936-a5f1-567ecedb577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867222985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1867222985
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.967258221
Short name T93
Test name
Test status
Simulation time 6777514832 ps
CPU time 13.78 seconds
Started May 26 02:40:19 PM PDT 24
Finished May 26 02:40:34 PM PDT 24
Peak memory 233488 kb
Host smart-4c604495-62e5-4944-a385-12f681264126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967258221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.967258221
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2341929668
Short name T300
Test name
Test status
Simulation time 4154959759 ps
CPU time 19.83 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 219508 kb
Host smart-33771e27-e1af-4bab-8a27-089384e663da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341929668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2341929668
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.572405708
Short name T747
Test name
Test status
Simulation time 1090872645 ps
CPU time 7.35 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:29 PM PDT 24
Peak memory 248976 kb
Host smart-b9771918-3264-43bd-97f9-1781b05bf2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572405708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.572405708
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3040769390
Short name T760
Test name
Test status
Simulation time 55218456 ps
CPU time 1.94 seconds
Started May 26 02:40:22 PM PDT 24
Finished May 26 02:40:25 PM PDT 24
Peak memory 215764 kb
Host smart-b5ab29f2-248f-48cf-a260-354209182bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040769390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3040769390
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3601565893
Short name T456
Test name
Test status
Simulation time 365913928 ps
CPU time 3.61 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:25 PM PDT 24
Peak memory 220292 kb
Host smart-0633c9fe-56b4-4103-bf1c-e2e5187dc3bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3601565893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3601565893
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2526661509
Short name T692
Test name
Test status
Simulation time 5211319129 ps
CPU time 74.3 seconds
Started May 26 02:40:19 PM PDT 24
Finished May 26 02:41:35 PM PDT 24
Peak memory 256748 kb
Host smart-e94932f6-3736-44f3-b1de-1118ad7aef48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526661509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2526661509
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2002653505
Short name T161
Test name
Test status
Simulation time 12716214906 ps
CPU time 18.04 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:39 PM PDT 24
Peak memory 215944 kb
Host smart-abf3bc64-03ec-497d-b540-1e89428db748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002653505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2002653505
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3944813459
Short name T79
Test name
Test status
Simulation time 4173837037 ps
CPU time 5.76 seconds
Started May 26 02:40:21 PM PDT 24
Finished May 26 02:40:28 PM PDT 24
Peak memory 215916 kb
Host smart-4aa6d981-8a9f-4dfa-8c26-e6cdc070094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944813459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3944813459
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3693552725
Short name T724
Test name
Test status
Simulation time 243322400 ps
CPU time 3.06 seconds
Started May 26 02:40:22 PM PDT 24
Finished May 26 02:40:26 PM PDT 24
Peak memory 216140 kb
Host smart-16369a9e-177e-4897-af59-0f27870fbcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693552725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3693552725
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3972195751
Short name T414
Test name
Test status
Simulation time 1011874989 ps
CPU time 0.91 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:30 PM PDT 24
Peak memory 206344 kb
Host smart-9d992f6e-05c4-49e8-afc2-f076be9dadce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972195751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3972195751
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2965640248
Short name T468
Test name
Test status
Simulation time 153036842 ps
CPU time 2.05 seconds
Started May 26 02:40:19 PM PDT 24
Finished May 26 02:40:23 PM PDT 24
Peak memory 220356 kb
Host smart-b85b6dc1-a1a2-4a28-9582-bd60282a50fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965640248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2965640248
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2992660177
Short name T344
Test name
Test status
Simulation time 13054501 ps
CPU time 0.73 seconds
Started May 26 02:40:30 PM PDT 24
Finished May 26 02:40:31 PM PDT 24
Peak memory 205264 kb
Host smart-f6a76957-4452-42b9-a63d-9aa203a4eb0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992660177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2992660177
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1888798179
Short name T371
Test name
Test status
Simulation time 976297878 ps
CPU time 6.64 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:36 PM PDT 24
Peak memory 219336 kb
Host smart-7feb6977-312e-47ef-89b2-db0cd25fc5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888798179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1888798179
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3531528355
Short name T516
Test name
Test status
Simulation time 20892115 ps
CPU time 0.82 seconds
Started May 26 02:40:20 PM PDT 24
Finished May 26 02:40:23 PM PDT 24
Peak memory 206276 kb
Host smart-f7b402ae-5ed7-4f91-b3bb-55cabf5f40e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531528355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3531528355
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2375800882
Short name T751
Test name
Test status
Simulation time 15242976025 ps
CPU time 54.45 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 237108 kb
Host smart-0b7e1441-1ab6-48e7-9a60-3d327bedbce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375800882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2375800882
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2997432088
Short name T224
Test name
Test status
Simulation time 2688234843 ps
CPU time 57.36 seconds
Started May 26 02:40:26 PM PDT 24
Finished May 26 02:41:25 PM PDT 24
Peak memory 249672 kb
Host smart-41bc5f63-466a-4cd9-b3f6-1ebad840c77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997432088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2997432088
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1413662884
Short name T718
Test name
Test status
Simulation time 6299146978 ps
CPU time 14.38 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:43 PM PDT 24
Peak memory 216980 kb
Host smart-88128497-0773-4f51-b723-540dde604588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413662884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1413662884
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2579232745
Short name T729
Test name
Test status
Simulation time 1511011018 ps
CPU time 11.34 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 240608 kb
Host smart-a777e934-c537-4e2d-8787-261b2ff26a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579232745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2579232745
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.704515788
Short name T897
Test name
Test status
Simulation time 2705465481 ps
CPU time 8.53 seconds
Started May 26 02:40:18 PM PDT 24
Finished May 26 02:40:29 PM PDT 24
Peak memory 233880 kb
Host smart-14b5d3ec-ba38-402d-aff6-6e28dc0bb7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704515788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.704515788
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.364475000
Short name T474
Test name
Test status
Simulation time 163173574 ps
CPU time 3.97 seconds
Started May 26 02:40:25 PM PDT 24
Finished May 26 02:40:30 PM PDT 24
Peak memory 218428 kb
Host smart-bdfe3b6f-509e-4154-bc9e-c7e8d619d4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364475000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.364475000
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.211312241
Short name T382
Test name
Test status
Simulation time 176573543 ps
CPU time 2.2 seconds
Started May 26 02:40:21 PM PDT 24
Finished May 26 02:40:25 PM PDT 24
Peak memory 215708 kb
Host smart-fec5e96d-89f7-4d07-83c4-3463e86f5e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211312241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.211312241
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.943655309
Short name T856
Test name
Test status
Simulation time 928608009 ps
CPU time 4.15 seconds
Started May 26 02:40:25 PM PDT 24
Finished May 26 02:40:30 PM PDT 24
Peak memory 233328 kb
Host smart-a7b8b8cb-c4fe-4ad3-b287-4a78814df2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943655309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.943655309
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1006749707
Short name T671
Test name
Test status
Simulation time 4762436714 ps
CPU time 14.77 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:43 PM PDT 24
Peak memory 222632 kb
Host smart-f4defbef-a1ae-4bd0-a90f-e94c5cb40ce4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1006749707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1006749707
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2439566748
Short name T254
Test name
Test status
Simulation time 32904047252 ps
CPU time 159.62 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:43:09 PM PDT 24
Peak memory 281144 kb
Host smart-343cd1e0-aeb6-4924-b041-5a01f4ad12f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439566748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2439566748
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.933078129
Short name T691
Test name
Test status
Simulation time 1149998867 ps
CPU time 11.16 seconds
Started May 26 02:40:25 PM PDT 24
Finished May 26 02:40:37 PM PDT 24
Peak memory 216028 kb
Host smart-943172fb-f257-42eb-b8a2-8462b0218faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933078129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.933078129
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.640664425
Short name T917
Test name
Test status
Simulation time 159823129 ps
CPU time 1.76 seconds
Started May 26 02:40:21 PM PDT 24
Finished May 26 02:40:24 PM PDT 24
Peak memory 207440 kb
Host smart-7e321843-0ca9-4002-8c8d-a0a3d4965f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640664425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.640664425
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2787208896
Short name T730
Test name
Test status
Simulation time 723245398 ps
CPU time 2.13 seconds
Started May 26 02:40:19 PM PDT 24
Finished May 26 02:40:23 PM PDT 24
Peak memory 217112 kb
Host smart-d282b559-400d-484d-bf18-be6471e06beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787208896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2787208896
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1001579243
Short name T324
Test name
Test status
Simulation time 96968276 ps
CPU time 0.86 seconds
Started May 26 02:40:24 PM PDT 24
Finished May 26 02:40:26 PM PDT 24
Peak memory 205312 kb
Host smart-aceab8c4-6761-4a40-99ad-f9fe63e1daac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001579243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1001579243
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2018688742
Short name T864
Test name
Test status
Simulation time 6711347327 ps
CPU time 24.35 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:54 PM PDT 24
Peak memory 233884 kb
Host smart-802430cb-c12d-430d-a447-961e3663468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018688742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2018688742
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1095699391
Short name T801
Test name
Test status
Simulation time 90956210 ps
CPU time 0.77 seconds
Started May 26 02:40:30 PM PDT 24
Finished May 26 02:40:32 PM PDT 24
Peak memory 204292 kb
Host smart-fb760215-3ad9-4378-a4fe-9bccde14ab9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095699391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1095699391
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1292690773
Short name T952
Test name
Test status
Simulation time 193837962 ps
CPU time 2.45 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:31 PM PDT 24
Peak memory 235288 kb
Host smart-c44b260a-0380-4b31-8103-255683809eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292690773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1292690773
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2198475877
Short name T476
Test name
Test status
Simulation time 71608367 ps
CPU time 0.79 seconds
Started May 26 02:40:30 PM PDT 24
Finished May 26 02:40:32 PM PDT 24
Peak memory 206264 kb
Host smart-d60f3395-2fc7-4767-a453-01a2e815d5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198475877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2198475877
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1185794892
Short name T14
Test name
Test status
Simulation time 17727994843 ps
CPU time 33.55 seconds
Started May 26 02:40:26 PM PDT 24
Finished May 26 02:41:01 PM PDT 24
Peak memory 234748 kb
Host smart-b92e0349-7e79-49bc-baf5-5da2f427d0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185794892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1185794892
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2954343945
Short name T281
Test name
Test status
Simulation time 86825153911 ps
CPU time 226.68 seconds
Started May 26 02:40:33 PM PDT 24
Finished May 26 02:44:21 PM PDT 24
Peak memory 257080 kb
Host smart-014b228f-daed-4e7c-9825-b7767ac51ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954343945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2954343945
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2012435848
Short name T261
Test name
Test status
Simulation time 26145972167 ps
CPU time 135.53 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:42:45 PM PDT 24
Peak memory 249992 kb
Host smart-4859c0c7-5231-4adb-9a51-7f5bcd6ca46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012435848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2012435848
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2019284364
Short name T924
Test name
Test status
Simulation time 2041460383 ps
CPU time 28.28 seconds
Started May 26 02:40:29 PM PDT 24
Finished May 26 02:40:58 PM PDT 24
Peak memory 232400 kb
Host smart-d346e3ce-e3d9-4bb1-9887-e77c87125771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019284364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2019284364
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2497075175
Short name T441
Test name
Test status
Simulation time 1682008341 ps
CPU time 20.71 seconds
Started May 26 02:40:29 PM PDT 24
Finished May 26 02:40:51 PM PDT 24
Peak memory 224140 kb
Host smart-c966c58d-928c-4491-aa2e-50db4571a6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497075175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2497075175
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4200394739
Short name T544
Test name
Test status
Simulation time 5629183103 ps
CPU time 18.58 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:48 PM PDT 24
Peak memory 218580 kb
Host smart-8d72ae2d-059c-46ff-b274-3dc08fdb3582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200394739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4200394739
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2054209274
Short name T781
Test name
Test status
Simulation time 2664134140 ps
CPU time 8.85 seconds
Started May 26 02:40:30 PM PDT 24
Finished May 26 02:40:40 PM PDT 24
Peak memory 226680 kb
Host smart-135a8da5-307c-4230-8832-d4e8159c1f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054209274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2054209274
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2084406632
Short name T552
Test name
Test status
Simulation time 1602462552 ps
CPU time 4.26 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:34 PM PDT 24
Peak memory 218156 kb
Host smart-b5a86093-2aaa-4d7d-a693-8055c89e856c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084406632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2084406632
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.427528002
Short name T811
Test name
Test status
Simulation time 391250322 ps
CPU time 4.18 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:32 PM PDT 24
Peak memory 218568 kb
Host smart-10dbccd0-650c-40e6-9283-d0d44889ace1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=427528002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.427528002
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.655572989
Short name T351
Test name
Test status
Simulation time 3248939132 ps
CPU time 11.18 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 216124 kb
Host smart-fc650a16-cee6-4f66-b02b-be8c9e59f5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655572989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.655572989
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3351024212
Short name T768
Test name
Test status
Simulation time 4234090486 ps
CPU time 7.37 seconds
Started May 26 02:40:31 PM PDT 24
Finished May 26 02:40:39 PM PDT 24
Peak memory 215936 kb
Host smart-17bb1a77-ede7-4e5a-b888-17cfeabdb170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351024212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3351024212
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2312997593
Short name T333
Test name
Test status
Simulation time 174624029 ps
CPU time 1.36 seconds
Started May 26 02:40:35 PM PDT 24
Finished May 26 02:40:38 PM PDT 24
Peak memory 215912 kb
Host smart-6b572792-30eb-447b-ae3b-d6fde66ea552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312997593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2312997593
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3138843082
Short name T921
Test name
Test status
Simulation time 48733942 ps
CPU time 0.81 seconds
Started May 26 02:40:30 PM PDT 24
Finished May 26 02:40:32 PM PDT 24
Peak memory 205304 kb
Host smart-6632fd50-4424-438a-b428-7715c7b2d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138843082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3138843082
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2049833126
Short name T209
Test name
Test status
Simulation time 13984827446 ps
CPU time 47.2 seconds
Started May 26 02:40:29 PM PDT 24
Finished May 26 02:41:17 PM PDT 24
Peak memory 250504 kb
Host smart-d5bfcd28-d1ae-4b8b-8a50-05a6d5c31f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049833126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2049833126
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4068543991
Short name T882
Test name
Test status
Simulation time 36060457 ps
CPU time 0.71 seconds
Started May 26 02:40:36 PM PDT 24
Finished May 26 02:40:39 PM PDT 24
Peak memory 204880 kb
Host smart-da414ba8-c23e-4a99-84eb-2a1c568fae57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068543991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4068543991
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2975130538
Short name T460
Test name
Test status
Simulation time 492681264 ps
CPU time 3.31 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:32 PM PDT 24
Peak memory 234128 kb
Host smart-a80ac7d9-fb42-4029-992c-7c54777abd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975130538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2975130538
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3405811053
Short name T66
Test name
Test status
Simulation time 233355074 ps
CPU time 0.74 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:29 PM PDT 24
Peak memory 206236 kb
Host smart-6eb5b26c-58f7-42e2-b2ea-a8928c61801a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405811053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3405811053
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3312318389
Short name T264
Test name
Test status
Simulation time 87831680115 ps
CPU time 584.24 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:50:14 PM PDT 24
Peak memory 251776 kb
Host smart-061c1453-ba39-474e-a222-103ee2b47517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312318389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3312318389
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1750771750
Short name T193
Test name
Test status
Simulation time 37109895299 ps
CPU time 377.8 seconds
Started May 26 02:40:37 PM PDT 24
Finished May 26 02:46:57 PM PDT 24
Peak memory 257112 kb
Host smart-a6f5beaa-2ec2-407e-a17b-48b15510b242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750771750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1750771750
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4020858399
Short name T284
Test name
Test status
Simulation time 992029932 ps
CPU time 6.07 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:36 PM PDT 24
Peak memory 224192 kb
Host smart-3fdf27a3-688c-4539-b9c0-0682b763c88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020858399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4020858399
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2161141858
Short name T690
Test name
Test status
Simulation time 1632585769 ps
CPU time 19.63 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:49 PM PDT 24
Peak memory 219508 kb
Host smart-43ea5158-628e-4125-98f6-e1739a190304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161141858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2161141858
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1831157383
Short name T861
Test name
Test status
Simulation time 2252160016 ps
CPU time 28.6 seconds
Started May 26 02:40:31 PM PDT 24
Finished May 26 02:41:00 PM PDT 24
Peak memory 218348 kb
Host smart-b04ffa86-f7ca-4e7d-b770-84aa46940baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831157383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1831157383
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.486392813
Short name T265
Test name
Test status
Simulation time 84194434 ps
CPU time 2.52 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:32 PM PDT 24
Peak memory 216440 kb
Host smart-83cb6cb4-558f-43e6-92ea-93e29ef9feb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486392813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.486392813
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1499829188
Short name T823
Test name
Test status
Simulation time 59912792 ps
CPU time 2.36 seconds
Started May 26 02:40:33 PM PDT 24
Finished May 26 02:40:37 PM PDT 24
Peak memory 220804 kb
Host smart-771015e6-e637-4bf2-b0f9-9ac5ea5b4edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499829188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1499829188
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2933378668
Short name T512
Test name
Test status
Simulation time 1347263572 ps
CPU time 6.47 seconds
Started May 26 02:40:27 PM PDT 24
Finished May 26 02:40:35 PM PDT 24
Peak memory 218484 kb
Host smart-327f3faf-70b9-4e4f-80b3-e5ae2571bc28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2933378668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2933378668
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1414223791
Short name T234
Test name
Test status
Simulation time 127514314343 ps
CPU time 343.85 seconds
Started May 26 02:40:36 PM PDT 24
Finished May 26 02:46:23 PM PDT 24
Peak memory 269720 kb
Host smart-40360f20-bdcc-491d-96df-530b86f74bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414223791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1414223791
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2292485419
Short name T320
Test name
Test status
Simulation time 312878525 ps
CPU time 2.84 seconds
Started May 26 02:40:33 PM PDT 24
Finished May 26 02:40:37 PM PDT 24
Peak memory 215892 kb
Host smart-62c930b8-faea-4a17-a98d-d133274b7818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292485419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2292485419
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2441601060
Short name T778
Test name
Test status
Simulation time 1733407562 ps
CPU time 6.3 seconds
Started May 26 02:40:28 PM PDT 24
Finished May 26 02:40:36 PM PDT 24
Peak memory 215796 kb
Host smart-372bef82-1d7d-45bd-9e90-d41014380a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441601060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2441601060
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1049554576
Short name T965
Test name
Test status
Simulation time 92215037 ps
CPU time 1.24 seconds
Started May 26 02:40:29 PM PDT 24
Finished May 26 02:40:32 PM PDT 24
Peak memory 207564 kb
Host smart-177d7f6f-27ce-4ea4-acd0-a0ed0d29a2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049554576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1049554576
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.535725039
Short name T374
Test name
Test status
Simulation time 232585143 ps
CPU time 0.89 seconds
Started May 26 02:40:26 PM PDT 24
Finished May 26 02:40:28 PM PDT 24
Peak memory 205308 kb
Host smart-f5494dcd-4abe-48a2-b115-c9be2333f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535725039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.535725039
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.895338421
Short name T223
Test name
Test status
Simulation time 45919320594 ps
CPU time 16.95 seconds
Started May 26 02:40:30 PM PDT 24
Finished May 26 02:40:48 PM PDT 24
Peak memory 233148 kb
Host smart-18f57455-be2e-441e-9abb-496ece59c9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895338421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.895338421
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3737393288
Short name T653
Test name
Test status
Simulation time 19396145 ps
CPU time 0.69 seconds
Started May 26 02:40:37 PM PDT 24
Finished May 26 02:40:40 PM PDT 24
Peak memory 204868 kb
Host smart-cc2dd40c-698b-4d1c-b974-9661e34f2db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737393288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3737393288
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2232286463
Short name T827
Test name
Test status
Simulation time 124548165 ps
CPU time 2.42 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:42 PM PDT 24
Peak memory 231644 kb
Host smart-40164816-c2f0-4bcf-a9d1-dc60794fdccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232286463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2232286463
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.512595646
Short name T894
Test name
Test status
Simulation time 33318684 ps
CPU time 0.74 seconds
Started May 26 02:40:37 PM PDT 24
Finished May 26 02:40:40 PM PDT 24
Peak memory 205248 kb
Host smart-7bcaeb71-152b-4c2e-be9d-02141415bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512595646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.512595646
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.87837044
Short name T228
Test name
Test status
Simulation time 22981142397 ps
CPU time 80.57 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:42:01 PM PDT 24
Peak memory 249480 kb
Host smart-6f51f3ca-2a41-4bd9-8a55-acec4d27b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87837044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.87837044
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4101208743
Short name T236
Test name
Test status
Simulation time 49814973329 ps
CPU time 53.51 seconds
Started May 26 02:40:35 PM PDT 24
Finished May 26 02:41:30 PM PDT 24
Peak memory 252560 kb
Host smart-9a08dba4-4f5b-4e0e-94bc-99a4ed89b99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101208743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4101208743
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2786079590
Short name T507
Test name
Test status
Simulation time 309697113 ps
CPU time 3.5 seconds
Started May 26 02:40:36 PM PDT 24
Finished May 26 02:40:42 PM PDT 24
Peak memory 238580 kb
Host smart-ee9881fc-ee40-4d1e-bdb0-f15cd601a18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786079590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2786079590
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2757119774
Short name T787
Test name
Test status
Simulation time 1487938815 ps
CPU time 7.3 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:47 PM PDT 24
Peak memory 233336 kb
Host smart-b258a697-6c1b-4554-b0b8-e4c999b08730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757119774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2757119774
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4130705933
Short name T542
Test name
Test status
Simulation time 5854461925 ps
CPU time 53.19 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:41:33 PM PDT 24
Peak memory 228732 kb
Host smart-a8fa0946-604d-405e-92a7-278b341d4f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130705933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4130705933
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1703027378
Short name T406
Test name
Test status
Simulation time 99781225 ps
CPU time 2.11 seconds
Started May 26 02:40:34 PM PDT 24
Finished May 26 02:40:37 PM PDT 24
Peak memory 215768 kb
Host smart-d1c06810-acbf-48d5-b7e7-ec5adeddbc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703027378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1703027378
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3118526340
Short name T418
Test name
Test status
Simulation time 140354190 ps
CPU time 2.67 seconds
Started May 26 02:40:40 PM PDT 24
Finished May 26 02:40:44 PM PDT 24
Peak memory 232328 kb
Host smart-bd8afafd-9618-4ba2-ba3b-2df526c243cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118526340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3118526340
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1248313415
Short name T874
Test name
Test status
Simulation time 106717212 ps
CPU time 3.6 seconds
Started May 26 02:40:35 PM PDT 24
Finished May 26 02:40:40 PM PDT 24
Peak memory 222696 kb
Host smart-7c2fc8a7-08cd-4a32-b6e2-3b6febece34e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1248313415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1248313415
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2641956776
Short name T639
Test name
Test status
Simulation time 50553090 ps
CPU time 0.97 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 206092 kb
Host smart-654a3a23-b010-40fa-8062-3f432a8a916d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641956776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2641956776
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3810536448
Short name T592
Test name
Test status
Simulation time 4072364390 ps
CPU time 26.1 seconds
Started May 26 02:40:37 PM PDT 24
Finished May 26 02:41:06 PM PDT 24
Peak memory 216024 kb
Host smart-493fb47d-5714-43bf-ab9b-17e2bcf92392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810536448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3810536448
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1328804025
Short name T433
Test name
Test status
Simulation time 11881853820 ps
CPU time 16.06 seconds
Started May 26 02:40:40 PM PDT 24
Finished May 26 02:40:57 PM PDT 24
Peak memory 215892 kb
Host smart-c5e0ff00-254b-497e-9c4c-d5d6d8b620a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328804025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1328804025
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2127592628
Short name T771
Test name
Test status
Simulation time 21206570 ps
CPU time 0.83 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 205020 kb
Host smart-9c0459d3-9c9d-43e7-aff9-6ba835df178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127592628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2127592628
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3668774512
Short name T581
Test name
Test status
Simulation time 17579645 ps
CPU time 0.74 seconds
Started May 26 02:40:43 PM PDT 24
Finished May 26 02:40:45 PM PDT 24
Peak memory 205312 kb
Host smart-001d4e50-b6cc-4b3f-8765-ed12a666317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668774512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3668774512
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.980224402
Short name T539
Test name
Test status
Simulation time 190906917 ps
CPU time 2.16 seconds
Started May 26 02:40:40 PM PDT 24
Finished May 26 02:40:43 PM PDT 24
Peak memory 215820 kb
Host smart-f4402bc9-7bec-4eb3-b217-783f16335831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980224402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.980224402
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3472803102
Short name T500
Test name
Test status
Simulation time 17389471 ps
CPU time 0.75 seconds
Started May 26 02:40:41 PM PDT 24
Finished May 26 02:40:43 PM PDT 24
Peak memory 204940 kb
Host smart-2dcf0b58-a10b-4c2a-83ad-2eb388522af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472803102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3472803102
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1896002883
Short name T904
Test name
Test status
Simulation time 600625610 ps
CPU time 3.8 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:44 PM PDT 24
Peak memory 232536 kb
Host smart-7de57d6f-7c9c-4c21-b674-d6d6ef90b350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896002883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1896002883
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1206148664
Short name T403
Test name
Test status
Simulation time 34940937 ps
CPU time 0.83 seconds
Started May 26 02:40:44 PM PDT 24
Finished May 26 02:40:45 PM PDT 24
Peak memory 206072 kb
Host smart-e4c81eb9-1ddd-45eb-a927-6af5ee526e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206148664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1206148664
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2778916285
Short name T30
Test name
Test status
Simulation time 14607779552 ps
CPU time 49.63 seconds
Started May 26 02:40:41 PM PDT 24
Finished May 26 02:41:32 PM PDT 24
Peak memory 248848 kb
Host smart-65e497e5-cf64-4097-81ec-891064733cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778916285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2778916285
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3041932026
Short name T473
Test name
Test status
Simulation time 15634241627 ps
CPU time 30.53 seconds
Started May 26 02:40:41 PM PDT 24
Finished May 26 02:41:12 PM PDT 24
Peak memory 249616 kb
Host smart-3d486b02-96cd-414a-9079-5247bcd979d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041932026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3041932026
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1190951922
Short name T647
Test name
Test status
Simulation time 30922968682 ps
CPU time 55.97 seconds
Started May 26 02:40:35 PM PDT 24
Finished May 26 02:41:33 PM PDT 24
Peak memory 248792 kb
Host smart-27472a7d-5d8c-450a-8ca0-e8ce3a4ac24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190951922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1190951922
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1822842381
Short name T573
Test name
Test status
Simulation time 289145060 ps
CPU time 3.16 seconds
Started May 26 02:40:36 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 224160 kb
Host smart-d26a91df-d35d-4207-a441-3bfd4ca6d8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822842381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1822842381
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1863261396
Short name T527
Test name
Test status
Simulation time 284514530 ps
CPU time 4.64 seconds
Started May 26 02:40:35 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 233208 kb
Host smart-06e797b4-140b-4652-8bfe-1ab2e2a69b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863261396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1863261396
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1229900929
Short name T604
Test name
Test status
Simulation time 1707958081 ps
CPU time 20.72 seconds
Started May 26 02:40:37 PM PDT 24
Finished May 26 02:41:00 PM PDT 24
Peak memory 245788 kb
Host smart-504dc9bf-c49e-45b9-b3a1-76600f582043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229900929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1229900929
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2963874227
Short name T487
Test name
Test status
Simulation time 275547922 ps
CPU time 6.2 seconds
Started May 26 02:40:37 PM PDT 24
Finished May 26 02:40:45 PM PDT 24
Peak memory 233248 kb
Host smart-381be0bb-3a59-4fe0-96d5-177d5426e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963874227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2963874227
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.147690661
Short name T293
Test name
Test status
Simulation time 2560406146 ps
CPU time 8.37 seconds
Started May 26 02:40:35 PM PDT 24
Finished May 26 02:40:44 PM PDT 24
Peak memory 218284 kb
Host smart-eda2f35f-934c-4b0e-b37a-b2333cf8372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147690661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.147690661
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.993292825
Short name T622
Test name
Test status
Simulation time 186651199 ps
CPU time 3.59 seconds
Started May 26 02:40:40 PM PDT 24
Finished May 26 02:40:45 PM PDT 24
Peak memory 222596 kb
Host smart-bcc9ad4f-34d0-4555-a688-59315c531480
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=993292825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.993292825
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2784643822
Short name T637
Test name
Test status
Simulation time 17554850301 ps
CPU time 47.47 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:41:27 PM PDT 24
Peak memory 215996 kb
Host smart-aa3b60ed-a2a0-4f4f-bef6-3b009f084e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784643822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2784643822
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1338802533
Short name T720
Test name
Test status
Simulation time 13466912682 ps
CPU time 10.12 seconds
Started May 26 02:40:40 PM PDT 24
Finished May 26 02:40:51 PM PDT 24
Peak memory 216076 kb
Host smart-b35fbc87-d0fe-405b-b18c-1e080df02c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338802533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1338802533
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3154856085
Short name T585
Test name
Test status
Simulation time 23424873 ps
CPU time 0.8 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 205552 kb
Host smart-76663580-d1d6-4678-a06e-70882089c839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154856085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3154856085
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1129665315
Short name T42
Test name
Test status
Simulation time 25674649 ps
CPU time 0.69 seconds
Started May 26 02:40:35 PM PDT 24
Finished May 26 02:40:38 PM PDT 24
Peak memory 205276 kb
Host smart-6e03a905-0582-4416-bfa8-997486e90909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129665315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1129665315
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1949909182
Short name T943
Test name
Test status
Simulation time 335837605 ps
CPU time 5.68 seconds
Started May 26 02:40:36 PM PDT 24
Finished May 26 02:40:44 PM PDT 24
Peak memory 218580 kb
Host smart-6fdc5f4b-610c-4d06-a2a1-aa2abaa2f818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949909182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1949909182
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.479441227
Short name T845
Test name
Test status
Simulation time 37395377 ps
CPU time 0.75 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:40:49 PM PDT 24
Peak memory 204456 kb
Host smart-8e20fc06-2334-48c0-abb1-976f77bea8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479441227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.479441227
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.426653862
Short name T713
Test name
Test status
Simulation time 218648751 ps
CPU time 3.78 seconds
Started May 26 02:40:51 PM PDT 24
Finished May 26 02:40:56 PM PDT 24
Peak memory 234940 kb
Host smart-a32160d5-30b1-471e-b33a-855784a14f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426653862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.426653862
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2985172544
Short name T367
Test name
Test status
Simulation time 21123075 ps
CPU time 0.74 seconds
Started May 26 02:40:36 PM PDT 24
Finished May 26 02:40:39 PM PDT 24
Peak memory 205896 kb
Host smart-75e930cc-04e5-4253-a2b3-3bfdd3be4975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985172544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2985172544
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2778745929
Short name T891
Test name
Test status
Simulation time 342667416416 ps
CPU time 163.28 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:43:31 PM PDT 24
Peak memory 248844 kb
Host smart-00529812-35e9-408f-ada1-4fa42b146178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778745929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2778745929
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3175863986
Short name T629
Test name
Test status
Simulation time 38236597545 ps
CPU time 56.91 seconds
Started May 26 02:40:51 PM PDT 24
Finished May 26 02:41:49 PM PDT 24
Peak memory 248896 kb
Host smart-fcf8ebd0-22d6-477a-a8e0-64b062cd3d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175863986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3175863986
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3171406201
Short name T43
Test name
Test status
Simulation time 125684685049 ps
CPU time 251.23 seconds
Started May 26 02:40:49 PM PDT 24
Finished May 26 02:45:01 PM PDT 24
Peak memory 248864 kb
Host smart-504dc5fb-ecb9-4d2d-9fe7-065a1fa912e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171406201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3171406201
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3089619860
Short name T426
Test name
Test status
Simulation time 1352306740 ps
CPU time 14.11 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:41:03 PM PDT 24
Peak memory 240552 kb
Host smart-b4e8d384-642b-48ef-904e-e743f9d36894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089619860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3089619860
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2406631178
Short name T863
Test name
Test status
Simulation time 311670403 ps
CPU time 4.41 seconds
Started May 26 02:40:37 PM PDT 24
Finished May 26 02:40:44 PM PDT 24
Peak memory 232364 kb
Host smart-5cd00ba8-d9a2-41ea-a07f-fef87ee273b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406631178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2406631178
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.620288549
Short name T423
Test name
Test status
Simulation time 2358274335 ps
CPU time 10.73 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:51 PM PDT 24
Peak memory 227128 kb
Host smart-0ae53577-4e01-49ef-a96f-1fc5aa4bd48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620288549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.620288549
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4208168235
Short name T677
Test name
Test status
Simulation time 296013321 ps
CPU time 2.12 seconds
Started May 26 02:40:35 PM PDT 24
Finished May 26 02:40:38 PM PDT 24
Peak memory 215768 kb
Host smart-1e299c39-a288-412d-9baa-1ad1d3ab436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208168235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4208168235
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2675324358
Short name T399
Test name
Test status
Simulation time 301438061 ps
CPU time 5.25 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:46 PM PDT 24
Peak memory 233480 kb
Host smart-3f231f68-3449-4dee-9714-cb66ea3220c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675324358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2675324358
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2470992447
Short name T663
Test name
Test status
Simulation time 2394434262 ps
CPU time 14.33 seconds
Started May 26 02:40:50 PM PDT 24
Finished May 26 02:41:06 PM PDT 24
Peak memory 218948 kb
Host smart-99561bfc-01c2-47a6-88e8-505f3361ac16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2470992447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2470992447
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2431946006
Short name T551
Test name
Test status
Simulation time 6425394673 ps
CPU time 34.62 seconds
Started May 26 02:40:37 PM PDT 24
Finished May 26 02:41:14 PM PDT 24
Peak memory 216032 kb
Host smart-2eb1083b-9ac1-41f6-999c-13e995eb8491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431946006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2431946006
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2315374849
Short name T839
Test name
Test status
Simulation time 19933477514 ps
CPU time 7.16 seconds
Started May 26 02:40:40 PM PDT 24
Finished May 26 02:40:49 PM PDT 24
Peak memory 215592 kb
Host smart-9b5b724b-3b09-482c-a3fe-a2f0c798d66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315374849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2315374849
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3334495871
Short name T971
Test name
Test status
Simulation time 10788273 ps
CPU time 0.68 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 204988 kb
Host smart-6690b194-b5bf-4d4f-a496-b7d39d45795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334495871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3334495871
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1214934234
Short name T443
Test name
Test status
Simulation time 175144762 ps
CPU time 0.85 seconds
Started May 26 02:40:38 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 205024 kb
Host smart-23209ece-b724-4946-9093-f02a875a44e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214934234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1214934234
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2174294870
Short name T286
Test name
Test status
Simulation time 238036628 ps
CPU time 2.66 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:40:50 PM PDT 24
Peak memory 218048 kb
Host smart-f7d331e0-78cc-4893-9d87-c0d7eaec02df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174294870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2174294870
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1552318044
Short name T530
Test name
Test status
Simulation time 14380670 ps
CPU time 0.72 seconds
Started May 26 02:40:49 PM PDT 24
Finished May 26 02:40:51 PM PDT 24
Peak memory 204908 kb
Host smart-7a760137-77e5-4f8c-9916-55d8ef51f0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552318044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1552318044
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3999908060
Short name T672
Test name
Test status
Simulation time 70557877 ps
CPU time 2.1 seconds
Started May 26 02:40:46 PM PDT 24
Finished May 26 02:40:49 PM PDT 24
Peak memory 220924 kb
Host smart-a995903a-1d48-4086-ae85-12373fd8e70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999908060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3999908060
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1653121816
Short name T7
Test name
Test status
Simulation time 32559568 ps
CPU time 0.76 seconds
Started May 26 02:40:48 PM PDT 24
Finished May 26 02:40:50 PM PDT 24
Peak memory 206276 kb
Host smart-f11a45d8-870b-4a7d-80e8-5872825a7204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653121816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1653121816
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.293045763
Short name T479
Test name
Test status
Simulation time 177693826482 ps
CPU time 98.28 seconds
Started May 26 02:40:46 PM PDT 24
Finished May 26 02:42:26 PM PDT 24
Peak memory 239064 kb
Host smart-c7816f1c-ad76-44eb-b6d4-f1a844ff76e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293045763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.293045763
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4028114512
Short name T24
Test name
Test status
Simulation time 28117319831 ps
CPU time 313.73 seconds
Started May 26 02:40:49 PM PDT 24
Finished May 26 02:46:04 PM PDT 24
Peak memory 255400 kb
Host smart-34dc7060-7f76-43e0-9118-08891240e057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028114512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4028114512
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3102070531
Short name T899
Test name
Test status
Simulation time 13400158382 ps
CPU time 157.84 seconds
Started May 26 02:40:50 PM PDT 24
Finished May 26 02:43:29 PM PDT 24
Peak memory 254376 kb
Host smart-03f542b9-00db-4425-b431-9343c2450dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102070531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3102070531
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1514948504
Short name T875
Test name
Test status
Simulation time 91121085 ps
CPU time 2.33 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:40:51 PM PDT 24
Peak memory 218364 kb
Host smart-7b2c3512-8402-4e26-b765-d97af001883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514948504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1514948504
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3161636252
Short name T505
Test name
Test status
Simulation time 82776467966 ps
CPU time 139.15 seconds
Started May 26 02:40:49 PM PDT 24
Finished May 26 02:43:10 PM PDT 24
Peak memory 238028 kb
Host smart-d5ba335f-3834-4e7e-94a6-f644c60d4b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161636252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3161636252
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1867921474
Short name T591
Test name
Test status
Simulation time 12263809139 ps
CPU time 19.72 seconds
Started May 26 02:40:48 PM PDT 24
Finished May 26 02:41:09 PM PDT 24
Peak memory 233084 kb
Host smart-594e1f8a-c2df-4de7-8e8b-4036a29dc102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867921474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1867921474
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3020857043
Short name T20
Test name
Test status
Simulation time 1176672539 ps
CPU time 3.89 seconds
Started May 26 02:40:48 PM PDT 24
Finished May 26 02:40:53 PM PDT 24
Peak memory 232704 kb
Host smart-21167e4a-2d77-4d3b-8d04-8ed9aae0767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020857043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3020857043
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1747948538
Short name T41
Test name
Test status
Simulation time 2256313316 ps
CPU time 6.77 seconds
Started May 26 02:40:48 PM PDT 24
Finished May 26 02:40:56 PM PDT 24
Peak memory 222724 kb
Host smart-311a7fe4-a524-4788-9603-aed889613835
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1747948538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1747948538
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2166049074
Short name T715
Test name
Test status
Simulation time 52490765693 ps
CPU time 333.07 seconds
Started May 26 02:40:46 PM PDT 24
Finished May 26 02:46:20 PM PDT 24
Peak memory 252724 kb
Host smart-845d1229-0f76-4acd-b50e-e0790da3a46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166049074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2166049074
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2654942896
Short name T797
Test name
Test status
Simulation time 13614169001 ps
CPU time 16.58 seconds
Started May 26 02:40:54 PM PDT 24
Finished May 26 02:41:11 PM PDT 24
Peak memory 215984 kb
Host smart-ae7dd073-3c72-4441-994f-0cb81a8210f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654942896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2654942896
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.241022163
Short name T345
Test name
Test status
Simulation time 9591322669 ps
CPU time 7.6 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:40:56 PM PDT 24
Peak memory 215896 kb
Host smart-cee60c46-c639-4d95-ab10-7dccbe6402b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241022163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.241022163
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.563960414
Short name T361
Test name
Test status
Simulation time 55802473 ps
CPU time 1.1 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:40:50 PM PDT 24
Peak memory 206564 kb
Host smart-b999586c-6338-419b-91e0-9f67aaa8f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563960414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.563960414
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2317590024
Short name T363
Test name
Test status
Simulation time 154475687 ps
CPU time 0.77 seconds
Started May 26 02:40:48 PM PDT 24
Finished May 26 02:40:50 PM PDT 24
Peak memory 205268 kb
Host smart-ed330438-2a8d-4b1b-884b-f88aec9864e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317590024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2317590024
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.239311707
Short name T658
Test name
Test status
Simulation time 246166334 ps
CPU time 2.56 seconds
Started May 26 02:40:53 PM PDT 24
Finished May 26 02:40:57 PM PDT 24
Peak memory 218136 kb
Host smart-f82c67da-22a5-4d35-bee0-665410103b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239311707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.239311707
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.208412240
Short name T806
Test name
Test status
Simulation time 14117950 ps
CPU time 0.71 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 204880 kb
Host smart-0e0cf808-4159-4c1b-b7ea-c9e1df04fd30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208412240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.208412240
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3478859134
Short name T322
Test name
Test status
Simulation time 425836748 ps
CPU time 7.38 seconds
Started May 26 02:40:46 PM PDT 24
Finished May 26 02:40:55 PM PDT 24
Peak memory 234476 kb
Host smart-dabef2be-5867-44d0-8b39-96abd8ec8a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478859134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3478859134
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2197104402
Short name T448
Test name
Test status
Simulation time 65138462 ps
CPU time 0.78 seconds
Started May 26 02:40:49 PM PDT 24
Finished May 26 02:40:51 PM PDT 24
Peak memory 205740 kb
Host smart-bf0c4754-30fb-45c1-91aa-04e046d57204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197104402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2197104402
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2674408731
Short name T946
Test name
Test status
Simulation time 7118239262 ps
CPU time 13.57 seconds
Started May 26 02:40:54 PM PDT 24
Finished May 26 02:41:08 PM PDT 24
Peak memory 232456 kb
Host smart-3b65c65f-4dcc-423d-9bbb-91500f52ea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674408731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2674408731
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.315320374
Short name T619
Test name
Test status
Simulation time 4147951590 ps
CPU time 6.72 seconds
Started May 26 02:40:50 PM PDT 24
Finished May 26 02:40:58 PM PDT 24
Peak memory 217060 kb
Host smart-b287865f-7b3b-4580-b2fc-9aea4bccc4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315320374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.315320374
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.375339013
Short name T665
Test name
Test status
Simulation time 1864259637 ps
CPU time 26.49 seconds
Started May 26 02:40:51 PM PDT 24
Finished May 26 02:41:18 PM PDT 24
Peak memory 250084 kb
Host smart-1e312538-e77e-4a47-9b21-5ec4f226c1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375339013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.375339013
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4203323684
Short name T210
Test name
Test status
Simulation time 1695703720 ps
CPU time 3.37 seconds
Started May 26 02:40:49 PM PDT 24
Finished May 26 02:40:53 PM PDT 24
Peak memory 218080 kb
Host smart-328fd02e-1edb-4204-8994-c59e23b38d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203323684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4203323684
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3613729211
Short name T852
Test name
Test status
Simulation time 978181761 ps
CPU time 7.03 seconds
Started May 26 02:40:46 PM PDT 24
Finished May 26 02:40:54 PM PDT 24
Peak memory 216216 kb
Host smart-b71fc044-f6bf-4db8-957b-0553206b9c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613729211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3613729211
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2462057078
Short name T719
Test name
Test status
Simulation time 3216406941 ps
CPU time 12.86 seconds
Started May 26 02:40:52 PM PDT 24
Finished May 26 02:41:06 PM PDT 24
Peak memory 233276 kb
Host smart-a4d6daf0-7a16-44d5-b7c1-e63d44b222aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462057078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2462057078
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1615679749
Short name T623
Test name
Test status
Simulation time 1090962589 ps
CPU time 2.84 seconds
Started May 26 02:40:48 PM PDT 24
Finished May 26 02:40:52 PM PDT 24
Peak memory 218064 kb
Host smart-22e35379-fd0b-4373-9029-cdc4728d3049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615679749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1615679749
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3820130089
Short name T357
Test name
Test status
Simulation time 632782286 ps
CPU time 4.9 seconds
Started May 26 02:40:50 PM PDT 24
Finished May 26 02:40:56 PM PDT 24
Peak memory 222724 kb
Host smart-7dcc1641-2f21-48cf-bad6-1440313e4c33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3820130089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3820130089
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2923652269
Short name T810
Test name
Test status
Simulation time 38824681588 ps
CPU time 111.72 seconds
Started May 26 02:40:58 PM PDT 24
Finished May 26 02:42:52 PM PDT 24
Peak memory 253680 kb
Host smart-557b7382-b59e-4f08-b832-0b31ad615e83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923652269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2923652269
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1253684128
Short name T857
Test name
Test status
Simulation time 3304563761 ps
CPU time 28.13 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:41:17 PM PDT 24
Peak memory 216036 kb
Host smart-0f28d5bb-3480-47a7-92d9-343ff3e524c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253684128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1253684128
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2849711175
Short name T786
Test name
Test status
Simulation time 22476308354 ps
CPU time 10.59 seconds
Started May 26 02:40:48 PM PDT 24
Finished May 26 02:41:00 PM PDT 24
Peak memory 215952 kb
Host smart-dbb0d3ae-0640-4f97-97bd-7b10f39785e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849711175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2849711175
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1296483241
Short name T805
Test name
Test status
Simulation time 34801437 ps
CPU time 1.61 seconds
Started May 26 02:40:54 PM PDT 24
Finished May 26 02:40:56 PM PDT 24
Peak memory 215924 kb
Host smart-e7bd776a-5b88-46e6-a89f-f2ad58265516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296483241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1296483241
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.691583794
Short name T556
Test name
Test status
Simulation time 92293431 ps
CPU time 0.79 seconds
Started May 26 02:40:49 PM PDT 24
Finished May 26 02:40:51 PM PDT 24
Peak memory 205320 kb
Host smart-3461f96f-b774-46a6-a7ac-977b9ab688a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691583794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.691583794
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2706992028
Short name T616
Test name
Test status
Simulation time 4449955697 ps
CPU time 8.41 seconds
Started May 26 02:40:47 PM PDT 24
Finished May 26 02:40:57 PM PDT 24
Peak memory 234156 kb
Host smart-d24e31bc-76b1-47ab-8948-5e98bdefb351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706992028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2706992028
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3764900897
Short name T813
Test name
Test status
Simulation time 24032697 ps
CPU time 0.72 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:04 PM PDT 24
Peak memory 204212 kb
Host smart-43ec0a2c-66bc-444e-bab2-c1921f3563f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764900897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3764900897
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.4058558320
Short name T289
Test name
Test status
Simulation time 250381234 ps
CPU time 3.55 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:41:01 PM PDT 24
Peak memory 218440 kb
Host smart-30dd4ab8-0325-41fa-a0c3-08292710fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058558320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.4058558320
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3539260734
Short name T925
Test name
Test status
Simulation time 27060874 ps
CPU time 0.74 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 206284 kb
Host smart-d63b53bc-1f3f-409b-b829-83ccbce4a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539260734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3539260734
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1804287055
Short name T918
Test name
Test status
Simulation time 19554893871 ps
CPU time 81.29 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:42:19 PM PDT 24
Peak memory 255344 kb
Host smart-c63a994d-a891-497b-a269-f09cf695835b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804287055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1804287055
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.77598908
Short name T645
Test name
Test status
Simulation time 2204748338 ps
CPU time 18.56 seconds
Started May 26 02:41:04 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 224364 kb
Host smart-da7236f4-750d-49b2-b6d2-64ecfc558767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77598908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.77598908
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4132989297
Short name T940
Test name
Test status
Simulation time 1421036664 ps
CPU time 4.92 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:41:02 PM PDT 24
Peak memory 232408 kb
Host smart-e540d2a6-0b3f-4d54-919c-8d3293877db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132989297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4132989297
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1147646993
Short name T926
Test name
Test status
Simulation time 2387120996 ps
CPU time 11.46 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:10 PM PDT 24
Peak memory 234836 kb
Host smart-06978b9c-96f5-4961-a05d-0ed0c88e220b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147646993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1147646993
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.720208077
Short name T706
Test name
Test status
Simulation time 1408224544 ps
CPU time 7.66 seconds
Started May 26 02:40:58 PM PDT 24
Finished May 26 02:41:07 PM PDT 24
Peak memory 235452 kb
Host smart-0cbc9fb4-7743-4262-a939-a99a73c302ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720208077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.720208077
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1627658885
Short name T370
Test name
Test status
Simulation time 62957114 ps
CPU time 2.86 seconds
Started May 26 02:40:55 PM PDT 24
Finished May 26 02:40:59 PM PDT 24
Peak memory 232392 kb
Host smart-7ec387b4-a05e-43b5-8991-492c8d9b93c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627658885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1627658885
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.721511629
Short name T922
Test name
Test status
Simulation time 17918930576 ps
CPU time 13.02 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:17 PM PDT 24
Peak memory 233944 kb
Host smart-c007785a-49cf-4dcb-a53c-a46bfe784808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721511629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.721511629
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2392018469
Short name T648
Test name
Test status
Simulation time 799415137 ps
CPU time 7.55 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:06 PM PDT 24
Peak memory 218796 kb
Host smart-370b6fe2-e0e0-4f40-aa59-05ae9d5f687e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2392018469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2392018469
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1078927982
Short name T312
Test name
Test status
Simulation time 6618166361 ps
CPU time 18.77 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:17 PM PDT 24
Peak memory 216040 kb
Host smart-22a84985-f474-48d3-85d6-d5952989ce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078927982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1078927982
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.924771430
Short name T410
Test name
Test status
Simulation time 34215419233 ps
CPU time 10.84 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:09 PM PDT 24
Peak memory 215900 kb
Host smart-4fa10d9f-3c86-43ad-bcef-24bd7593628e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924771430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.924771430
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2818904615
Short name T860
Test name
Test status
Simulation time 119748824 ps
CPU time 1.39 seconds
Started May 26 02:40:55 PM PDT 24
Finished May 26 02:40:58 PM PDT 24
Peak memory 215928 kb
Host smart-96318655-7307-413a-81e0-3f77bc7a3aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818904615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2818904615
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3713404041
Short name T816
Test name
Test status
Simulation time 160192914 ps
CPU time 1.15 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:00 PM PDT 24
Peak memory 205316 kb
Host smart-480952de-fb94-4e44-a7aa-cdf3d2b7ea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713404041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3713404041
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1684585901
Short name T464
Test name
Test status
Simulation time 4981177025 ps
CPU time 19.2 seconds
Started May 26 02:40:58 PM PDT 24
Finished May 26 02:41:18 PM PDT 24
Peak memory 234300 kb
Host smart-fb654091-8c79-46ff-8003-905cbdd81951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684585901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1684585901
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3353401175
Short name T453
Test name
Test status
Simulation time 40087557 ps
CPU time 0.71 seconds
Started May 26 02:39:11 PM PDT 24
Finished May 26 02:39:13 PM PDT 24
Peak memory 205288 kb
Host smart-5c83d696-10ff-4d0e-a662-9821f8d5f470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353401175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
353401175
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2851818592
Short name T566
Test name
Test status
Simulation time 592713938 ps
CPU time 4.66 seconds
Started May 26 02:39:12 PM PDT 24
Finished May 26 02:39:18 PM PDT 24
Peak memory 233524 kb
Host smart-febca467-b8b2-4e77-86a2-ae846632dc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851818592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2851818592
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.861903078
Short name T694
Test name
Test status
Simulation time 58303045 ps
CPU time 0.75 seconds
Started May 26 02:39:14 PM PDT 24
Finished May 26 02:39:15 PM PDT 24
Peak memory 205812 kb
Host smart-66d00575-b971-4c23-8906-e3367e6e7853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861903078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.861903078
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.533086448
Short name T229
Test name
Test status
Simulation time 28280140835 ps
CPU time 69.68 seconds
Started May 26 02:39:11 PM PDT 24
Finished May 26 02:40:22 PM PDT 24
Peak memory 253100 kb
Host smart-42f9b850-9e4d-48f7-8c20-595a61364b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533086448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.533086448
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4188232309
Short name T240
Test name
Test status
Simulation time 9977757885 ps
CPU time 120.08 seconds
Started May 26 02:39:16 PM PDT 24
Finished May 26 02:41:17 PM PDT 24
Peak memory 250404 kb
Host smart-1cb92e4b-e7ad-4c10-8b69-34b79ca83c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188232309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4188232309
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2205505881
Short name T683
Test name
Test status
Simulation time 19857084980 ps
CPU time 98.57 seconds
Started May 26 02:39:17 PM PDT 24
Finished May 26 02:40:56 PM PDT 24
Peak memory 248864 kb
Host smart-ceb76a04-2980-4f0d-856e-362d84cdae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205505881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2205505881
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3914134321
Short name T434
Test name
Test status
Simulation time 185927099 ps
CPU time 4.65 seconds
Started May 26 02:39:12 PM PDT 24
Finished May 26 02:39:18 PM PDT 24
Peak memory 221012 kb
Host smart-8f6cd45c-a74d-470a-8407-2dd0f55d3c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914134321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3914134321
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3634334024
Short name T64
Test name
Test status
Simulation time 605091923 ps
CPU time 4.94 seconds
Started May 26 02:39:17 PM PDT 24
Finished May 26 02:39:23 PM PDT 24
Peak memory 235532 kb
Host smart-d6df64a4-6cde-45bf-a83f-434c799ff329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634334024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3634334024
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1883804603
Short name T442
Test name
Test status
Simulation time 25150338691 ps
CPU time 55.14 seconds
Started May 26 02:39:13 PM PDT 24
Finished May 26 02:40:09 PM PDT 24
Peak memory 248152 kb
Host smart-96a48d96-53d0-42c3-b1c9-df08fbfeda4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883804603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1883804603
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2973477761
Short name T717
Test name
Test status
Simulation time 112497390 ps
CPU time 1.04 seconds
Started May 26 02:39:13 PM PDT 24
Finished May 26 02:39:15 PM PDT 24
Peak memory 216212 kb
Host smart-99876906-d3b0-4999-8d84-dacb6bdaf066
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973477761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2973477761
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2524770539
Short name T250
Test name
Test status
Simulation time 3174551252 ps
CPU time 4.6 seconds
Started May 26 02:39:12 PM PDT 24
Finished May 26 02:39:17 PM PDT 24
Peak memory 218268 kb
Host smart-6ab114b5-6b70-4e88-be50-232a616a33a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524770539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2524770539
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1393940817
Short name T739
Test name
Test status
Simulation time 1244175935 ps
CPU time 6.37 seconds
Started May 26 02:39:13 PM PDT 24
Finished May 26 02:39:21 PM PDT 24
Peak memory 235196 kb
Host smart-fd8b4b9d-5d59-4005-8fa5-af3d2bc5cb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393940817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1393940817
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2741360133
Short name T757
Test name
Test status
Simulation time 1891801523 ps
CPU time 11.02 seconds
Started May 26 02:39:15 PM PDT 24
Finished May 26 02:39:27 PM PDT 24
Peak memory 221908 kb
Host smart-ef90d033-e6e4-47f6-8939-2c66d1b31278
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2741360133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2741360133
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1458116494
Short name T76
Test name
Test status
Simulation time 82488234 ps
CPU time 1.09 seconds
Started May 26 02:39:14 PM PDT 24
Finished May 26 02:39:16 PM PDT 24
Peak memory 234788 kb
Host smart-ca620f4d-4bbe-40cd-9e08-2629465562fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458116494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1458116494
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3973194924
Short name T526
Test name
Test status
Simulation time 19106301655 ps
CPU time 25.38 seconds
Started May 26 02:39:12 PM PDT 24
Finished May 26 02:39:38 PM PDT 24
Peak memory 215988 kb
Host smart-df4d8cca-a40f-4216-9018-0a6fee34351a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973194924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3973194924
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3349027009
Short name T655
Test name
Test status
Simulation time 49570080170 ps
CPU time 13.5 seconds
Started May 26 02:39:13 PM PDT 24
Finished May 26 02:39:27 PM PDT 24
Peak memory 215956 kb
Host smart-ce932de5-d24c-4607-8919-3cf3e0eb970d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349027009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3349027009
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.193125602
Short name T447
Test name
Test status
Simulation time 100686593 ps
CPU time 1.33 seconds
Started May 26 02:39:17 PM PDT 24
Finished May 26 02:39:19 PM PDT 24
Peak memory 215876 kb
Host smart-8250ecad-db30-40f8-b3fd-cd0f94a36b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193125602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.193125602
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1663145845
Short name T19
Test name
Test status
Simulation time 21295106 ps
CPU time 0.69 seconds
Started May 26 02:39:14 PM PDT 24
Finished May 26 02:39:16 PM PDT 24
Peak memory 205316 kb
Host smart-ec476ea1-fb87-4bcb-ad86-8eaef164510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663145845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1663145845
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2241582780
Short name T528
Test name
Test status
Simulation time 113082836 ps
CPU time 2.28 seconds
Started May 26 02:39:12 PM PDT 24
Finished May 26 02:39:16 PM PDT 24
Peak memory 215708 kb
Host smart-0d17a045-4f39-4e70-8ce7-42f8aba8efee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241582780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2241582780
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3379533568
Short name T355
Test name
Test status
Simulation time 14918467 ps
CPU time 0.74 seconds
Started May 26 02:40:58 PM PDT 24
Finished May 26 02:41:00 PM PDT 24
Peak memory 204456 kb
Host smart-b430b8a8-07c8-450b-8d3d-91417be23614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379533568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3379533568
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2109612740
Short name T129
Test name
Test status
Simulation time 637035206 ps
CPU time 7.88 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 235000 kb
Host smart-db37628d-a7bc-4916-8881-0b0a62c30c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109612740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2109612740
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3448576660
Short name T666
Test name
Test status
Simulation time 102658171 ps
CPU time 0.8 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:40:58 PM PDT 24
Peak memory 206224 kb
Host smart-7d128a75-e454-4bc4-b2b2-13b11c22d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448576660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3448576660
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.923182069
Short name T901
Test name
Test status
Simulation time 27358203431 ps
CPU time 198.04 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:44:16 PM PDT 24
Peak memory 257032 kb
Host smart-55ab9c64-09c7-4fc2-8f11-fead640c39d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923182069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.923182069
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.38602945
Short name T936
Test name
Test status
Simulation time 41035263834 ps
CPU time 117.71 seconds
Started May 26 02:40:55 PM PDT 24
Finished May 26 02:42:54 PM PDT 24
Peak memory 255776 kb
Host smart-a16e399f-21fe-47be-909d-a5eb678b6044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38602945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.38602945
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1237287310
Short name T52
Test name
Test status
Simulation time 7363625271 ps
CPU time 87.65 seconds
Started May 26 02:40:58 PM PDT 24
Finished May 26 02:42:27 PM PDT 24
Peak memory 256692 kb
Host smart-0d4c1dcb-1751-48f3-a409-457183947951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237287310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1237287310
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1732619965
Short name T598
Test name
Test status
Simulation time 333257904 ps
CPU time 3.23 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:41:01 PM PDT 24
Peak memory 232356 kb
Host smart-6f0a2e9b-90a8-4e83-9548-65261a993fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732619965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1732619965
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1790073791
Short name T482
Test name
Test status
Simulation time 75372404 ps
CPU time 2.87 seconds
Started May 26 02:40:54 PM PDT 24
Finished May 26 02:40:58 PM PDT 24
Peak memory 224168 kb
Host smart-294966f8-b757-452b-9cd7-5375c4d5cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790073791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1790073791
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3704551875
Short name T614
Test name
Test status
Simulation time 33350482673 ps
CPU time 100.6 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:42:38 PM PDT 24
Peak memory 240624 kb
Host smart-95f6d87b-809d-4fdb-ad27-501e761d8642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704551875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3704551875
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.461182938
Short name T522
Test name
Test status
Simulation time 1301679036 ps
CPU time 5.23 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:03 PM PDT 24
Peak memory 218648 kb
Host smart-bfb7d081-9e4a-4124-ab71-bf2b1959a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461182938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.461182938
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1488507109
Short name T944
Test name
Test status
Simulation time 107622993 ps
CPU time 2.18 seconds
Started May 26 02:41:04 PM PDT 24
Finished May 26 02:41:07 PM PDT 24
Peak memory 215792 kb
Host smart-a1521956-c05d-471d-977e-6fbbfabbcdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488507109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1488507109
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2707537290
Short name T427
Test name
Test status
Simulation time 732533931 ps
CPU time 7.66 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 218744 kb
Host smart-188d0e10-85de-4e03-8204-0f0d5f6a40d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2707537290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2707537290
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1600286303
Short name T972
Test name
Test status
Simulation time 26221521958 ps
CPU time 211.49 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:44:28 PM PDT 24
Peak memory 256748 kb
Host smart-0fe6cca4-b1fc-45ec-98ea-1ff5f4c5b1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600286303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1600286303
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3237748584
Short name T727
Test name
Test status
Simulation time 771253464 ps
CPU time 3.6 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:02 PM PDT 24
Peak memory 215912 kb
Host smart-4f67b1db-59e9-449f-aa9b-c9bda93092f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237748584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3237748584
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1284262281
Short name T369
Test name
Test status
Simulation time 6194298658 ps
CPU time 17.21 seconds
Started May 26 02:41:01 PM PDT 24
Finished May 26 02:41:19 PM PDT 24
Peak memory 215928 kb
Host smart-d381af2f-9ef9-4e9c-8358-fe0b24c0f6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284262281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1284262281
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.216101381
Short name T700
Test name
Test status
Simulation time 184764084 ps
CPU time 1.25 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:00 PM PDT 24
Peak memory 215724 kb
Host smart-45d2eb44-610c-4fca-90a7-6461fe5faf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216101381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.216101381
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2656022728
Short name T586
Test name
Test status
Simulation time 75568029 ps
CPU time 0.84 seconds
Started May 26 02:40:58 PM PDT 24
Finished May 26 02:41:00 PM PDT 24
Peak memory 205264 kb
Host smart-53097091-6ae7-4d71-aa2f-d7b8452ddfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656022728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2656022728
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1303761849
Short name T422
Test name
Test status
Simulation time 932334526 ps
CPU time 3.99 seconds
Started May 26 02:40:56 PM PDT 24
Finished May 26 02:41:01 PM PDT 24
Peak memory 232428 kb
Host smart-15ff89d3-3da1-4ccc-bd92-522c4c593c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303761849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1303761849
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3693258681
Short name T401
Test name
Test status
Simulation time 23913866 ps
CPU time 0.7 seconds
Started May 26 02:41:05 PM PDT 24
Finished May 26 02:41:07 PM PDT 24
Peak memory 204992 kb
Host smart-a37cb4cb-7ae4-4083-9907-ee27b5f5cee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693258681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3693258681
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1607474902
Short name T484
Test name
Test status
Simulation time 103967613 ps
CPU time 2.26 seconds
Started May 26 02:41:05 PM PDT 24
Finished May 26 02:41:09 PM PDT 24
Peak memory 215732 kb
Host smart-973b0723-3b6d-41d9-8c81-452fd2075cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607474902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1607474902
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1340077798
Short name T329
Test name
Test status
Simulation time 21534233 ps
CPU time 0.83 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:40:59 PM PDT 24
Peak memory 205924 kb
Host smart-088af337-50d5-4696-bf42-926b930e3f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340077798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1340077798
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1958371775
Short name T51
Test name
Test status
Simulation time 81010250211 ps
CPU time 153.52 seconds
Started May 26 02:41:15 PM PDT 24
Finished May 26 02:43:51 PM PDT 24
Peak memory 249952 kb
Host smart-c7e00459-c2a2-445f-ad4c-b2e6c0dcdc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958371775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1958371775
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3482315683
Short name T960
Test name
Test status
Simulation time 17720139267 ps
CPU time 40.96 seconds
Started May 26 02:41:07 PM PDT 24
Finished May 26 02:41:49 PM PDT 24
Peak memory 248884 kb
Host smart-0b893e60-f1ba-43e6-9041-b27caa2057d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482315683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3482315683
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.436018908
Short name T890
Test name
Test status
Simulation time 1688994963 ps
CPU time 24.12 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 232400 kb
Host smart-9b60b05b-ea37-4916-bd57-3a6dcf72bbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436018908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.436018908
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4219427660
Short name T217
Test name
Test status
Simulation time 1604199953 ps
CPU time 19.08 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:23 PM PDT 24
Peak memory 218124 kb
Host smart-2298a82e-25d0-4814-bf43-e4e3d3e79ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219427660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4219427660
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2462102563
Short name T804
Test name
Test status
Simulation time 1054548485 ps
CPU time 6.29 seconds
Started May 26 02:41:17 PM PDT 24
Finished May 26 02:41:25 PM PDT 24
Peak memory 218400 kb
Host smart-19f16f8e-5ae6-414f-a4d2-50dfe12f5090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462102563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2462102563
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.4004901142
Short name T748
Test name
Test status
Simulation time 994840176 ps
CPU time 5.85 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:04 PM PDT 24
Peak memory 217648 kb
Host smart-d4440722-5f33-4ecc-b659-358d71b1c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004901142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.4004901142
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4248904445
Short name T182
Test name
Test status
Simulation time 1222545474 ps
CPU time 11.65 seconds
Started May 26 02:41:00 PM PDT 24
Finished May 26 02:41:13 PM PDT 24
Peak memory 223752 kb
Host smart-5f0627ad-7928-4614-82f2-428a59688c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248904445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4248904445
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2981928223
Short name T416
Test name
Test status
Simulation time 12171933351 ps
CPU time 10.53 seconds
Started May 26 02:41:04 PM PDT 24
Finished May 26 02:41:16 PM PDT 24
Peak memory 220296 kb
Host smart-85ae6be9-affd-475f-a88e-eab25158be45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2981928223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2981928223
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1802375194
Short name T151
Test name
Test status
Simulation time 44057606 ps
CPU time 0.94 seconds
Started May 26 02:41:05 PM PDT 24
Finished May 26 02:41:07 PM PDT 24
Peak memory 204972 kb
Host smart-110c0f55-c423-4b7f-8abd-36e797c1076d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802375194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1802375194
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1639110801
Short name T967
Test name
Test status
Simulation time 8499784105 ps
CPU time 11.28 seconds
Started May 26 02:40:58 PM PDT 24
Finished May 26 02:41:11 PM PDT 24
Peak memory 215988 kb
Host smart-7bc79cba-9da4-4f34-9756-d57f6e2ff9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639110801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1639110801
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4167814207
Short name T957
Test name
Test status
Simulation time 7216787667 ps
CPU time 6.25 seconds
Started May 26 02:40:57 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 215956 kb
Host smart-523a1e3f-5e93-4a4d-b88f-cdd7b7abf9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167814207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4167814207
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2765425959
Short name T17
Test name
Test status
Simulation time 172487488 ps
CPU time 1.15 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 207420 kb
Host smart-b110527a-5bb3-43b7-be31-c573648023db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765425959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2765425959
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2791371158
Short name T889
Test name
Test status
Simulation time 202935200 ps
CPU time 1.03 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 205560 kb
Host smart-169dabc7-6ebe-402a-9ced-dc4fd7e5a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791371158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2791371158
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.494298555
Short name T618
Test name
Test status
Simulation time 30685546801 ps
CPU time 11.44 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 231860 kb
Host smart-612e99f4-bef2-4655-aada-288f05e9ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494298555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.494298555
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1994550615
Short name T777
Test name
Test status
Simulation time 29415710 ps
CPU time 0.75 seconds
Started May 26 02:41:04 PM PDT 24
Finished May 26 02:41:06 PM PDT 24
Peak memory 204920 kb
Host smart-29d167d2-5710-49db-8ac9-4ba283b8c360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994550615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1994550615
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3842737262
Short name T408
Test name
Test status
Simulation time 101334805 ps
CPU time 2.6 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:15 PM PDT 24
Peak memory 218288 kb
Host smart-d990708a-cabf-4ce4-8a12-a97414d4b84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842737262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3842737262
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1463932690
Short name T424
Test name
Test status
Simulation time 30932600 ps
CPU time 0.75 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:04 PM PDT 24
Peak memory 204924 kb
Host smart-f228334f-ebb1-4d44-8071-18c46685cff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463932690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1463932690
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1429788961
Short name T206
Test name
Test status
Simulation time 14949241636 ps
CPU time 99.36 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:42:44 PM PDT 24
Peak memory 250536 kb
Host smart-df151790-cd20-4118-aa86-d371b2d69b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429788961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1429788961
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3719090179
Short name T764
Test name
Test status
Simulation time 20731248176 ps
CPU time 95.68 seconds
Started May 26 02:41:07 PM PDT 24
Finished May 26 02:42:43 PM PDT 24
Peak memory 256840 kb
Host smart-85def7aa-d2ff-4c5a-9cd3-4fcf18bef3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719090179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3719090179
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1492852965
Short name T248
Test name
Test status
Simulation time 20172437598 ps
CPU time 218.66 seconds
Started May 26 02:41:06 PM PDT 24
Finished May 26 02:44:46 PM PDT 24
Peak memory 257088 kb
Host smart-30092ad1-247a-4668-bf2a-abffd01c8c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492852965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1492852965
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1748590018
Short name T750
Test name
Test status
Simulation time 3630191055 ps
CPU time 12.34 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:30 PM PDT 24
Peak memory 224184 kb
Host smart-58b8d184-d176-42e3-a876-502db86e98b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748590018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1748590018
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3137257051
Short name T13
Test name
Test status
Simulation time 224329044 ps
CPU time 3.72 seconds
Started May 26 02:41:04 PM PDT 24
Finished May 26 02:41:10 PM PDT 24
Peak memory 218304 kb
Host smart-cf142137-46db-497a-a580-7ffafdd61fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137257051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3137257051
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2446703370
Short name T451
Test name
Test status
Simulation time 78436284 ps
CPU time 2.71 seconds
Started May 26 02:41:05 PM PDT 24
Finished May 26 02:41:09 PM PDT 24
Peak memory 224088 kb
Host smart-b01394ee-f5b8-4c5c-8844-e95ade7d2478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446703370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2446703370
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3079651085
Short name T633
Test name
Test status
Simulation time 13046667441 ps
CPU time 13.72 seconds
Started May 26 02:41:06 PM PDT 24
Finished May 26 02:41:21 PM PDT 24
Peak memory 238668 kb
Host smart-69935530-2b97-44e3-9b94-43909c92a6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079651085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3079651085
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3210145990
Short name T297
Test name
Test status
Simulation time 855148000 ps
CPU time 2.58 seconds
Started May 26 02:41:06 PM PDT 24
Finished May 26 02:41:10 PM PDT 24
Peak memory 216556 kb
Host smart-58504dc8-cf95-4eea-94ca-79796d813d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210145990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3210145990
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1094040247
Short name T709
Test name
Test status
Simulation time 139493142 ps
CPU time 3.34 seconds
Started May 26 02:41:06 PM PDT 24
Finished May 26 02:41:10 PM PDT 24
Peak memory 218920 kb
Host smart-f286ae46-3926-4512-89d1-dc9a1a23e4d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1094040247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1094040247
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2727024037
Short name T267
Test name
Test status
Simulation time 3558517838 ps
CPU time 70.45 seconds
Started May 26 02:41:05 PM PDT 24
Finished May 26 02:42:17 PM PDT 24
Peak memory 248944 kb
Host smart-65bbd846-2b18-4a33-b3c4-65aaac4849ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727024037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2727024037
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3527047770
Short name T440
Test name
Test status
Simulation time 2912383053 ps
CPU time 27.57 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 215992 kb
Host smart-83d00842-7c8a-427f-b2d5-53dbbc164bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527047770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3527047770
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2806624303
Short name T908
Test name
Test status
Simulation time 537482712 ps
CPU time 2.24 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:15 PM PDT 24
Peak memory 207444 kb
Host smart-bddd7959-7fab-4b3e-9479-e15492bb7b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806624303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2806624303
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2746723972
Short name T373
Test name
Test status
Simulation time 29299175 ps
CPU time 1.57 seconds
Started May 26 02:41:05 PM PDT 24
Finished May 26 02:41:08 PM PDT 24
Peak memory 215948 kb
Host smart-39d77e3a-d8b3-4fa2-9b06-481992366328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746723972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2746723972
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1271690270
Short name T849
Test name
Test status
Simulation time 171298783 ps
CPU time 0.84 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 205280 kb
Host smart-2aff1810-e1da-4e3b-b1cd-e67ccaeebeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271690270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1271690270
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2455237974
Short name T575
Test name
Test status
Simulation time 5411070626 ps
CPU time 6.56 seconds
Started May 26 02:41:04 PM PDT 24
Finished May 26 02:41:12 PM PDT 24
Peak memory 218696 kb
Host smart-33495aaa-03e9-4a47-9770-a67d4970a02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455237974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2455237974
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2108270950
Short name T331
Test name
Test status
Simulation time 37204046 ps
CPU time 0.76 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:41:15 PM PDT 24
Peak memory 204300 kb
Host smart-9ad80d62-8fda-47cf-a709-cec25c4d3434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108270950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2108270950
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.782458780
Short name T501
Test name
Test status
Simulation time 62237380 ps
CPU time 2.7 seconds
Started May 26 02:41:05 PM PDT 24
Finished May 26 02:41:09 PM PDT 24
Peak memory 233724 kb
Host smart-dd6789c9-18b0-4640-bc76-4372cee571e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782458780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.782458780
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2036125424
Short name T912
Test name
Test status
Simulation time 139386621 ps
CPU time 0.74 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:17 PM PDT 24
Peak memory 205960 kb
Host smart-cecf7dfe-1828-44d5-aa0d-61afaa82fd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036125424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2036125424
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2550584016
Short name T419
Test name
Test status
Simulation time 1267532254 ps
CPU time 7.38 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:20 PM PDT 24
Peak memory 232412 kb
Host smart-0d6aba69-94de-4c1b-a205-64ec16fb0b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550584016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2550584016
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3057480413
Short name T47
Test name
Test status
Simulation time 44408630200 ps
CPU time 21.46 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:39 PM PDT 24
Peak memory 221784 kb
Host smart-16d48407-e753-4069-b097-df3d008e4a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057480413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3057480413
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.518818529
Short name T734
Test name
Test status
Simulation time 3414174370 ps
CPU time 9.15 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:22 PM PDT 24
Peak memory 234752 kb
Host smart-f2a66b0f-cd34-435f-bc7e-c90b98e45fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518818529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.518818529
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1724752690
Short name T620
Test name
Test status
Simulation time 1969571357 ps
CPU time 7.28 seconds
Started May 26 02:41:04 PM PDT 24
Finished May 26 02:41:13 PM PDT 24
Peak memory 222728 kb
Host smart-73b1c3fc-1399-40ae-9813-f71a4b8f1d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724752690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1724752690
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1320851811
Short name T802
Test name
Test status
Simulation time 25383538947 ps
CPU time 22.56 seconds
Started May 26 02:41:05 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 233680 kb
Host smart-9c8a2307-bbaf-4973-99ee-2df9b5e3d3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320851811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1320851811
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2438782493
Short name T705
Test name
Test status
Simulation time 384895857 ps
CPU time 3.56 seconds
Started May 26 02:41:15 PM PDT 24
Finished May 26 02:41:22 PM PDT 24
Peak memory 219744 kb
Host smart-a317d6da-fa84-48c4-9492-7a7362af9feb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2438782493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2438782493
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.314532062
Short name T263
Test name
Test status
Simulation time 7656097539 ps
CPU time 119.87 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:43:13 PM PDT 24
Peak memory 249040 kb
Host smart-d9b2a2a6-5589-4d53-8871-6ff92ef35894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314532062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.314532062
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4190870105
Short name T842
Test name
Test status
Simulation time 12256904216 ps
CPU time 43.25 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:42:01 PM PDT 24
Peak memory 216004 kb
Host smart-7d45b480-446b-4143-a8e2-9be0f2551ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190870105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4190870105
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3643761116
Short name T883
Test name
Test status
Simulation time 2701546931 ps
CPU time 4.28 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:21 PM PDT 24
Peak memory 215364 kb
Host smart-499e3e13-7db6-4118-8be6-47c89741fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643761116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3643761116
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.562703343
Short name T428
Test name
Test status
Simulation time 265558828 ps
CPU time 1.69 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:06 PM PDT 24
Peak memory 215920 kb
Host smart-0f0acd27-da47-4c0a-a40d-5a03592ad145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562703343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.562703343
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1737756210
Short name T503
Test name
Test status
Simulation time 56011128 ps
CPU time 0.72 seconds
Started May 26 02:41:03 PM PDT 24
Finished May 26 02:41:05 PM PDT 24
Peak memory 205288 kb
Host smart-3acf5ef9-f4d5-487a-b3ef-5ddf649b9d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737756210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1737756210
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3433016857
Short name T578
Test name
Test status
Simulation time 3596347500 ps
CPU time 11.91 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 233420 kb
Host smart-6843158c-e90e-4b69-b2eb-64352e23b4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433016857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3433016857
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4118299488
Short name T69
Test name
Test status
Simulation time 22899762 ps
CPU time 0.7 seconds
Started May 26 02:41:12 PM PDT 24
Finished May 26 02:41:14 PM PDT 24
Peak memory 204932 kb
Host smart-88176aa9-0fc8-4ca4-b039-b53746bea935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118299488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4118299488
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2093450035
Short name T951
Test name
Test status
Simulation time 4186907217 ps
CPU time 6.81 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:41:21 PM PDT 24
Peak memory 234056 kb
Host smart-92c94c5c-f82f-4dbb-b954-aab2697996d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093450035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2093450035
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1306747644
Short name T466
Test name
Test status
Simulation time 14100507 ps
CPU time 0.72 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:13 PM PDT 24
Peak memory 205932 kb
Host smart-80364680-0dc5-47b4-a481-4c2e41088349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306747644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1306747644
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4182874200
Short name T725
Test name
Test status
Simulation time 11742810647 ps
CPU time 71.3 seconds
Started May 26 02:41:12 PM PDT 24
Finished May 26 02:42:24 PM PDT 24
Peak memory 254288 kb
Host smart-6e4c05bd-9433-4777-8bbd-64015df3c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182874200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4182874200
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1571195331
Short name T523
Test name
Test status
Simulation time 11444874122 ps
CPU time 42.5 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:41:56 PM PDT 24
Peak memory 237276 kb
Host smart-0f48576a-bd2e-4a6a-8c4f-df409732cbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571195331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1571195331
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2784172108
Short name T740
Test name
Test status
Simulation time 11396619360 ps
CPU time 11.84 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 224224 kb
Host smart-f0591e8d-010c-40c1-9991-ba6303a41629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784172108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2784172108
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.391830100
Short name T716
Test name
Test status
Simulation time 3792094567 ps
CPU time 24.3 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:41 PM PDT 24
Peak memory 240624 kb
Host smart-6a26e1df-aa45-4e7c-94de-2a00ae0f92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391830100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.391830100
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4099778083
Short name T535
Test name
Test status
Simulation time 276484196 ps
CPU time 5.46 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:22 PM PDT 24
Peak memory 234732 kb
Host smart-c5fe83be-8aff-4bcd-a33f-44b2946667bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099778083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4099778083
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3628937252
Short name T187
Test name
Test status
Simulation time 6415420300 ps
CPU time 19.41 seconds
Started May 26 02:41:15 PM PDT 24
Finished May 26 02:41:37 PM PDT 24
Peak memory 233424 kb
Host smart-74cdc083-1bad-4720-be67-b50ff099100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628937252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3628937252
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3655542744
Short name T36
Test name
Test status
Simulation time 1395295340 ps
CPU time 3.24 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:41:19 PM PDT 24
Peak memory 216300 kb
Host smart-02268fd5-43e5-42e8-a68c-6f7a8e7a5d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655542744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3655542744
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1331505446
Short name T763
Test name
Test status
Simulation time 14340713807 ps
CPU time 10.97 seconds
Started May 26 02:41:12 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 232832 kb
Host smart-4fc734bf-ad9a-4605-9369-db1972dd9aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331505446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1331505446
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3822714674
Short name T685
Test name
Test status
Simulation time 113318042 ps
CPU time 4.66 seconds
Started May 26 02:41:16 PM PDT 24
Finished May 26 02:41:23 PM PDT 24
Peak memory 222280 kb
Host smart-4df52960-8cdf-43bf-acdd-d5a6615d48eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3822714674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3822714674
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.908298694
Short name T942
Test name
Test status
Simulation time 44101521 ps
CPU time 0.99 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:41:16 PM PDT 24
Peak memory 206100 kb
Host smart-bbc8593e-5c82-47ac-9968-67479a918b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908298694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.908298694
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3047552221
Short name T480
Test name
Test status
Simulation time 116079049 ps
CPU time 0.74 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:41:16 PM PDT 24
Peak memory 205212 kb
Host smart-2ad96ae1-686f-4ec6-a0b8-29b85fe7f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047552221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3047552221
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1997568610
Short name T402
Test name
Test status
Simulation time 619024278 ps
CPU time 1.6 seconds
Started May 26 02:41:16 PM PDT 24
Finished May 26 02:41:20 PM PDT 24
Peak memory 207364 kb
Host smart-ef97e6a8-cc3f-468d-8094-eb2f86f5272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997568610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1997568610
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.425747374
Short name T360
Test name
Test status
Simulation time 141315384 ps
CPU time 2.46 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:15 PM PDT 24
Peak memory 215928 kb
Host smart-b53bba0d-5980-428b-9071-86adffd33f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425747374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.425747374
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.242122293
Short name T876
Test name
Test status
Simulation time 53630554 ps
CPU time 0.81 seconds
Started May 26 02:41:12 PM PDT 24
Finished May 26 02:41:14 PM PDT 24
Peak memory 205316 kb
Host smart-92a51c71-c22b-42ae-a7c3-a09ee3725f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242122293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.242122293
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3817011880
Short name T4
Test name
Test status
Simulation time 9176126533 ps
CPU time 8.95 seconds
Started May 26 02:41:12 PM PDT 24
Finished May 26 02:41:22 PM PDT 24
Peak memory 218560 kb
Host smart-6bb64325-5917-4754-8c4b-a9b2552055be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817011880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3817011880
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.805369945
Short name T862
Test name
Test status
Simulation time 13304741 ps
CPU time 0.7 seconds
Started May 26 02:41:18 PM PDT 24
Finished May 26 02:41:21 PM PDT 24
Peak memory 204296 kb
Host smart-6f4c76b6-f667-454f-ba61-91d34b7d9765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805369945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.805369945
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3377899909
Short name T563
Test name
Test status
Simulation time 80518523 ps
CPU time 2.2 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:26 PM PDT 24
Peak memory 218172 kb
Host smart-36f4db21-057b-4273-9421-09d06a5546bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377899909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3377899909
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1277293494
Short name T483
Test name
Test status
Simulation time 30680516 ps
CPU time 0.74 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:18 PM PDT 24
Peak memory 204924 kb
Host smart-aa64d2cb-82f7-4ffc-8949-5cc93e32910b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277293494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1277293494
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1218999166
Short name T46
Test name
Test status
Simulation time 13652456935 ps
CPU time 49.61 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:42:15 PM PDT 24
Peak memory 240100 kb
Host smart-67becafb-6938-43c4-8d39-aa46c1ee43bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218999166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1218999166
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1452195221
Short name T871
Test name
Test status
Simulation time 263745622223 ps
CPU time 145.52 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:43:48 PM PDT 24
Peak memory 252184 kb
Host smart-3b23ac7d-9af4-48df-be74-8cbe966614a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452195221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1452195221
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3274472142
Short name T288
Test name
Test status
Simulation time 10576760834 ps
CPU time 126.96 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:43:31 PM PDT 24
Peak memory 255868 kb
Host smart-0d5374c2-5cd6-48a0-bcde-1d5511d575f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274472142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3274472142
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.863596821
Short name T343
Test name
Test status
Simulation time 72556420 ps
CPU time 2.61 seconds
Started May 26 02:41:19 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 224168 kb
Host smart-6c7cc6eb-3f45-44b4-87fc-388e847ded87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863596821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.863596821
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3301632058
Short name T205
Test name
Test status
Simulation time 46681608 ps
CPU time 2.79 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:20 PM PDT 24
Peak memory 232400 kb
Host smart-c86ce74a-f189-419a-b505-fed5991858a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301632058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3301632058
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1523750229
Short name T295
Test name
Test status
Simulation time 702032898 ps
CPU time 6.3 seconds
Started May 26 02:41:15 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 226796 kb
Host smart-b45cec1f-810b-426c-ad32-fe72bd97d4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523750229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1523750229
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.380503694
Short name T194
Test name
Test status
Simulation time 3229200966 ps
CPU time 10.68 seconds
Started May 26 02:41:11 PM PDT 24
Finished May 26 02:41:23 PM PDT 24
Peak memory 233468 kb
Host smart-fe4c2151-cb90-4a7f-8385-e02bdf457640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380503694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.380503694
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.425470697
Short name T698
Test name
Test status
Simulation time 5345115717 ps
CPU time 17.44 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:35 PM PDT 24
Peak memory 232484 kb
Host smart-cae965ce-ea86-4580-a49a-cc71cfed52e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425470697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.425470697
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.551972101
Short name T511
Test name
Test status
Simulation time 145517682 ps
CPU time 3.35 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:41:29 PM PDT 24
Peak memory 220248 kb
Host smart-19bb762f-16e9-4934-90a2-730e81d2a792
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=551972101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.551972101
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4075642594
Short name T459
Test name
Test status
Simulation time 22233702023 ps
CPU time 34.68 seconds
Started May 26 02:41:14 PM PDT 24
Finished May 26 02:41:51 PM PDT 24
Peak memory 215944 kb
Host smart-abbe9e05-da66-40fe-9ef0-960cc3c5011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075642594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4075642594
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1389741136
Short name T879
Test name
Test status
Simulation time 8873671454 ps
CPU time 10.4 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:41:26 PM PDT 24
Peak memory 215944 kb
Host smart-7f16682a-c174-420f-90b1-eb0eebd2f8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389741136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1389741136
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2042909657
Short name T819
Test name
Test status
Simulation time 129801650 ps
CPU time 1.72 seconds
Started May 26 02:41:15 PM PDT 24
Finished May 26 02:41:20 PM PDT 24
Peak memory 215576 kb
Host smart-da411d73-a05e-4278-a329-f800f13b314f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042909657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2042909657
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2347877719
Short name T892
Test name
Test status
Simulation time 177998362 ps
CPU time 0.7 seconds
Started May 26 02:41:13 PM PDT 24
Finished May 26 02:41:17 PM PDT 24
Peak memory 205264 kb
Host smart-f1a664b4-b5ca-495b-9817-d84ec972fb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347877719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2347877719
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4011953000
Short name T919
Test name
Test status
Simulation time 1953962971 ps
CPU time 6.25 seconds
Started May 26 02:41:12 PM PDT 24
Finished May 26 02:41:20 PM PDT 24
Peak memory 233712 kb
Host smart-3ff1fd6f-94a7-4649-8298-ae4236bf793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011953000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4011953000
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1152259937
Short name T643
Test name
Test status
Simulation time 38265585 ps
CPU time 0.74 seconds
Started May 26 02:41:24 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 204464 kb
Host smart-ef6c4d79-0b47-4c42-872e-c33aee51cf35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152259937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1152259937
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.844109525
Short name T214
Test name
Test status
Simulation time 120090205 ps
CPU time 3.47 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 233256 kb
Host smart-b783d57f-ba9e-4481-9b19-77f7800c0f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844109525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.844109525
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.228641545
Short name T328
Test name
Test status
Simulation time 52986290 ps
CPU time 0.78 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:41:27 PM PDT 24
Peak memory 205932 kb
Host smart-d350ea23-5200-49bd-86ef-b1afce812b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228641545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.228641545
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3973959614
Short name T928
Test name
Test status
Simulation time 32783233627 ps
CPU time 213.41 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:44:58 PM PDT 24
Peak memory 255316 kb
Host smart-20dfbaa0-7ee9-4347-a156-935e5fc9304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973959614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3973959614
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1218785226
Short name T769
Test name
Test status
Simulation time 3417547795 ps
CPU time 56.41 seconds
Started May 26 02:41:19 PM PDT 24
Finished May 26 02:42:18 PM PDT 24
Peak memory 248888 kb
Host smart-ce039108-0bc7-4ce1-ba8e-dc5d85a7319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218785226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1218785226
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.6739080
Short name T903
Test name
Test status
Simulation time 835017469 ps
CPU time 7.6 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 233432 kb
Host smart-db8783a1-c4ae-4bca-a7ac-e4770012405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6739080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.6739080
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3910566557
Short name T59
Test name
Test status
Simulation time 1825352007 ps
CPU time 19.21 seconds
Started May 26 02:41:19 PM PDT 24
Finished May 26 02:41:40 PM PDT 24
Peak memory 233440 kb
Host smart-a0886fdd-5392-43d8-ae37-29ee24347f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910566557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3910566557
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3936400290
Short name T62
Test name
Test status
Simulation time 11339046521 ps
CPU time 78.47 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:42:45 PM PDT 24
Peak memory 245808 kb
Host smart-94af4f9e-c10f-425a-99b5-c192833f84da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936400290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3936400290
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.291574864
Short name T583
Test name
Test status
Simulation time 5935018157 ps
CPU time 9.22 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:32 PM PDT 24
Peak memory 234404 kb
Host smart-b1f555e7-384a-4b0c-9c05-778896f2bc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291574864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.291574864
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2844004964
Short name T98
Test name
Test status
Simulation time 397299825 ps
CPU time 4.68 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 234308 kb
Host smart-0ade0e02-c3bc-4d7e-89a8-e87b2dad74cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844004964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2844004964
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3174661321
Short name T795
Test name
Test status
Simulation time 1918784039 ps
CPU time 14.62 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:39 PM PDT 24
Peak memory 218564 kb
Host smart-4d691e61-f017-418c-96d2-aed858acc07a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3174661321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3174661321
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.859431404
Short name T221
Test name
Test status
Simulation time 119546682186 ps
CPU time 556.66 seconds
Started May 26 02:41:24 PM PDT 24
Finished May 26 02:50:44 PM PDT 24
Peak memory 255868 kb
Host smart-61cba99e-4509-43fb-80ca-9a0644982086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859431404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.859431404
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3368626852
Short name T524
Test name
Test status
Simulation time 514667770 ps
CPU time 8.78 seconds
Started May 26 02:41:25 PM PDT 24
Finished May 26 02:41:36 PM PDT 24
Peak memory 216076 kb
Host smart-da7d904b-7449-461a-ab21-caf5be756f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368626852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3368626852
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4161852655
Short name T84
Test name
Test status
Simulation time 9247413497 ps
CPU time 8.66 seconds
Started May 26 02:41:18 PM PDT 24
Finished May 26 02:41:29 PM PDT 24
Peak memory 215852 kb
Host smart-98f63bf9-30d8-45c1-ac9e-a6dbe1c47518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161852655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4161852655
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.416421135
Short name T837
Test name
Test status
Simulation time 22956790 ps
CPU time 1.26 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 215908 kb
Host smart-fed8acc1-7496-4053-888c-2e2340f5eb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416421135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.416421135
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1988110758
Short name T335
Test name
Test status
Simulation time 90835319 ps
CPU time 0.8 seconds
Started May 26 02:41:24 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 205164 kb
Host smart-06aff992-f6fd-4cee-9d09-1307d43c836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988110758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1988110758
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.331205772
Short name T458
Test name
Test status
Simulation time 4626291169 ps
CPU time 19.07 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:41:46 PM PDT 24
Peak memory 239904 kb
Host smart-0867fa68-8465-492c-b228-85528dd4f87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331205772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.331205772
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2841599484
Short name T385
Test name
Test status
Simulation time 37417921 ps
CPU time 0.7 seconds
Started May 26 02:41:19 PM PDT 24
Finished May 26 02:41:22 PM PDT 24
Peak memory 204304 kb
Host smart-f0d9c471-5e24-4619-b309-6e16ae53e693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841599484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2841599484
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3211260808
Short name T832
Test name
Test status
Simulation time 1031906527 ps
CPU time 3.45 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:41:30 PM PDT 24
Peak memory 218440 kb
Host smart-20b4c1a5-7fac-402d-ac6d-2fbc086178ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211260808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3211260808
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3953219868
Short name T636
Test name
Test status
Simulation time 68356373 ps
CPU time 0.75 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:41:27 PM PDT 24
Peak memory 205940 kb
Host smart-1d739fea-ddfb-48d6-95de-a5347fd045e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953219868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3953219868
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2381998365
Short name T27
Test name
Test status
Simulation time 2987636719 ps
CPU time 35.03 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 248836 kb
Host smart-8249aba0-bce5-479e-b98b-ea65027ba7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381998365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2381998365
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2215901496
Short name T830
Test name
Test status
Simulation time 23477820821 ps
CPU time 36.65 seconds
Started May 26 02:41:24 PM PDT 24
Finished May 26 02:42:04 PM PDT 24
Peak memory 217120 kb
Host smart-ad524636-5551-4c76-a167-a303049105f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215901496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2215901496
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4010136016
Short name T670
Test name
Test status
Simulation time 4817525665 ps
CPU time 72.79 seconds
Started May 26 02:41:19 PM PDT 24
Finished May 26 02:42:33 PM PDT 24
Peak memory 248848 kb
Host smart-ed615a24-896f-4ae8-95be-69065464422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010136016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4010136016
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3661599140
Short name T798
Test name
Test status
Simulation time 9044097241 ps
CPU time 30.69 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:41:57 PM PDT 24
Peak memory 224228 kb
Host smart-bf86193a-a874-45c1-b56e-d85994ccc9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661599140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3661599140
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.382346241
Short name T844
Test name
Test status
Simulation time 34429454 ps
CPU time 2.42 seconds
Started May 26 02:41:19 PM PDT 24
Finished May 26 02:41:25 PM PDT 24
Peak memory 224176 kb
Host smart-6cb14b30-1d75-4fd7-a10e-dc9de122dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382346241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.382346241
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.623131263
Short name T608
Test name
Test status
Simulation time 979534795 ps
CPU time 11.07 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:34 PM PDT 24
Peak memory 232044 kb
Host smart-1b2e93ce-615d-4942-87dc-946859180c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623131263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.623131263
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1874169527
Short name T634
Test name
Test status
Simulation time 5359992744 ps
CPU time 5.04 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:29 PM PDT 24
Peak memory 216440 kb
Host smart-23a960d2-e206-4153-8ed3-6922937941f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874169527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1874169527
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4261731060
Short name T825
Test name
Test status
Simulation time 33132898291 ps
CPU time 19.49 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 224244 kb
Host smart-79f2283d-532f-4570-9d4b-aa3bf6667f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261731060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4261731060
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.288230250
Short name T955
Test name
Test status
Simulation time 2848119334 ps
CPU time 4.81 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 221780 kb
Host smart-25a908d1-4b7d-476a-b4ee-72d32aa111fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=288230250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.288230250
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2035358806
Short name T155
Test name
Test status
Simulation time 68110051694 ps
CPU time 179.85 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:44:25 PM PDT 24
Peak memory 254112 kb
Host smart-b1778652-ec14-4132-9c43-af4d79eade1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035358806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2035358806
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1332658214
Short name T348
Test name
Test status
Simulation time 301358713 ps
CPU time 3.54 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:41:29 PM PDT 24
Peak memory 217632 kb
Host smart-a771fc25-36b1-416e-a426-ce91add994d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332658214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1332658214
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.58415721
Short name T415
Test name
Test status
Simulation time 416446486 ps
CPU time 2.31 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 215868 kb
Host smart-d8d582b6-51a8-4589-a24b-313ccf20d52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58415721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.58415721
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.223062378
Short name T412
Test name
Test status
Simulation time 45628446 ps
CPU time 0.95 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:25 PM PDT 24
Peak memory 206584 kb
Host smart-c14c3817-ab43-4883-ba9f-4aafc159f81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223062378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.223062378
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2468559773
Short name T564
Test name
Test status
Simulation time 328121209 ps
CPU time 0.77 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:23 PM PDT 24
Peak memory 205188 kb
Host smart-e25a5d67-f904-4232-a836-c5b6ffb17471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468559773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2468559773
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.483331739
Short name T191
Test name
Test status
Simulation time 2419237365 ps
CPU time 5.59 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 217144 kb
Host smart-4c0e348a-aee8-4a1d-86af-f1f71742b08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483331739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.483331739
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3573127908
Short name T962
Test name
Test status
Simulation time 11923031 ps
CPU time 0.72 seconds
Started May 26 02:41:29 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 204940 kb
Host smart-e1726538-aa1c-4a5f-95d4-cff812af826d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573127908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3573127908
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1928388064
Short name T673
Test name
Test status
Simulation time 123663882 ps
CPU time 2.62 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:41:29 PM PDT 24
Peak memory 233376 kb
Host smart-88a606d5-28f0-4197-9a8e-dfecc88d3763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928388064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1928388064
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1966455222
Short name T970
Test name
Test status
Simulation time 68510898 ps
CPU time 0.77 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:41:27 PM PDT 24
Peak memory 205936 kb
Host smart-ed7d043d-3005-43f1-85ee-2f63c4ec0464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966455222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1966455222
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1980221813
Short name T582
Test name
Test status
Simulation time 2385434500 ps
CPU time 13.78 seconds
Started May 26 02:41:25 PM PDT 24
Finished May 26 02:41:41 PM PDT 24
Peak memory 251212 kb
Host smart-4a8894d1-ae77-4fe1-8339-778ab1093ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980221813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1980221813
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.895913610
Short name T22
Test name
Test status
Simulation time 357589376234 ps
CPU time 229.54 seconds
Started May 26 02:41:30 PM PDT 24
Finished May 26 02:45:21 PM PDT 24
Peak memory 257100 kb
Host smart-83a78315-edcb-4379-a865-ef9d636435cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895913610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.895913610
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.31682482
Short name T285
Test name
Test status
Simulation time 151438956196 ps
CPU time 168.03 seconds
Started May 26 02:41:27 PM PDT 24
Finished May 26 02:44:16 PM PDT 24
Peak memory 254804 kb
Host smart-07a4447c-b1c1-4077-aace-5ff7038718d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31682482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.31682482
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3977488589
Short name T931
Test name
Test status
Simulation time 2050482398 ps
CPU time 12.38 seconds
Started May 26 02:41:25 PM PDT 24
Finished May 26 02:41:40 PM PDT 24
Peak memory 232448 kb
Host smart-07059233-686f-47ed-a782-be74001b00cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977488589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3977488589
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3596296243
Short name T63
Test name
Test status
Simulation time 160273571 ps
CPU time 4.08 seconds
Started May 26 02:41:22 PM PDT 24
Finished May 26 02:41:30 PM PDT 24
Peak memory 219080 kb
Host smart-1feb1176-44ac-417c-8b85-e1a5bafd973c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596296243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3596296243
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2393687565
Short name T569
Test name
Test status
Simulation time 1972943733 ps
CPU time 8.92 seconds
Started May 26 02:41:23 PM PDT 24
Finished May 26 02:41:36 PM PDT 24
Peak memory 228348 kb
Host smart-60888b72-ad83-4be7-8079-bf9790fdfe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393687565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2393687565
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1780878192
Short name T134
Test name
Test status
Simulation time 2223692728 ps
CPU time 11 seconds
Started May 26 02:41:24 PM PDT 24
Finished May 26 02:41:38 PM PDT 24
Peak memory 229076 kb
Host smart-00fa2eda-71bd-476c-80df-35995150da21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780878192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1780878192
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1529819839
Short name T386
Test name
Test status
Simulation time 2161307776 ps
CPU time 6.64 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 227716 kb
Host smart-f2283464-3d27-4b44-8be5-6ca12f3ce1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529819839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1529819839
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.80216832
Short name T815
Test name
Test status
Simulation time 950599163 ps
CPU time 6.15 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:31 PM PDT 24
Peak memory 222560 kb
Host smart-9fd55532-444c-499b-9761-8fb0840b7d74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=80216832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direc
t.80216832
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3898123442
Short name T599
Test name
Test status
Simulation time 321767554 ps
CPU time 4.65 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:28 PM PDT 24
Peak memory 215972 kb
Host smart-a80b7451-beed-4772-9e28-3506eb210a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898123442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3898123442
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.273992921
Short name T431
Test name
Test status
Simulation time 602589975 ps
CPU time 3.55 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:27 PM PDT 24
Peak memory 215852 kb
Host smart-e98ae7ed-808b-4a36-bbbf-120226a5c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273992921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.273992921
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1821830898
Short name T851
Test name
Test status
Simulation time 37796030 ps
CPU time 0.74 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:24 PM PDT 24
Peak memory 205340 kb
Host smart-a48638f6-0122-4cd5-a139-aaf406ecbbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821830898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1821830898
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4020433529
Short name T470
Test name
Test status
Simulation time 12828682 ps
CPU time 0.71 seconds
Started May 26 02:41:21 PM PDT 24
Finished May 26 02:41:25 PM PDT 24
Peak memory 204936 kb
Host smart-0f76b983-5d7b-4b88-8890-6d8fd8d9677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020433529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4020433529
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3155294226
Short name T550
Test name
Test status
Simulation time 2545774638 ps
CPU time 13.73 seconds
Started May 26 02:41:20 PM PDT 24
Finished May 26 02:41:37 PM PDT 24
Peak memory 218252 kb
Host smart-9b7a9da0-0168-4012-8ae7-aa0f0966bff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155294226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3155294226
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1331686980
Short name T454
Test name
Test status
Simulation time 14612755 ps
CPU time 0.7 seconds
Started May 26 02:41:29 PM PDT 24
Finished May 26 02:41:30 PM PDT 24
Peak memory 204928 kb
Host smart-348df15c-dfa0-494c-a27e-5a58c5c0fa0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331686980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1331686980
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3348251524
Short name T211
Test name
Test status
Simulation time 214609501 ps
CPU time 5.26 seconds
Started May 26 02:41:30 PM PDT 24
Finished May 26 02:41:36 PM PDT 24
Peak memory 233244 kb
Host smart-ff68e8bc-a026-49f5-9d78-f792ed339af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348251524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3348251524
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3118159455
Short name T323
Test name
Test status
Simulation time 93530630 ps
CPU time 0.75 seconds
Started May 26 02:41:31 PM PDT 24
Finished May 26 02:41:33 PM PDT 24
Peak memory 204884 kb
Host smart-273ce3fb-e4d2-43bb-9039-c377b10a8fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118159455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3118159455
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.73353930
Short name T436
Test name
Test status
Simulation time 88740433546 ps
CPU time 140.92 seconds
Started May 26 02:41:31 PM PDT 24
Finished May 26 02:43:54 PM PDT 24
Peak memory 248748 kb
Host smart-672681ad-5bb1-4acf-b5a3-4aec52510d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73353930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.73353930
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3179507386
Short name T237
Test name
Test status
Simulation time 28555084783 ps
CPU time 258.9 seconds
Started May 26 02:41:31 PM PDT 24
Finished May 26 02:45:51 PM PDT 24
Peak memory 248876 kb
Host smart-a279d830-761b-4d86-837f-41900117044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179507386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3179507386
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4127574698
Short name T735
Test name
Test status
Simulation time 17808232853 ps
CPU time 89.63 seconds
Started May 26 02:41:28 PM PDT 24
Finished May 26 02:42:59 PM PDT 24
Peak memory 248840 kb
Host smart-dc421230-dd7d-44aa-99b8-3e7031593c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127574698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4127574698
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3193189488
Short name T559
Test name
Test status
Simulation time 2895005256 ps
CPU time 9.95 seconds
Started May 26 02:41:31 PM PDT 24
Finished May 26 02:41:42 PM PDT 24
Peak memory 224376 kb
Host smart-62e3a95e-b808-4d60-85bf-346e8f508fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193189488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3193189488
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.440771908
Short name T183
Test name
Test status
Simulation time 109380989 ps
CPU time 4.15 seconds
Started May 26 02:41:30 PM PDT 24
Finished May 26 02:41:35 PM PDT 24
Peak memory 232924 kb
Host smart-9cc82ca8-156e-4f8f-b758-4a41a3f0da73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440771908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.440771908
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1901976864
Short name T838
Test name
Test status
Simulation time 2798467288 ps
CPU time 15.72 seconds
Started May 26 02:41:28 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 250644 kb
Host smart-0eb1f4e1-dd48-4762-b57b-b9c1f9d2ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901976864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1901976864
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1427520111
Short name T273
Test name
Test status
Simulation time 20453913835 ps
CPU time 11.6 seconds
Started May 26 02:41:28 PM PDT 24
Finished May 26 02:41:40 PM PDT 24
Peak memory 218292 kb
Host smart-a734af17-6f49-415a-b78e-de5f9a5d3abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427520111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1427520111
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1926000633
Short name T841
Test name
Test status
Simulation time 520191313 ps
CPU time 5.53 seconds
Started May 26 02:41:44 PM PDT 24
Finished May 26 02:41:50 PM PDT 24
Peak memory 233512 kb
Host smart-170d6b08-35c4-4a5f-b5ad-1b29caa5f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926000633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1926000633
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.823411268
Short name T143
Test name
Test status
Simulation time 3734338889 ps
CPU time 18.93 seconds
Started May 26 02:41:33 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 219948 kb
Host smart-48986613-da19-40e0-a1d0-bc6bc6abfbfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=823411268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.823411268
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1856716921
Short name T316
Test name
Test status
Simulation time 4259913929 ps
CPU time 7.88 seconds
Started May 26 02:41:31 PM PDT 24
Finished May 26 02:41:40 PM PDT 24
Peak memory 216152 kb
Host smart-77cfb179-a682-4244-bd06-44558ec917ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856716921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1856716921
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1848648058
Short name T927
Test name
Test status
Simulation time 1306957375 ps
CPU time 7.62 seconds
Started May 26 02:41:29 PM PDT 24
Finished May 26 02:41:38 PM PDT 24
Peak memory 215868 kb
Host smart-e9ad159e-910d-476b-8f87-28ac0bdbf7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848648058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1848648058
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1177959875
Short name T519
Test name
Test status
Simulation time 253568236 ps
CPU time 3.4 seconds
Started May 26 02:41:29 PM PDT 24
Finished May 26 02:41:34 PM PDT 24
Peak memory 207716 kb
Host smart-6c8f3d89-fc43-4da4-91c9-4d346001d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177959875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1177959875
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.824507206
Short name T340
Test name
Test status
Simulation time 153840517 ps
CPU time 0.8 seconds
Started May 26 02:41:30 PM PDT 24
Finished May 26 02:41:32 PM PDT 24
Peak memory 205316 kb
Host smart-1a1a2061-deae-4481-880f-b67b106c9ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824507206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.824507206
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.784731388
Short name T818
Test name
Test status
Simulation time 6170773612 ps
CPU time 8.46 seconds
Started May 26 02:41:32 PM PDT 24
Finished May 26 02:41:41 PM PDT 24
Peak memory 226252 kb
Host smart-794d4d2c-eec8-4e47-a658-bedbe255c630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784731388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.784731388
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1356195960
Short name T950
Test name
Test status
Simulation time 20530126 ps
CPU time 0.71 seconds
Started May 26 02:39:23 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 204948 kb
Host smart-6e76da08-4526-4c59-8968-eb63b9a7d636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356195960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
356195960
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3112310422
Short name T743
Test name
Test status
Simulation time 682474167 ps
CPU time 3.36 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:39:27 PM PDT 24
Peak memory 218176 kb
Host smart-1e43316e-a67d-4e83-9e2c-b321419a3f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112310422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3112310422
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.456273971
Short name T937
Test name
Test status
Simulation time 15542906 ps
CPU time 0.75 seconds
Started May 26 02:39:13 PM PDT 24
Finished May 26 02:39:15 PM PDT 24
Peak memory 205936 kb
Host smart-cb8b5492-8b6c-454f-ab0f-36163c7cf4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456273971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.456273971
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2584270642
Short name T262
Test name
Test status
Simulation time 17442174924 ps
CPU time 96.32 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:41:01 PM PDT 24
Peak memory 249224 kb
Host smart-9a76d3c6-8aa3-41bc-8e62-687678452dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584270642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2584270642
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.23401613
Short name T902
Test name
Test status
Simulation time 181099621 ps
CPU time 3.06 seconds
Started May 26 02:39:20 PM PDT 24
Finished May 26 02:39:24 PM PDT 24
Peak memory 232336 kb
Host smart-b8a9dc8a-eaf6-4cfa-a9ef-d4fa5c77ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23401613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.23401613
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2194636982
Short name T693
Test name
Test status
Simulation time 91702074 ps
CPU time 2.81 seconds
Started May 26 02:39:17 PM PDT 24
Finished May 26 02:39:21 PM PDT 24
Peak memory 233224 kb
Host smart-2ca5af66-c174-4aef-bfb3-2ce27a045068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194636982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2194636982
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2288612329
Short name T930
Test name
Test status
Simulation time 7394520758 ps
CPU time 36.39 seconds
Started May 26 02:39:24 PM PDT 24
Finished May 26 02:40:03 PM PDT 24
Peak memory 230528 kb
Host smart-84a42f30-5d7a-4a27-a3a9-ea630d3b302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288612329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2288612329
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3879780827
Short name T867
Test name
Test status
Simulation time 33747042 ps
CPU time 1.03 seconds
Started May 26 02:39:12 PM PDT 24
Finished May 26 02:39:15 PM PDT 24
Peak memory 216192 kb
Host smart-bec86f39-fd40-4b17-b6f5-a1f98d4daed0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879780827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3879780827
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1267968486
Short name T255
Test name
Test status
Simulation time 3932961303 ps
CPU time 7.53 seconds
Started May 26 02:39:16 PM PDT 24
Finished May 26 02:39:25 PM PDT 24
Peak memory 226264 kb
Host smart-57bf3d2a-dc78-40c9-91bd-ae877938ee85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267968486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1267968486
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.718346674
Short name T710
Test name
Test status
Simulation time 505351880 ps
CPU time 5.58 seconds
Started May 26 02:39:13 PM PDT 24
Finished May 26 02:39:20 PM PDT 24
Peak memory 238340 kb
Host smart-60c4d44b-8bc2-4a5e-bdf9-196ac37b4acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718346674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.718346674
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3633036045
Short name T843
Test name
Test status
Simulation time 2721911134 ps
CPU time 19.65 seconds
Started May 26 02:39:23 PM PDT 24
Finished May 26 02:39:45 PM PDT 24
Peak memory 220412 kb
Host smart-91b2c701-e282-42ad-a973-bdd0055d18d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3633036045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3633036045
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1079399287
Short name T78
Test name
Test status
Simulation time 297361373 ps
CPU time 1.1 seconds
Started May 26 02:39:21 PM PDT 24
Finished May 26 02:39:23 PM PDT 24
Peak memory 234660 kb
Host smart-ab2fd7a7-4718-4e13-a4bb-4d383a4208f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079399287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1079399287
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3322626519
Short name T420
Test name
Test status
Simulation time 1681135072 ps
CPU time 4.96 seconds
Started May 26 02:39:16 PM PDT 24
Finished May 26 02:39:22 PM PDT 24
Peak memory 215944 kb
Host smart-63752dd7-986b-4747-92bd-60c28e5e082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322626519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3322626519
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2487807935
Short name T615
Test name
Test status
Simulation time 22045164565 ps
CPU time 10.17 seconds
Started May 26 02:39:14 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 215944 kb
Host smart-0eea0462-6797-4699-ac7b-19bcda109ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487807935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2487807935
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1562867431
Short name T733
Test name
Test status
Simulation time 208961244 ps
CPU time 1.59 seconds
Started May 26 02:39:13 PM PDT 24
Finished May 26 02:39:16 PM PDT 24
Peak memory 215960 kb
Host smart-09aa3cd8-4198-4761-992a-d9a7360b8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562867431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1562867431
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2620885691
Short name T390
Test name
Test status
Simulation time 61845870 ps
CPU time 0.83 seconds
Started May 26 02:39:14 PM PDT 24
Finished May 26 02:39:16 PM PDT 24
Peak memory 205316 kb
Host smart-017fce1f-0416-4a02-ac33-3d0d3f9d10a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620885691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2620885691
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.86626650
Short name T394
Test name
Test status
Simulation time 36037237997 ps
CPU time 18.51 seconds
Started May 26 02:39:21 PM PDT 24
Finished May 26 02:39:41 PM PDT 24
Peak memory 235476 kb
Host smart-54773d71-f760-43d9-a441-741cb5c5857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86626650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.86626650
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1728079474
Short name T326
Test name
Test status
Simulation time 80417092 ps
CPU time 0.73 seconds
Started May 26 02:41:42 PM PDT 24
Finished May 26 02:41:44 PM PDT 24
Peak memory 204904 kb
Host smart-59102a68-0c9c-4e11-9b75-fc21df18f259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728079474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1728079474
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3587033155
Short name T679
Test name
Test status
Simulation time 4597040877 ps
CPU time 11.2 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 219856 kb
Host smart-5629c254-6c8a-4d4c-b2d7-1569428d4b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587033155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3587033155
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.796411943
Short name T746
Test name
Test status
Simulation time 32875831 ps
CPU time 0.82 seconds
Started May 26 02:41:28 PM PDT 24
Finished May 26 02:41:30 PM PDT 24
Peak memory 205892 kb
Host smart-7ca0d224-4b2e-42d6-871b-cf28322b2191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796411943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.796411943
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1693179521
Short name T602
Test name
Test status
Simulation time 4095929626 ps
CPU time 54.49 seconds
Started May 26 02:41:38 PM PDT 24
Finished May 26 02:42:34 PM PDT 24
Peak memory 249148 kb
Host smart-c54cf5c6-1790-4f66-8989-b640327fb5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693179521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1693179521
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.549454289
Short name T514
Test name
Test status
Simulation time 162520454525 ps
CPU time 344.97 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:47:25 PM PDT 24
Peak memory 248920 kb
Host smart-aee37703-1523-451c-942f-7ddbf0ffd371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549454289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.549454289
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.460333037
Short name T463
Test name
Test status
Simulation time 252236029773 ps
CPU time 347.19 seconds
Started May 26 02:41:40 PM PDT 24
Finished May 26 02:47:28 PM PDT 24
Peak memory 253288 kb
Host smart-17fc51af-d122-4773-bcb2-0241b236e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460333037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.460333037
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3783822347
Short name T308
Test name
Test status
Simulation time 612935582 ps
CPU time 6.84 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:49 PM PDT 24
Peak memory 224220 kb
Host smart-d3f29dea-a1f7-46af-a5d9-d7acf1f9ee6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783822347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3783822347
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2031310161
Short name T574
Test name
Test status
Simulation time 132031816 ps
CPU time 2.27 seconds
Started May 26 02:41:32 PM PDT 24
Finished May 26 02:41:35 PM PDT 24
Peak memory 220900 kb
Host smart-255b64b3-176e-4ee1-a305-3764bd0d5fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031310161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2031310161
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2774634582
Short name T664
Test name
Test status
Simulation time 445103110 ps
CPU time 4.3 seconds
Started May 26 02:41:29 PM PDT 24
Finished May 26 02:41:34 PM PDT 24
Peak memory 233432 kb
Host smart-3e6d9a8c-21b0-4210-88c7-68e4d4a6f769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774634582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2774634582
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1032597281
Short name T600
Test name
Test status
Simulation time 118722793 ps
CPU time 2.68 seconds
Started May 26 02:41:32 PM PDT 24
Finished May 26 02:41:36 PM PDT 24
Peak memory 218212 kb
Host smart-c5b9ad59-ed35-4e90-b879-2c65ba2b8334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032597281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1032597281
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2100718837
Short name T488
Test name
Test status
Simulation time 2219083432 ps
CPU time 7.59 seconds
Started May 26 02:41:29 PM PDT 24
Finished May 26 02:41:38 PM PDT 24
Peak memory 234012 kb
Host smart-a2bbad86-2f48-4afe-bd7b-e7e99d4aba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100718837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2100718837
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3493895457
Short name T387
Test name
Test status
Simulation time 1060724589 ps
CPU time 15.42 seconds
Started May 26 02:41:44 PM PDT 24
Finished May 26 02:42:00 PM PDT 24
Peak memory 222672 kb
Host smart-05362d51-3e5c-4eed-81fd-d3b4aba68c3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493895457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3493895457
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3586018577
Short name T457
Test name
Test status
Simulation time 3745235745 ps
CPU time 65.02 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:42:46 PM PDT 24
Peak memory 252600 kb
Host smart-168a2333-f62e-4fa0-a60b-3eea767dead0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586018577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3586018577
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.104854482
Short name T682
Test name
Test status
Simulation time 4548353216 ps
CPU time 7.09 seconds
Started May 26 02:41:30 PM PDT 24
Finished May 26 02:41:39 PM PDT 24
Peak memory 216044 kb
Host smart-3c2ce4d8-0c91-4a07-b1e4-4f62e56995fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104854482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.104854482
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1631947837
Short name T877
Test name
Test status
Simulation time 1706287695 ps
CPU time 4.08 seconds
Started May 26 02:41:30 PM PDT 24
Finished May 26 02:41:35 PM PDT 24
Peak memory 215860 kb
Host smart-ed1b9006-169b-436c-8103-870b3f826d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631947837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1631947837
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3647874143
Short name T327
Test name
Test status
Simulation time 98990555 ps
CPU time 0.68 seconds
Started May 26 02:41:31 PM PDT 24
Finished May 26 02:41:33 PM PDT 24
Peak memory 204948 kb
Host smart-41d7f0e0-253f-4b12-89b7-29389857464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647874143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3647874143
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2955230728
Short name T356
Test name
Test status
Simulation time 202567621 ps
CPU time 0.7 seconds
Started May 26 02:41:33 PM PDT 24
Finished May 26 02:41:35 PM PDT 24
Peak memory 205312 kb
Host smart-0bc62b3b-7c25-40ae-a9ec-f8d6d564ef10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955230728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2955230728
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2606817382
Short name T287
Test name
Test status
Simulation time 14229966640 ps
CPU time 15.69 seconds
Started May 26 02:41:30 PM PDT 24
Finished May 26 02:41:46 PM PDT 24
Peak memory 233764 kb
Host smart-a7c8557e-37e3-4a39-9ce6-8a7b7de14643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606817382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2606817382
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2706213717
Short name T969
Test name
Test status
Simulation time 14452188 ps
CPU time 0.72 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:41:41 PM PDT 24
Peak memory 204892 kb
Host smart-dddaaeb3-8c18-4f6e-8dd2-235e08e6302e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706213717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2706213717
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3572797114
Short name T291
Test name
Test status
Simulation time 8418648262 ps
CPU time 14.21 seconds
Started May 26 02:41:38 PM PDT 24
Finished May 26 02:41:54 PM PDT 24
Peak memory 237180 kb
Host smart-d7282485-04f8-4c68-bf12-ad985e58e834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572797114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3572797114
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.927533823
Short name T376
Test name
Test status
Simulation time 59386144 ps
CPU time 0.76 seconds
Started May 26 02:41:43 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 204924 kb
Host smart-a8174645-40fd-4f9e-8709-e9111c1ad327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927533823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.927533823
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4019369725
Short name T905
Test name
Test status
Simulation time 3920878855 ps
CPU time 50.32 seconds
Started May 26 02:41:37 PM PDT 24
Finished May 26 02:42:28 PM PDT 24
Peak memory 249008 kb
Host smart-9f3b89f1-fb2d-465e-8243-7c20babdbe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019369725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4019369725
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1315772228
Short name T400
Test name
Test status
Simulation time 6063471083 ps
CPU time 14.24 seconds
Started May 26 02:41:37 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 219304 kb
Host smart-f21b4044-e053-43d6-b750-6b538f5daa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315772228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1315772228
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.102488003
Short name T452
Test name
Test status
Simulation time 23892569501 ps
CPU time 184.78 seconds
Started May 26 02:41:38 PM PDT 24
Finished May 26 02:44:44 PM PDT 24
Peak memory 249164 kb
Host smart-f5c7d5a3-062d-400d-9e70-985eeba36368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102488003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.102488003
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3703328200
Short name T305
Test name
Test status
Simulation time 179480997 ps
CPU time 5.21 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:47 PM PDT 24
Peak memory 224144 kb
Host smart-f41b8a26-8925-4087-bf78-62930738944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703328200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3703328200
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3360298274
Short name T220
Test name
Test status
Simulation time 7769502960 ps
CPU time 13.4 seconds
Started May 26 02:41:37 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 235020 kb
Host smart-2ae28861-5db4-4a11-a539-13c8a154b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360298274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3360298274
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2058055279
Short name T896
Test name
Test status
Simulation time 31429482270 ps
CPU time 62.93 seconds
Started May 26 02:41:43 PM PDT 24
Finished May 26 02:42:47 PM PDT 24
Peak memory 240512 kb
Host smart-7ff7a425-8fa3-4700-95a6-63599ca146f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058055279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2058055279
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1255397832
Short name T299
Test name
Test status
Simulation time 2344988510 ps
CPU time 5.44 seconds
Started May 26 02:41:40 PM PDT 24
Finished May 26 02:41:47 PM PDT 24
Peak memory 218248 kb
Host smart-a496eef2-676b-47f9-8cb3-f0ac4b2ea00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255397832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1255397832
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.644489226
Short name T555
Test name
Test status
Simulation time 764135516 ps
CPU time 5.81 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:48 PM PDT 24
Peak memory 224140 kb
Host smart-f7f3d839-e045-43e3-aac1-900b8915706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644489226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.644489226
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3927920976
Short name T142
Test name
Test status
Simulation time 634453826 ps
CPU time 4.57 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 218356 kb
Host smart-a27694f9-9451-42e8-bff0-bd968b44805a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3927920976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3927920976
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3844605532
Short name T50
Test name
Test status
Simulation time 30498286575 ps
CPU time 33.12 seconds
Started May 26 02:41:43 PM PDT 24
Finished May 26 02:42:17 PM PDT 24
Peak memory 215880 kb
Host smart-a9dc3fce-f943-4c03-b604-d8003dc0e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844605532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3844605532
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2714519176
Short name T429
Test name
Test status
Simulation time 439120018 ps
CPU time 2.87 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 215848 kb
Host smart-f2c17672-f512-47a1-b302-21fc1946f5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714519176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2714519176
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1352309267
Short name T824
Test name
Test status
Simulation time 72664139 ps
CPU time 0.79 seconds
Started May 26 02:41:37 PM PDT 24
Finished May 26 02:41:39 PM PDT 24
Peak memory 205992 kb
Host smart-ca9e9161-b07d-445f-93e9-9d5da6ffe7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352309267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1352309267
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3852455861
Short name T498
Test name
Test status
Simulation time 489366044 ps
CPU time 1.11 seconds
Started May 26 02:41:37 PM PDT 24
Finished May 26 02:41:40 PM PDT 24
Peak memory 206328 kb
Host smart-0890a877-b868-4e75-a370-c26b9a6275b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852455861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3852455861
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3873127428
Short name T391
Test name
Test status
Simulation time 9718261297 ps
CPU time 8.62 seconds
Started May 26 02:41:43 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 216976 kb
Host smart-5f7e71d4-e01a-4d16-89fe-0c3807f80f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873127428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3873127428
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3008225885
Short name T886
Test name
Test status
Simulation time 21722314 ps
CPU time 0.76 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:43 PM PDT 24
Peak memory 205080 kb
Host smart-98a87a1f-2309-4abd-bd24-93e2986e78ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008225885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3008225885
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.216772716
Short name T33
Test name
Test status
Simulation time 314743635 ps
CPU time 2.04 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:44 PM PDT 24
Peak memory 218288 kb
Host smart-d50b8c55-2824-42a2-a7b4-cd9471c3ed83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216772716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.216772716
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1429227362
Short name T964
Test name
Test status
Simulation time 20838453 ps
CPU time 0.78 seconds
Started May 26 02:41:43 PM PDT 24
Finished May 26 02:41:44 PM PDT 24
Peak memory 205244 kb
Host smart-ac53202e-d7a1-4532-aec7-70f04c902e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429227362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1429227362
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2694849849
Short name T938
Test name
Test status
Simulation time 69670186439 ps
CPU time 249.07 seconds
Started May 26 02:41:43 PM PDT 24
Finished May 26 02:45:53 PM PDT 24
Peak memory 252380 kb
Host smart-91adcdd0-63e4-4f4e-b6dc-92a683c4faf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694849849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2694849849
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.834277880
Short name T257
Test name
Test status
Simulation time 5406138717 ps
CPU time 82.73 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:43:03 PM PDT 24
Peak memory 250156 kb
Host smart-718df467-c6e8-4ef2-930f-ea225ff7febf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834277880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.834277880
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1579496701
Short name T900
Test name
Test status
Simulation time 261624748139 ps
CPU time 582.41 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:51:32 PM PDT 24
Peak memory 251668 kb
Host smart-6b324c72-6bdc-4550-904d-adff0c0ea108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579496701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1579496701
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2987084792
Short name T758
Test name
Test status
Simulation time 168824254 ps
CPU time 3.51 seconds
Started May 26 02:41:44 PM PDT 24
Finished May 26 02:41:48 PM PDT 24
Peak memory 232556 kb
Host smart-f588d8c4-31e0-444a-a58e-ed79288438f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987084792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2987084792
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3321298977
Short name T753
Test name
Test status
Simulation time 6790790103 ps
CPU time 5.22 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:47 PM PDT 24
Peak memory 218788 kb
Host smart-d7122bbc-2acf-40d8-ad03-cc641ef3dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321298977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3321298977
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2806159488
Short name T184
Test name
Test status
Simulation time 6152150339 ps
CPU time 78.55 seconds
Started May 26 02:41:37 PM PDT 24
Finished May 26 02:42:56 PM PDT 24
Peak memory 232212 kb
Host smart-83575a90-35e4-4224-a120-237fd1f26252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806159488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2806159488
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1648725083
Short name T568
Test name
Test status
Simulation time 1216572304 ps
CPU time 9.08 seconds
Started May 26 02:41:42 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 228812 kb
Host smart-4db9dcfb-643e-48d6-8161-04db4678287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648725083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1648725083
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2107250421
Short name T562
Test name
Test status
Simulation time 63542182 ps
CPU time 2.47 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 221020 kb
Host smart-f87c1789-74cb-44f6-b6f7-442d0ababcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107250421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2107250421
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4232967529
Short name T352
Test name
Test status
Simulation time 3920097594 ps
CPU time 12.06 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 222592 kb
Host smart-d173b2f0-1e75-4577-bf47-2b39e2861c31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4232967529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4232967529
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1970067535
Short name T630
Test name
Test status
Simulation time 28756561891 ps
CPU time 15.81 seconds
Started May 26 02:41:39 PM PDT 24
Finished May 26 02:41:56 PM PDT 24
Peak memory 215992 kb
Host smart-d912952a-af6c-45fb-bb5c-c0bcc269628e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970067535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1970067535
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2969432863
Short name T626
Test name
Test status
Simulation time 327709166 ps
CPU time 2.15 seconds
Started May 26 02:41:41 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 215828 kb
Host smart-6e07c3eb-0d31-45c5-8411-8863f88af489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969432863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2969432863
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.400899752
Short name T347
Test name
Test status
Simulation time 18012612 ps
CPU time 0.69 seconds
Started May 26 02:41:37 PM PDT 24
Finished May 26 02:41:39 PM PDT 24
Peak memory 204952 kb
Host smart-2f4ab835-7737-41c9-9cc9-26213c5d7e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400899752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.400899752
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2135135037
Short name T381
Test name
Test status
Simulation time 180032032 ps
CPU time 0.87 seconds
Started May 26 02:41:43 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 205300 kb
Host smart-2d0dc2fb-16ee-48ba-8481-e79c8c126875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135135037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2135135037
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3274481850
Short name T296
Test name
Test status
Simulation time 101219975999 ps
CPU time 27.91 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:42:17 PM PDT 24
Peak memory 233860 kb
Host smart-67fe7a27-69ef-43ea-a072-5d088943b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274481850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3274481850
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2911793882
Short name T741
Test name
Test status
Simulation time 11087656 ps
CPU time 0.69 seconds
Started May 26 02:41:49 PM PDT 24
Finished May 26 02:41:51 PM PDT 24
Peak memory 204676 kb
Host smart-c8c0c6e9-df36-4e46-8f3f-700ef082dfa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911793882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2911793882
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.15311545
Short name T772
Test name
Test status
Simulation time 48503405 ps
CPU time 2.57 seconds
Started May 26 02:41:49 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 233200 kb
Host smart-0cd82bca-b42b-4a9e-af0a-754bcffde151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15311545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.15311545
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.822856916
Short name T723
Test name
Test status
Simulation time 27419620 ps
CPU time 0.79 seconds
Started May 26 02:41:38 PM PDT 24
Finished May 26 02:41:40 PM PDT 24
Peak memory 205960 kb
Host smart-9a609f82-491b-4833-a53b-63f8ff5d29c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822856916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.822856916
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.739295240
Short name T266
Test name
Test status
Simulation time 42047688641 ps
CPU time 333.48 seconds
Started May 26 02:41:49 PM PDT 24
Finished May 26 02:47:24 PM PDT 24
Peak memory 257016 kb
Host smart-8828479c-0b99-41ee-af89-373adea41cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739295240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.739295240
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1122811206
Short name T239
Test name
Test status
Simulation time 9559946499 ps
CPU time 144.02 seconds
Started May 26 02:41:47 PM PDT 24
Finished May 26 02:44:11 PM PDT 24
Peak memory 256780 kb
Host smart-bb3e3ded-2a27-459b-910c-c163320ca1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122811206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1122811206
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3947448405
Short name T23
Test name
Test status
Simulation time 152156311737 ps
CPU time 591 seconds
Started May 26 02:41:46 PM PDT 24
Finished May 26 02:51:38 PM PDT 24
Peak memory 255832 kb
Host smart-b00ad65c-2e26-4e6c-81fc-cd999642d983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947448405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3947448405
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1435596943
Short name T311
Test name
Test status
Simulation time 8012507046 ps
CPU time 41.83 seconds
Started May 26 02:41:50 PM PDT 24
Finished May 26 02:42:33 PM PDT 24
Peak memory 232488 kb
Host smart-a7b48c95-1e8f-4b70-8830-ed90e8a0aeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435596943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1435596943
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.875574215
Short name T128
Test name
Test status
Simulation time 63741379 ps
CPU time 3.04 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:01 PM PDT 24
Peak memory 232392 kb
Host smart-0d51278b-9925-4d14-8160-2d1e93f5d7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875574215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.875574215
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1410322887
Short name T58
Test name
Test status
Simulation time 1893291907 ps
CPU time 11.28 seconds
Started May 26 02:41:45 PM PDT 24
Finished May 26 02:41:57 PM PDT 24
Peak memory 233356 kb
Host smart-7404e52b-1893-406f-95b7-917ffbb88d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410322887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1410322887
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1533939342
Short name T588
Test name
Test status
Simulation time 134844994 ps
CPU time 3.47 seconds
Started May 26 02:41:50 PM PDT 24
Finished May 26 02:41:55 PM PDT 24
Peak memory 232400 kb
Host smart-6dc96aa5-b227-4d52-9056-caf9778a726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533939342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1533939342
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3783966292
Short name T916
Test name
Test status
Simulation time 1134101533 ps
CPU time 2.39 seconds
Started May 26 02:41:47 PM PDT 24
Finished May 26 02:41:50 PM PDT 24
Peak memory 218096 kb
Host smart-a5a12510-9e4f-4297-8f5b-a32ab49d879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783966292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3783966292
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4287459997
Short name T792
Test name
Test status
Simulation time 121781712 ps
CPU time 3.95 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 219756 kb
Host smart-1d9590b5-0091-4c8b-a167-903600aa63d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4287459997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4287459997
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4198561851
Short name T135
Test name
Test status
Simulation time 32412264629 ps
CPU time 210.05 seconds
Started May 26 02:41:46 PM PDT 24
Finished May 26 02:45:17 PM PDT 24
Peak memory 255308 kb
Host smart-5ccec821-5785-4e64-83f6-dbcea724b5a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198561851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4198561851
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3328341869
Short name T469
Test name
Test status
Simulation time 550497888 ps
CPU time 6.22 seconds
Started May 26 02:41:38 PM PDT 24
Finished May 26 02:41:45 PM PDT 24
Peak memory 215956 kb
Host smart-17208b6e-a7c3-4e20-87c0-0ee3f1205295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328341869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3328341869
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1322066630
Short name T425
Test name
Test status
Simulation time 7462384205 ps
CPU time 6.87 seconds
Started May 26 02:41:38 PM PDT 24
Finished May 26 02:41:47 PM PDT 24
Peak memory 215896 kb
Host smart-ed305d0a-875f-4f29-931f-80a034b9fbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322066630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1322066630
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3064240835
Short name T321
Test name
Test status
Simulation time 271871338 ps
CPU time 1.06 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:41:58 PM PDT 24
Peak memory 207468 kb
Host smart-bf7ee6f5-bb9f-4e64-b279-9e2623bf8789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064240835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3064240835
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1819085937
Short name T640
Test name
Test status
Simulation time 124404441 ps
CPU time 0.9 seconds
Started May 26 02:41:37 PM PDT 24
Finished May 26 02:41:40 PM PDT 24
Peak memory 205292 kb
Host smart-7e92db4e-66c4-4388-8f94-cdd29bca5117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819085937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1819085937
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.494417901
Short name T834
Test name
Test status
Simulation time 137792843 ps
CPU time 4.32 seconds
Started May 26 02:41:50 PM PDT 24
Finished May 26 02:41:56 PM PDT 24
Peak memory 223860 kb
Host smart-904178ff-51e8-43e7-94d1-2bcb0a96284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494417901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.494417901
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3393100033
Short name T467
Test name
Test status
Simulation time 202737313 ps
CPU time 0.74 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:41:50 PM PDT 24
Peak memory 205264 kb
Host smart-598fb325-ccd9-44f1-b622-da0609d7ed4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393100033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3393100033
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2219479807
Short name T219
Test name
Test status
Simulation time 732119647 ps
CPU time 3.8 seconds
Started May 26 02:41:46 PM PDT 24
Finished May 26 02:41:51 PM PDT 24
Peak memory 218460 kb
Host smart-2e7a167f-0f7d-46d2-bd1f-8084809cd60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219479807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2219479807
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1708452791
Short name T383
Test name
Test status
Simulation time 41033225 ps
CPU time 0.78 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:41:50 PM PDT 24
Peak memory 205936 kb
Host smart-3bd03f6b-5cfd-4d65-9873-5dd0ac16ba7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708452791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1708452791
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2305864066
Short name T96
Test name
Test status
Simulation time 72540877467 ps
CPU time 121.07 seconds
Started May 26 02:41:51 PM PDT 24
Finished May 26 02:43:53 PM PDT 24
Peak memory 224220 kb
Host smart-41c499e8-4bdb-4ee0-8123-347bbf1a2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305864066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2305864066
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1034750351
Short name T603
Test name
Test status
Simulation time 26312024757 ps
CPU time 211.65 seconds
Started May 26 02:41:47 PM PDT 24
Finished May 26 02:45:19 PM PDT 24
Peak memory 254292 kb
Host smart-ca15d6ef-fde6-41a6-9023-52f4db26c9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034750351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1034750351
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3385144197
Short name T499
Test name
Test status
Simulation time 3639691226 ps
CPU time 79.55 seconds
Started May 26 02:41:49 PM PDT 24
Finished May 26 02:43:10 PM PDT 24
Peak memory 248868 kb
Host smart-d3f30673-1132-4e67-ac20-e3580a7288d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385144197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3385144197
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1118240591
Short name T310
Test name
Test status
Simulation time 197494819 ps
CPU time 6.55 seconds
Started May 26 02:41:51 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 224216 kb
Host smart-85c80af4-c312-4ece-907b-6881bd869da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118240591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1118240591
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3928901896
Short name T276
Test name
Test status
Simulation time 201119483 ps
CPU time 5.38 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 233588 kb
Host smart-4f1b6ff3-13b8-4e59-9f4d-a5e4db394a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928901896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3928901896
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2449138701
Short name T850
Test name
Test status
Simulation time 948536723 ps
CPU time 13.92 seconds
Started May 26 02:41:45 PM PDT 24
Finished May 26 02:42:00 PM PDT 24
Peak memory 232372 kb
Host smart-3c3aac9c-0123-43d5-be38-ff642f3964eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449138701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2449138701
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3906768078
Short name T865
Test name
Test status
Simulation time 895809306 ps
CPU time 5.76 seconds
Started May 26 02:41:47 PM PDT 24
Finished May 26 02:41:54 PM PDT 24
Peak memory 237216 kb
Host smart-becad92d-a2a0-4bb6-b8c5-ced8bcbf062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906768078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3906768078
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.763885289
Short name T785
Test name
Test status
Simulation time 3491209172 ps
CPU time 10.27 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 233156 kb
Host smart-d108323c-e1b4-4d6d-af46-4f65e44822c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763885289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.763885289
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1732933775
Short name T783
Test name
Test status
Simulation time 784359358 ps
CPU time 9.29 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 218392 kb
Host smart-ab642d7f-9f79-4d37-9419-ceeab40277f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1732933775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1732933775
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.428355604
Short name T256
Test name
Test status
Simulation time 16981279231 ps
CPU time 101.31 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:43:30 PM PDT 24
Peak memory 254072 kb
Host smart-f6278841-0b56-4cff-ad4b-797cd605ba00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428355604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.428355604
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3875975914
Short name T91
Test name
Test status
Simulation time 1160223371 ps
CPU time 9.19 seconds
Started May 26 02:41:51 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 219672 kb
Host smart-10cf5917-6111-495e-8085-dddd741947a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875975914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3875975914
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2850142476
Short name T18
Test name
Test status
Simulation time 8367052556 ps
CPU time 4.54 seconds
Started May 26 02:41:49 PM PDT 24
Finished May 26 02:41:55 PM PDT 24
Peak memory 216104 kb
Host smart-c1d09c21-782c-48cb-9f4f-ed90c5d459f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850142476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2850142476
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2608987534
Short name T127
Test name
Test status
Simulation time 137599066 ps
CPU time 6.68 seconds
Started May 26 02:41:50 PM PDT 24
Finished May 26 02:41:58 PM PDT 24
Peak memory 215980 kb
Host smart-3bc3d45b-9161-4cca-9bfe-47047d6de39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608987534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2608987534
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2100769387
Short name T820
Test name
Test status
Simulation time 29036915 ps
CPU time 0.69 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:41:50 PM PDT 24
Peak memory 205092 kb
Host smart-4669cee9-215c-48cc-a3c1-56ada92c5763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100769387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2100769387
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1887853509
Short name T377
Test name
Test status
Simulation time 3911033835 ps
CPU time 8.3 seconds
Started May 26 02:41:49 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 216988 kb
Host smart-af51bcfb-165b-46b9-9717-a4aaf7b38e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887853509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1887853509
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.144761002
Short name T545
Test name
Test status
Simulation time 43272310 ps
CPU time 0.72 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:00 PM PDT 24
Peak memory 204924 kb
Host smart-6cbfc564-ff33-46de-af7a-a36271873f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144761002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.144761002
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.110771960
Short name T814
Test name
Test status
Simulation time 1544842875 ps
CPU time 3.21 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 217480 kb
Host smart-e90cdce3-2952-4f0f-8d76-bb3139d5426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110771960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.110771960
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3489116698
Short name T413
Test name
Test status
Simulation time 15303151 ps
CPU time 0.77 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:41:58 PM PDT 24
Peak memory 206244 kb
Host smart-58636605-b2e0-44b1-9e59-f6170a33702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489116698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3489116698
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3998953968
Short name T366
Test name
Test status
Simulation time 1570861407 ps
CPU time 9.36 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:08 PM PDT 24
Peak memory 237368 kb
Host smart-db9adff6-1a9b-4e89-b944-60d0afb31c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998953968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3998953968
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1774705118
Short name T53
Test name
Test status
Simulation time 75775623620 ps
CPU time 384.15 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:48:22 PM PDT 24
Peak memory 251856 kb
Host smart-1bf5651e-aec2-47be-b7b2-6b848aeb22e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774705118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1774705118
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.508674796
Short name T502
Test name
Test status
Simulation time 11964893407 ps
CPU time 47.07 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:45 PM PDT 24
Peak memory 249068 kb
Host smart-59a87915-4eb3-4a77-8186-601455036f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508674796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.508674796
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.350719631
Short name T635
Test name
Test status
Simulation time 582908921 ps
CPU time 3.7 seconds
Started May 26 02:41:51 PM PDT 24
Finished May 26 02:41:56 PM PDT 24
Peak memory 224104 kb
Host smart-f59017e7-928b-4040-95ba-3a1c62c7667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350719631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.350719631
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2938469457
Short name T212
Test name
Test status
Simulation time 253007985 ps
CPU time 6.06 seconds
Started May 26 02:41:50 PM PDT 24
Finished May 26 02:41:58 PM PDT 24
Peak memory 219372 kb
Host smart-35dc380a-3009-466c-af10-0a38b6f21d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938469457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2938469457
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2349064990
Short name T218
Test name
Test status
Simulation time 8414537213 ps
CPU time 34.22 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:42:23 PM PDT 24
Peak memory 226188 kb
Host smart-1fdfc94f-65b0-4366-abc2-968753e1dc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349064990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2349064990
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.356160184
Short name T185
Test name
Test status
Simulation time 6004771885 ps
CPU time 16.46 seconds
Started May 26 02:41:49 PM PDT 24
Finished May 26 02:42:07 PM PDT 24
Peak memory 233180 kb
Host smart-28607177-3950-447e-9322-bd3698bed3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356160184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.356160184
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2613274762
Short name T906
Test name
Test status
Simulation time 12309764761 ps
CPU time 11.01 seconds
Started May 26 02:41:50 PM PDT 24
Finished May 26 02:42:03 PM PDT 24
Peak memory 236492 kb
Host smart-12d18928-5f13-4738-82b1-726f930eaa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613274762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2613274762
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.372146953
Short name T945
Test name
Test status
Simulation time 1533079594 ps
CPU time 7.41 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:05 PM PDT 24
Peak memory 222648 kb
Host smart-5b035054-b6d5-4e5a-84db-71e2739bd000
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=372146953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.372146953
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3218482332
Short name T726
Test name
Test status
Simulation time 39198412 ps
CPU time 1 seconds
Started May 26 02:42:01 PM PDT 24
Finished May 26 02:42:03 PM PDT 24
Peak memory 205980 kb
Host smart-4d48378f-3147-4cca-b6fb-0f9452ac6f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218482332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3218482332
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3750154789
Short name T61
Test name
Test status
Simulation time 601820285 ps
CPU time 9.98 seconds
Started May 26 02:41:51 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 215976 kb
Host smart-f3bad327-68a8-4843-a67b-449682969ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750154789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3750154789
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.273237327
Short name T596
Test name
Test status
Simulation time 2622523094 ps
CPU time 6.04 seconds
Started May 26 02:41:46 PM PDT 24
Finished May 26 02:41:53 PM PDT 24
Peak memory 215924 kb
Host smart-913ffd3b-34df-4c41-bf00-b03df34e8000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273237327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.273237327
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3166185056
Short name T840
Test name
Test status
Simulation time 178525748 ps
CPU time 2.22 seconds
Started May 26 02:41:51 PM PDT 24
Finished May 26 02:41:55 PM PDT 24
Peak memory 215976 kb
Host smart-8fb38ac7-43f2-4941-a53c-96c4ba25a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166185056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3166185056
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4247427637
Short name T775
Test name
Test status
Simulation time 40777914 ps
CPU time 0.78 seconds
Started May 26 02:41:48 PM PDT 24
Finished May 26 02:41:51 PM PDT 24
Peak memory 205312 kb
Host smart-b114a320-f839-46db-8933-5c66feb8d69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247427637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4247427637
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1508591805
Short name T28
Test name
Test status
Simulation time 578139490 ps
CPU time 4.57 seconds
Started May 26 02:41:47 PM PDT 24
Finished May 26 02:41:52 PM PDT 24
Peak memory 218468 kb
Host smart-c2aced48-982d-433f-94e9-7efa6e8cc34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508591805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1508591805
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.963692746
Short name T80
Test name
Test status
Simulation time 14557091 ps
CPU time 0.71 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 204932 kb
Host smart-7d8d2338-c56c-4293-aaff-916159aaf6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963692746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.963692746
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4007199040
Short name T776
Test name
Test status
Simulation time 349779740 ps
CPU time 3.7 seconds
Started May 26 02:41:54 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 218268 kb
Host smart-90e16a99-240a-41d4-a7d8-0cfc74f64ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007199040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4007199040
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.935346066
Short name T641
Test name
Test status
Simulation time 18170332 ps
CPU time 0.82 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:00 PM PDT 24
Peak memory 206420 kb
Host smart-0ae40c6c-7f87-4fb2-b86c-7848dc82fd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935346066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.935346066
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.587102172
Short name T812
Test name
Test status
Simulation time 2357953184 ps
CPU time 31.05 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:30 PM PDT 24
Peak memory 240060 kb
Host smart-342b7499-a973-4686-9eae-5164a2403569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587102172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.587102172
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3285227765
Short name T878
Test name
Test status
Simulation time 4350107040 ps
CPU time 18.54 seconds
Started May 26 02:41:58 PM PDT 24
Finished May 26 02:42:18 PM PDT 24
Peak memory 233492 kb
Host smart-bef2d28b-19c6-4429-b0ce-263b43f8702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285227765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3285227765
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3310176790
Short name T913
Test name
Test status
Simulation time 191985741 ps
CPU time 2.46 seconds
Started May 26 02:41:55 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 220648 kb
Host smart-db793dce-5727-4d12-9b28-da0cd3377239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310176790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3310176790
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3799528787
Short name T932
Test name
Test status
Simulation time 75155906 ps
CPU time 2.2 seconds
Started May 26 02:42:02 PM PDT 24
Finished May 26 02:42:05 PM PDT 24
Peak memory 215780 kb
Host smart-99ae66b4-8566-4528-9e8b-705f7c510c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799528787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3799528787
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1779872267
Short name T703
Test name
Test status
Simulation time 2469929396 ps
CPU time 7.3 seconds
Started May 26 02:41:55 PM PDT 24
Finished May 26 02:42:03 PM PDT 24
Peak memory 218432 kb
Host smart-60f2a80f-3747-4b1e-943c-6183babe9e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779872267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1779872267
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.768297184
Short name T593
Test name
Test status
Simulation time 11714678802 ps
CPU time 9.96 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:07 PM PDT 24
Peak memory 232476 kb
Host smart-83bcf084-4f02-486d-b7cf-3d1f041bd4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768297184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.768297184
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2087373677
Short name T565
Test name
Test status
Simulation time 1271767798 ps
CPU time 13.07 seconds
Started May 26 02:41:53 PM PDT 24
Finished May 26 02:42:07 PM PDT 24
Peak memory 220244 kb
Host smart-8bd173fe-3af8-4baa-85bd-345506f75b20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087373677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2087373677
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2666258945
Short name T72
Test name
Test status
Simulation time 32411927268 ps
CPU time 67.5 seconds
Started May 26 02:42:00 PM PDT 24
Finished May 26 02:43:09 PM PDT 24
Peak memory 248700 kb
Host smart-edc281ab-0763-48aa-b1e3-6b96294d2273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666258945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2666258945
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.194030065
Short name T319
Test name
Test status
Simulation time 1169860355 ps
CPU time 8.57 seconds
Started May 26 02:41:58 PM PDT 24
Finished May 26 02:42:08 PM PDT 24
Peak memory 215980 kb
Host smart-e2721700-658f-4327-abb3-e03ac639b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194030065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.194030065
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1541197061
Short name T339
Test name
Test status
Simulation time 704186416 ps
CPU time 5.29 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:04 PM PDT 24
Peak memory 215820 kb
Host smart-09375014-9730-4c49-b24f-2730e809c43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541197061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1541197061
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2991833581
Short name T738
Test name
Test status
Simulation time 184455692 ps
CPU time 5.53 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:04 PM PDT 24
Peak memory 215936 kb
Host smart-a022795f-eee3-4e37-bdb0-0af34881d017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991833581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2991833581
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.730674678
Short name T439
Test name
Test status
Simulation time 15971529 ps
CPU time 0.75 seconds
Started May 26 02:42:02 PM PDT 24
Finished May 26 02:42:03 PM PDT 24
Peak memory 205340 kb
Host smart-3202f17c-2460-47c3-ac67-fabd3137dbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730674678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.730674678
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3926102129
Short name T660
Test name
Test status
Simulation time 104778826 ps
CPU time 2.13 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:41:59 PM PDT 24
Peak memory 207492 kb
Host smart-951a19f3-6eca-4ecc-af16-896bcbbb7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926102129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3926102129
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.514928686
Short name T325
Test name
Test status
Simulation time 30187202 ps
CPU time 0.73 seconds
Started May 26 02:42:01 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 204304 kb
Host smart-85c92d8a-90e5-4a0d-a285-af9880f1e3d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514928686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.514928686
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3624843556
Short name T887
Test name
Test status
Simulation time 1783333890 ps
CPU time 6.14 seconds
Started May 26 02:41:55 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 219868 kb
Host smart-c3bb6ce6-3461-47df-bac0-509045654650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624843556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3624843556
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.538182633
Short name T130
Test name
Test status
Simulation time 17940533 ps
CPU time 0.75 seconds
Started May 26 02:41:55 PM PDT 24
Finished May 26 02:41:57 PM PDT 24
Peak memory 206280 kb
Host smart-3f1d2c18-339c-4e63-9d25-bb829bf74dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538182633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.538182633
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.51489241
Short name T915
Test name
Test status
Simulation time 427797218229 ps
CPU time 388.97 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:48:26 PM PDT 24
Peak memory 262384 kb
Host smart-86809670-15c0-45bc-b029-90934c2dc17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51489241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.51489241
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2964321962
Short name T192
Test name
Test status
Simulation time 100429666106 ps
CPU time 204.28 seconds
Started May 26 02:41:59 PM PDT 24
Finished May 26 02:45:24 PM PDT 24
Peak memory 253752 kb
Host smart-89d4c0cf-3785-48b5-84a0-f6a0a4d53b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964321962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2964321962
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4269218778
Short name T85
Test name
Test status
Simulation time 5380434650 ps
CPU time 32.31 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:38 PM PDT 24
Peak memory 234672 kb
Host smart-8b7f9140-2853-4468-8556-fd867daa722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269218778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4269218778
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1015825708
Short name T707
Test name
Test status
Simulation time 338649245 ps
CPU time 6.55 seconds
Started May 26 02:42:03 PM PDT 24
Finished May 26 02:42:11 PM PDT 24
Peak memory 238464 kb
Host smart-bf057ae0-836f-47db-b749-ea228ae3fbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015825708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1015825708
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1950470577
Short name T87
Test name
Test status
Simulation time 1354643132 ps
CPU time 13.06 seconds
Started May 26 02:42:00 PM PDT 24
Finished May 26 02:42:14 PM PDT 24
Peak memory 233448 kb
Host smart-f31f7cc7-f762-4f2c-bdba-0b10ed5134bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950470577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1950470577
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3808596818
Short name T745
Test name
Test status
Simulation time 20922724912 ps
CPU time 22.85 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:21 PM PDT 24
Peak memory 224196 kb
Host smart-83c0a59c-2e9c-4907-b710-63ee80563d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808596818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3808596818
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.511649516
Short name T701
Test name
Test status
Simulation time 115195361 ps
CPU time 2.09 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:00 PM PDT 24
Peak memory 224120 kb
Host smart-1f38d05e-eb0d-4244-9d9d-29e11416e285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511649516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.511649516
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.880720943
Short name T29
Test name
Test status
Simulation time 441225134 ps
CPU time 2.5 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 232404 kb
Host smart-ea7cad1c-b586-44a9-8e59-84d1ee25c55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880720943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.880720943
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1392326186
Short name T496
Test name
Test status
Simulation time 4199712888 ps
CPU time 9.65 seconds
Started May 26 02:41:56 PM PDT 24
Finished May 26 02:42:08 PM PDT 24
Peak memory 222740 kb
Host smart-74a04031-a438-42f0-a66a-0c6e44621c33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1392326186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1392326186
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1855509857
Short name T506
Test name
Test status
Simulation time 227610509 ps
CPU time 1.04 seconds
Started May 26 02:42:02 PM PDT 24
Finished May 26 02:42:04 PM PDT 24
Peak memory 206616 kb
Host smart-8af88d9f-9faa-4e71-a7ad-64f18d12fc6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855509857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1855509857
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.986403889
Short name T477
Test name
Test status
Simulation time 11727375373 ps
CPU time 17.79 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:17 PM PDT 24
Peak memory 215968 kb
Host smart-62f1ad95-621f-422f-997b-b669227ddaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986403889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.986403889
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2532033059
Short name T708
Test name
Test status
Simulation time 59788746110 ps
CPU time 15.33 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:14 PM PDT 24
Peak memory 215908 kb
Host smart-2bdbac73-2703-4148-8bd9-ea192117fc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532033059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2532033059
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3139749175
Short name T543
Test name
Test status
Simulation time 74197621 ps
CPU time 1.44 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:00 PM PDT 24
Peak memory 215856 kb
Host smart-690c1304-0060-4428-8045-60438961a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139749175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3139749175
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1059234424
Short name T380
Test name
Test status
Simulation time 211884995 ps
CPU time 0.98 seconds
Started May 26 02:42:00 PM PDT 24
Finished May 26 02:42:01 PM PDT 24
Peak memory 205556 kb
Host smart-abe6acab-e47f-45f5-88b2-c12f3afb50dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059234424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1059234424
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1126370011
Short name T455
Test name
Test status
Simulation time 46300331771 ps
CPU time 34.69 seconds
Started May 26 02:41:57 PM PDT 24
Finished May 26 02:42:33 PM PDT 24
Peak memory 233076 kb
Host smart-d566b469-86fa-4607-8d40-9319d2021c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126370011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1126370011
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4173006656
Short name T362
Test name
Test status
Simulation time 41059150 ps
CPU time 0.72 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:06 PM PDT 24
Peak memory 204304 kb
Host smart-0ac9c285-73bd-433b-8f5d-4192e5020539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173006656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4173006656
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3292106492
Short name T597
Test name
Test status
Simulation time 1308698857 ps
CPU time 5.33 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:11 PM PDT 24
Peak memory 233444 kb
Host smart-11b7fcae-d7ed-4e30-ae9c-9dd9aebdf0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292106492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3292106492
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3974923672
Short name T341
Test name
Test status
Simulation time 21343502 ps
CPU time 0.79 seconds
Started May 26 02:42:01 PM PDT 24
Finished May 26 02:42:03 PM PDT 24
Peak memory 204892 kb
Host smart-605f34ae-85d2-49fc-9149-7a0dade448b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974923672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3974923672
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2224838350
Short name T180
Test name
Test status
Simulation time 53870884038 ps
CPU time 43.8 seconds
Started May 26 02:42:07 PM PDT 24
Finished May 26 02:42:52 PM PDT 24
Peak memory 240284 kb
Host smart-97f1d6a7-feff-49a5-80bc-c642e356e2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224838350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2224838350
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2868596943
Short name T253
Test name
Test status
Simulation time 77480174086 ps
CPU time 191.88 seconds
Started May 26 02:42:03 PM PDT 24
Finished May 26 02:45:16 PM PDT 24
Peak memory 252580 kb
Host smart-c8b191c4-7ad2-4a46-b938-32f3d74713fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868596943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2868596943
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2806695614
Short name T721
Test name
Test status
Simulation time 3517188544 ps
CPU time 64.97 seconds
Started May 26 02:42:06 PM PDT 24
Finished May 26 02:43:12 PM PDT 24
Peak memory 248888 kb
Host smart-cdf33914-87c0-43e5-9ee5-897fb716e51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806695614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2806695614
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.566207009
Short name T303
Test name
Test status
Simulation time 3771169802 ps
CPU time 44.23 seconds
Started May 26 02:42:02 PM PDT 24
Finished May 26 02:42:47 PM PDT 24
Peak memory 238612 kb
Host smart-9745da17-c2c8-4bc4-ac9e-ff0423a142b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566207009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.566207009
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4228782706
Short name T200
Test name
Test status
Simulation time 43139250 ps
CPU time 2.75 seconds
Started May 26 02:42:00 PM PDT 24
Finished May 26 02:42:04 PM PDT 24
Peak memory 232532 kb
Host smart-b4ca7129-8c60-478f-a236-acc5e62b5d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228782706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4228782706
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2801242581
Short name T389
Test name
Test status
Simulation time 14914806433 ps
CPU time 12.63 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:18 PM PDT 24
Peak memory 238180 kb
Host smart-3182c397-7248-4828-b0bc-70ebead403b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801242581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2801242581
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1315219423
Short name T537
Test name
Test status
Simulation time 1780184268 ps
CPU time 5.78 seconds
Started May 26 02:42:03 PM PDT 24
Finished May 26 02:42:10 PM PDT 24
Peak memory 216428 kb
Host smart-d2ab9e4f-5396-46bf-b96d-383bbc918293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315219423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1315219423
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3356475131
Short name T546
Test name
Test status
Simulation time 497410842 ps
CPU time 4.63 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:10 PM PDT 24
Peak memory 232696 kb
Host smart-19160e80-f7ea-45bd-8beb-8b5bc1de41a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356475131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3356475131
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3938457521
Short name T409
Test name
Test status
Simulation time 2781072002 ps
CPU time 5.58 seconds
Started May 26 02:42:08 PM PDT 24
Finished May 26 02:42:15 PM PDT 24
Peak memory 222708 kb
Host smart-ad40087e-3ed8-4181-aba8-5982820fd87f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3938457521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3938457521
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4091281511
Short name T606
Test name
Test status
Simulation time 3024486972 ps
CPU time 25.31 seconds
Started May 26 02:42:03 PM PDT 24
Finished May 26 02:42:30 PM PDT 24
Peak memory 219480 kb
Host smart-c17c1b20-bebd-4a72-9bc4-c51d11f78c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091281511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4091281511
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2242129367
Short name T744
Test name
Test status
Simulation time 2355467018 ps
CPU time 6.92 seconds
Started May 26 02:42:05 PM PDT 24
Finished May 26 02:42:13 PM PDT 24
Peak memory 215900 kb
Host smart-98239f74-0a14-42c4-a7a3-810d252ead88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242129367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2242129367
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2779283523
Short name T485
Test name
Test status
Simulation time 48298619 ps
CPU time 2.01 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:07 PM PDT 24
Peak memory 215972 kb
Host smart-10c3356b-3e13-4779-86c8-97ce30cc3b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779283523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2779283523
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.561293134
Short name T44
Test name
Test status
Simulation time 436906499 ps
CPU time 0.77 seconds
Started May 26 02:42:03 PM PDT 24
Finished May 26 02:42:05 PM PDT 24
Peak memory 205312 kb
Host smart-b1ec418d-38a3-4c3e-8a73-3ae08a3a2992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561293134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.561293134
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2231026498
Short name T632
Test name
Test status
Simulation time 2587427183 ps
CPU time 11.15 seconds
Started May 26 02:42:02 PM PDT 24
Finished May 26 02:42:14 PM PDT 24
Peak memory 248856 kb
Host smart-bd95f19a-2ab1-4f15-a25e-1da46ac5070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231026498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2231026498
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1073208598
Short name T784
Test name
Test status
Simulation time 37463676 ps
CPU time 0.71 seconds
Started May 26 02:42:02 PM PDT 24
Finished May 26 02:42:04 PM PDT 24
Peak memory 204160 kb
Host smart-7235b381-eedf-40d0-abca-fa0183b4e4e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073208598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1073208598
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1639982141
Short name T83
Test name
Test status
Simulation time 900500129 ps
CPU time 10.01 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:15 PM PDT 24
Peak memory 234012 kb
Host smart-f9e1be49-8b0b-406c-bb02-13155fa1fa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639982141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1639982141
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1751232148
Short name T954
Test name
Test status
Simulation time 56549683 ps
CPU time 0.77 seconds
Started May 26 02:42:06 PM PDT 24
Finished May 26 02:42:08 PM PDT 24
Peak memory 205932 kb
Host smart-edefe2ed-cbd3-4699-852c-dac9efad51f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751232148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1751232148
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1773945155
Short name T49
Test name
Test status
Simulation time 12413524187 ps
CPU time 26.73 seconds
Started May 26 02:42:09 PM PDT 24
Finished May 26 02:42:37 PM PDT 24
Peak memory 220148 kb
Host smart-56f3eb38-3ae0-4bc0-9858-602a0acfcffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773945155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1773945155
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.503665310
Short name T171
Test name
Test status
Simulation time 2625300430 ps
CPU time 14.27 seconds
Started May 26 02:42:07 PM PDT 24
Finished May 26 02:42:22 PM PDT 24
Peak memory 235552 kb
Host smart-1cbd86e9-3a25-4d42-9853-cca59f8b198c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503665310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.503665310
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3157250615
Short name T762
Test name
Test status
Simulation time 11753116812 ps
CPU time 72.22 seconds
Started May 26 02:42:06 PM PDT 24
Finished May 26 02:43:20 PM PDT 24
Peak memory 222224 kb
Host smart-c861ecba-fec9-4488-b0cc-86fb884b29cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157250615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3157250615
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.388369203
Short name T536
Test name
Test status
Simulation time 17138382879 ps
CPU time 32.55 seconds
Started May 26 02:42:03 PM PDT 24
Finished May 26 02:42:37 PM PDT 24
Peak memory 236096 kb
Host smart-a822c233-2235-4229-bb23-1f8ad2e7bc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388369203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.388369203
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3769920011
Short name T275
Test name
Test status
Simulation time 11558076845 ps
CPU time 25.75 seconds
Started May 26 02:42:02 PM PDT 24
Finished May 26 02:42:29 PM PDT 24
Peak memory 224232 kb
Host smart-0d99dd22-8a48-4c74-8419-28ecaa47c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769920011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3769920011
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1423894810
Short name T292
Test name
Test status
Simulation time 184435954 ps
CPU time 4.06 seconds
Started May 26 02:42:08 PM PDT 24
Finished May 26 02:42:13 PM PDT 24
Peak memory 224172 kb
Host smart-defefd7a-5096-46ec-aafe-c6cbb565fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423894810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1423894810
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2805285695
Short name T728
Test name
Test status
Simulation time 1719397682 ps
CPU time 4.35 seconds
Started May 26 02:42:03 PM PDT 24
Finished May 26 02:42:08 PM PDT 24
Peak memory 234980 kb
Host smart-3d5ae8aa-4241-4cdc-ac84-c7130361cf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805285695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2805285695
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1019789183
Short name T731
Test name
Test status
Simulation time 302753670 ps
CPU time 3.62 seconds
Started May 26 02:42:05 PM PDT 24
Finished May 26 02:42:10 PM PDT 24
Peak memory 235476 kb
Host smart-63657028-1847-4196-8d2e-c72597122420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019789183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1019789183
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3069627250
Short name T140
Test name
Test status
Simulation time 75900963 ps
CPU time 3.73 seconds
Started May 26 02:42:01 PM PDT 24
Finished May 26 02:42:06 PM PDT 24
Peak memory 222064 kb
Host smart-20356d34-f10b-47b1-9284-babd2119c3bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3069627250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3069627250
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1561923927
Short name T518
Test name
Test status
Simulation time 1538711659 ps
CPU time 14.65 seconds
Started May 26 02:42:07 PM PDT 24
Finished May 26 02:42:23 PM PDT 24
Peak memory 224240 kb
Host smart-b976df4c-cf96-4f12-b6ce-ef2a969e83a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561923927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1561923927
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1480988481
Short name T510
Test name
Test status
Simulation time 459310192 ps
CPU time 3.04 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:08 PM PDT 24
Peak memory 215908 kb
Host smart-f8b58348-eeca-4192-b556-4156d6945c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480988481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1480988481
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1435542183
Short name T609
Test name
Test status
Simulation time 6435770728 ps
CPU time 4.56 seconds
Started May 26 02:42:03 PM PDT 24
Finished May 26 02:42:08 PM PDT 24
Peak memory 215776 kb
Host smart-70d9a981-1cb5-438c-a7dd-11bd4b998e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435542183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1435542183
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.184352008
Short name T398
Test name
Test status
Simulation time 203752866 ps
CPU time 1.51 seconds
Started May 26 02:42:05 PM PDT 24
Finished May 26 02:42:07 PM PDT 24
Peak memory 215940 kb
Host smart-85d38eb4-717a-4198-8c93-9a55928343e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184352008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.184352008
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2528571833
Short name T508
Test name
Test status
Simulation time 29060190 ps
CPU time 0.71 seconds
Started May 26 02:42:01 PM PDT 24
Finished May 26 02:42:02 PM PDT 24
Peak memory 205292 kb
Host smart-aa6d7716-a08a-4a49-9ab2-172177d46137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528571833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2528571833
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1099760363
Short name T576
Test name
Test status
Simulation time 6361645321 ps
CPU time 7.15 seconds
Started May 26 02:42:04 PM PDT 24
Finished May 26 02:42:13 PM PDT 24
Peak memory 229708 kb
Host smart-3b03cc41-7a65-4d13-88c9-49bbeb8e6ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099760363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1099760363
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4219528330
Short name T465
Test name
Test status
Simulation time 27296773 ps
CPU time 0.7 seconds
Started May 26 02:39:23 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 204308 kb
Host smart-2e8bf3fc-4578-4bd6-8f26-9394bae6c9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219528330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
219528330
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1015575629
Short name T580
Test name
Test status
Simulation time 198267106 ps
CPU time 2.34 seconds
Started May 26 02:39:23 PM PDT 24
Finished May 26 02:39:27 PM PDT 24
Peak memory 221184 kb
Host smart-a5b88cfc-d5f9-477d-b3cd-ab02f4957e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015575629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1015575629
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2725467288
Short name T754
Test name
Test status
Simulation time 38863029 ps
CPU time 0.81 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:39:25 PM PDT 24
Peak memory 205936 kb
Host smart-2414b5c1-8331-443e-a9fc-a97d1f1a58b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725467288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2725467288
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2423187271
Short name T654
Test name
Test status
Simulation time 10641844116 ps
CPU time 80.69 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:40:44 PM PDT 24
Peak memory 240516 kb
Host smart-23e6c35e-207a-468f-806a-471c4a31ee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423187271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2423187271
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3783534882
Short name T696
Test name
Test status
Simulation time 7835996460 ps
CPU time 21.14 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:39:45 PM PDT 24
Peak memory 219080 kb
Host smart-ca909338-33f1-4526-8856-68bde0871171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783534882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3783534882
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.150032417
Short name T31
Test name
Test status
Simulation time 9080374083 ps
CPU time 55.42 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:40:19 PM PDT 24
Peak memory 240560 kb
Host smart-f3afb1bb-1a19-4ee3-832c-b8480d24f7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150032417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
150032417
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.27177602
Short name T304
Test name
Test status
Simulation time 2111083567 ps
CPU time 9.59 seconds
Started May 26 02:39:24 PM PDT 24
Finished May 26 02:39:36 PM PDT 24
Peak memory 236128 kb
Host smart-0a65b58a-720f-4141-9f0b-dd6f1dabab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27177602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.27177602
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4212926437
Short name T570
Test name
Test status
Simulation time 150134534 ps
CPU time 3.58 seconds
Started May 26 02:39:23 PM PDT 24
Finished May 26 02:39:29 PM PDT 24
Peak memory 218132 kb
Host smart-c7833f59-3aeb-4fd6-a4fe-582d0021ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212926437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4212926437
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1059025998
Short name T359
Test name
Test status
Simulation time 31175867 ps
CPU time 1.03 seconds
Started May 26 02:39:23 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 216232 kb
Host smart-88c0e0b3-2a32-41a7-866c-4b322480784c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059025998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1059025998
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1466557677
Short name T532
Test name
Test status
Simulation time 11314315703 ps
CPU time 17.24 seconds
Started May 26 02:39:24 PM PDT 24
Finished May 26 02:39:43 PM PDT 24
Peak memory 240412 kb
Host smart-5c9fb822-fa3c-457e-bb26-f6ca87ca7144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466557677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1466557677
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2885511592
Short name T910
Test name
Test status
Simulation time 5743942617 ps
CPU time 18.87 seconds
Started May 26 02:39:24 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 233312 kb
Host smart-892202da-cf1b-4a6c-a072-9530eb0f6e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885511592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2885511592
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3384127909
Short name T45
Test name
Test status
Simulation time 8253107444 ps
CPU time 9.75 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:39:34 PM PDT 24
Peak memory 219612 kb
Host smart-883a0513-f790-46cf-babd-fddeebea2512
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3384127909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3384127909
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2750335471
Short name T170
Test name
Test status
Simulation time 186583927 ps
CPU time 0.96 seconds
Started May 26 02:39:24 PM PDT 24
Finished May 26 02:39:27 PM PDT 24
Peak memory 206092 kb
Host smart-696aebfd-8e7b-4a30-8f76-1a4468af3ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750335471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2750335471
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2142365586
Short name T848
Test name
Test status
Simulation time 10160967755 ps
CPU time 52.4 seconds
Started May 26 02:39:26 PM PDT 24
Finished May 26 02:40:20 PM PDT 24
Peak memory 216040 kb
Host smart-3dfcaff1-c7db-4ab2-bedc-74f03a08586f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142365586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2142365586
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.950895281
Short name T584
Test name
Test status
Simulation time 2853311884 ps
CPU time 3 seconds
Started May 26 02:39:25 PM PDT 24
Finished May 26 02:39:30 PM PDT 24
Peak memory 215960 kb
Host smart-adf5655e-94d8-4f3f-b19e-38e9f217e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950895281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.950895281
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1567891758
Short name T794
Test name
Test status
Simulation time 370220516 ps
CPU time 1.74 seconds
Started May 26 02:39:23 PM PDT 24
Finished May 26 02:39:27 PM PDT 24
Peak memory 207656 kb
Host smart-45513421-7f3d-4377-8f56-458dd416cc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567891758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1567891758
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3883582045
Short name T885
Test name
Test status
Simulation time 114071631 ps
CPU time 0.79 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:39:25 PM PDT 24
Peak memory 205296 kb
Host smart-78706136-a33c-45fc-8d5c-3b01c76b6deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883582045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3883582045
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1804426130
Short name T509
Test name
Test status
Simulation time 7184106865 ps
CPU time 11.48 seconds
Started May 26 02:39:21 PM PDT 24
Finished May 26 02:39:33 PM PDT 24
Peak memory 224240 kb
Host smart-0169c2ff-5494-493b-bfbc-3c414928d01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804426130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1804426130
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2556097290
Short name T880
Test name
Test status
Simulation time 13575003 ps
CPU time 0.74 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:38 PM PDT 24
Peak memory 204276 kb
Host smart-aeb4cb69-c390-435c-9e7a-d9ce7bb0a9fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556097290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
556097290
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2291417887
Short name T770
Test name
Test status
Simulation time 182572456 ps
CPU time 3.64 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:39:39 PM PDT 24
Peak memory 234088 kb
Host smart-87070d11-4d7e-4e27-97f5-345a6e32dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291417887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2291417887
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1379933282
Short name T126
Test name
Test status
Simulation time 277701018 ps
CPU time 0.75 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:39:25 PM PDT 24
Peak memory 206300 kb
Host smart-4c9f7897-096b-4b7f-953e-3ea77809a8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379933282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1379933282
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.747361719
Short name T661
Test name
Test status
Simulation time 9512716511 ps
CPU time 95.84 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:41:15 PM PDT 24
Peak memory 250660 kb
Host smart-12dbe500-9db1-47d6-804a-9f946f43fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747361719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.747361719
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.824830538
Short name T131
Test name
Test status
Simulation time 217644949058 ps
CPU time 717.23 seconds
Started May 26 02:39:35 PM PDT 24
Finished May 26 02:51:34 PM PDT 24
Peak memory 257060 kb
Host smart-bdd47d6c-9d47-4305-8e75-d109b93c96d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824830538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.824830538
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.311777745
Short name T935
Test name
Test status
Simulation time 32081631134 ps
CPU time 153.26 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:42:08 PM PDT 24
Peak memory 248936 kb
Host smart-7ef00dca-2572-47bb-8f5f-dd25af99d863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311777745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
311777745
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2474769948
Short name T914
Test name
Test status
Simulation time 29703709482 ps
CPU time 45.25 seconds
Started May 26 02:39:35 PM PDT 24
Finished May 26 02:40:22 PM PDT 24
Peak memory 240636 kb
Host smart-b17ccbba-70c1-4dac-8c5e-993df08b66f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474769948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2474769948
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2578757177
Short name T722
Test name
Test status
Simulation time 485138625 ps
CPU time 8.31 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:47 PM PDT 24
Peak memory 234932 kb
Host smart-7e1cbb6a-e285-4715-b013-75c3c5c71029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578757177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2578757177
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.916876070
Short name T646
Test name
Test status
Simulation time 44086374064 ps
CPU time 103.33 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:41:17 PM PDT 24
Peak memory 234548 kb
Host smart-d0e6c47d-7a11-4046-82d8-19eda8159fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916876070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.916876070
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3237256899
Short name T688
Test name
Test status
Simulation time 16026965 ps
CPU time 1.04 seconds
Started May 26 02:39:21 PM PDT 24
Finished May 26 02:39:24 PM PDT 24
Peak memory 216236 kb
Host smart-170cf381-e493-4a22-a8b0-717b1152ad35
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237256899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3237256899
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3989403738
Short name T611
Test name
Test status
Simulation time 17040931826 ps
CPU time 13.66 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:39:48 PM PDT 24
Peak memory 233992 kb
Host smart-c19cace5-cde7-4600-a661-31c51169a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989403738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3989403738
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1739688481
Short name T963
Test name
Test status
Simulation time 110643346 ps
CPU time 2.2 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:39:26 PM PDT 24
Peak memory 215748 kb
Host smart-814e0215-f75b-4d46-a08d-36619bcf9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739688481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1739688481
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2523498040
Short name T141
Test name
Test status
Simulation time 994728711 ps
CPU time 5.24 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:39:47 PM PDT 24
Peak memory 219948 kb
Host smart-f83971b1-4e40-4256-ad27-dc73f785c411
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2523498040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2523498040
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2222173093
Short name T157
Test name
Test status
Simulation time 44258965430 ps
CPU time 247.96 seconds
Started May 26 02:39:34 PM PDT 24
Finished May 26 02:43:44 PM PDT 24
Peak memory 264620 kb
Host smart-aef1e86d-6379-4858-ac47-ef5eeb4c279b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222173093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2222173093
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.507010996
Short name T318
Test name
Test status
Simulation time 10342422811 ps
CPU time 50.11 seconds
Started May 26 02:39:23 PM PDT 24
Finished May 26 02:40:15 PM PDT 24
Peak memory 215996 kb
Host smart-91ad0860-fc30-4e54-a86b-ed1c4ea3c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507010996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.507010996
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4037841133
Short name T378
Test name
Test status
Simulation time 1564505835 ps
CPU time 7.77 seconds
Started May 26 02:39:21 PM PDT 24
Finished May 26 02:39:30 PM PDT 24
Peak memory 215816 kb
Host smart-68657e40-1e66-4ecb-8aca-d07aeb4c4be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037841133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4037841133
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3964410786
Short name T162
Test name
Test status
Simulation time 85917510 ps
CPU time 2.46 seconds
Started May 26 02:39:24 PM PDT 24
Finished May 26 02:39:29 PM PDT 24
Peak memory 215976 kb
Host smart-51e2c83a-b89e-42be-9ac2-e0dbb4987d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964410786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3964410786
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2530067764
Short name T589
Test name
Test status
Simulation time 36860636 ps
CPU time 0.85 seconds
Started May 26 02:39:22 PM PDT 24
Finished May 26 02:39:24 PM PDT 24
Peak memory 205320 kb
Host smart-e90dcaaf-c77b-49eb-8d45-e77770ec01c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530067764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2530067764
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2019370373
Short name T923
Test name
Test status
Simulation time 13597170003 ps
CPU time 11.21 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 217100 kb
Host smart-03ccea71-3d81-4021-8b05-8341578773da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019370373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2019370373
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2728481671
Short name T494
Test name
Test status
Simulation time 45824179 ps
CPU time 0.73 seconds
Started May 26 02:39:34 PM PDT 24
Finished May 26 02:39:37 PM PDT 24
Peak memory 204892 kb
Host smart-92341dd8-a651-4d1c-be02-7be7811f7281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728481671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
728481671
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3697839535
Short name T397
Test name
Test status
Simulation time 3754912842 ps
CPU time 5.25 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:44 PM PDT 24
Peak memory 219616 kb
Host smart-b3dd0844-a654-4dcb-87d3-cc3bd7b2821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697839535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3697839535
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2807537854
Short name T789
Test name
Test status
Simulation time 21622616 ps
CPU time 0.82 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:40 PM PDT 24
Peak memory 205964 kb
Host smart-a2b26757-728e-4892-9327-9a8cea1ec23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807537854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2807537854
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1806255908
Short name T907
Test name
Test status
Simulation time 22874459826 ps
CPU time 148.21 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:42:04 PM PDT 24
Peak memory 255348 kb
Host smart-29ac0129-99a4-4de7-8996-ee172602662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806255908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1806255908
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1301195097
Short name T755
Test name
Test status
Simulation time 782637813 ps
CPU time 15.88 seconds
Started May 26 02:39:34 PM PDT 24
Finished May 26 02:39:51 PM PDT 24
Peak memory 237880 kb
Host smart-0f8cf9cc-cec0-4cb4-bd36-c114de46b66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301195097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1301195097
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1007014977
Short name T859
Test name
Test status
Simulation time 10731683728 ps
CPU time 32.35 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:40:07 PM PDT 24
Peak memory 232528 kb
Host smart-548191b1-b9c4-4378-9347-128c47a3a780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007014977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1007014977
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2978753876
Short name T799
Test name
Test status
Simulation time 1120588535 ps
CPU time 6.66 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:39:40 PM PDT 24
Peak memory 218080 kb
Host smart-4de3d5d1-5e07-41cc-9d89-2d199a1edbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978753876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2978753876
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3035492174
Short name T752
Test name
Test status
Simulation time 202873574 ps
CPU time 4.61 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:39:40 PM PDT 24
Peak memory 233588 kb
Host smart-580e7585-fc91-46ae-9ff5-a28a0159a8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035492174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3035492174
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1763325908
Short name T888
Test name
Test status
Simulation time 55848639 ps
CPU time 0.97 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:39:34 PM PDT 24
Peak memory 217464 kb
Host smart-ab108e4e-2b05-4115-948d-7f32ccfe59a8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763325908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1763325908
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3431465711
Short name T702
Test name
Test status
Simulation time 148432206 ps
CPU time 2.72 seconds
Started May 26 02:39:31 PM PDT 24
Finished May 26 02:39:35 PM PDT 24
Peak memory 232400 kb
Host smart-e6481a69-cc25-47ab-bd6a-ffb1ad9f56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431465711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3431465711
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3151520879
Short name T204
Test name
Test status
Simulation time 8428051868 ps
CPU time 27.62 seconds
Started May 26 02:39:38 PM PDT 24
Finished May 26 02:40:08 PM PDT 24
Peak memory 232108 kb
Host smart-d0ea9e88-1988-489d-a355-15178268d975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151520879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3151520879
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.332144612
Short name T847
Test name
Test status
Simulation time 312323075 ps
CPU time 3.64 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:39:37 PM PDT 24
Peak memory 219656 kb
Host smart-7e1b1939-0d23-4bac-a5de-e787c5d75d2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332144612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.332144612
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2855685078
Short name T35
Test name
Test status
Simulation time 30567932581 ps
CPU time 139.99 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:41:53 PM PDT 24
Peak memory 249948 kb
Host smart-035743d9-98d6-43d9-9af4-44ce6389994e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855685078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2855685078
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1008902120
Short name T587
Test name
Test status
Simulation time 676309185 ps
CPU time 11.15 seconds
Started May 26 02:39:35 PM PDT 24
Finished May 26 02:39:48 PM PDT 24
Peak memory 219476 kb
Host smart-74697d51-c44b-4494-8a7f-e05fdf05edb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008902120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1008902120
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3025958481
Short name T796
Test name
Test status
Simulation time 25070068910 ps
CPU time 18.45 seconds
Started May 26 02:39:34 PM PDT 24
Finished May 26 02:39:55 PM PDT 24
Peak memory 215880 kb
Host smart-0834efe2-1640-4de3-8d28-e8b3d9fb49b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025958481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3025958481
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3781044486
Short name T774
Test name
Test status
Simulation time 53196909 ps
CPU time 1.04 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:39:36 PM PDT 24
Peak memory 206492 kb
Host smart-75574a87-479b-46a0-84fb-cb8f1335f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781044486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3781044486
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2775213113
Short name T866
Test name
Test status
Simulation time 134128274 ps
CPU time 0.79 seconds
Started May 26 02:39:35 PM PDT 24
Finished May 26 02:39:38 PM PDT 24
Peak memory 205292 kb
Host smart-f74ca03e-e33f-4687-b674-670043abaef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775213113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2775213113
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3756143381
Short name T298
Test name
Test status
Simulation time 3539448335 ps
CPU time 11.86 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:51 PM PDT 24
Peak memory 236468 kb
Host smart-3ae93b74-9c06-4d15-8d0e-656c1bf23415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756143381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3756143381
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3928703275
Short name T486
Test name
Test status
Simulation time 17391683 ps
CPU time 0.7 seconds
Started May 26 02:39:39 PM PDT 24
Finished May 26 02:39:42 PM PDT 24
Peak memory 204300 kb
Host smart-279bb265-5748-4598-840d-14c64926c59b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928703275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
928703275
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3098717443
Short name T749
Test name
Test status
Simulation time 78730644 ps
CPU time 2.48 seconds
Started May 26 02:39:34 PM PDT 24
Finished May 26 02:39:38 PM PDT 24
Peak memory 232852 kb
Host smart-87a7390d-d757-47fc-b023-d5f05d6a1ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098717443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3098717443
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2710834950
Short name T956
Test name
Test status
Simulation time 16087475 ps
CPU time 0.78 seconds
Started May 26 02:39:35 PM PDT 24
Finished May 26 02:39:37 PM PDT 24
Peak memory 205924 kb
Host smart-f2991fb2-c448-42c4-b623-44d0791a9028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710834950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2710834950
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.710777817
Short name T949
Test name
Test status
Simulation time 19686472749 ps
CPU time 72.4 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:40:51 PM PDT 24
Peak memory 253628 kb
Host smart-6f074730-249f-4c9e-b6c3-5c37093679db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710777817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.710777817
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.87098403
Short name T676
Test name
Test status
Simulation time 33719876588 ps
CPU time 159.72 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:42:15 PM PDT 24
Peak memory 249276 kb
Host smart-db311449-72ae-4d73-9209-6e812f1fb6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87098403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.87098403
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3924475660
Short name T547
Test name
Test status
Simulation time 6961311582 ps
CPU time 95.16 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:41:10 PM PDT 24
Peak memory 251136 kb
Host smart-3c7cc8fa-e3d0-496b-8463-8ba93371eb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924475660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3924475660
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2375442351
Short name T444
Test name
Test status
Simulation time 367708943 ps
CPU time 7.34 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:46 PM PDT 24
Peak memory 232280 kb
Host smart-746d3aab-9cdb-43cc-b2da-48cddac9b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375442351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2375442351
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1917627478
Short name T94
Test name
Test status
Simulation time 1490754150 ps
CPU time 20.76 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:40:00 PM PDT 24
Peak memory 224164 kb
Host smart-2a65565b-cb77-4b73-a5d7-1d4e65e6a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917627478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1917627478
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2972111844
Short name T159
Test name
Test status
Simulation time 63990434 ps
CPU time 2.05 seconds
Started May 26 02:39:31 PM PDT 24
Finished May 26 02:39:35 PM PDT 24
Peak memory 218272 kb
Host smart-afe77bfd-9061-486e-92b2-3d58718bc4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972111844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2972111844
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.103057168
Short name T617
Test name
Test status
Simulation time 27430777 ps
CPU time 1.06 seconds
Started May 26 02:39:35 PM PDT 24
Finished May 26 02:39:38 PM PDT 24
Peak memory 216212 kb
Host smart-22be1978-fd1d-40f8-9bfe-103d1ac11fc1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103057168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.103057168
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2317677949
Short name T132
Test name
Test status
Simulation time 328738527 ps
CPU time 3.47 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:39:37 PM PDT 24
Peak memory 224180 kb
Host smart-af696dd6-fab3-4186-8934-a3e0eb0feae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317677949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2317677949
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.85839807
Short name T809
Test name
Test status
Simulation time 1560074790 ps
CPU time 8.8 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:39:42 PM PDT 24
Peak memory 233240 kb
Host smart-a7261bed-6210-468b-a88a-d11af741b23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85839807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.85839807
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2295491983
Short name T435
Test name
Test status
Simulation time 1225967505 ps
CPU time 6.41 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:45 PM PDT 24
Peak memory 219956 kb
Host smart-fb845d86-b890-4f55-8505-a1cb91e9816e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2295491983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2295491983
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.764824231
Short name T579
Test name
Test status
Simulation time 57720179 ps
CPU time 1.02 seconds
Started May 26 02:39:35 PM PDT 24
Finished May 26 02:39:38 PM PDT 24
Peak memory 206588 kb
Host smart-32b72dc1-4d79-42fd-a2fb-fe01372a8126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764824231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.764824231
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3803916918
Short name T317
Test name
Test status
Simulation time 5261778256 ps
CPU time 28.05 seconds
Started May 26 02:39:31 PM PDT 24
Finished May 26 02:40:00 PM PDT 24
Peak memory 215984 kb
Host smart-fcafd1cd-c466-46ac-bf68-d0d195d4b529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803916918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3803916918
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.797986149
Short name T831
Test name
Test status
Simulation time 663622926 ps
CPU time 1.45 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:39:37 PM PDT 24
Peak memory 207272 kb
Host smart-26b52a14-1d03-4c5e-800f-cfe5c51dab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797986149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.797986149
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1042672770
Short name T656
Test name
Test status
Simulation time 82952704 ps
CPU time 1.75 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:41 PM PDT 24
Peak memory 215884 kb
Host smart-9dfd994c-e21c-4a4b-888a-31fdb232b764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042672770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1042672770
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.190430901
Short name T495
Test name
Test status
Simulation time 44543572 ps
CPU time 0.75 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:39:35 PM PDT 24
Peak memory 205316 kb
Host smart-1e087f90-1dea-4bcf-8a51-b79569d04081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190430901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.190430901
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1574810470
Short name T181
Test name
Test status
Simulation time 811192948 ps
CPU time 11.81 seconds
Started May 26 02:39:40 PM PDT 24
Finished May 26 02:39:54 PM PDT 24
Peak memory 232332 kb
Host smart-9de8bc6f-d17d-4fbb-864f-5fc7488d726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574810470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1574810470
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2704253174
Short name T678
Test name
Test status
Simulation time 21359441 ps
CPU time 0.75 seconds
Started May 26 02:39:41 PM PDT 24
Finished May 26 02:39:44 PM PDT 24
Peak memory 205092 kb
Host smart-e06e5ad5-e5da-4138-9ad8-fc3a243f7f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704253174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
704253174
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1384609211
Short name T57
Test name
Test status
Simulation time 4701803292 ps
CPU time 21.43 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:59 PM PDT 24
Peak memory 232428 kb
Host smart-5e99c2ba-4514-44ab-a5bd-50ccf136d45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384609211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1384609211
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.251736970
Short name T358
Test name
Test status
Simulation time 38510153 ps
CPU time 0.76 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:39:35 PM PDT 24
Peak memory 205960 kb
Host smart-4ec81e9c-d4ff-4e6e-a7c9-552e0e6203b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251736970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.251736970
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2894014034
Short name T395
Test name
Test status
Simulation time 9442883697 ps
CPU time 63.75 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:40:41 PM PDT 24
Peak memory 248920 kb
Host smart-fdf401c8-dc42-4129-8c1c-041d657936d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894014034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2894014034
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1914992460
Short name T233
Test name
Test status
Simulation time 3663822067 ps
CPU time 80.72 seconds
Started May 26 02:39:34 PM PDT 24
Finished May 26 02:40:57 PM PDT 24
Peak memory 264568 kb
Host smart-4f457542-ac8a-4245-8bd6-a5ca0452e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914992460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1914992460
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.601399257
Short name T306
Test name
Test status
Simulation time 9662718944 ps
CPU time 13.57 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:51 PM PDT 24
Peak memory 240592 kb
Host smart-e42c0246-a2ff-4ebe-a1e2-576697ef66eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601399257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.601399257
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2121017482
Short name T881
Test name
Test status
Simulation time 2907958913 ps
CPU time 16.28 seconds
Started May 26 02:39:32 PM PDT 24
Finished May 26 02:39:50 PM PDT 24
Peak memory 234136 kb
Host smart-eeb9c3e2-85d2-44b1-bcf9-4507d2f73636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121017482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2121017482
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.341776522
Short name T278
Test name
Test status
Simulation time 22723453157 ps
CPU time 97.05 seconds
Started May 26 02:39:38 PM PDT 24
Finished May 26 02:41:18 PM PDT 24
Peak memory 240292 kb
Host smart-0cc6c5f2-1cc8-4fd2-81ae-af962ed7aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341776522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.341776522
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4162020688
Short name T26
Test name
Test status
Simulation time 27239572 ps
CPU time 1.02 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:39 PM PDT 24
Peak memory 216228 kb
Host smart-ee696177-a8ec-4b15-a934-b8db830d99ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162020688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4162020688
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2868671722
Short name T244
Test name
Test status
Simulation time 1482835147 ps
CPU time 10.65 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:50 PM PDT 24
Peak memory 228716 kb
Host smart-779c444f-15d7-4f4e-b0d7-25d3d682da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868671722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2868671722
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4165488657
Short name T958
Test name
Test status
Simulation time 1535813480 ps
CPU time 3.44 seconds
Started May 26 02:39:34 PM PDT 24
Finished May 26 02:39:39 PM PDT 24
Peak memory 232964 kb
Host smart-3a54ed13-d624-4231-8c5b-59a2c067358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165488657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4165488657
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3107936417
Short name T492
Test name
Test status
Simulation time 1307648745 ps
CPU time 6.16 seconds
Started May 26 02:39:42 PM PDT 24
Finished May 26 02:39:50 PM PDT 24
Peak memory 221876 kb
Host smart-598c2f13-6234-4c7c-bd94-afd63d35ae6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3107936417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3107936417
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4260990409
Short name T601
Test name
Test status
Simulation time 70317079321 ps
CPU time 154.09 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:42:14 PM PDT 24
Peak memory 240504 kb
Host smart-a7a0830d-8f5b-4633-996a-fbbfad8a4d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260990409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4260990409
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2892131225
Short name T405
Test name
Test status
Simulation time 3242795504 ps
CPU time 15.31 seconds
Started May 26 02:39:36 PM PDT 24
Finished May 26 02:39:54 PM PDT 24
Peak memory 215976 kb
Host smart-25c2d112-3521-46a3-bae0-1f1077de765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892131225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2892131225
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2500826838
Short name T493
Test name
Test status
Simulation time 8752501003 ps
CPU time 8.18 seconds
Started May 26 02:39:33 PM PDT 24
Finished May 26 02:39:43 PM PDT 24
Peak memory 215896 kb
Host smart-c1863249-f3b2-421d-87e3-df752c66af1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500826838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2500826838
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3284569842
Short name T421
Test name
Test status
Simulation time 77293516 ps
CPU time 1.01 seconds
Started May 26 02:39:34 PM PDT 24
Finished May 26 02:39:37 PM PDT 24
Peak memory 207684 kb
Host smart-41a71599-73b7-4037-85ea-357f4c717ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284569842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3284569842
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3439359103
Short name T659
Test name
Test status
Simulation time 23683749 ps
CPU time 0.72 seconds
Started May 26 02:39:37 PM PDT 24
Finished May 26 02:39:40 PM PDT 24
Peak memory 205352 kb
Host smart-9fa90373-6148-4c6e-93b7-c94fcad19567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439359103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3439359103
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2152166575
Short name T504
Test name
Test status
Simulation time 854710252 ps
CPU time 3.21 seconds
Started May 26 02:39:38 PM PDT 24
Finished May 26 02:39:43 PM PDT 24
Peak memory 234524 kb
Host smart-b7a981f3-ec46-4f33-9ab7-618c94d34ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152166575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2152166575
Directory /workspace/9.spi_device_upload/latest
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