Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3357590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3852893

1

T1

343

T2

8512

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3923108	1			T1	1		T2	2858		T3	1
values[0x0]	1643439	1			T1	231		T2	3516		T3	14
values[0x1]	1643936	1			T1	188		T2	3530		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2370406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4840077

1

T1

363

T2

8814

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27231	1			T2	29		T5	65		T6	3
valid_sources[0x01]	26087	1			T2	32		T5	62		T6	5
valid_sources[0x02]	27324	1			T2	47		T5	72		T6	5
valid_sources[0x03]	27104	1			T2	49		T5	61		T6	4
valid_sources[0x04]	28124	1			T2	34		T4	36		T5	57
valid_sources[0x05]	41670	1			T2	22		T5	72		T6	8
valid_sources[0x06]	26878	1			T2	49		T5	62		T6	5
valid_sources[0x07]	31853	1			T2	49		T5	46		T6	4
valid_sources[0x08]	28381	1			T2	33		T5	54		T6	3
valid_sources[0x09]	25457	1			T2	4		T4	1		T5	52
valid_sources[0x0a]	26228	1			T2	44		T4	2		T5	58
valid_sources[0x0b]	26867	1			T2	29		T5	48		T6	5
valid_sources[0x0c]	25911	1			T2	50		T5	55		T6	2
valid_sources[0x0d]	26888	1			T2	18		T5	70		T6	5
valid_sources[0x0e]	29872	1			T2	38		T4	1106		T5	67
valid_sources[0x0f]	26883	1			T2	28		T5	53		T6	5
valid_sources[0x10]	26923	1			T2	48		T5	50		T6	4
valid_sources[0x11]	27134	1			T2	20		T5	42		T6	1
valid_sources[0x12]	26378	1			T2	36		T5	59		T6	5
valid_sources[0x13]	26762	1			T2	57		T5	83		T7	4
valid_sources[0x14]	26635	1			T2	22		T5	73		T6	3
valid_sources[0x15]	28976	1			T2	35		T5	76		T6	1
valid_sources[0x16]	31548	1			T2	48		T3	2		T5	48
valid_sources[0x17]	27866	1			T2	27		T4	1		T5	53
valid_sources[0x18]	28296	1			T2	45		T5	68		T6	4
valid_sources[0x19]	29320	1			T2	29		T5	58		T6	1
valid_sources[0x1a]	26056	1			T2	25		T5	54		T6	10
valid_sources[0x1b]	25980	1			T2	20		T5	50		T7	4
valid_sources[0x1c]	26009	1			T2	44		T5	55		T6	2
valid_sources[0x1d]	26321	1			T2	19		T5	46		T6	11
valid_sources[0x1e]	26954	1			T2	41		T5	53		T7	6
valid_sources[0x1f]	25256	1			T2	42		T5	74		T6	2
valid_sources[0x20]	33352	1			T2	47		T5	55		T6	11
valid_sources[0x21]	30045	1			T2	49		T5	60		T6	1
valid_sources[0x22]	28798	1			T2	37		T5	80		T6	3
valid_sources[0x23]	27048	1			T2	17		T5	74		T6	7
valid_sources[0x24]	25702	1			T2	47		T5	50		T6	2
valid_sources[0x25]	27467	1			T2	39		T4	1		T5	61
valid_sources[0x26]	25953	1			T2	14		T5	51		T6	2
valid_sources[0x27]	27731	1			T2	24		T4	1		T5	57
valid_sources[0x28]	27683	1			T2	24		T5	45		T6	2
valid_sources[0x29]	25981	1			T2	53		T5	57		T7	7
valid_sources[0x2a]	26797	1			T2	39		T5	51		T6	9
valid_sources[0x2b]	26727	1			T2	31		T4	1		T5	44
valid_sources[0x2c]	27680	1			T2	59		T5	56		T6	4
valid_sources[0x2d]	26827	1			T2	52		T4	416		T5	46
valid_sources[0x2e]	28020	1			T2	43		T5	51		T6	6
valid_sources[0x2f]	26529	1			T2	37		T5	56		T6	2
valid_sources[0x30]	29106	1			T2	51		T4	378		T5	53
valid_sources[0x31]	27983	1			T2	31		T4	1		T5	47
valid_sources[0x32]	28153	1			T2	21		T5	75		T6	3
valid_sources[0x33]	27512	1			T2	65		T5	57		T6	2
valid_sources[0x34]	28754	1			T2	42		T5	60		T6	1
valid_sources[0x35]	27403	1			T2	47		T5	58		T6	3
valid_sources[0x36]	25918	1			T2	36		T5	61		T6	5
valid_sources[0x37]	27682	1			T2	49		T4	1		T5	69
valid_sources[0x38]	26189	1			T2	43		T5	70		T7	2
valid_sources[0x39]	25476	1			T2	33		T4	1		T5	49
valid_sources[0x3a]	38102	1			T2	34		T5	60		T6	6
valid_sources[0x3b]	29037	1			T2	10		T5	50		T6	1
valid_sources[0x3c]	27387	1			T2	16		T5	68		T6	2
valid_sources[0x3d]	26364	1			T2	55		T3	1		T5	62
valid_sources[0x3e]	28379	1			T2	33		T4	1		T5	64
valid_sources[0x3f]	26741	1			T2	37		T5	41		T6	11
valid_sources[0x40]	24393	1			T2	31		T5	64		T6	1
valid_sources[0x41]	30929	1			T2	52		T5	61		T7	5
valid_sources[0x42]	27046	1			T2	49		T5	65		T6	4
valid_sources[0x43]	27966	1			T2	33		T4	1		T5	68
valid_sources[0x44]	27379	1			T2	61		T5	54		T6	7
valid_sources[0x45]	27128	1			T2	41		T5	63		T6	1
valid_sources[0x46]	29023	1			T2	17		T5	54		T6	2
valid_sources[0x47]	27739	1			T2	46		T5	68		T6	4
valid_sources[0x48]	26040	1			T2	23		T4	3		T5	55
valid_sources[0x49]	30261	1			T2	39		T5	65		T6	3
valid_sources[0x4a]	27811	1			T2	61		T5	35		T7	3
valid_sources[0x4b]	27856	1			T2	30		T5	61		T6	3
valid_sources[0x4c]	29944	1			T2	9		T5	73		T6	5
valid_sources[0x4d]	28137	1			T2	20		T5	46		T7	4
valid_sources[0x4e]	27676	1			T2	44		T5	57		T6	8
valid_sources[0x4f]	30510	1			T2	18		T5	60		T7	2
valid_sources[0x50]	29207	1			T2	43		T5	66		T6	1
valid_sources[0x51]	53111	1			T2	42		T5	59		T6	1
valid_sources[0x52]	27371	1			T2	60		T5	52		T6	7
valid_sources[0x53]	29458	1			T2	26		T5	66		T6	9
valid_sources[0x54]	29313	1			T2	74		T5	61		T6	1
valid_sources[0x55]	28505	1			T2	30		T5	54		T6	6
valid_sources[0x56]	26235	1			T2	7		T4	1		T5	76
valid_sources[0x57]	31093	1			T2	34		T4	1		T5	53
valid_sources[0x58]	27690	1			T2	72		T5	56		T6	12
valid_sources[0x59]	28389	1			T2	64		T3	9		T5	60
valid_sources[0x5a]	25204	1			T2	41		T5	63		T6	9
valid_sources[0x5b]	25777	1			T2	41		T5	70		T6	4
valid_sources[0x5c]	29894	1			T2	39		T5	41		T6	10
valid_sources[0x5d]	26185	1			T2	51		T5	67		T6	2
valid_sources[0x5e]	25783	1			T2	17		T5	58		T6	4
valid_sources[0x5f]	25301	1			T2	17		T5	47		T6	3
valid_sources[0x60]	26017	1			T2	37		T5	54		T6	6
valid_sources[0x61]	29364	1			T2	42		T5	52		T6	4
valid_sources[0x62]	26753	1			T2	30		T4	1		T5	58
valid_sources[0x63]	29398	1			T2	35		T4	3278		T5	58
valid_sources[0x64]	27637	1			T2	45		T5	55		T6	5
valid_sources[0x65]	28193	1			T2	35		T5	66		T6	7
valid_sources[0x66]	26990	1			T2	39		T4	1		T5	57
valid_sources[0x67]	24871	1			T2	65		T5	44		T6	3
valid_sources[0x68]	26772	1			T2	58		T5	49		T9	139
valid_sources[0x69]	28434	1			T2	28		T5	56		T6	12
valid_sources[0x6a]	27502	1			T2	45		T5	56		T6	6
valid_sources[0x6b]	29999	1			T2	27		T5	54		T6	2
valid_sources[0x6c]	29136	1			T2	53		T5	61		T6	3
valid_sources[0x6d]	28502	1			T2	33		T5	55		T6	6
valid_sources[0x6e]	27271	1			T2	56		T4	1		T5	61
valid_sources[0x6f]	27888	1			T2	49		T5	61		T6	9
valid_sources[0x70]	28284	1			T2	30		T4	1		T5	59
valid_sources[0x71]	26508	1			T2	28		T5	45		T6	5
valid_sources[0x72]	33581	1			T2	31		T5	60		T6	6
valid_sources[0x73]	27248	1			T2	47		T5	57		T6	7
valid_sources[0x74]	44897	1			T2	57		T3	4		T5	51
valid_sources[0x75]	27536	1			T2	61		T5	66		T6	1
valid_sources[0x76]	27511	1			T2	59		T5	55		T6	3
valid_sources[0x77]	29470	1			T2	21		T4	2		T5	70
valid_sources[0x78]	27571	1			T2	52		T5	65		T6	3
valid_sources[0x79]	27073	1			T2	25		T5	68		T6	3
valid_sources[0x7a]	25073	1			T2	22		T5	56		T6	4
valid_sources[0x7b]	29497	1			T2	46		T3	1		T5	58
valid_sources[0x7c]	26801	1			T2	36		T5	53		T6	7
valid_sources[0x7d]	30854	1			T2	37		T5	61		T6	1
valid_sources[0x7e]	27981	1			T2	45		T5	63		T7	2
valid_sources[0x7f]	25829	1			T2	43		T5	53		T7	3
valid_sources[0x80]	32087	1			T2	29		T3	1		T5	62

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

882803

1

T2

1501

T4

1403

T5

698

values[0x0]

all_enables

biggest_size

1496547

1

T1

191

T2

3509

T3

11

values[0x1]

all_enables

biggest_size

1473543

1

T1

152

T2

3502

T3

8