Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3374870

1

T1

77

T2

1392

T3

4

full_word

3851824

1

T1

343

T2

8512

T3

19

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7226284	1			T1	420		T2	9904		T3	23
auto[TlIntgErrCmd]	142	1			T88	3		T89	8		T90	2
auto[TlIntgErrData]	138	1			T88	4		T89	8		T90	5
auto[TlIntgErrBoth]	130	1			T88	3		T89	4		T90	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3924636

1

T1

1

T2

2858

T3

1

auto[1]

3302058

1

T1

419

T2

7046

T3

22

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3041527	1			T1	1		T2	1357		T3	1
auto[TlIntgErrNone]	partial	auto[1]	332952	1			T1	76		T2	35		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	882907	1			T2	1501		T4	1403		T5	698
auto[TlIntgErrNone]	full_word	auto[1]	2968898	1			T1	343		T2	7011		T3	19
auto[TlIntgErrCmd]	partial	auto[0]	64	1			T88	1		T89	1		T90	1
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T88	2		T89	6		T90	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T89	1		T170	1		T145	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T171	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	64	1			T88	2		T89	2		T90	4
auto[TlIntgErrData]	partial	auto[1]	65	1			T88	1		T89	6		T90	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T104	1		T172	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T88	1		T144	1		T145	1
auto[TlIntgErrBoth]	partial	auto[0]	65	1			T88	2		T89	1		T90	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T88	1		T89	2		T104	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T106	1		T170	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T89	1		T174	1		-	-