Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402870186	2637070	0	0
DepthKnown_A	402870186	402742243	0	0
RvalidKnown_A	402870186	402742243	0	0
WreadyKnown_A	402870186	402742243	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	2637070	0	0
T2	183064	9149	0	0
T3	3686	0	0	0
T4	128719	10812	0	0
T5	441395	17464	0	0
T6	10706	832	0	0
T7	6715	1663	0	0
T8	1127	0	0	0
T9	501520	12474	0	0
T10	21777	1663	0	0
T11	908	0	0	0
T12	0	9991	0	0
T13	0	2690	0	0
T14	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402870186	3013161	0	0
DepthKnown_A	402870186	402742243	0	0
RvalidKnown_A	402870186	402742243	0	0
WreadyKnown_A	402870186	402742243	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	3013161	0	0
T2	183064	6656	0	0
T3	3686	0	0	0
T4	128719	7488	0	0
T5	441395	10816	0	0
T6	10706	832	0	0
T7	6715	832	0	0
T8	1127	0	0	0
T9	501520	7488	0	0
T10	21777	832	0	0
T11	908	0	0	0
T12	0	25630	0	0
T13	0	1350	0	0
T14	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402870186	155536	0	0
DepthKnown_A	402870186	402742243	0	0
RvalidKnown_A	402870186	402742243	0	0
WreadyKnown_A	402870186	402742243	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	155536	0	0
T2	183064	192	0	0
T3	3686	0	0	0
T4	128719	422	0	0
T5	441395	279	0	0
T6	10706	0	0	0
T7	6715	0	0	0
T8	1127	0	0	0
T9	501520	904	0	0
T10	21777	0	0	0
T11	908	2	0	0
T12	0	731	0	0
T15	0	943	0	0
T17	0	739	0	0
T18	0	950	0	0
T28	0	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402870186	412530	0	0
DepthKnown_A	402870186	402742243	0	0
RvalidKnown_A	402870186	402742243	0	0
WreadyKnown_A	402870186	402742243	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	412530	0	0
T2	183064	192	0	0
T3	3686	0	0	0
T4	128719	422	0	0
T5	441395	279	0	0
T6	10706	0	0	0
T7	6715	0	0	0
T8	1127	0	0	0
T9	501520	904	0	0
T10	21777	0	0	0
T11	908	2	0	0
T12	0	3401	0	0
T15	0	943	0	0
T17	0	735	0	0
T18	0	950	0	0
T28	0	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402870186	5834593	0	0
DepthKnown_A	402870186	402742243	0	0
RvalidKnown_A	402870186	402742243	0	0
WreadyKnown_A	402870186	402742243	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	5834593	0	0
T1	174079	420	0	0
T2	183064	3059	0	0
T3	3686	23	0	0
T4	128719	2428	0	0
T5	441395	3929	0	0
T6	10706	51	0	0
T7	6715	49	0	0
T8	1127	19	0	0
T9	501520	53634	0	0
T10	21777	661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402870186	13597722	0	0
DepthKnown_A	402870186	402742243	0	0
RvalidKnown_A	402870186	402742243	0	0
WreadyKnown_A	402870186	402742243	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	13597722	0	0
T1	174079	1207	0	0
T2	183064	3056	0	0
T3	3686	50	0	0
T4	128719	2426	0	0
T5	441395	3854	0	0
T6	10706	51	0	0
T7	6715	100	0	0
T8	1127	94	0	0
T9	501520	53337	0	0
T10	21777	661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402870186	402742243	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0