Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T11
1	0	Covered	T5,T9,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T5,T9,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	666683716	532444819	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	666683716	3155192	0	0
GntImpliesValid_A	666683716	3155192	0	0
GrantKnown_A	666683716	532444819	0	0
IdxKnown_A	666683716	532444819	0	0
IndexIsCorrect_A	666683716	3155192	0	0
LockArbDecision_A	666683716	0	0	0
NoReadyValidNoGrant_A	666683716	0	0	0
ReadyAndValidImplyGrant_A	666683716	3155192	0	0
ReqAndReadyImplyGrant_A	666683716	3155192	0	0
ReqImpliesValid_A	666683716	3155192	0	0
ReqStaysHighUntilGranted0_M	666683716	0	0	0
RoundRobin_A	666683716	5	0	926
ValidKnown_A	666683716	532444819	0	0
gen_data_port_assertion.DataFlow_A	666683716	3155192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	532444819	0	0
T1	227430	224366	0	0
T2	1368400	774746	0	0
T3	5098	4106	0	0
T4	945843	536490	0	0
T5	665789	636751	0	0
T6	25978	18283	0	0
T7	32271	19028	0	0
T8	1127	1068	0	0
T9	1775546	1132813	0	0
T10	50289	35520	0	0
T11	480	240	0	0
T12	382647	378391	0	0
T13	0	28181	0	0
T14	0	53116	0	0
T15	0	169208	0	0
T16	0	44824	0	0
T17	0	127824	0	0
T19	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	3155192	0	0
T2	775732	7896	0	0
T3	4392	0	0	0
T4	537281	14081	0	0
T5	665789	13572	0	0
T6	25978	832	0	0
T7	32271	832	0	0
T8	1127	0	0	0
T9	1775546	21386	0	0
T10	50289	832	0	0
T11	1388	8	0	0
T12	765294	14254	0	0
T13	28181	1344	0	0
T14	53502	0	0	0
T15	0	7691	0	0
T17	0	5702	0	0
T18	0	6069	0	0
T26	0	529	0	0
T27	0	5155	0	0
T28	0	3739	0	0
T30	0	19179	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	3155192	0	0
T2	775732	7896	0	0
T3	4392	0	0	0
T4	537281	14081	0	0
T5	665789	13572	0	0
T6	25978	832	0	0
T7	32271	832	0	0
T8	1127	0	0	0
T9	1775546	21386	0	0
T10	50289	832	0	0
T11	1388	8	0	0
T12	765294	14254	0	0
T13	28181	1344	0	0
T14	53502	0	0	0
T15	0	7691	0	0
T17	0	5702	0	0
T18	0	6069	0	0
T26	0	529	0	0
T27	0	5155	0	0
T28	0	3739	0	0
T30	0	19179	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	532444819	0	0
T1	227430	224366	0	0
T2	1368400	774746	0	0
T3	5098	4106	0	0
T4	945843	536490	0	0
T5	665789	636751	0	0
T6	25978	18283	0	0
T7	32271	19028	0	0
T8	1127	1068	0	0
T9	1775546	1132813	0	0
T10	50289	35520	0	0
T11	480	240	0	0
T12	382647	378391	0	0
T13	0	28181	0	0
T14	0	53116	0	0
T15	0	169208	0	0
T16	0	44824	0	0
T17	0	127824	0	0
T19	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	532444819	0	0
T1	227430	224366	0	0
T2	1368400	774746	0	0
T3	5098	4106	0	0
T4	945843	536490	0	0
T5	665789	636751	0	0
T6	25978	18283	0	0
T7	32271	19028	0	0
T8	1127	1068	0	0
T9	1775546	1132813	0	0
T10	50289	35520	0	0
T11	480	240	0	0
T12	382647	378391	0	0
T13	0	28181	0	0
T14	0	53116	0	0
T15	0	169208	0	0
T16	0	44824	0	0
T17	0	127824	0	0
T19	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	3155192	0	0
T2	775732	7896	0	0
T3	4392	0	0	0
T4	537281	14081	0	0
T5	665789	13572	0	0
T6	25978	832	0	0
T7	32271	832	0	0
T8	1127	0	0	0
T9	1775546	21386	0	0
T10	50289	832	0	0
T11	1388	8	0	0
T12	765294	14254	0	0
T13	28181	1344	0	0
T14	53502	0	0	0
T15	0	7691	0	0
T17	0	5702	0	0
T18	0	6069	0	0
T26	0	529	0	0
T27	0	5155	0	0
T28	0	3739	0	0
T30	0	19179	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	3155192	0	0
T2	775732	7896	0	0
T3	4392	0	0	0
T4	537281	14081	0	0
T5	665789	13572	0	0
T6	25978	832	0	0
T7	32271	832	0	0
T8	1127	0	0	0
T9	1775546	21386	0	0
T10	50289	832	0	0
T11	1388	8	0	0
T12	765294	14254	0	0
T13	28181	1344	0	0
T14	53502	0	0	0
T15	0	7691	0	0
T17	0	5702	0	0
T18	0	6069	0	0
T26	0	529	0	0
T27	0	5155	0	0
T28	0	3739	0	0
T30	0	19179	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	3155192	0	0
T2	775732	7896	0	0
T3	4392	0	0	0
T4	537281	14081	0	0
T5	665789	13572	0	0
T6	25978	832	0	0
T7	32271	832	0	0
T8	1127	0	0	0
T9	1775546	21386	0	0
T10	50289	832	0	0
T11	1388	8	0	0
T12	765294	14254	0	0
T13	28181	1344	0	0
T14	53502	0	0	0
T15	0	7691	0	0
T17	0	5702	0	0
T18	0	6069	0	0
T26	0	529	0	0
T27	0	5155	0	0
T28	0	3739	0	0
T30	0	19179	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	3155192	0	0
T2	775732	7896	0	0
T3	4392	0	0	0
T4	537281	14081	0	0
T5	665789	13572	0	0
T6	25978	832	0	0
T7	32271	832	0	0
T8	1127	0	0	0
T9	1775546	21386	0	0
T10	50289	832	0	0
T11	1388	8	0	0
T12	765294	14254	0	0
T13	28181	1344	0	0
T14	53502	0	0	0
T15	0	7691	0	0
T17	0	5702	0	0
T18	0	6069	0	0
T26	0	529	0	0
T27	0	5155	0	0
T28	0	3739	0	0
T30	0	19179	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	5	0	926
T36	240901	1	0	1
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	61472	0	0	1
T42	348059	0	0	1
T43	9910	0	0	1
T44	81926	0	0	1
T45	56508	0	0	1
T46	2171	0	0	1
T47	322828	0	0	1
T48	27496	0	0	1
T49	17930	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	532444819	0	0
T1	227430	224366	0	0
T2	1368400	774746	0	0
T3	5098	4106	0	0
T4	945843	536490	0	0
T5	665789	636751	0	0
T6	25978	18283	0	0
T7	32271	19028	0	0
T8	1127	1068	0	0
T9	1775546	1132813	0	0
T10	50289	35520	0	0
T11	480	240	0	0
T12	382647	378391	0	0
T13	0	28181	0	0
T14	0	53116	0	0
T15	0	169208	0	0
T16	0	44824	0	0
T17	0	127824	0	0
T19	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	666683716	3155192	0	0
T2	775732	7896	0	0
T3	4392	0	0	0
T4	537281	14081	0	0
T5	665789	13572	0	0
T6	25978	832	0	0
T7	32271	832	0	0
T8	1127	0	0	0
T9	1775546	21386	0	0
T10	50289	832	0	0
T11	1388	8	0	0
T12	765294	14254	0	0
T13	28181	1344	0	0
T14	53502	0	0	0
T15	0	7691	0	0
T17	0	5702	0	0
T18	0	6069	0	0
T26	0	529	0	0
T27	0	5155	0	0
T28	0	3739	0	0
T30	0	19179	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T11
1	0	Covered	T5,T9,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T5,T9,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T9,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132949227	26577587	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	132949227	573575	0	0
GntImpliesValid_A	132949227	573575	0	0
GrantKnown_A	132949227	26577587	0	0
IdxKnown_A	132949227	26577587	0	0
IndexIsCorrect_A	132949227	573575	0	0
LockArbDecision_A	132949227	0	0	0
NoReadyValidNoGrant_A	132949227	0	0	0
ReadyAndValidImplyGrant_A	132949227	573575	0	0
ReqAndReadyImplyGrant_A	132949227	573575	0	0
ReqImpliesValid_A	132949227	573575	0	0
ReqStaysHighUntilGranted0_M	132949227	0	0	0
RoundRobin_A	132949227	0	0	0
ValidKnown_A	132949227	26577587	0	0
gen_data_port_assertion.DataFlow_A	132949227	573575	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	26577587	0	0
T1	53351	50344	0	0
T2	592668	0	0	0
T3	706	504	0	0
T4	408562	0	0	0
T5	112197	92944	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	77872	0	0
T10	14256	0	0	0
T11	240	240	0	0
T12	0	82984	0	0
T15	0	169208	0	0
T16	0	44824	0	0
T17	0	127824	0	0
T19	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	573575	0	0
T5	112197	767	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	3579	0	0
T10	14256	0	0	0
T11	240	5	0	0
T12	382647	3552	0	0
T13	28181	0	0	0
T14	53502	0	0	0
T15	0	2209	0	0
T17	0	3317	0	0
T18	0	6069	0	0
T27	0	5155	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	573575	0	0
T5	112197	767	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	3579	0	0
T10	14256	0	0	0
T11	240	5	0	0
T12	382647	3552	0	0
T13	28181	0	0	0
T14	53502	0	0	0
T15	0	2209	0	0
T17	0	3317	0	0
T18	0	6069	0	0
T27	0	5155	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	26577587	0	0
T1	53351	50344	0	0
T2	592668	0	0	0
T3	706	504	0	0
T4	408562	0	0	0
T5	112197	92944	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	77872	0	0
T10	14256	0	0	0
T11	240	240	0	0
T12	0	82984	0	0
T15	0	169208	0	0
T16	0	44824	0	0
T17	0	127824	0	0
T19	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	26577587	0	0
T1	53351	50344	0	0
T2	592668	0	0	0
T3	706	504	0	0
T4	408562	0	0	0
T5	112197	92944	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	77872	0	0
T10	14256	0	0	0
T11	240	240	0	0
T12	0	82984	0	0
T15	0	169208	0	0
T16	0	44824	0	0
T17	0	127824	0	0
T19	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	573575	0	0
T5	112197	767	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	3579	0	0
T10	14256	0	0	0
T11	240	5	0	0
T12	382647	3552	0	0
T13	28181	0	0	0
T14	53502	0	0	0
T15	0	2209	0	0
T17	0	3317	0	0
T18	0	6069	0	0
T27	0	5155	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	573575	0	0
T5	112197	767	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	3579	0	0
T10	14256	0	0	0
T11	240	5	0	0
T12	382647	3552	0	0
T13	28181	0	0	0
T14	53502	0	0	0
T15	0	2209	0	0
T17	0	3317	0	0
T18	0	6069	0	0
T27	0	5155	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	573575	0	0
T5	112197	767	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	3579	0	0
T10	14256	0	0	0
T11	240	5	0	0
T12	382647	3552	0	0
T13	28181	0	0	0
T14	53502	0	0	0
T15	0	2209	0	0
T17	0	3317	0	0
T18	0	6069	0	0
T27	0	5155	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	573575	0	0
T5	112197	767	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	3579	0	0
T10	14256	0	0	0
T11	240	5	0	0
T12	382647	3552	0	0
T13	28181	0	0	0
T14	53502	0	0	0
T15	0	2209	0	0
T17	0	3317	0	0
T18	0	6069	0	0
T27	0	5155	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	26577587	0	0
T1	53351	50344	0	0
T2	592668	0	0	0
T3	706	504	0	0
T4	408562	0	0	0
T5	112197	92944	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	77872	0	0
T10	14256	0	0	0
T11	240	240	0	0
T12	0	82984	0	0
T15	0	169208	0	0
T16	0	44824	0	0
T17	0	127824	0	0
T19	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	573575	0	0
T5	112197	767	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	3579	0	0
T10	14256	0	0	0
T11	240	5	0	0
T12	382647	3552	0	0
T13	28181	0	0	0
T14	53502	0	0	0
T15	0	2209	0	0
T17	0	3317	0	0
T18	0	6069	0	0
T27	0	5155	0	0
T33	20176	0	0	0
T34	0	3309	0	0
T35	0	74	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132949227	105164575	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	132949227	551323	0	0
GntImpliesValid_A	132949227	551323	0	0
GrantKnown_A	132949227	105164575	0	0
IdxKnown_A	132949227	105164575	0	0
IndexIsCorrect_A	132949227	551323	0	0
LockArbDecision_A	132949227	0	0	0
NoReadyValidNoGrant_A	132949227	0	0	0
ReadyAndValidImplyGrant_A	132949227	551323	0	0
ReqAndReadyImplyGrant_A	132949227	551323	0	0
ReqImpliesValid_A	132949227	551323	0	0
ReqStaysHighUntilGranted0_M	132949227	0	0	0
RoundRobin_A	132949227	0	0	0
ValidKnown_A	132949227	105164575	0	0
gen_data_port_assertion.DataFlow_A	132949227	551323	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	105164575	0	0
T2	592668	591692	0	0
T3	706	0	0	0
T4	408562	407776	0	0
T5	112197	102510	0	0
T6	7636	7636	0	0
T7	12778	12384	0	0
T9	637013	553447	0	0
T10	14256	13837	0	0
T11	240	0	0	0
T12	382647	295407	0	0
T13	0	28181	0	0
T14	0	53116	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	551323	0	0
T2	592668	1036	0	0
T3	706	0	0	0
T4	408562	6149	0	0
T5	112197	1288	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	8404	0	0
T10	14256	0	0	0
T11	240	0	0	0
T12	382647	1225	0	0
T15	0	5482	0	0
T17	0	2385	0	0
T26	0	529	0	0
T28	0	3739	0	0
T30	0	19179	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	551323	0	0
T2	592668	1036	0	0
T3	706	0	0	0
T4	408562	6149	0	0
T5	112197	1288	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	8404	0	0
T10	14256	0	0	0
T11	240	0	0	0
T12	382647	1225	0	0
T15	0	5482	0	0
T17	0	2385	0	0
T26	0	529	0	0
T28	0	3739	0	0
T30	0	19179	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	105164575	0	0
T2	592668	591692	0	0
T3	706	0	0	0
T4	408562	407776	0	0
T5	112197	102510	0	0
T6	7636	7636	0	0
T7	12778	12384	0	0
T9	637013	553447	0	0
T10	14256	13837	0	0
T11	240	0	0	0
T12	382647	295407	0	0
T13	0	28181	0	0
T14	0	53116	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	105164575	0	0
T2	592668	591692	0	0
T3	706	0	0	0
T4	408562	407776	0	0
T5	112197	102510	0	0
T6	7636	7636	0	0
T7	12778	12384	0	0
T9	637013	553447	0	0
T10	14256	13837	0	0
T11	240	0	0	0
T12	382647	295407	0	0
T13	0	28181	0	0
T14	0	53116	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	551323	0	0
T2	592668	1036	0	0
T3	706	0	0	0
T4	408562	6149	0	0
T5	112197	1288	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	8404	0	0
T10	14256	0	0	0
T11	240	0	0	0
T12	382647	1225	0	0
T15	0	5482	0	0
T17	0	2385	0	0
T26	0	529	0	0
T28	0	3739	0	0
T30	0	19179	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	551323	0	0
T2	592668	1036	0	0
T3	706	0	0	0
T4	408562	6149	0	0
T5	112197	1288	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	8404	0	0
T10	14256	0	0	0
T11	240	0	0	0
T12	382647	1225	0	0
T15	0	5482	0	0
T17	0	2385	0	0
T26	0	529	0	0
T28	0	3739	0	0
T30	0	19179	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	551323	0	0
T2	592668	1036	0	0
T3	706	0	0	0
T4	408562	6149	0	0
T5	112197	1288	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	8404	0	0
T10	14256	0	0	0
T11	240	0	0	0
T12	382647	1225	0	0
T15	0	5482	0	0
T17	0	2385	0	0
T26	0	529	0	0
T28	0	3739	0	0
T30	0	19179	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	551323	0	0
T2	592668	1036	0	0
T3	706	0	0	0
T4	408562	6149	0	0
T5	112197	1288	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	8404	0	0
T10	14256	0	0	0
T11	240	0	0	0
T12	382647	1225	0	0
T15	0	5482	0	0
T17	0	2385	0	0
T26	0	529	0	0
T28	0	3739	0	0
T30	0	19179	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	105164575	0	0
T2	592668	591692	0	0
T3	706	0	0	0
T4	408562	407776	0	0
T5	112197	102510	0	0
T6	7636	7636	0	0
T7	12778	12384	0	0
T9	637013	553447	0	0
T10	14256	13837	0	0
T11	240	0	0	0
T12	382647	295407	0	0
T13	0	28181	0	0
T14	0	53116	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132949227	551323	0	0
T2	592668	1036	0	0
T3	706	0	0	0
T4	408562	6149	0	0
T5	112197	1288	0	0
T6	7636	0	0	0
T7	12778	0	0	0
T9	637013	8404	0	0
T10	14256	0	0	0
T11	240	0	0	0
T12	382647	1225	0	0
T15	0	5482	0	0
T17	0	2385	0	0
T26	0	529	0	0
T28	0	3739	0	0
T30	0	19179	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400785262	400702657	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	400785262	2030294	0	0
GntImpliesValid_A	400785262	2030294	0	0
GrantKnown_A	400785262	400702657	0	0
IdxKnown_A	400785262	400702657	0	0
IndexIsCorrect_A	400785262	2030294	0	0
LockArbDecision_A	400785262	0	0	0
NoReadyValidNoGrant_A	400785262	0	0	0
ReadyAndValidImplyGrant_A	400785262	2030294	0	0
ReqAndReadyImplyGrant_A	400785262	2030294	0	0
ReqImpliesValid_A	400785262	2030294	0	0
ReqStaysHighUntilGranted0_M	400785262	0	0	0
RoundRobin_A	400785262	5	0	926
ValidKnown_A	400785262	400702657	0	0
gen_data_port_assertion.DataFlow_A	400785262	2030294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	400702657	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	2030294	0	0
T2	183064	6860	0	0
T3	3686	0	0	0
T4	128719	7932	0	0
T5	441395	11517	0	0
T6	10706	832	0	0
T7	6715	832	0	0
T8	1127	0	0	0
T9	501520	9403	0	0
T10	21777	832	0	0
T11	908	3	0	0
T12	0	9477	0	0
T13	0	1344	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	2030294	0	0
T2	183064	6860	0	0
T3	3686	0	0	0
T4	128719	7932	0	0
T5	441395	11517	0	0
T6	10706	832	0	0
T7	6715	832	0	0
T8	1127	0	0	0
T9	501520	9403	0	0
T10	21777	832	0	0
T11	908	3	0	0
T12	0	9477	0	0
T13	0	1344	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	400702657	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	400702657	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	2030294	0	0
T2	183064	6860	0	0
T3	3686	0	0	0
T4	128719	7932	0	0
T5	441395	11517	0	0
T6	10706	832	0	0
T7	6715	832	0	0
T8	1127	0	0	0
T9	501520	9403	0	0
T10	21777	832	0	0
T11	908	3	0	0
T12	0	9477	0	0
T13	0	1344	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	2030294	0	0
T2	183064	6860	0	0
T3	3686	0	0	0
T4	128719	7932	0	0
T5	441395	11517	0	0
T6	10706	832	0	0
T7	6715	832	0	0
T8	1127	0	0	0
T9	501520	9403	0	0
T10	21777	832	0	0
T11	908	3	0	0
T12	0	9477	0	0
T13	0	1344	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	2030294	0	0
T2	183064	6860	0	0
T3	3686	0	0	0
T4	128719	7932	0	0
T5	441395	11517	0	0
T6	10706	832	0	0
T7	6715	832	0	0
T8	1127	0	0	0
T9	501520	9403	0	0
T10	21777	832	0	0
T11	908	3	0	0
T12	0	9477	0	0
T13	0	1344	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	2030294	0	0
T2	183064	6860	0	0
T3	3686	0	0	0
T4	128719	7932	0	0
T5	441395	11517	0	0
T6	10706	832	0	0
T7	6715	832	0	0
T8	1127	0	0	0
T9	501520	9403	0	0
T10	21777	832	0	0
T11	908	3	0	0
T12	0	9477	0	0
T13	0	1344	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	5	0	926
T36	240901	1	0	1
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	61472	0	0	1
T42	348059	0	0	1
T43	9910	0	0	1
T44	81926	0	0	1
T45	56508	0	0	1
T46	2171	0	0	1
T47	322828	0	0	1
T48	27496	0	0	1
T49	17930	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	400702657	0	0
T1	174079	174022	0	0
T2	183064	183054	0	0
T3	3686	3602	0	0
T4	128719	128714	0	0
T5	441395	441297	0	0
T6	10706	10647	0	0
T7	6715	6644	0	0
T8	1127	1068	0	0
T9	501520	501494	0	0
T10	21777	21683	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400785262	2030294	0	0
T2	183064	6860	0	0
T3	3686	0	0	0
T4	128719	7932	0	0
T5	441395	11517	0	0
T6	10706	832	0	0
T7	6715	832	0	0
T8	1127	0	0	0
T9	501520	9403	0	0
T10	21777	832	0	0
T11	908	3	0	0
T12	0	9477	0	0
T13	0	1344	0	0