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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.11 98.35 94.21 98.61 89.36 97.23 95.82 99.15


Total test records in report: 1101
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T1012 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1449491121 May 28 01:36:33 PM PDT 24 May 28 01:36:37 PM PDT 24 33310091 ps
T147 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.315250349 May 28 01:36:00 PM PDT 24 May 28 01:36:08 PM PDT 24 1021957070 ps
T1013 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4091063214 May 28 01:35:39 PM PDT 24 May 28 01:35:45 PM PDT 24 58940655 ps
T1014 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.202538713 May 28 01:36:29 PM PDT 24 May 28 01:36:36 PM PDT 24 75012960 ps
T1015 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3561674346 May 28 01:35:37 PM PDT 24 May 28 01:35:42 PM PDT 24 143053628 ps
T1016 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1250549900 May 28 01:36:01 PM PDT 24 May 28 01:36:05 PM PDT 24 73314496 ps
T148 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1825994465 May 28 01:35:55 PM PDT 24 May 28 01:35:58 PM PDT 24 67616691 ps
T1017 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4113931046 May 28 01:36:28 PM PDT 24 May 28 01:36:33 PM PDT 24 51630118 ps
T1018 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1943728685 May 28 01:35:52 PM PDT 24 May 28 01:35:55 PM PDT 24 46022380 ps
T1019 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4276118561 May 28 01:35:38 PM PDT 24 May 28 01:35:44 PM PDT 24 37675730 ps
T1020 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4176565993 May 28 01:36:31 PM PDT 24 May 28 01:36:36 PM PDT 24 16260682 ps
T1021 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1102362356 May 28 01:35:54 PM PDT 24 May 28 01:35:58 PM PDT 24 89726278 ps
T1022 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3180931376 May 28 01:35:53 PM PDT 24 May 28 01:35:55 PM PDT 24 25497057 ps
T101 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1193792895 May 28 01:36:02 PM PDT 24 May 28 01:36:08 PM PDT 24 51265836 ps
T1023 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3060094903 May 28 01:36:28 PM PDT 24 May 28 01:36:32 PM PDT 24 113027613 ps
T1024 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.658731002 May 28 01:35:54 PM PDT 24 May 28 01:36:00 PM PDT 24 159755721 ps
T1025 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3356345816 May 28 01:36:27 PM PDT 24 May 28 01:36:28 PM PDT 24 14477909 ps
T1026 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.389121838 May 28 01:35:38 PM PDT 24 May 28 01:36:05 PM PDT 24 706652714 ps
T1027 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1266225046 May 28 01:36:30 PM PDT 24 May 28 01:36:35 PM PDT 24 12191794 ps
T1028 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2897746391 May 28 01:35:36 PM PDT 24 May 28 01:35:39 PM PDT 24 15461456 ps
T98 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.13890487 May 28 01:35:36 PM PDT 24 May 28 01:35:44 PM PDT 24 937904007 ps
T1029 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1929739343 May 28 01:35:48 PM PDT 24 May 28 01:35:53 PM PDT 24 213960022 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4128578966 May 28 01:35:40 PM PDT 24 May 28 01:35:45 PM PDT 24 55871417 ps
T173 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3668244423 May 28 01:36:27 PM PDT 24 May 28 01:36:41 PM PDT 24 1499448759 ps
T1031 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1507971216 May 28 01:35:38 PM PDT 24 May 28 01:35:42 PM PDT 24 15794683 ps
T1032 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3854640585 May 28 01:36:13 PM PDT 24 May 28 01:36:15 PM PDT 24 142788799 ps
T1033 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3958308796 May 28 01:35:38 PM PDT 24 May 28 01:35:43 PM PDT 24 31662819 ps
T1034 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4096442712 May 28 01:35:58 PM PDT 24 May 28 01:36:00 PM PDT 24 51908152 ps
T164 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.554970078 May 28 01:35:35 PM PDT 24 May 28 01:36:18 PM PDT 24 18026467678 ps
T1035 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.101433097 May 28 01:35:36 PM PDT 24 May 28 01:35:50 PM PDT 24 184568875 ps
T1036 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4212083755 May 28 01:36:28 PM PDT 24 May 28 01:36:32 PM PDT 24 64672030 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.778663083 May 28 01:35:50 PM PDT 24 May 28 01:35:52 PM PDT 24 31033780 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3096469796 May 28 01:35:36 PM PDT 24 May 28 01:35:39 PM PDT 24 42892326 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3310094837 May 28 01:35:37 PM PDT 24 May 28 01:35:42 PM PDT 24 272311238 ps
T1040 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2790294734 May 28 01:36:02 PM PDT 24 May 28 01:36:07 PM PDT 24 277850914 ps
T1041 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3691474155 May 28 01:35:53 PM PDT 24 May 28 01:35:58 PM PDT 24 157324605 ps
T1042 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1640922905 May 28 01:36:31 PM PDT 24 May 28 01:36:36 PM PDT 24 14587304 ps
T97 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2457458338 May 28 01:36:01 PM PDT 24 May 28 01:36:06 PM PDT 24 32315554 ps
T1043 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4168499668 May 28 01:35:50 PM PDT 24 May 28 01:35:53 PM PDT 24 248924654 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4240610635 May 28 01:35:38 PM PDT 24 May 28 01:35:46 PM PDT 24 130543560 ps
T1045 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1432995802 May 28 01:36:29 PM PDT 24 May 28 01:36:36 PM PDT 24 308944209 ps
T1046 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4136981674 May 28 01:36:15 PM PDT 24 May 28 01:36:35 PM PDT 24 294240861 ps
T1047 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2473608974 May 28 01:35:50 PM PDT 24 May 28 01:35:53 PM PDT 24 53947325 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.503399510 May 28 01:36:01 PM PDT 24 May 28 01:36:08 PM PDT 24 164143521 ps
T1049 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3672953127 May 28 01:35:38 PM PDT 24 May 28 01:35:45 PM PDT 24 400031795 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2834119518 May 28 01:35:38 PM PDT 24 May 28 01:35:44 PM PDT 24 774638496 ps
T1051 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3286941861 May 28 01:35:59 PM PDT 24 May 28 01:36:03 PM PDT 24 94966448 ps
T1052 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1959008262 May 28 01:36:13 PM PDT 24 May 28 01:36:16 PM PDT 24 233392597 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2458618272 May 28 01:35:37 PM PDT 24 May 28 01:35:43 PM PDT 24 59352158 ps
T1054 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2647634881 May 28 01:36:29 PM PDT 24 May 28 01:36:35 PM PDT 24 743486952 ps
T1055 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.620687622 May 28 01:35:59 PM PDT 24 May 28 01:36:05 PM PDT 24 1103414501 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2428607116 May 28 01:36:02 PM PDT 24 May 28 01:36:08 PM PDT 24 381527182 ps
T1057 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.594042696 May 28 01:35:54 PM PDT 24 May 28 01:35:58 PM PDT 24 93003527 ps
T1058 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.700816404 May 28 01:36:30 PM PDT 24 May 28 01:36:34 PM PDT 24 19187195 ps
T1059 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2856070873 May 28 01:36:06 PM PDT 24 May 28 01:36:09 PM PDT 24 25002433 ps
T1060 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3443692952 May 28 01:36:14 PM PDT 24 May 28 01:36:20 PM PDT 24 60076792 ps
T1061 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1921818504 May 28 01:36:00 PM PDT 24 May 28 01:36:05 PM PDT 24 67309395 ps
T1062 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1069353015 May 28 01:36:25 PM PDT 24 May 28 01:36:28 PM PDT 24 354382485 ps
T1063 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2432700396 May 28 01:36:14 PM PDT 24 May 28 01:36:17 PM PDT 24 28284241 ps
T1064 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.870338155 May 28 01:36:27 PM PDT 24 May 28 01:36:30 PM PDT 24 43468395 ps
T1065 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2315972405 May 28 01:35:52 PM PDT 24 May 28 01:36:12 PM PDT 24 585326320 ps
T1066 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2861697881 May 28 01:36:29 PM PDT 24 May 28 01:36:33 PM PDT 24 162396030 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1971473682 May 28 01:36:06 PM PDT 24 May 28 01:36:08 PM PDT 24 63509897 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.947547446 May 28 01:35:37 PM PDT 24 May 28 01:35:42 PM PDT 24 10325869 ps
T1069 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3076257580 May 28 01:36:28 PM PDT 24 May 28 01:36:32 PM PDT 24 89937313 ps
T1070 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.54894213 May 28 01:35:37 PM PDT 24 May 28 01:36:19 PM PDT 24 3762633018 ps
T171 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.540221785 May 28 01:36:29 PM PDT 24 May 28 01:36:53 PM PDT 24 4045196153 ps
T1071 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.334338014 May 28 01:36:27 PM PDT 24 May 28 01:36:30 PM PDT 24 84087979 ps
T1072 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2749752 May 28 01:36:26 PM PDT 24 May 28 01:36:28 PM PDT 24 26954669 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.20631960 May 28 01:35:58 PM PDT 24 May 28 01:36:01 PM PDT 24 145707398 ps
T1074 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3421200308 May 28 01:35:59 PM PDT 24 May 28 01:36:03 PM PDT 24 87869259 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1423691843 May 28 01:35:37 PM PDT 24 May 28 01:35:56 PM PDT 24 720378563 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1217925442 May 28 01:35:58 PM PDT 24 May 28 01:36:03 PM PDT 24 129778529 ps
T1077 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.474550115 May 28 01:35:35 PM PDT 24 May 28 01:35:38 PM PDT 24 24171263 ps
T1078 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.454326420 May 28 01:36:15 PM PDT 24 May 28 01:36:19 PM PDT 24 165273992 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3535769337 May 28 01:35:49 PM PDT 24 May 28 01:35:51 PM PDT 24 81486308 ps
T1080 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.111048029 May 28 01:36:01 PM PDT 24 May 28 01:36:07 PM PDT 24 176378991 ps
T1081 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2970033687 May 28 01:36:15 PM PDT 24 May 28 01:36:19 PM PDT 24 1144192808 ps
T174 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4077369723 May 28 01:35:40 PM PDT 24 May 28 01:36:01 PM PDT 24 1555140666 ps
T1082 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3358426195 May 28 01:36:15 PM PDT 24 May 28 01:36:18 PM PDT 24 16951537 ps
T1083 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3942099236 May 28 01:36:00 PM PDT 24 May 28 01:36:05 PM PDT 24 466650080 ps
T1084 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1735520334 May 28 01:36:14 PM PDT 24 May 28 01:36:17 PM PDT 24 182066999 ps
T1085 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4111400499 May 28 01:36:13 PM PDT 24 May 28 01:36:26 PM PDT 24 825005711 ps
T1086 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3439887086 May 28 01:36:13 PM PDT 24 May 28 01:36:14 PM PDT 24 41977015 ps
T1087 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2939416222 May 28 01:36:12 PM PDT 24 May 28 01:36:15 PM PDT 24 230988358 ps
T1088 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.709865044 May 28 01:36:29 PM PDT 24 May 28 01:36:34 PM PDT 24 31346093 ps
T1089 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2433676080 May 28 01:35:51 PM PDT 24 May 28 01:35:53 PM PDT 24 46126136 ps
T172 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1257735992 May 28 01:35:37 PM PDT 24 May 28 01:35:52 PM PDT 24 380897154 ps
T1090 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2198734203 May 28 01:35:53 PM PDT 24 May 28 01:35:58 PM PDT 24 196328525 ps
T1091 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.732380468 May 28 01:36:27 PM PDT 24 May 28 01:36:30 PM PDT 24 30109520 ps
T1092 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1584150252 May 28 01:36:02 PM PDT 24 May 28 01:36:09 PM PDT 24 149661966 ps
T1093 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2449594741 May 28 01:36:15 PM PDT 24 May 28 01:36:20 PM PDT 24 192197667 ps
T1094 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4080912043 May 28 01:36:28 PM PDT 24 May 28 01:36:32 PM PDT 24 77530160 ps
T103 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3689522978 May 28 01:35:48 PM PDT 24 May 28 01:36:07 PM PDT 24 299895985 ps
T1095 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.462786516 May 28 01:35:37 PM PDT 24 May 28 01:36:01 PM PDT 24 310308894 ps
T1096 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1047005435 May 28 01:36:15 PM PDT 24 May 28 01:36:17 PM PDT 24 31374568 ps
T1097 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3822815580 May 28 01:35:55 PM PDT 24 May 28 01:35:57 PM PDT 24 15840914 ps
T1098 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.384011136 May 28 01:35:52 PM PDT 24 May 28 01:36:16 PM PDT 24 702511615 ps
T1099 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3095031601 May 28 01:36:30 PM PDT 24 May 28 01:36:35 PM PDT 24 67171470 ps
T1100 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3553269602 May 28 01:36:29 PM PDT 24 May 28 01:36:34 PM PDT 24 75316041 ps
T1101 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.722767953 May 28 01:36:26 PM PDT 24 May 28 01:36:30 PM PDT 24 529713182 ps

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1991024094
Short name T5
Test name
Test status
Simulation time 11317840471 ps
CPU time 94.38 seconds
Started May 28 02:45:54 PM PDT 24
Finished May 28 02:47:36 PM PDT 24
Peak memory 269584 kb
Host smart-cd9724ad-04ae-4e73-8e3c-5e3561a59b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991024094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1991024094
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2639151746
Short name T20
Test name
Test status
Simulation time 192832357761 ps
CPU time 584.74 seconds
Started May 28 02:45:54 PM PDT 24
Finished May 28 02:55:46 PM PDT 24
Peak memory 272548 kb
Host smart-b8db802a-31ab-4de3-a925-c9f97a1e13ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639151746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2639151746
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.471545736
Short name T9
Test name
Test status
Simulation time 98338246601 ps
CPU time 402.71 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:52:49 PM PDT 24
Peak memory 266000 kb
Host smart-39ebc4a3-ac10-4b6f-9b18-3d045ca4fb1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471545736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.471545736
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1341577063
Short name T108
Test name
Test status
Simulation time 621063830 ps
CPU time 14.15 seconds
Started May 28 01:36:13 PM PDT 24
Finished May 28 01:36:29 PM PDT 24
Peak memory 216876 kb
Host smart-18fd0413-ac4b-412b-b5e8-a86f33afec1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341577063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1341577063
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.403054831
Short name T15
Test name
Test status
Simulation time 9260497727 ps
CPU time 101.2 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:47:04 PM PDT 24
Peak memory 265288 kb
Host smart-94aa679b-079b-4b91-a1f0-b7d1e05994a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403054831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.403054831
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.707730145
Short name T57
Test name
Test status
Simulation time 49825999 ps
CPU time 0.75 seconds
Started May 28 02:44:00 PM PDT 24
Finished May 28 02:44:03 PM PDT 24
Peak memory 215748 kb
Host smart-a4e956b1-d34f-4598-96d7-212ae2c4955d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707730145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.707730145
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1846369299
Short name T93
Test name
Test status
Simulation time 876459887 ps
CPU time 4.84 seconds
Started May 28 01:36:27 PM PDT 24
Finished May 28 01:36:34 PM PDT 24
Peak memory 215512 kb
Host smart-7ea2275f-3840-4af3-9bb6-b35881036760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846369299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1846369299
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.965098400
Short name T31
Test name
Test status
Simulation time 122941071354 ps
CPU time 162.33 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:48:46 PM PDT 24
Peak memory 248888 kb
Host smart-009d67a7-eaf0-43d8-92c7-eaf95f02621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965098400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.965098400
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3932649917
Short name T150
Test name
Test status
Simulation time 309235442218 ps
CPU time 641.94 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:56:30 PM PDT 24
Peak memory 254196 kb
Host smart-3663b916-5fd3-454e-8b48-0d685b8840d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932649917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3932649917
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2514289592
Short name T206
Test name
Test status
Simulation time 70837764671 ps
CPU time 255.34 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:49:18 PM PDT 24
Peak memory 269016 kb
Host smart-149f2b52-3261-49f5-9c5f-98185607e379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514289592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2514289592
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2251620913
Short name T55
Test name
Test status
Simulation time 197889142764 ps
CPU time 398.82 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:51:12 PM PDT 24
Peak memory 268356 kb
Host smart-a275ebdf-6200-4187-bafb-5fa24c7efb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251620913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2251620913
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3421858471
Short name T13
Test name
Test status
Simulation time 618354703 ps
CPU time 7.91 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:08 PM PDT 24
Peak memory 240536 kb
Host smart-f3dbd3a9-1341-45a5-8c98-7b0f405d0122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421858471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3421858471
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1186673604
Short name T378
Test name
Test status
Simulation time 15654790 ps
CPU time 0.73 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:44 PM PDT 24
Peak memory 204300 kb
Host smart-90aa6dcf-05e9-4990-b151-c59c3beb396a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186673604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1186673604
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3005842703
Short name T223
Test name
Test status
Simulation time 11534321932 ps
CPU time 146.92 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:48:34 PM PDT 24
Peak memory 261720 kb
Host smart-dc04693a-8768-4228-9b83-0dea0c944a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005842703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3005842703
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3439674383
Short name T29
Test name
Test status
Simulation time 186438595056 ps
CPU time 411.51 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:51:36 PM PDT 24
Peak memory 256692 kb
Host smart-10a5285e-643b-4867-a164-e049085a7a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439674383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3439674383
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2598880204
Short name T61
Test name
Test status
Simulation time 163521651 ps
CPU time 0.96 seconds
Started May 28 02:43:58 PM PDT 24
Finished May 28 02:44:01 PM PDT 24
Peak memory 234796 kb
Host smart-66ebb76d-1fde-40c6-b25b-0ef783c28b5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598880204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2598880204
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.121057031
Short name T154
Test name
Test status
Simulation time 266057421948 ps
CPU time 662.27 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:56:15 PM PDT 24
Peak memory 265272 kb
Host smart-097ced6a-2b92-4d17-bc5e-026450ce9dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121057031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.121057031
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.553962943
Short name T77
Test name
Test status
Simulation time 53050995 ps
CPU time 0.99 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 206940 kb
Host smart-d5406985-7cce-4542-a0a7-a1fd59b38656
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553962943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.553962943
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.121124402
Short name T30
Test name
Test status
Simulation time 21385849485 ps
CPU time 94.14 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:47:20 PM PDT 24
Peak memory 273364 kb
Host smart-b2098226-cea9-4d5c-b790-bcc055050c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121124402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.121124402
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1777432022
Short name T127
Test name
Test status
Simulation time 9078900088 ps
CPU time 36.37 seconds
Started May 28 02:44:00 PM PDT 24
Finished May 28 02:44:38 PM PDT 24
Peak memory 219672 kb
Host smart-77439120-b2a8-4337-a5f8-984cefb9fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777432022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1777432022
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1714897042
Short name T204
Test name
Test status
Simulation time 72382449684 ps
CPU time 704.92 seconds
Started May 28 02:45:56 PM PDT 24
Finished May 28 02:57:49 PM PDT 24
Peak memory 288860 kb
Host smart-1f0035f8-b7a1-4968-9bec-20a86fcdb834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714897042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1714897042
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2742055473
Short name T524
Test name
Test status
Simulation time 25533089 ps
CPU time 1.11 seconds
Started May 28 02:44:27 PM PDT 24
Finished May 28 02:44:39 PM PDT 24
Peak memory 216208 kb
Host smart-9fcbd1c0-2da9-4d51-82d3-f6f0ab13d8e8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742055473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2742055473
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2541554231
Short name T219
Test name
Test status
Simulation time 366376175070 ps
CPU time 863.9 seconds
Started May 28 02:44:15 PM PDT 24
Finished May 28 02:58:42 PM PDT 24
Peak memory 268648 kb
Host smart-81fdce5b-61cc-4bd9-8274-2bf0e693b0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541554231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2541554231
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2549926279
Short name T37
Test name
Test status
Simulation time 48745120713 ps
CPU time 528.94 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:53:09 PM PDT 24
Peak memory 268316 kb
Host smart-dc52d46c-72de-4d78-8f2b-a72f54425fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549926279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2549926279
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1853190890
Short name T27
Test name
Test status
Simulation time 3610838306 ps
CPU time 28.2 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 217328 kb
Host smart-aeb94eeb-53d8-4cbb-a5b1-9a68381163ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853190890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1853190890
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2988922378
Short name T38
Test name
Test status
Simulation time 89805639781 ps
CPU time 249.26 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 257008 kb
Host smart-12de9991-df88-4d9d-b991-1ce7756e3d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988922378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2988922378
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1651811125
Short name T21
Test name
Test status
Simulation time 209652352962 ps
CPU time 987.42 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 03:02:18 PM PDT 24
Peak memory 263112 kb
Host smart-b2b18a7f-8c23-4350-a9b5-24c9a70d94a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651811125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1651811125
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.540221785
Short name T171
Test name
Test status
Simulation time 4045196153 ps
CPU time 20.63 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:53 PM PDT 24
Peak memory 215540 kb
Host smart-5dd3703f-df77-4167-8f39-a34440bd015e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540221785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.540221785
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2969409117
Short name T183
Test name
Test status
Simulation time 359603639260 ps
CPU time 453.03 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:52:03 PM PDT 24
Peak memory 249596 kb
Host smart-3d8dd6f6-ab75-489c-8ce7-0f35652630f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969409117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2969409117
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1128071082
Short name T304
Test name
Test status
Simulation time 1102150982 ps
CPU time 12.73 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:45 PM PDT 24
Peak memory 232388 kb
Host smart-b4e13ac4-af57-4da0-b3d7-03a43e71365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128071082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1128071082
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2574091624
Short name T212
Test name
Test status
Simulation time 33505937039 ps
CPU time 344.06 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:51:06 PM PDT 24
Peak memory 248920 kb
Host smart-9afd3784-4a47-4768-9ec1-b2b4f84a6fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574091624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2574091624
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.261889115
Short name T205
Test name
Test status
Simulation time 142466821277 ps
CPU time 414.95 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:51:32 PM PDT 24
Peak memory 254220 kb
Host smart-041d5fcb-7827-46f7-bfd6-60ff659930e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261889115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
261889115
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1360584520
Short name T89
Test name
Test status
Simulation time 579977396 ps
CPU time 14.55 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:54 PM PDT 24
Peak memory 217852 kb
Host smart-ca3cdec1-6f01-4ec1-935b-23171fdf689e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360584520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1360584520
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1826563226
Short name T276
Test name
Test status
Simulation time 12430689694 ps
CPU time 196.89 seconds
Started May 28 02:43:58 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 266556 kb
Host smart-660e1435-49e0-4fb1-ba40-0330cc5b8b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826563226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1826563226
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1192941486
Short name T123
Test name
Test status
Simulation time 3268634592 ps
CPU time 54.33 seconds
Started May 28 02:44:31 PM PDT 24
Finished May 28 02:45:37 PM PDT 24
Peak memory 240692 kb
Host smart-79b00a5f-61f6-465b-be74-39323a54b9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192941486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1192941486
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1027200066
Short name T281
Test name
Test status
Simulation time 158027170576 ps
CPU time 280.14 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:49:50 PM PDT 24
Peak memory 257080 kb
Host smart-9c682f27-2328-4df1-9fe1-a6236850f9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027200066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1027200066
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2910240748
Short name T291
Test name
Test status
Simulation time 71789642142 ps
CPU time 717.68 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:57:45 PM PDT 24
Peak memory 272652 kb
Host smart-45709928-d66f-4bf0-b2cb-8ab907f59a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910240748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2910240748
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3383883573
Short name T186
Test name
Test status
Simulation time 11879900283 ps
CPU time 47.68 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:47:37 PM PDT 24
Peak memory 250356 kb
Host smart-e2e67e47-4f6b-4db2-859d-f4005681cee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383883573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3383883573
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.13890487
Short name T98
Test name
Test status
Simulation time 937904007 ps
CPU time 5.49 seconds
Started May 28 01:35:36 PM PDT 24
Finished May 28 01:35:44 PM PDT 24
Peak memory 215756 kb
Host smart-cfad05b3-08f1-49ba-a0c6-3fb39b72e1dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.13890487
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3526893042
Short name T83
Test name
Test status
Simulation time 174450498 ps
CPU time 2.36 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:26 PM PDT 24
Peak memory 216460 kb
Host smart-09c6fc35-deac-48e1-ae61-9acf1a8281b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526893042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3526893042
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1372934267
Short name T32
Test name
Test status
Simulation time 5012414564 ps
CPU time 5.02 seconds
Started May 28 02:45:13 PM PDT 24
Finished May 28 02:45:20 PM PDT 24
Peak memory 233396 kb
Host smart-1e0b2130-9967-4ee8-a2fc-a1b7bc5bff73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372934267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1372934267
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1257735992
Short name T172
Test name
Test status
Simulation time 380897154 ps
CPU time 12.16 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:52 PM PDT 24
Peak memory 215396 kb
Host smart-63d6c44d-c074-402c-9aec-344ff963fe62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257735992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1257735992
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2251659078
Short name T669
Test name
Test status
Simulation time 151909697 ps
CPU time 4.99 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:56 PM PDT 24
Peak memory 224184 kb
Host smart-7da25540-33b8-4b07-9809-ebf72913e323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251659078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2251659078
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3261588877
Short name T403
Test name
Test status
Simulation time 7855575065 ps
CPU time 52.65 seconds
Started May 28 02:44:58 PM PDT 24
Finished May 28 02:45:56 PM PDT 24
Peak memory 257076 kb
Host smart-0be44cc1-bf7d-4abf-b999-e79e1868cae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261588877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3261588877
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.413866587
Short name T303
Test name
Test status
Simulation time 1267662067 ps
CPU time 21.83 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 224184 kb
Host smart-e7562970-a403-460e-855e-dbbcf44ddf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413866587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.413866587
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2064064042
Short name T283
Test name
Test status
Simulation time 52578624258 ps
CPU time 120.7 seconds
Started May 28 02:44:52 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 272292 kb
Host smart-e8bfe3d9-af77-4f85-8c08-f625793d29a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064064042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2064064042
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2502138659
Short name T2
Test name
Test status
Simulation time 38137794218 ps
CPU time 166.83 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 245584 kb
Host smart-c5c49d0a-9bde-4deb-8e98-24571fef754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502138659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2502138659
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3356183494
Short name T76
Test name
Test status
Simulation time 22905649 ps
CPU time 1.35 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:43 PM PDT 24
Peak memory 207148 kb
Host smart-ee61680c-a9cf-472f-90d9-5a6e473cb4e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356183494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3356183494
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3689522978
Short name T103
Test name
Test status
Simulation time 299895985 ps
CPU time 18.63 seconds
Started May 28 01:35:48 PM PDT 24
Finished May 28 01:36:07 PM PDT 24
Peak memory 215504 kb
Host smart-4a6c7855-480c-43df-8709-08df3e937c24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689522978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3689522978
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1834808327
Short name T113
Test name
Test status
Simulation time 20483473025 ps
CPU time 22.84 seconds
Started May 28 01:35:36 PM PDT 24
Finished May 28 01:36:01 PM PDT 24
Peak memory 215564 kb
Host smart-f527086d-93cf-4564-894e-5340eea972fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834808327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1834808327
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.389121838
Short name T1026
Test name
Test status
Simulation time 706652714 ps
CPU time 23.52 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:36:05 PM PDT 24
Peak memory 207308 kb
Host smart-cc4da3c1-bd0a-40b0-b27b-9618e81275ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389121838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.389121838
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3958308796
Short name T1033
Test name
Test status
Simulation time 31662819 ps
CPU time 1.16 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:43 PM PDT 24
Peak memory 216548 kb
Host smart-57142117-bdfd-42a2-9d06-b7589f96931c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958308796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3958308796
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3711303799
Short name T87
Test name
Test status
Simulation time 257500656 ps
CPU time 3.25 seconds
Started May 28 01:35:39 PM PDT 24
Finished May 28 01:35:46 PM PDT 24
Peak memory 217456 kb
Host smart-cafa98dd-1418-40e7-b265-bc02a1bbb7fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711303799 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3711303799
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2454388281
Short name T111
Test name
Test status
Simulation time 70960225 ps
CPU time 2.75 seconds
Started May 28 01:35:39 PM PDT 24
Finished May 28 01:35:46 PM PDT 24
Peak memory 215544 kb
Host smart-4632c0e6-96a8-48d0-baee-d4cb4a93681f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454388281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
454388281
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1781888705
Short name T1004
Test name
Test status
Simulation time 55019125 ps
CPU time 0.75 seconds
Started May 28 01:35:36 PM PDT 24
Finished May 28 01:35:39 PM PDT 24
Peak memory 203784 kb
Host smart-961a6127-5f05-4a08-bed9-161e6cf23b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781888705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
781888705
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2334387601
Short name T119
Test name
Test status
Simulation time 28883859 ps
CPU time 2.03 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:44 PM PDT 24
Peak memory 215544 kb
Host smart-b13bc0d6-04d0-44d5-87ff-edbd967a394b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334387601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2334387601
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1418909527
Short name T984
Test name
Test status
Simulation time 30719705 ps
CPU time 0.66 seconds
Started May 28 01:35:36 PM PDT 24
Finished May 28 01:35:40 PM PDT 24
Peak memory 203668 kb
Host smart-9264312b-9e71-4c38-b30e-b1b6480d9b03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418909527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1418909527
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3672953127
Short name T1049
Test name
Test status
Simulation time 400031795 ps
CPU time 3.05 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:45 PM PDT 24
Peak memory 215720 kb
Host smart-ec9d5fdc-3c92-4aab-ae1b-363cd0502748
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672953127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3672953127
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2834119518
Short name T1050
Test name
Test status
Simulation time 774638496 ps
CPU time 2.22 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:44 PM PDT 24
Peak memory 215640 kb
Host smart-2b0d36a2-2408-4151-aabe-0b4469b71d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834119518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
834119518
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1423691843
Short name T1075
Test name
Test status
Simulation time 720378563 ps
CPU time 16.71 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:56 PM PDT 24
Peak memory 215512 kb
Host smart-6aa93239-6ba6-4618-9812-fd9cf4780624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423691843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1423691843
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.785556932
Short name T1010
Test name
Test status
Simulation time 113071951 ps
CPU time 7.58 seconds
Started May 28 01:35:39 PM PDT 24
Finished May 28 01:35:51 PM PDT 24
Peak memory 207276 kb
Host smart-d8fc26b5-57b4-4a23-bd0a-50ed077dceb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785556932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.785556932
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.101433097
Short name T1035
Test name
Test status
Simulation time 184568875 ps
CPU time 12.76 seconds
Started May 28 01:35:36 PM PDT 24
Finished May 28 01:35:50 PM PDT 24
Peak memory 207360 kb
Host smart-002c0fec-3a6c-485e-8dd7-a04eb66008a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101433097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.101433097
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4240610635
Short name T1044
Test name
Test status
Simulation time 130543560 ps
CPU time 3.61 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:46 PM PDT 24
Peak memory 217800 kb
Host smart-9974e932-730c-4df2-aac6-9ec2b2a40f66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240610635 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4240610635
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3407184399
Short name T134
Test name
Test status
Simulation time 66081184 ps
CPU time 1.27 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 215524 kb
Host smart-d7e29450-5a06-40b4-b4b4-fba17ed995f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407184399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
407184399
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3263776571
Short name T996
Test name
Test status
Simulation time 21478921 ps
CPU time 0.73 seconds
Started May 28 01:35:40 PM PDT 24
Finished May 28 01:35:44 PM PDT 24
Peak memory 204040 kb
Host smart-43965927-74f3-4b8e-94e3-6807e5865b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263776571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
263776571
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.474550115
Short name T1077
Test name
Test status
Simulation time 24171263 ps
CPU time 1.7 seconds
Started May 28 01:35:35 PM PDT 24
Finished May 28 01:35:38 PM PDT 24
Peak memory 215556 kb
Host smart-b94d986e-b5ac-4b79-82a7-90fa808fb8ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474550115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.474550115
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2897746391
Short name T1028
Test name
Test status
Simulation time 15461456 ps
CPU time 0.66 seconds
Started May 28 01:35:36 PM PDT 24
Finished May 28 01:35:39 PM PDT 24
Peak memory 203644 kb
Host smart-13e66e6a-4ce1-4936-b3be-52123696cc1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897746391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2897746391
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1801335137
Short name T133
Test name
Test status
Simulation time 37769304 ps
CPU time 2.49 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:43 PM PDT 24
Peak memory 215596 kb
Host smart-b952832f-8efa-4b57-91b6-a58b379b323d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801335137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1801335137
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.882834357
Short name T99
Test name
Test status
Simulation time 159430847 ps
CPU time 4.12 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:45 PM PDT 24
Peak memory 215620 kb
Host smart-460188a8-a486-4053-a0c2-5b5395ce334c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882834357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.882834357
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1316495490
Short name T1005
Test name
Test status
Simulation time 26791603 ps
CPU time 1.81 seconds
Started May 28 01:35:59 PM PDT 24
Finished May 28 01:36:02 PM PDT 24
Peak memory 215708 kb
Host smart-5b5e7594-7132-47f1-a258-7230f6bfa902
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316495490 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1316495490
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3936468227
Short name T982
Test name
Test status
Simulation time 63506522 ps
CPU time 1.38 seconds
Started May 28 01:36:00 PM PDT 24
Finished May 28 01:36:04 PM PDT 24
Peak memory 215564 kb
Host smart-2ca05099-541f-413c-8de5-0a336e33f8e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936468227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3936468227
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.108180108
Short name T995
Test name
Test status
Simulation time 14415539 ps
CPU time 0.74 seconds
Started May 28 01:36:00 PM PDT 24
Finished May 28 01:36:02 PM PDT 24
Peak memory 203728 kb
Host smart-b5dd29ce-78aa-4dff-9640-bec4664787bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108180108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.108180108
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2007429034
Short name T981
Test name
Test status
Simulation time 112998070 ps
CPU time 1.95 seconds
Started May 28 01:36:02 PM PDT 24
Finished May 28 01:36:06 PM PDT 24
Peak memory 215480 kb
Host smart-3252122d-a98b-4f52-b408-bd5998866e3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007429034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2007429034
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1921818504
Short name T1061
Test name
Test status
Simulation time 67309395 ps
CPU time 2.05 seconds
Started May 28 01:36:00 PM PDT 24
Finished May 28 01:36:05 PM PDT 24
Peak memory 215716 kb
Host smart-fd379edc-f10f-4609-99bf-292d8b4991a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921818504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1921818504
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3882866759
Short name T105
Test name
Test status
Simulation time 1061940198 ps
CPU time 20.06 seconds
Started May 28 01:36:01 PM PDT 24
Finished May 28 01:36:24 PM PDT 24
Peak memory 215932 kb
Host smart-04ba8e11-50f8-47f4-ad4a-b77a2051193b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882866759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3882866759
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2090773917
Short name T146
Test name
Test status
Simulation time 378565237 ps
CPU time 2.84 seconds
Started May 28 01:36:04 PM PDT 24
Finished May 28 01:36:09 PM PDT 24
Peak memory 218112 kb
Host smart-13dc8833-1baa-4095-a9f6-eb2caa289fea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090773917 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2090773917
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3759087529
Short name T110
Test name
Test status
Simulation time 106175973 ps
CPU time 2.01 seconds
Started May 28 01:36:00 PM PDT 24
Finished May 28 01:36:05 PM PDT 24
Peak memory 207256 kb
Host smart-f3f0a7dd-440d-4750-8e81-8496f2af888d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759087529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3759087529
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.866705392
Short name T997
Test name
Test status
Simulation time 13798004 ps
CPU time 0.72 seconds
Started May 28 01:36:02 PM PDT 24
Finished May 28 01:36:05 PM PDT 24
Peak memory 203684 kb
Host smart-66ce7c34-4a97-4f38-9613-346a5d428d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866705392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.866705392
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2790294734
Short name T1040
Test name
Test status
Simulation time 277850914 ps
CPU time 1.7 seconds
Started May 28 01:36:02 PM PDT 24
Finished May 28 01:36:07 PM PDT 24
Peak memory 215592 kb
Host smart-7c335697-e0d5-4ab4-a00d-d08f83d9f338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790294734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2790294734
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2457458338
Short name T97
Test name
Test status
Simulation time 32315554 ps
CPU time 1.93 seconds
Started May 28 01:36:01 PM PDT 24
Finished May 28 01:36:06 PM PDT 24
Peak memory 215548 kb
Host smart-4dd9068e-968b-4d2c-9240-4fa34ef8b336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457458338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2457458338
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1488755915
Short name T170
Test name
Test status
Simulation time 203044305 ps
CPU time 13.6 seconds
Started May 28 01:36:00 PM PDT 24
Finished May 28 01:36:16 PM PDT 24
Peak memory 215504 kb
Host smart-085d9af7-0e77-4300-afb2-70a39712592c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488755915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1488755915
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2428607116
Short name T1056
Test name
Test status
Simulation time 381527182 ps
CPU time 3.07 seconds
Started May 28 01:36:02 PM PDT 24
Finished May 28 01:36:08 PM PDT 24
Peak memory 217268 kb
Host smart-7e5624e7-27d0-4471-aa07-bee31bd8c271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428607116 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2428607116
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2246519369
Short name T1001
Test name
Test status
Simulation time 136986481 ps
CPU time 1.35 seconds
Started May 28 01:36:01 PM PDT 24
Finished May 28 01:36:05 PM PDT 24
Peak memory 207300 kb
Host smart-ff8d42da-0c76-426b-862f-9f397f72367d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246519369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2246519369
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1971473682
Short name T1067
Test name
Test status
Simulation time 63509897 ps
CPU time 0.78 seconds
Started May 28 01:36:06 PM PDT 24
Finished May 28 01:36:08 PM PDT 24
Peak memory 203556 kb
Host smart-6a6ababf-d9a7-4b37-88b7-0d0b657226f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971473682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1971473682
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.503399510
Short name T1048
Test name
Test status
Simulation time 164143521 ps
CPU time 4.32 seconds
Started May 28 01:36:01 PM PDT 24
Finished May 28 01:36:08 PM PDT 24
Peak memory 215532 kb
Host smart-2db96ae7-8a2f-44fd-aba3-c3382e06f5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503399510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.503399510
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1143835101
Short name T96
Test name
Test status
Simulation time 460935759 ps
CPU time 3.53 seconds
Started May 28 01:36:01 PM PDT 24
Finished May 28 01:36:07 PM PDT 24
Peak memory 215580 kb
Host smart-ed98e6eb-5bd1-49a5-9840-62955c14c70f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143835101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1143835101
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3190032159
Short name T90
Test name
Test status
Simulation time 1143784149 ps
CPU time 8.52 seconds
Started May 28 01:36:00 PM PDT 24
Finished May 28 01:36:11 PM PDT 24
Peak memory 215520 kb
Host smart-98135603-5b57-41e5-b770-201da43c74b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190032159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3190032159
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1193792895
Short name T101
Test name
Test status
Simulation time 51265836 ps
CPU time 3.49 seconds
Started May 28 01:36:02 PM PDT 24
Finished May 28 01:36:08 PM PDT 24
Peak memory 217460 kb
Host smart-ac821a7d-d008-4a9b-a27b-f7d72477de78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193792895 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1193792895
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2367912582
Short name T999
Test name
Test status
Simulation time 329857364 ps
CPU time 1.96 seconds
Started May 28 01:36:01 PM PDT 24
Finished May 28 01:36:06 PM PDT 24
Peak memory 215520 kb
Host smart-66fa02f5-592a-431a-8aea-1c8d5a1963fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367912582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2367912582
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1250549900
Short name T1016
Test name
Test status
Simulation time 73314496 ps
CPU time 0.75 seconds
Started May 28 01:36:01 PM PDT 24
Finished May 28 01:36:05 PM PDT 24
Peak memory 203776 kb
Host smart-1f259a6b-b31d-4afb-8141-acf156c0137d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250549900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1250549900
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.111048029
Short name T1080
Test name
Test status
Simulation time 176378991 ps
CPU time 2.82 seconds
Started May 28 01:36:01 PM PDT 24
Finished May 28 01:36:07 PM PDT 24
Peak memory 215560 kb
Host smart-49160490-0b24-42ac-9217-9701d79ecd2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111048029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.111048029
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.620687622
Short name T1055
Test name
Test status
Simulation time 1103414501 ps
CPU time 4.3 seconds
Started May 28 01:35:59 PM PDT 24
Finished May 28 01:36:05 PM PDT 24
Peak memory 215552 kb
Host smart-9814ffe4-9c75-4445-b0c8-be7d1e97a4a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620687622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.620687622
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1987941282
Short name T145
Test name
Test status
Simulation time 1637965308 ps
CPU time 8.18 seconds
Started May 28 01:36:04 PM PDT 24
Finished May 28 01:36:14 PM PDT 24
Peak memory 216676 kb
Host smart-683eb91c-152a-48df-ad0b-40ab70ed76e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987941282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1987941282
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3443692952
Short name T1060
Test name
Test status
Simulation time 60076792 ps
CPU time 4.3 seconds
Started May 28 01:36:14 PM PDT 24
Finished May 28 01:36:20 PM PDT 24
Peak memory 217716 kb
Host smart-84d977e5-a497-4425-a256-15b64ad9092b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443692952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3443692952
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2833910948
Short name T112
Test name
Test status
Simulation time 27608866 ps
CPU time 1.84 seconds
Started May 28 01:36:14 PM PDT 24
Finished May 28 01:36:18 PM PDT 24
Peak memory 215596 kb
Host smart-10b9dbb6-f991-4bec-b6e3-4aaeaccc414e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833910948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2833910948
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3358426195
Short name T1082
Test name
Test status
Simulation time 16951537 ps
CPU time 0.78 seconds
Started May 28 01:36:15 PM PDT 24
Finished May 28 01:36:18 PM PDT 24
Peak memory 204000 kb
Host smart-b8c3b29b-3a92-4170-9fcb-7f257b5ffaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358426195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3358426195
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2939416222
Short name T1087
Test name
Test status
Simulation time 230988358 ps
CPU time 1.97 seconds
Started May 28 01:36:12 PM PDT 24
Finished May 28 01:36:15 PM PDT 24
Peak memory 215556 kb
Host smart-a0f77e2c-e2c9-437a-a3ec-b9c55034ca40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939416222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2939416222
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1584150252
Short name T1092
Test name
Test status
Simulation time 149661966 ps
CPU time 3.9 seconds
Started May 28 01:36:02 PM PDT 24
Finished May 28 01:36:09 PM PDT 24
Peak memory 215772 kb
Host smart-74523cae-918e-428a-b3a3-299d889a9255
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584150252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1584150252
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1735520334
Short name T1084
Test name
Test status
Simulation time 182066999 ps
CPU time 1.7 seconds
Started May 28 01:36:14 PM PDT 24
Finished May 28 01:36:17 PM PDT 24
Peak memory 215680 kb
Host smart-bcd678d7-1bcc-455d-9c04-538855ebfcc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735520334 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1735520334
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3854640585
Short name T1032
Test name
Test status
Simulation time 142788799 ps
CPU time 1.37 seconds
Started May 28 01:36:13 PM PDT 24
Finished May 28 01:36:15 PM PDT 24
Peak memory 215416 kb
Host smart-6c875f09-8709-4bbe-81a7-cfa77dada4a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854640585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3854640585
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2432700396
Short name T1063
Test name
Test status
Simulation time 28284241 ps
CPU time 0.71 seconds
Started May 28 01:36:14 PM PDT 24
Finished May 28 01:36:17 PM PDT 24
Peak memory 203924 kb
Host smart-cd01fc63-3c28-4229-8bed-5168bc5db204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432700396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2432700396
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2970033687
Short name T1081
Test name
Test status
Simulation time 1144192808 ps
CPU time 2.91 seconds
Started May 28 01:36:15 PM PDT 24
Finished May 28 01:36:19 PM PDT 24
Peak memory 215524 kb
Host smart-75cb2b68-3bac-4c0b-aba7-216f6b6e5089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970033687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2970033687
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.454326420
Short name T1078
Test name
Test status
Simulation time 165273992 ps
CPU time 1.63 seconds
Started May 28 01:36:15 PM PDT 24
Finished May 28 01:36:19 PM PDT 24
Peak memory 215612 kb
Host smart-7ed429be-2308-4cbd-9ac7-db33a8c50037
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454326420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.454326420
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3596942333
Short name T88
Test name
Test status
Simulation time 303972087 ps
CPU time 8.79 seconds
Started May 28 01:36:14 PM PDT 24
Finished May 28 01:36:25 PM PDT 24
Peak memory 215732 kb
Host smart-8da12c63-eb2a-4057-a0f6-8fb27f976f44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596942333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3596942333
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3554262793
Short name T102
Test name
Test status
Simulation time 199249668 ps
CPU time 1.59 seconds
Started May 28 01:36:15 PM PDT 24
Finished May 28 01:36:19 PM PDT 24
Peak memory 215632 kb
Host smart-d341dd24-53c8-49d0-962b-04b90e3bf05d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554262793 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3554262793
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1959008262
Short name T1052
Test name
Test status
Simulation time 233392597 ps
CPU time 1.67 seconds
Started May 28 01:36:13 PM PDT 24
Finished May 28 01:36:16 PM PDT 24
Peak memory 207212 kb
Host smart-5ad9f1f8-e57d-475e-b41d-00aba0de27b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959008262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1959008262
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1047005435
Short name T1096
Test name
Test status
Simulation time 31374568 ps
CPU time 0.71 seconds
Started May 28 01:36:15 PM PDT 24
Finished May 28 01:36:17 PM PDT 24
Peak memory 203568 kb
Host smart-e5887059-9025-4863-8c10-01af7f4d3ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047005435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1047005435
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4144332609
Short name T983
Test name
Test status
Simulation time 58949544 ps
CPU time 3.62 seconds
Started May 28 01:36:14 PM PDT 24
Finished May 28 01:36:18 PM PDT 24
Peak memory 215512 kb
Host smart-d19ec17a-88d5-43b0-bb30-6154064538d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144332609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4144332609
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2449594741
Short name T1093
Test name
Test status
Simulation time 192197667 ps
CPU time 2.65 seconds
Started May 28 01:36:15 PM PDT 24
Finished May 28 01:36:20 PM PDT 24
Peak memory 215592 kb
Host smart-f7ff0aab-329a-41e3-82ab-eee02a3a38eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449594741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2449594741
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4111400499
Short name T1085
Test name
Test status
Simulation time 825005711 ps
CPU time 12.05 seconds
Started May 28 01:36:13 PM PDT 24
Finished May 28 01:36:26 PM PDT 24
Peak memory 215548 kb
Host smart-093896bd-d738-409b-b670-790ff6c67aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111400499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4111400499
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.722767953
Short name T1101
Test name
Test status
Simulation time 529713182 ps
CPU time 3.42 seconds
Started May 28 01:36:26 PM PDT 24
Finished May 28 01:36:30 PM PDT 24
Peak memory 218444 kb
Host smart-03eea0ad-a683-4743-a1b2-afe7bb946844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722767953 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.722767953
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2709229749
Short name T117
Test name
Test status
Simulation time 19114058 ps
CPU time 1.24 seconds
Started May 28 01:36:14 PM PDT 24
Finished May 28 01:36:16 PM PDT 24
Peak memory 207260 kb
Host smart-43af7836-70f8-4fe7-a5aa-4c21d9806488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709229749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2709229749
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3439887086
Short name T1086
Test name
Test status
Simulation time 41977015 ps
CPU time 0.72 seconds
Started May 28 01:36:13 PM PDT 24
Finished May 28 01:36:14 PM PDT 24
Peak memory 204040 kb
Host smart-5a67c9dc-9a5d-4861-935f-757643475d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439887086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3439887086
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3259690759
Short name T985
Test name
Test status
Simulation time 941656879 ps
CPU time 4.24 seconds
Started May 28 01:36:14 PM PDT 24
Finished May 28 01:36:19 PM PDT 24
Peak memory 215512 kb
Host smart-30d44eea-5c03-4e73-b17f-c6f45b08a367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259690759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3259690759
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4258789402
Short name T100
Test name
Test status
Simulation time 27971357 ps
CPU time 1.91 seconds
Started May 28 01:36:15 PM PDT 24
Finished May 28 01:36:19 PM PDT 24
Peak memory 215704 kb
Host smart-e6b4dcec-f935-4e25-b3e0-7e64f6570e91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258789402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4258789402
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4136981674
Short name T1046
Test name
Test status
Simulation time 294240861 ps
CPU time 17.81 seconds
Started May 28 01:36:15 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 215568 kb
Host smart-86c61e8e-ba90-492d-8f37-25cf10e4bf6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136981674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4136981674
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.202538713
Short name T1014
Test name
Test status
Simulation time 75012960 ps
CPU time 2.57 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:36 PM PDT 24
Peak memory 216668 kb
Host smart-c6de1b4b-7ec7-4c26-8bbb-5439967fb832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202538713 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.202538713
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2625270156
Short name T109
Test name
Test status
Simulation time 34401100 ps
CPU time 1.2 seconds
Started May 28 01:36:26 PM PDT 24
Finished May 28 01:36:28 PM PDT 24
Peak memory 215540 kb
Host smart-fa33b9eb-3cdd-48eb-b99d-d8d35126706a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625270156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2625270156
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.732380468
Short name T1091
Test name
Test status
Simulation time 30109520 ps
CPU time 0.71 seconds
Started May 28 01:36:27 PM PDT 24
Finished May 28 01:36:30 PM PDT 24
Peak memory 203652 kb
Host smart-c9e7f872-8113-42df-aed9-f182b7d66561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732380468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.732380468
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.334338014
Short name T1071
Test name
Test status
Simulation time 84087979 ps
CPU time 2.85 seconds
Started May 28 01:36:27 PM PDT 24
Finished May 28 01:36:30 PM PDT 24
Peak memory 215520 kb
Host smart-53687a68-2520-4795-881c-a5adc5cde66a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334338014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.334338014
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1069353015
Short name T1062
Test name
Test status
Simulation time 354382485 ps
CPU time 2.36 seconds
Started May 28 01:36:25 PM PDT 24
Finished May 28 01:36:28 PM PDT 24
Peak memory 215464 kb
Host smart-276ae19b-2127-48ae-99fa-3379094f6824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069353015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1069353015
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2647634881
Short name T1054
Test name
Test status
Simulation time 743486952 ps
CPU time 2.73 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 216588 kb
Host smart-64da6ed5-650d-487c-ad00-2f95ea7abbef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647634881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2647634881
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4080912043
Short name T1094
Test name
Test status
Simulation time 77530160 ps
CPU time 1.24 seconds
Started May 28 01:36:28 PM PDT 24
Finished May 28 01:36:32 PM PDT 24
Peak memory 207068 kb
Host smart-b9b8c069-5f9b-46f6-a594-ad7c96fc030a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080912043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4080912043
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.571603769
Short name T987
Test name
Test status
Simulation time 76259277 ps
CPU time 0.71 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 203676 kb
Host smart-d0e23078-4e6e-4644-8d8d-c20bb47e699b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571603769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.571603769
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1432995802
Short name T1045
Test name
Test status
Simulation time 308944209 ps
CPU time 3.03 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:36 PM PDT 24
Peak memory 215592 kb
Host smart-3e690cd8-10b1-47f1-a898-ca798c94359a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432995802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1432995802
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3668244423
Short name T173
Test name
Test status
Simulation time 1499448759 ps
CPU time 13.36 seconds
Started May 28 01:36:27 PM PDT 24
Finished May 28 01:36:41 PM PDT 24
Peak memory 215544 kb
Host smart-ebd446ee-b29a-4114-80c1-837af5350399
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668244423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3668244423
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2819134626
Short name T116
Test name
Test status
Simulation time 317333392 ps
CPU time 8.79 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:49 PM PDT 24
Peak memory 207360 kb
Host smart-90dff54b-4944-41fc-a694-736f9b581548
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819134626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2819134626
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.54894213
Short name T1070
Test name
Test status
Simulation time 3762633018 ps
CPU time 37.95 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:36:19 PM PDT 24
Peak memory 207396 kb
Host smart-d4917b50-2931-4ef3-a00f-a111c16326b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54894213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
bit_bash.54894213
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4091063214
Short name T1013
Test name
Test status
Simulation time 58940655 ps
CPU time 1.88 seconds
Started May 28 01:35:39 PM PDT 24
Finished May 28 01:35:45 PM PDT 24
Peak memory 215668 kb
Host smart-c931ccdb-7f1d-42b1-a079-cf47d60ff0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091063214 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4091063214
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4276118561
Short name T1019
Test name
Test status
Simulation time 37675730 ps
CPU time 2.3 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:44 PM PDT 24
Peak memory 215412 kb
Host smart-822f56b0-aee0-4c3a-b2ed-23ac811803eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276118561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
276118561
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3096469796
Short name T1038
Test name
Test status
Simulation time 42892326 ps
CPU time 0.7 seconds
Started May 28 01:35:36 PM PDT 24
Finished May 28 01:35:39 PM PDT 24
Peak memory 203616 kb
Host smart-2b530fc5-ca40-452f-9c95-839359309655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096469796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
096469796
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3310094837
Short name T1039
Test name
Test status
Simulation time 272311238 ps
CPU time 2.07 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 215596 kb
Host smart-7b5783f6-6fa2-46bf-bd32-a6cabf2dcc36
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310094837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3310094837
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3111713217
Short name T1006
Test name
Test status
Simulation time 12955254 ps
CPU time 0.67 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:41 PM PDT 24
Peak memory 203668 kb
Host smart-90cd93c9-ba74-4c8e-af09-7db6d447296d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111713217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3111713217
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2458618272
Short name T1053
Test name
Test status
Simulation time 59352158 ps
CPU time 3.85 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:43 PM PDT 24
Peak memory 215556 kb
Host smart-5c17b15b-6124-46a3-a282-eebffe78c914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458618272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2458618272
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1895062067
Short name T91
Test name
Test status
Simulation time 97020982 ps
CPU time 2.59 seconds
Started May 28 01:35:40 PM PDT 24
Finished May 28 01:35:46 PM PDT 24
Peak memory 215808 kb
Host smart-0e7810b5-eedf-400e-8608-923b3a44a6ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895062067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
895062067
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4077369723
Short name T174
Test name
Test status
Simulation time 1555140666 ps
CPU time 18.23 seconds
Started May 28 01:35:40 PM PDT 24
Finished May 28 01:36:01 PM PDT 24
Peak memory 215568 kb
Host smart-308b0dd8-d211-464d-9de8-20b7d67da2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077369723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4077369723
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1449491121
Short name T1012
Test name
Test status
Simulation time 33310091 ps
CPU time 0.76 seconds
Started May 28 01:36:33 PM PDT 24
Finished May 28 01:36:37 PM PDT 24
Peak memory 204020 kb
Host smart-9a3311e1-74d4-43f5-a802-efed493247ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449491121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1449491121
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2749752
Short name T1072
Test name
Test status
Simulation time 26954669 ps
CPU time 0.7 seconds
Started May 28 01:36:26 PM PDT 24
Finished May 28 01:36:28 PM PDT 24
Peak memory 203616 kb
Host smart-56edb85a-499d-4c2f-af86-fa38115205b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.2749752
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2820266724
Short name T979
Test name
Test status
Simulation time 13967922 ps
CPU time 0.76 seconds
Started May 28 01:36:31 PM PDT 24
Finished May 28 01:36:36 PM PDT 24
Peak memory 203784 kb
Host smart-bcb5e6eb-3e8a-405a-8122-1aec6a709575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820266724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2820266724
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3095031601
Short name T1099
Test name
Test status
Simulation time 67171470 ps
CPU time 0.72 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 203944 kb
Host smart-5ecbe4bd-bdb1-4f3d-93c1-39c1c6416e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095031601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3095031601
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1000833655
Short name T1011
Test name
Test status
Simulation time 14243737 ps
CPU time 0.72 seconds
Started May 28 01:36:26 PM PDT 24
Finished May 28 01:36:28 PM PDT 24
Peak memory 204020 kb
Host smart-6210d401-6c13-4830-9c45-ddbc98e6429b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000833655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1000833655
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4113931046
Short name T1017
Test name
Test status
Simulation time 51630118 ps
CPU time 0.75 seconds
Started May 28 01:36:28 PM PDT 24
Finished May 28 01:36:33 PM PDT 24
Peak memory 204016 kb
Host smart-8fba9a3e-a66d-4191-b459-fd191f5251f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113931046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4113931046
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.870338155
Short name T1064
Test name
Test status
Simulation time 43468395 ps
CPU time 0.74 seconds
Started May 28 01:36:27 PM PDT 24
Finished May 28 01:36:30 PM PDT 24
Peak memory 204052 kb
Host smart-534d6e06-1c45-4f21-8dd8-736e1ad6d0f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870338155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.870338155
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2296847198
Short name T991
Test name
Test status
Simulation time 47768353 ps
CPU time 0.72 seconds
Started May 28 01:36:31 PM PDT 24
Finished May 28 01:36:36 PM PDT 24
Peak memory 203728 kb
Host smart-073a04b9-05a9-4f79-95d9-af841c747385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296847198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2296847198
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3060094903
Short name T1023
Test name
Test status
Simulation time 113027613 ps
CPU time 0.77 seconds
Started May 28 01:36:28 PM PDT 24
Finished May 28 01:36:32 PM PDT 24
Peak memory 203608 kb
Host smart-90916015-4f0a-43ac-89fc-5479e1aa301c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060094903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3060094903
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3356345816
Short name T1025
Test name
Test status
Simulation time 14477909 ps
CPU time 0.76 seconds
Started May 28 01:36:27 PM PDT 24
Finished May 28 01:36:28 PM PDT 24
Peak memory 203992 kb
Host smart-4efa2d6e-ce87-4e57-86e7-2391b0efaa25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356345816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3356345816
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.462786516
Short name T1095
Test name
Test status
Simulation time 310308894 ps
CPU time 20.47 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:36:01 PM PDT 24
Peak memory 215496 kb
Host smart-b2fdb346-04f9-4a42-a137-5a3ab1efd193
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462786516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.462786516
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.554970078
Short name T164
Test name
Test status
Simulation time 18026467678 ps
CPU time 41.35 seconds
Started May 28 01:35:35 PM PDT 24
Finished May 28 01:36:18 PM PDT 24
Peak memory 207444 kb
Host smart-362aab1a-7843-4356-a671-776a6bb00d51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554970078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.554970078
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1799753331
Short name T118
Test name
Test status
Simulation time 45799193 ps
CPU time 1.42 seconds
Started May 28 01:35:41 PM PDT 24
Finished May 28 01:35:45 PM PDT 24
Peak memory 207316 kb
Host smart-33552eae-0839-48c7-ae02-00bb7ce63570
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799753331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1799753331
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1220139263
Short name T92
Test name
Test status
Simulation time 54122992 ps
CPU time 1.88 seconds
Started May 28 01:35:50 PM PDT 24
Finished May 28 01:35:53 PM PDT 24
Peak memory 216620 kb
Host smart-0f90aec8-b47a-4f01-a9fc-0293c85bbb9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220139263 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1220139263
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3561674346
Short name T1015
Test name
Test status
Simulation time 143053628 ps
CPU time 1.4 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 215544 kb
Host smart-5812f490-9edf-405c-a60f-23cc52dd40b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561674346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
561674346
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1507971216
Short name T1031
Test name
Test status
Simulation time 15794683 ps
CPU time 0.82 seconds
Started May 28 01:35:38 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 203704 kb
Host smart-41c752b7-ae22-4a49-86f5-1d2706ceb0f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507971216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
507971216
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4128578966
Short name T1030
Test name
Test status
Simulation time 55871417 ps
CPU time 1.3 seconds
Started May 28 01:35:40 PM PDT 24
Finished May 28 01:35:45 PM PDT 24
Peak memory 215528 kb
Host smart-998dffd6-af12-4afc-bfc1-d922d6a64f18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128578966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4128578966
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.947547446
Short name T1068
Test name
Test status
Simulation time 10325869 ps
CPU time 0.67 seconds
Started May 28 01:35:37 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 203976 kb
Host smart-0ed413b6-2935-4e85-9ec7-07c4c84d247a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947547446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.947547446
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1825994465
Short name T148
Test name
Test status
Simulation time 67616691 ps
CPU time 1.77 seconds
Started May 28 01:35:55 PM PDT 24
Finished May 28 01:35:58 PM PDT 24
Peak memory 215088 kb
Host smart-f4cb7933-1af0-423e-acd5-fffda989a8d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825994465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1825994465
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4176565993
Short name T1020
Test name
Test status
Simulation time 16260682 ps
CPU time 0.8 seconds
Started May 28 01:36:31 PM PDT 24
Finished May 28 01:36:36 PM PDT 24
Peak memory 204016 kb
Host smart-5f7c8018-d986-434c-be5c-212226a8df0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176565993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4176565993
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4212083755
Short name T1036
Test name
Test status
Simulation time 64672030 ps
CPU time 0.69 seconds
Started May 28 01:36:28 PM PDT 24
Finished May 28 01:36:32 PM PDT 24
Peak memory 203652 kb
Host smart-3d649c0d-d635-4af6-9a73-dcfd55ef94a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212083755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4212083755
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3901398123
Short name T988
Test name
Test status
Simulation time 23682660 ps
CPU time 0.74 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:33 PM PDT 24
Peak memory 203940 kb
Host smart-16f54264-545b-4331-897a-fa9995f9668b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901398123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3901398123
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1344569654
Short name T1003
Test name
Test status
Simulation time 23904319 ps
CPU time 0.75 seconds
Started May 28 01:36:27 PM PDT 24
Finished May 28 01:36:29 PM PDT 24
Peak memory 203752 kb
Host smart-a45c1635-0c3d-4dc7-9ac9-49ebba9a528d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344569654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1344569654
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2672534458
Short name T976
Test name
Test status
Simulation time 32724491 ps
CPU time 0.75 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:34 PM PDT 24
Peak memory 203768 kb
Host smart-4ad61577-8eea-4f0b-97d2-3f1fabf04d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672534458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2672534458
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.709865044
Short name T1088
Test name
Test status
Simulation time 31346093 ps
CPU time 0.7 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:34 PM PDT 24
Peak memory 204024 kb
Host smart-e5dce111-f236-4903-ba23-2814f9d48185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709865044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.709865044
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1102296552
Short name T994
Test name
Test status
Simulation time 24253464 ps
CPU time 0.67 seconds
Started May 28 01:36:28 PM PDT 24
Finished May 28 01:36:32 PM PDT 24
Peak memory 203964 kb
Host smart-78f0e487-452a-4693-9e15-fb7d8d6c0e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102296552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1102296552
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1925595239
Short name T986
Test name
Test status
Simulation time 42290361 ps
CPU time 0.73 seconds
Started May 28 01:36:26 PM PDT 24
Finished May 28 01:36:27 PM PDT 24
Peak memory 203976 kb
Host smart-feb4c186-2c2c-490e-a2f4-d3536d18e710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925595239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1925595239
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2200817753
Short name T978
Test name
Test status
Simulation time 27686335 ps
CPU time 0.71 seconds
Started May 28 01:36:28 PM PDT 24
Finished May 28 01:36:32 PM PDT 24
Peak memory 203624 kb
Host smart-2ee9a2a4-d7f5-41c4-b907-087b8de79cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200817753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2200817753
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1528624708
Short name T998
Test name
Test status
Simulation time 16401046 ps
CPU time 0.75 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 204020 kb
Host smart-4d551296-79f6-4a10-a524-ba359df84845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528624708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1528624708
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.735910638
Short name T1008
Test name
Test status
Simulation time 1256576340 ps
CPU time 21.94 seconds
Started May 28 01:35:51 PM PDT 24
Finished May 28 01:36:15 PM PDT 24
Peak memory 215560 kb
Host smart-3e6674f3-c9f1-42ba-aa55-9465422766c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735910638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.735910638
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.384011136
Short name T1098
Test name
Test status
Simulation time 702511615 ps
CPU time 23.27 seconds
Started May 28 01:35:52 PM PDT 24
Finished May 28 01:36:16 PM PDT 24
Peak memory 206948 kb
Host smart-f5f5e91f-c3b3-48cc-af45-5f9fd8fee4a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384011136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.384011136
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.778663083
Short name T1037
Test name
Test status
Simulation time 31033780 ps
CPU time 1.22 seconds
Started May 28 01:35:50 PM PDT 24
Finished May 28 01:35:52 PM PDT 24
Peak memory 207276 kb
Host smart-e0375780-e06d-4089-8a98-b41946ec8a29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778663083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.778663083
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1217925442
Short name T1076
Test name
Test status
Simulation time 129778529 ps
CPU time 3.53 seconds
Started May 28 01:35:58 PM PDT 24
Finished May 28 01:36:03 PM PDT 24
Peak memory 217124 kb
Host smart-eabdc370-d659-482d-94cb-3e56f659792a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217925442 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1217925442
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2140234051
Short name T114
Test name
Test status
Simulation time 325465574 ps
CPU time 2.37 seconds
Started May 28 01:35:49 PM PDT 24
Finished May 28 01:35:53 PM PDT 24
Peak memory 215428 kb
Host smart-ca003aa1-b6e3-467a-93a5-8e159a4c03fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140234051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
140234051
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3822815580
Short name T1097
Test name
Test status
Simulation time 15840914 ps
CPU time 0.73 seconds
Started May 28 01:35:55 PM PDT 24
Finished May 28 01:35:57 PM PDT 24
Peak memory 203176 kb
Host smart-9809c3cd-c3ce-4deb-be63-53a2a7fe7547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822815580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
822815580
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2564669311
Short name T115
Test name
Test status
Simulation time 329859967 ps
CPU time 1.99 seconds
Started May 28 01:35:48 PM PDT 24
Finished May 28 01:35:51 PM PDT 24
Peak memory 215496 kb
Host smart-246f25ee-004f-401d-b28c-a03ee13d50a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564669311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2564669311
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2433676080
Short name T1089
Test name
Test status
Simulation time 46126136 ps
CPU time 0.67 seconds
Started May 28 01:35:51 PM PDT 24
Finished May 28 01:35:53 PM PDT 24
Peak memory 203940 kb
Host smart-283b0b10-bc6d-4d6d-8992-8d97a6c69c86
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433676080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2433676080
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3876806607
Short name T1007
Test name
Test status
Simulation time 56633452 ps
CPU time 3.68 seconds
Started May 28 01:35:58 PM PDT 24
Finished May 28 01:36:03 PM PDT 24
Peak memory 215504 kb
Host smart-11018196-4417-4bc9-bcc3-cc18c41d06cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876806607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3876806607
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3535769337
Short name T1079
Test name
Test status
Simulation time 81486308 ps
CPU time 1.36 seconds
Started May 28 01:35:49 PM PDT 24
Finished May 28 01:35:51 PM PDT 24
Peak memory 207412 kb
Host smart-13ac137f-3742-4296-9184-63f2a6de1bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535769337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
535769337
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.95824248
Short name T1002
Test name
Test status
Simulation time 116837632 ps
CPU time 6.86 seconds
Started May 28 01:35:49 PM PDT 24
Finished May 28 01:35:57 PM PDT 24
Peak memory 215744 kb
Host smart-2f230129-876d-44ef-b2cc-b4fc2e363994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95824248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_t
l_intg_err.95824248
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3093875033
Short name T990
Test name
Test status
Simulation time 18169609 ps
CPU time 0.72 seconds
Started May 28 01:36:28 PM PDT 24
Finished May 28 01:36:33 PM PDT 24
Peak memory 204020 kb
Host smart-0f9878c5-d1ea-436f-a326-0fe2194018ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093875033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3093875033
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.945316152
Short name T977
Test name
Test status
Simulation time 30252710 ps
CPU time 0.73 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 203664 kb
Host smart-ae92c699-6894-4667-9137-f5a2671eacdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945316152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.945316152
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3553269602
Short name T1100
Test name
Test status
Simulation time 75316041 ps
CPU time 0.79 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:34 PM PDT 24
Peak memory 203632 kb
Host smart-ec27fdf9-2225-4a51-9479-f65b2ad28373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553269602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3553269602
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2861697881
Short name T1066
Test name
Test status
Simulation time 162396030 ps
CPU time 0.71 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:33 PM PDT 24
Peak memory 203628 kb
Host smart-5c218f97-9785-4f3a-9b44-12c587a97e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861697881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2861697881
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3517941245
Short name T992
Test name
Test status
Simulation time 53420873 ps
CPU time 0.73 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:33 PM PDT 24
Peak memory 203616 kb
Host smart-4e6fc147-0229-47fb-b767-66e6936fa511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517941245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3517941245
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4054427697
Short name T980
Test name
Test status
Simulation time 143682471 ps
CPU time 0.73 seconds
Started May 28 01:36:29 PM PDT 24
Finished May 28 01:36:33 PM PDT 24
Peak memory 203640 kb
Host smart-2764991c-5935-4ae0-bfa8-4e304457562f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054427697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4054427697
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1266225046
Short name T1027
Test name
Test status
Simulation time 12191794 ps
CPU time 0.73 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:35 PM PDT 24
Peak memory 204036 kb
Host smart-2fcf6d19-35a6-42a9-b996-185ea2e33e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266225046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1266225046
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3076257580
Short name T1069
Test name
Test status
Simulation time 89937313 ps
CPU time 0.75 seconds
Started May 28 01:36:28 PM PDT 24
Finished May 28 01:36:32 PM PDT 24
Peak memory 203680 kb
Host smart-edea024a-9c95-4073-8156-c6ff25041ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076257580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3076257580
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.700816404
Short name T1058
Test name
Test status
Simulation time 19187195 ps
CPU time 0.75 seconds
Started May 28 01:36:30 PM PDT 24
Finished May 28 01:36:34 PM PDT 24
Peak memory 203780 kb
Host smart-13194433-8cfa-400c-9cfd-73e0efb6e0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700816404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.700816404
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1640922905
Short name T1042
Test name
Test status
Simulation time 14587304 ps
CPU time 0.72 seconds
Started May 28 01:36:31 PM PDT 24
Finished May 28 01:36:36 PM PDT 24
Peak memory 204040 kb
Host smart-2c0b47cd-1808-411a-a50b-983802739529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640922905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1640922905
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2473608974
Short name T1047
Test name
Test status
Simulation time 53947325 ps
CPU time 1.83 seconds
Started May 28 01:35:50 PM PDT 24
Finished May 28 01:35:53 PM PDT 24
Peak memory 215884 kb
Host smart-c12e1baf-2a21-46ad-9b61-8b9d88efdc48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473608974 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2473608974
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4108904282
Short name T142
Test name
Test status
Simulation time 113540679 ps
CPU time 2.65 seconds
Started May 28 01:35:48 PM PDT 24
Finished May 28 01:35:52 PM PDT 24
Peak memory 215420 kb
Host smart-0dfa66aa-adab-4296-9729-fde9dd617aaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108904282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
108904282
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1028036701
Short name T989
Test name
Test status
Simulation time 32480242 ps
CPU time 0.71 seconds
Started May 28 01:35:51 PM PDT 24
Finished May 28 01:35:53 PM PDT 24
Peak memory 204044 kb
Host smart-db623281-c25f-4a3f-925b-520cf7332906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028036701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
028036701
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1050995160
Short name T143
Test name
Test status
Simulation time 155288996 ps
CPU time 1.96 seconds
Started May 28 01:35:52 PM PDT 24
Finished May 28 01:35:56 PM PDT 24
Peak memory 207308 kb
Host smart-009216d4-b26a-4470-ae94-3e9c510ca7ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050995160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1050995160
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2819727179
Short name T94
Test name
Test status
Simulation time 437465143 ps
CPU time 3.35 seconds
Started May 28 01:35:55 PM PDT 24
Finished May 28 01:36:00 PM PDT 24
Peak memory 215420 kb
Host smart-5b5cc0ec-c438-4f56-abc3-612365c3e96c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819727179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
819727179
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3168091757
Short name T144
Test name
Test status
Simulation time 336870020 ps
CPU time 8.41 seconds
Started May 28 01:35:53 PM PDT 24
Finished May 28 01:36:02 PM PDT 24
Peak memory 215488 kb
Host smart-229580b5-02e0-485f-af79-c56fcdfb1cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168091757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3168091757
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2198734203
Short name T1090
Test name
Test status
Simulation time 196328525 ps
CPU time 3.62 seconds
Started May 28 01:35:53 PM PDT 24
Finished May 28 01:35:58 PM PDT 24
Peak memory 217600 kb
Host smart-c0d00b82-4f04-4c67-a930-57061e44b435
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198734203 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2198734203
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3286941861
Short name T1051
Test name
Test status
Simulation time 94966448 ps
CPU time 1.88 seconds
Started May 28 01:35:59 PM PDT 24
Finished May 28 01:36:03 PM PDT 24
Peak memory 207260 kb
Host smart-0e1ef184-d266-4641-b17c-39e9fb8d2af4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286941861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
286941861
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1943728685
Short name T1018
Test name
Test status
Simulation time 46022380 ps
CPU time 0.7 seconds
Started May 28 01:35:52 PM PDT 24
Finished May 28 01:35:55 PM PDT 24
Peak memory 203672 kb
Host smart-61544831-99f4-44cd-865b-cbbe16053b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943728685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
943728685
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.658731002
Short name T1024
Test name
Test status
Simulation time 159755721 ps
CPU time 4.5 seconds
Started May 28 01:35:54 PM PDT 24
Finished May 28 01:36:00 PM PDT 24
Peak memory 215452 kb
Host smart-692eccef-74fc-4e35-99a5-b4eae65073a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658731002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.658731002
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.415174857
Short name T107
Test name
Test status
Simulation time 22871797 ps
CPU time 1.59 seconds
Started May 28 01:35:56 PM PDT 24
Finished May 28 01:35:59 PM PDT 24
Peak memory 215408 kb
Host smart-c0a994fe-5ce6-4b04-8276-98a6e6ebf25f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415174857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.415174857
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1102362356
Short name T1021
Test name
Test status
Simulation time 89726278 ps
CPU time 2.64 seconds
Started May 28 01:35:54 PM PDT 24
Finished May 28 01:35:58 PM PDT 24
Peak memory 216724 kb
Host smart-be74dcd3-4071-490e-8f10-ea3f9d20049d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102362356 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1102362356
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.233605470
Short name T1009
Test name
Test status
Simulation time 716357709 ps
CPU time 2.85 seconds
Started May 28 01:35:52 PM PDT 24
Finished May 28 01:35:56 PM PDT 24
Peak memory 207220 kb
Host smart-0393dc06-4fff-4e13-84f6-05c6543e5333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233605470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.233605470
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3180931376
Short name T1022
Test name
Test status
Simulation time 25497057 ps
CPU time 0.72 seconds
Started May 28 01:35:53 PM PDT 24
Finished May 28 01:35:55 PM PDT 24
Peak memory 204028 kb
Host smart-a9eb95f5-56e2-4d43-8f10-694fd0605efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180931376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
180931376
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4168499668
Short name T1043
Test name
Test status
Simulation time 248924654 ps
CPU time 1.72 seconds
Started May 28 01:35:50 PM PDT 24
Finished May 28 01:35:53 PM PDT 24
Peak memory 215576 kb
Host smart-834c2871-ecbd-4422-8204-f74a01d706ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168499668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4168499668
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1929739343
Short name T1029
Test name
Test status
Simulation time 213960022 ps
CPU time 4.57 seconds
Started May 28 01:35:48 PM PDT 24
Finished May 28 01:35:53 PM PDT 24
Peak memory 215508 kb
Host smart-5948bc91-91d6-47de-964b-f8b394ea456d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929739343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
929739343
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2649017003
Short name T106
Test name
Test status
Simulation time 416464260 ps
CPU time 13.18 seconds
Started May 28 01:35:50 PM PDT 24
Finished May 28 01:36:04 PM PDT 24
Peak memory 215448 kb
Host smart-e8021125-dab2-4b8f-9935-fa4eb246976e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649017003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2649017003
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3421200308
Short name T1074
Test name
Test status
Simulation time 87869259 ps
CPU time 2.47 seconds
Started May 28 01:35:59 PM PDT 24
Finished May 28 01:36:03 PM PDT 24
Peak memory 216660 kb
Host smart-046bb2e9-33eb-4be4-81ec-a2a002ec587b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421200308 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3421200308
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.20631960
Short name T1073
Test name
Test status
Simulation time 145707398 ps
CPU time 2.22 seconds
Started May 28 01:35:58 PM PDT 24
Finished May 28 01:36:01 PM PDT 24
Peak memory 215444 kb
Host smart-af596ca0-4286-42fe-9644-900b82101fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20631960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.20631960
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1423186919
Short name T993
Test name
Test status
Simulation time 19064414 ps
CPU time 0.77 seconds
Started May 28 01:35:50 PM PDT 24
Finished May 28 01:35:52 PM PDT 24
Peak memory 203700 kb
Host smart-83aa4ab2-1080-4158-bd85-0d7c492d45e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423186919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
423186919
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.162079424
Short name T1000
Test name
Test status
Simulation time 25717151 ps
CPU time 1.67 seconds
Started May 28 01:35:52 PM PDT 24
Finished May 28 01:35:56 PM PDT 24
Peak memory 207140 kb
Host smart-ab625a0b-549d-476f-820f-64f5655f7c55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162079424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.162079424
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.594042696
Short name T1057
Test name
Test status
Simulation time 93003527 ps
CPU time 2.28 seconds
Started May 28 01:35:54 PM PDT 24
Finished May 28 01:35:58 PM PDT 24
Peak memory 215608 kb
Host smart-cd14f6d6-bdcd-41a3-98b8-21d79950868d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594042696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.594042696
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3532353840
Short name T104
Test name
Test status
Simulation time 499647661 ps
CPU time 12.44 seconds
Started May 28 01:35:50 PM PDT 24
Finished May 28 01:36:04 PM PDT 24
Peak memory 215500 kb
Host smart-bc8bc1ba-343e-480e-acf3-c7de4f3e0148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532353840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3532353840
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2856070873
Short name T1059
Test name
Test status
Simulation time 25002433 ps
CPU time 1.78 seconds
Started May 28 01:36:06 PM PDT 24
Finished May 28 01:36:09 PM PDT 24
Peak memory 215472 kb
Host smart-0435dcd0-3953-4a04-88ea-85e0836cb05a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856070873 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2856070873
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3942099236
Short name T1083
Test name
Test status
Simulation time 466650080 ps
CPU time 1.87 seconds
Started May 28 01:36:00 PM PDT 24
Finished May 28 01:36:05 PM PDT 24
Peak memory 207260 kb
Host smart-45e78e5b-e592-46a1-8e68-34820edf4eb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942099236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
942099236
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4096442712
Short name T1034
Test name
Test status
Simulation time 51908152 ps
CPU time 0.75 seconds
Started May 28 01:35:58 PM PDT 24
Finished May 28 01:36:00 PM PDT 24
Peak memory 203996 kb
Host smart-6860c256-dc68-4dc6-8eac-1b0352a8c1eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096442712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
096442712
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.315250349
Short name T147
Test name
Test status
Simulation time 1021957070 ps
CPU time 4.55 seconds
Started May 28 01:36:00 PM PDT 24
Finished May 28 01:36:08 PM PDT 24
Peak memory 215516 kb
Host smart-6baf09d0-742e-40ac-b158-30da94bb8703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315250349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.315250349
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3691474155
Short name T1041
Test name
Test status
Simulation time 157324605 ps
CPU time 3.69 seconds
Started May 28 01:35:53 PM PDT 24
Finished May 28 01:35:58 PM PDT 24
Peak memory 215588 kb
Host smart-b94e1b0a-202b-419d-9c2b-3746e9a53729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691474155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
691474155
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2315972405
Short name T1065
Test name
Test status
Simulation time 585326320 ps
CPU time 18.6 seconds
Started May 28 01:35:52 PM PDT 24
Finished May 28 01:36:12 PM PDT 24
Peak memory 216176 kb
Host smart-885f299d-14ea-45a3-ba6d-715e385f310d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315972405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2315972405
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1305450967
Short name T812
Test name
Test status
Simulation time 84341013 ps
CPU time 0.72 seconds
Started May 28 02:44:08 PM PDT 24
Finished May 28 02:44:09 PM PDT 24
Peak memory 204296 kb
Host smart-b1cca6db-39c3-4cb7-b2d6-f9d005d2136a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305450967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
305450967
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.688971105
Short name T824
Test name
Test status
Simulation time 703500817 ps
CPU time 5.19 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:44:20 PM PDT 24
Peak memory 217908 kb
Host smart-e36531b8-b01a-48f9-b6ce-f161d32a6837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688971105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.688971105
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2567848871
Short name T381
Test name
Test status
Simulation time 163042888 ps
CPU time 0.76 seconds
Started May 28 02:44:13 PM PDT 24
Finished May 28 02:44:16 PM PDT 24
Peak memory 204908 kb
Host smart-d98bf52d-cc75-494f-bf00-979d3497c563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567848871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2567848871
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1466702095
Short name T881
Test name
Test status
Simulation time 8434423262 ps
CPU time 54.81 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:56 PM PDT 24
Peak memory 256768 kb
Host smart-df477aa9-2cc3-493a-91a8-c1dc4a47281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466702095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1466702095
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.983518790
Short name T337
Test name
Test status
Simulation time 22642861 ps
CPU time 0.85 seconds
Started May 28 02:43:57 PM PDT 24
Finished May 28 02:43:59 PM PDT 24
Peak memory 216344 kb
Host smart-db55d768-644d-4005-b9b0-33e955810523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983518790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
983518790
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2835230508
Short name T801
Test name
Test status
Simulation time 9848787194 ps
CPU time 29.82 seconds
Started May 28 02:44:09 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 234752 kb
Host smart-af8f585b-2cdc-4789-aff8-343a8d8f233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835230508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2835230508
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2883290525
Short name T743
Test name
Test status
Simulation time 7181426959 ps
CPU time 15.47 seconds
Started May 28 02:43:58 PM PDT 24
Finished May 28 02:44:16 PM PDT 24
Peak memory 233952 kb
Host smart-b2e1d443-73fb-4da2-a556-e39947424c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883290525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2883290525
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2607295966
Short name T260
Test name
Test status
Simulation time 4634744787 ps
CPU time 44.69 seconds
Started May 28 02:44:00 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 224016 kb
Host smart-eb98d7ec-8079-4ae6-9368-5e71b7ccf70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607295966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2607295966
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.644965591
Short name T631
Test name
Test status
Simulation time 249424597 ps
CPU time 1.08 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:44:16 PM PDT 24
Peak memory 216192 kb
Host smart-c9717e78-37e5-4ab4-897d-9c38f35f67af
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644965591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.644965591
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1608010360
Short name T367
Test name
Test status
Simulation time 294702220 ps
CPU time 3.17 seconds
Started May 28 02:44:09 PM PDT 24
Finished May 28 02:44:13 PM PDT 24
Peak memory 233296 kb
Host smart-37830482-fea1-457f-b3ab-736a57722f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608010360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1608010360
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3216540304
Short name T603
Test name
Test status
Simulation time 171808962 ps
CPU time 2.62 seconds
Started May 28 02:44:00 PM PDT 24
Finished May 28 02:44:04 PM PDT 24
Peak memory 218412 kb
Host smart-d42fc84f-ef6f-414f-a8cd-754013309f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216540304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3216540304
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2817412650
Short name T595
Test name
Test status
Simulation time 6166206448 ps
CPU time 12.31 seconds
Started May 28 02:44:11 PM PDT 24
Finished May 28 02:44:25 PM PDT 24
Peak memory 222572 kb
Host smart-5c4236a0-2c05-4757-bcaf-d5dfa2793960
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2817412650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2817412650
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2149307841
Short name T826
Test name
Test status
Simulation time 8392132971 ps
CPU time 15.17 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:16 PM PDT 24
Peak memory 215712 kb
Host smart-28959dcb-689d-40c7-a8a6-71ef122b40cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149307841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2149307841
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3601010257
Short name T380
Test name
Test status
Simulation time 684296179 ps
CPU time 5.07 seconds
Started May 28 02:44:00 PM PDT 24
Finished May 28 02:44:07 PM PDT 24
Peak memory 215836 kb
Host smart-5b5d45ba-80c3-4b27-8fd0-36df40e05250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601010257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3601010257
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3992742305
Short name T621
Test name
Test status
Simulation time 683487457 ps
CPU time 1.34 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:02 PM PDT 24
Peak memory 215960 kb
Host smart-a2ca63f1-0a3e-4d36-a14d-f49ff7d3b970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992742305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3992742305
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2039239032
Short name T81
Test name
Test status
Simulation time 93235204 ps
CPU time 0.76 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:02 PM PDT 24
Peak memory 205320 kb
Host smart-ac6c2722-ba56-404e-9d42-02a420b958dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039239032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2039239032
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.404390687
Short name T261
Test name
Test status
Simulation time 2226694500 ps
CPU time 2.48 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:33 PM PDT 24
Peak memory 218828 kb
Host smart-e6260433-698d-449b-a614-a0c264e9d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404390687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.404390687
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.888677771
Short name T611
Test name
Test status
Simulation time 13732983 ps
CPU time 0.69 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:33 PM PDT 24
Peak memory 204932 kb
Host smart-f9f58802-4b6d-4660-95af-25e8316d8a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888677771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.888677771
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4143915901
Short name T513
Test name
Test status
Simulation time 266997395 ps
CPU time 4 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:05 PM PDT 24
Peak memory 233004 kb
Host smart-6b0f1916-be75-49b5-9f7a-246032f39797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143915901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4143915901
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2312218588
Short name T433
Test name
Test status
Simulation time 37392062 ps
CPU time 0.79 seconds
Started May 28 02:43:58 PM PDT 24
Finished May 28 02:44:01 PM PDT 24
Peak memory 206268 kb
Host smart-0b6d728b-0293-4cdd-99cb-d9a3ae0af269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312218588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2312218588
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1496033394
Short name T806
Test name
Test status
Simulation time 66468704493 ps
CPU time 201.28 seconds
Started May 28 02:44:06 PM PDT 24
Finished May 28 02:47:28 PM PDT 24
Peak memory 249100 kb
Host smart-a8e4a810-cd64-4dc2-af06-ee70c4cb72af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496033394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1496033394
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.4258289498
Short name T36
Test name
Test status
Simulation time 18530952022 ps
CPU time 76.11 seconds
Started May 28 02:44:18 PM PDT 24
Finished May 28 02:45:38 PM PDT 24
Peak memory 251612 kb
Host smart-2efc93e5-44c2-4282-9908-ff1f7f8c8681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258289498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.4258289498
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.4144943619
Short name T168
Test name
Test status
Simulation time 65246060137 ps
CPU time 155.66 seconds
Started May 28 02:44:17 PM PDT 24
Finished May 28 02:46:56 PM PDT 24
Peak memory 256808 kb
Host smart-eeaedb8e-b8fc-4051-9b6a-729b19cfd407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144943619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.4144943619
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1256178109
Short name T657
Test name
Test status
Simulation time 831359883 ps
CPU time 20.74 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:44:36 PM PDT 24
Peak memory 233404 kb
Host smart-31f45936-2059-476e-9fee-1f978f514ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256178109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1256178109
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2981374077
Short name T736
Test name
Test status
Simulation time 5165650421 ps
CPU time 14.05 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:15 PM PDT 24
Peak memory 237456 kb
Host smart-a193535b-01b5-4f56-8efd-7bba685e0212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981374077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2981374077
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3732547922
Short name T419
Test name
Test status
Simulation time 108947606 ps
CPU time 2.29 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:04 PM PDT 24
Peak memory 220700 kb
Host smart-65645a07-c42c-4db8-9e59-a9bd572c3c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732547922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3732547922
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4244350834
Short name T670
Test name
Test status
Simulation time 34663849 ps
CPU time 1.1 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:02 PM PDT 24
Peak memory 216208 kb
Host smart-6ba2231d-1547-4412-9767-f2cc6e4c5e46
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244350834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4244350834
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1042098063
Short name T557
Test name
Test status
Simulation time 3097271324 ps
CPU time 8.38 seconds
Started May 28 02:44:00 PM PDT 24
Finished May 28 02:44:10 PM PDT 24
Peak memory 220500 kb
Host smart-b432241f-ac49-42b5-a1ca-4ad87e6a7fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042098063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1042098063
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3630297543
Short name T969
Test name
Test status
Simulation time 99754069 ps
CPU time 2.66 seconds
Started May 28 02:44:08 PM PDT 24
Finished May 28 02:44:11 PM PDT 24
Peak memory 233508 kb
Host smart-b36cb7af-68cd-44b9-ac20-9c65d0b20e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630297543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3630297543
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2225581078
Short name T468
Test name
Test status
Simulation time 151893074 ps
CPU time 4.64 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:39 PM PDT 24
Peak memory 222540 kb
Host smart-88d454d9-d897-42d1-9010-1a5ae3d2a996
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2225581078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2225581078
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.702909386
Short name T62
Test name
Test status
Simulation time 68622549 ps
CPU time 0.93 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:37 PM PDT 24
Peak memory 234616 kb
Host smart-db2eb56a-af4c-4908-b915-b4a0fe46d118
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702909386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.702909386
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1538757662
Short name T79
Test name
Test status
Simulation time 810762923 ps
CPU time 5.35 seconds
Started May 28 02:43:59 PM PDT 24
Finished May 28 02:44:06 PM PDT 24
Peak memory 215772 kb
Host smart-1a51e479-1752-47fa-ab11-d86e760ff16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538757662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1538757662
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2894303537
Short name T546
Test name
Test status
Simulation time 678786432 ps
CPU time 2.7 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:44:17 PM PDT 24
Peak memory 215900 kb
Host smart-c1b332bf-7ea4-4edb-a7f4-86e54d033ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894303537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2894303537
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2926430250
Short name T408
Test name
Test status
Simulation time 52341767 ps
CPU time 0.84 seconds
Started May 28 02:43:57 PM PDT 24
Finished May 28 02:43:59 PM PDT 24
Peak memory 205304 kb
Host smart-0849e97b-27c0-425f-b3be-bf969ca4dfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926430250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2926430250
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3104952352
Short name T234
Test name
Test status
Simulation time 6703940301 ps
CPU time 14.79 seconds
Started May 28 02:44:07 PM PDT 24
Finished May 28 02:44:23 PM PDT 24
Peak memory 233504 kb
Host smart-7d49f76e-1168-4efe-951e-05a1237f95cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104952352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3104952352
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3630489226
Short name T620
Test name
Test status
Simulation time 389615239 ps
CPU time 3.46 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:43 PM PDT 24
Peak memory 233452 kb
Host smart-8193ae3c-d3fd-4410-ad12-9be821f3b80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630489226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3630489226
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1552588286
Short name T585
Test name
Test status
Simulation time 12950750 ps
CPU time 0.71 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:37 PM PDT 24
Peak memory 204896 kb
Host smart-d7c7db7c-fbc9-4dc1-9404-4780d691b663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552588286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1552588286
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1706445403
Short name T610
Test name
Test status
Simulation time 4132282497 ps
CPU time 43.85 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:45:32 PM PDT 24
Peak memory 253328 kb
Host smart-83f2de39-2abe-493c-b9f8-eda16444740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706445403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1706445403
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2225977604
Short name T903
Test name
Test status
Simulation time 20088915932 ps
CPU time 150.08 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:47:19 PM PDT 24
Peak memory 240436 kb
Host smart-299168da-15f8-4c76-8cf8-801c0ee05340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225977604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2225977604
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4052928431
Short name T217
Test name
Test status
Simulation time 14938387818 ps
CPU time 112.58 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:46:39 PM PDT 24
Peak memory 224304 kb
Host smart-c2463be8-3f71-42a0-9c5e-98fe2d70dee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052928431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4052928431
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2250629
Short name T307
Test name
Test status
Simulation time 8761658298 ps
CPU time 51.55 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:45:32 PM PDT 24
Peak memory 240632 kb
Host smart-63fa6beb-3e8b-4c93-8a72-b16181380977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2250629
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3802629446
Short name T651
Test name
Test status
Simulation time 3129841278 ps
CPU time 37.68 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 219240 kb
Host smart-7bdb06a2-5a83-4e77-95e5-a17cb75d7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802629446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3802629446
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2645597543
Short name T637
Test name
Test status
Simulation time 1424232928 ps
CPU time 17.21 seconds
Started May 28 02:44:31 PM PDT 24
Finished May 28 02:45:06 PM PDT 24
Peak memory 231172 kb
Host smart-65c5de5b-5771-49ea-9a7c-2f37347c72c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645597543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2645597543
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.549076800
Short name T561
Test name
Test status
Simulation time 15783214458 ps
CPU time 12.96 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 222576 kb
Host smart-8e40d7e5-a98b-46a0-bf79-fe6b8aad682f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549076800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.549076800
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.394525029
Short name T925
Test name
Test status
Simulation time 515245879 ps
CPU time 3.62 seconds
Started May 28 02:44:30 PM PDT 24
Finished May 28 02:44:45 PM PDT 24
Peak memory 234104 kb
Host smart-0a668ad8-b5a2-433c-ab7d-88d002ccf671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394525029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.394525029
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3601801646
Short name T659
Test name
Test status
Simulation time 303838541 ps
CPU time 5.68 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 221528 kb
Host smart-9bb6cb48-01db-4a72-b2bf-4fb37b1610cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3601801646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3601801646
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4293467625
Short name T971
Test name
Test status
Simulation time 736963841 ps
CPU time 6.26 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:50 PM PDT 24
Peak memory 218636 kb
Host smart-51e1b9e7-84d6-4445-8f28-67c4e736291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293467625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4293467625
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3417051885
Short name T331
Test name
Test status
Simulation time 914023159 ps
CPU time 5.01 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:49 PM PDT 24
Peak memory 215876 kb
Host smart-1c18cac7-7d7a-476a-939b-c15d3b1c0dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417051885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3417051885
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4000061879
Short name T492
Test name
Test status
Simulation time 60849711 ps
CPU time 1.06 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:44:41 PM PDT 24
Peak memory 206960 kb
Host smart-0e03c811-3bb1-47ac-8488-9bb9c08ae026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000061879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4000061879
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1252514091
Short name T786
Test name
Test status
Simulation time 41361081 ps
CPU time 0.76 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 205312 kb
Host smart-b260793d-e1c6-4572-8d63-f8d0ada4a5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252514091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1252514091
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1834495226
Short name T330
Test name
Test status
Simulation time 1030729355 ps
CPU time 9.14 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:44 PM PDT 24
Peak memory 238568 kb
Host smart-3e7cfb5d-765a-4002-be4e-a2ef4d462245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834495226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1834495226
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3079452189
Short name T784
Test name
Test status
Simulation time 175598261 ps
CPU time 0.72 seconds
Started May 28 02:44:43 PM PDT 24
Finished May 28 02:44:54 PM PDT 24
Peak memory 204932 kb
Host smart-015c96c5-dbf1-4bf5-aeae-4a2590279469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079452189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3079452189
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4089185889
Short name T854
Test name
Test status
Simulation time 329137413 ps
CPU time 3.4 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:44:44 PM PDT 24
Peak memory 219292 kb
Host smart-fb548b8e-c8ea-45c6-beca-8b74127e4be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089185889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4089185889
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.123190346
Short name T163
Test name
Test status
Simulation time 366319269 ps
CPU time 0.78 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:39 PM PDT 24
Peak memory 205928 kb
Host smart-b9bbfd9a-8685-428c-9407-55731f5dc3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123190346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.123190346
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2277101110
Short name T593
Test name
Test status
Simulation time 18097148 ps
CPU time 0.76 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:45 PM PDT 24
Peak memory 215428 kb
Host smart-d61a0227-8275-4cc8-b5a7-fc53a59ee661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277101110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2277101110
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2876134567
Short name T645
Test name
Test status
Simulation time 20698621323 ps
CPU time 90.88 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:46:20 PM PDT 24
Peak memory 232460 kb
Host smart-54e43683-a0fe-4338-96a3-aa85f2ae1a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876134567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2876134567
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.972598957
Short name T22
Test name
Test status
Simulation time 105082288708 ps
CPU time 237.83 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:48:47 PM PDT 24
Peak memory 255368 kb
Host smart-d824e9c5-d09a-4665-963f-370322fb9800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972598957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.972598957
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2763122267
Short name T897
Test name
Test status
Simulation time 1097153357 ps
CPU time 6.32 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:46 PM PDT 24
Peak memory 224208 kb
Host smart-a3ca038a-824f-40c7-a6d7-50061b2cb6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763122267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2763122267
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.324847815
Short name T540
Test name
Test status
Simulation time 3662583128 ps
CPU time 10.87 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:44:58 PM PDT 24
Peak memory 217528 kb
Host smart-e6d84d26-05f1-4f99-a3ef-7400432b20ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324847815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.324847815
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2061535371
Short name T772
Test name
Test status
Simulation time 169924890 ps
CPU time 5.31 seconds
Started May 28 02:44:31 PM PDT 24
Finished May 28 02:44:48 PM PDT 24
Peak memory 235108 kb
Host smart-ad826513-48a2-4a9c-9e72-edb1818e3606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061535371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2061535371
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.917475238
Short name T667
Test name
Test status
Simulation time 24917145 ps
CPU time 1.01 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:35 PM PDT 24
Peak memory 217464 kb
Host smart-8bc47a2a-5366-435c-8704-7f4258979008
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917475238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.917475238
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.226664196
Short name T787
Test name
Test status
Simulation time 21352739598 ps
CPU time 10.08 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 219532 kb
Host smart-6c48e16a-79a6-4712-84be-72b8380cd953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226664196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.226664196
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3546419420
Short name T964
Test name
Test status
Simulation time 682227600 ps
CPU time 5.39 seconds
Started May 28 02:44:27 PM PDT 24
Finished May 28 02:44:43 PM PDT 24
Peak memory 218208 kb
Host smart-b495fda7-8577-49ff-8006-e85bf246b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546419420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3546419420
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1118695330
Short name T555
Test name
Test status
Simulation time 1410631573 ps
CPU time 12.47 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 220260 kb
Host smart-217dfb31-3dfe-4fa9-8aa7-973a3ef09c11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1118695330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1118695330
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4121061524
Short name T763
Test name
Test status
Simulation time 98877562 ps
CPU time 0.95 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:45 PM PDT 24
Peak memory 206348 kb
Host smart-7719eaf5-6cdd-4502-b190-c8b61f81572c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121061524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4121061524
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1292904760
Short name T313
Test name
Test status
Simulation time 2753059427 ps
CPU time 10.48 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:44:56 PM PDT 24
Peak memory 216128 kb
Host smart-9a41e311-1ede-4a0a-bc90-c65078a09125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292904760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1292904760
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1271494201
Short name T382
Test name
Test status
Simulation time 8326485052 ps
CPU time 8.56 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 215932 kb
Host smart-cbe09e1a-beeb-4551-9575-03c9d45ff65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271494201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1271494201
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1247802977
Short name T35
Test name
Test status
Simulation time 170720407 ps
CPU time 1.08 seconds
Started May 28 02:44:41 PM PDT 24
Finished May 28 02:44:53 PM PDT 24
Peak memory 206804 kb
Host smart-433dbd8f-b74c-4f5e-9d41-50052a6e700e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247802977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1247802977
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2824353397
Short name T68
Test name
Test status
Simulation time 50513673 ps
CPU time 0.82 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 205300 kb
Host smart-a5d32919-731c-4738-9e00-55bcfce5bd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824353397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2824353397
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3326185546
Short name T644
Test name
Test status
Simulation time 2844408645 ps
CPU time 6.4 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:44:48 PM PDT 24
Peak memory 225856 kb
Host smart-17c1d481-0906-4612-8025-01445a02581c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326185546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3326185546
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1639086997
Short name T952
Test name
Test status
Simulation time 13372023 ps
CPU time 0.77 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 205276 kb
Host smart-e61e1c02-1045-4f77-9dee-9d506748908f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639086997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1639086997
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1398029988
Short name T242
Test name
Test status
Simulation time 1149815436 ps
CPU time 6.46 seconds
Started May 28 02:44:31 PM PDT 24
Finished May 28 02:44:49 PM PDT 24
Peak memory 218512 kb
Host smart-ad657539-1e8f-4e90-bba0-6a9501178307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398029988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1398029988
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3872858391
Short name T745
Test name
Test status
Simulation time 70910734 ps
CPU time 0.82 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 206252 kb
Host smart-dc1f574f-d620-4e33-b9aa-0ff6055bcb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872858391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3872858391
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2928204890
Short name T839
Test name
Test status
Simulation time 4902208446 ps
CPU time 49.52 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:45:37 PM PDT 24
Peak memory 248804 kb
Host smart-1261f501-ef80-4364-a8a6-317162990913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928204890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2928204890
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.526465486
Short name T181
Test name
Test status
Simulation time 6591600830 ps
CPU time 107.89 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:46:34 PM PDT 24
Peak memory 261376 kb
Host smart-48434912-b5cf-4235-8443-2946af582657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526465486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.526465486
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1453664167
Short name T828
Test name
Test status
Simulation time 4315373460 ps
CPU time 19.75 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:45:08 PM PDT 24
Peak memory 240600 kb
Host smart-de00a686-7d79-413c-a098-2e9ddce0fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453664167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1453664167
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.189296180
Short name T948
Test name
Test status
Simulation time 320262139 ps
CPU time 5.92 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 224148 kb
Host smart-4af50bf4-659d-4093-8d61-1fc5792cc2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189296180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.189296180
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2015803407
Short name T869
Test name
Test status
Simulation time 15284605726 ps
CPU time 82.49 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 233996 kb
Host smart-86f822ea-646d-41d7-8043-02fdcdd8b1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015803407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2015803407
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1509574981
Short name T584
Test name
Test status
Simulation time 26354057 ps
CPU time 1.06 seconds
Started May 28 02:44:36 PM PDT 24
Finished May 28 02:44:50 PM PDT 24
Peak memory 216272 kb
Host smart-ddd36290-64e2-47af-a023-5c9b08eca7fb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509574981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1509574981
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2123110546
Short name T819
Test name
Test status
Simulation time 24044719847 ps
CPU time 19.36 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:45:05 PM PDT 24
Peak memory 233976 kb
Host smart-f788a79f-6167-4a0b-8c95-0f4cb245a97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123110546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2123110546
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2740242341
Short name T271
Test name
Test status
Simulation time 38070616790 ps
CPU time 28.46 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:45:18 PM PDT 24
Peak memory 236780 kb
Host smart-f59f5bba-ba16-4a20-9fc9-871176cff562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740242341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2740242341
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2637481368
Short name T865
Test name
Test status
Simulation time 5218566490 ps
CPU time 9.95 seconds
Started May 28 02:44:30 PM PDT 24
Finished May 28 02:44:52 PM PDT 24
Peak memory 220136 kb
Host smart-fc6c95ef-a536-4d88-9003-a1e97cd96403
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2637481368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2637481368
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1089602005
Short name T718
Test name
Test status
Simulation time 74780084 ps
CPU time 1.14 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 206208 kb
Host smart-1113ab26-f4fe-42e0-897b-1d7fb656f563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089602005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1089602005
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1303977852
Short name T158
Test name
Test status
Simulation time 15049582846 ps
CPU time 24.04 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:45:10 PM PDT 24
Peak memory 216220 kb
Host smart-05b3af23-e77e-4af7-b018-e0da70ebbf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303977852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1303977852
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1175736706
Short name T616
Test name
Test status
Simulation time 2523487037 ps
CPU time 7.53 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 215824 kb
Host smart-2554b54f-81e6-40b4-95ce-1bb005401969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175736706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1175736706
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.379578452
Short name T487
Test name
Test status
Simulation time 80612496 ps
CPU time 1.65 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:45 PM PDT 24
Peak memory 215988 kb
Host smart-126238b5-da6f-4cb9-81b0-167e98a1e439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379578452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.379578452
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.360245655
Short name T618
Test name
Test status
Simulation time 176606656 ps
CPU time 0.9 seconds
Started May 28 02:44:31 PM PDT 24
Finished May 28 02:44:44 PM PDT 24
Peak memory 206276 kb
Host smart-ac4d640a-9e42-4f8e-8561-02c19b441744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360245655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.360245655
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2170541898
Short name T774
Test name
Test status
Simulation time 2667357078 ps
CPU time 2.74 seconds
Started May 28 02:44:36 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 218392 kb
Host smart-17799063-e9c7-4048-ad4a-2a86a39efe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170541898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2170541898
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3251189919
Short name T797
Test name
Test status
Simulation time 12342283 ps
CPU time 0.71 seconds
Started May 28 02:44:56 PM PDT 24
Finished May 28 02:45:02 PM PDT 24
Peak memory 204940 kb
Host smart-543a4f42-5a4d-49ab-bd7f-d60be7f2e06b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251189919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3251189919
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1658381367
Short name T407
Test name
Test status
Simulation time 408607604 ps
CPU time 4.31 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 233224 kb
Host smart-b8a361c7-53e7-430c-bafa-2de0b8ea9c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658381367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1658381367
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2376735323
Short name T937
Test name
Test status
Simulation time 39883188 ps
CPU time 0.78 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:52 PM PDT 24
Peak memory 206228 kb
Host smart-dae1e28d-5189-4efe-917e-1ee5af5b020c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376735323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2376735323
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2978868321
Short name T716
Test name
Test status
Simulation time 321054765 ps
CPU time 7.26 seconds
Started May 28 02:44:31 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 232356 kb
Host smart-2b3ba77d-dba7-456c-bb7a-d4b05d8112ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978868321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2978868321
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2336949804
Short name T187
Test name
Test status
Simulation time 15005856869 ps
CPU time 54.77 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:45:43 PM PDT 24
Peak memory 250920 kb
Host smart-7109d234-bcea-4678-b76d-767fe26d9fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336949804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2336949804
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3003881534
Short name T323
Test name
Test status
Simulation time 482927462 ps
CPU time 7.3 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 224168 kb
Host smart-a61909d2-af2b-49d9-bfc9-87fdb032f6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003881534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3003881534
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1231130118
Short name T178
Test name
Test status
Simulation time 193842956 ps
CPU time 4.17 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:54 PM PDT 24
Peak memory 224132 kb
Host smart-36d8ff2f-fac7-492b-92de-5ecacb4b60b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231130118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1231130118
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4137811512
Short name T587
Test name
Test status
Simulation time 110866422 ps
CPU time 2.34 seconds
Started May 28 02:44:36 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 220768 kb
Host smart-6b3ac53a-70bd-44cc-8713-56b3db7c0bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137811512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4137811512
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3846331612
Short name T808
Test name
Test status
Simulation time 13919438 ps
CPU time 0.95 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 217412 kb
Host smart-97191f2b-35fd-4f09-b8f7-f87618fb682a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846331612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3846331612
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.830796189
Short name T519
Test name
Test status
Simulation time 2844740821 ps
CPU time 4.12 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 233252 kb
Host smart-fc2555f0-a186-45f4-8372-4c07bc3d3227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830796189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.830796189
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.318038466
Short name T788
Test name
Test status
Simulation time 18259110779 ps
CPU time 13.29 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:45:03 PM PDT 24
Peak memory 219220 kb
Host smart-997fb88d-b536-4acf-a3d5-2994bd427204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318038466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.318038466
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.895170591
Short name T687
Test name
Test status
Simulation time 6834360064 ps
CPU time 12.52 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:45:11 PM PDT 24
Peak memory 222524 kb
Host smart-fd724da6-f797-416a-8480-8c98382efaea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=895170591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.895170591
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2826647741
Short name T919
Test name
Test status
Simulation time 9002338479 ps
CPU time 15.26 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:45:00 PM PDT 24
Peak memory 215976 kb
Host smart-217318e8-c5a4-4b1f-8c99-28269ac5d0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826647741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2826647741
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2398905873
Short name T49
Test name
Test status
Simulation time 717294518 ps
CPU time 2.05 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 207332 kb
Host smart-70171a31-1939-4970-a4f5-2a9dceb0995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398905873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2398905873
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.564706657
Short name T348
Test name
Test status
Simulation time 20448396 ps
CPU time 0.69 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:44:46 PM PDT 24
Peak memory 205320 kb
Host smart-6e6bf717-367f-4896-a701-7a3498574a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564706657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.564706657
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3462063369
Short name T19
Test name
Test status
Simulation time 14012502 ps
CPU time 0.68 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 205328 kb
Host smart-8239f111-fe90-4233-a87c-7feec7fa04f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462063369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3462063369
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3851537548
Short name T906
Test name
Test status
Simulation time 262352378 ps
CPU time 6.04 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 238164 kb
Host smart-6c76b0ec-7738-4dc5-99b0-cf0ee87caefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851537548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3851537548
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.329119439
Short name T53
Test name
Test status
Simulation time 55476199 ps
CPU time 0.71 seconds
Started May 28 02:44:36 PM PDT 24
Finished May 28 02:44:49 PM PDT 24
Peak memory 204928 kb
Host smart-b80275a3-48d8-44cc-b5cd-d90a90646724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329119439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.329119439
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3254699763
Short name T874
Test name
Test status
Simulation time 1040336092 ps
CPU time 3.3 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:45:06 PM PDT 24
Peak memory 218380 kb
Host smart-7a2603d5-de97-4673-9937-052147b66447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254699763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3254699763
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.258169446
Short name T503
Test name
Test status
Simulation time 13415323 ps
CPU time 0.75 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:50 PM PDT 24
Peak memory 206292 kb
Host smart-ec3821f8-acf4-4dfd-86de-1e5cb14cda3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258169446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.258169446
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1442624317
Short name T26
Test name
Test status
Simulation time 198725083962 ps
CPU time 377.29 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 248832 kb
Host smart-9dd9467b-a13e-42c9-92b8-40c4ebc337ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442624317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1442624317
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1381350509
Short name T625
Test name
Test status
Simulation time 5960796152 ps
CPU time 50.32 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:45:40 PM PDT 24
Peak memory 237164 kb
Host smart-c4c550f8-658d-4f4b-959b-55c9fc6518bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381350509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1381350509
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3537138458
Short name T816
Test name
Test status
Simulation time 2484061530 ps
CPU time 38.36 seconds
Started May 28 02:44:54 PM PDT 24
Finished May 28 02:45:38 PM PDT 24
Peak memory 248880 kb
Host smart-4e301c91-c8f5-4442-a963-3ca92e66bc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537138458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3537138458
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1138811263
Short name T825
Test name
Test status
Simulation time 18497876988 ps
CPU time 28.16 seconds
Started May 28 02:44:55 PM PDT 24
Finished May 28 02:45:29 PM PDT 24
Peak memory 233284 kb
Host smart-52a3b8a4-fd87-4d6d-ac98-f7e5ace8ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138811263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1138811263
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4009866547
Short name T780
Test name
Test status
Simulation time 14682370699 ps
CPU time 51.92 seconds
Started May 28 02:44:41 PM PDT 24
Finished May 28 02:45:45 PM PDT 24
Peak memory 238192 kb
Host smart-0bc60b06-cea9-48ee-b27a-117da5906a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009866547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4009866547
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1435054039
Short name T25
Test name
Test status
Simulation time 17080112 ps
CPU time 1.02 seconds
Started May 28 02:44:56 PM PDT 24
Finished May 28 02:45:03 PM PDT 24
Peak memory 216236 kb
Host smart-fb1f0913-3668-47cb-a751-c1afd4008957
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435054039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1435054039
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3789224278
Short name T264
Test name
Test status
Simulation time 4231040436 ps
CPU time 10.11 seconds
Started May 28 02:44:36 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 224260 kb
Host smart-597e9e4d-6f78-4889-b45a-3714a5cd3666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789224278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3789224278
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3847192480
Short name T431
Test name
Test status
Simulation time 916011875 ps
CPU time 4.58 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:44:53 PM PDT 24
Peak memory 234564 kb
Host smart-8cd4936b-5f0d-4d63-ac08-74fc78958180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847192480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3847192480
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2691726223
Short name T807
Test name
Test status
Simulation time 574217840 ps
CPU time 4.82 seconds
Started May 28 02:44:54 PM PDT 24
Finished May 28 02:45:05 PM PDT 24
Peak memory 218884 kb
Host smart-4a7903f6-c8e2-40eb-95db-bfe28bbd5f23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2691726223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2691726223
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1224348520
Short name T707
Test name
Test status
Simulation time 4825807726 ps
CPU time 15.32 seconds
Started May 28 02:44:54 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 224324 kb
Host smart-5e10647b-ab76-4cb9-b927-937e376047d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224348520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1224348520
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3125980140
Short name T345
Test name
Test status
Simulation time 40683163 ps
CPU time 0.7 seconds
Started May 28 02:44:36 PM PDT 24
Finished May 28 02:44:50 PM PDT 24
Peak memory 205060 kb
Host smart-504a90a5-c075-48b9-841d-55b3a9933b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125980140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3125980140
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1781848027
Short name T352
Test name
Test status
Simulation time 2776371768 ps
CPU time 5.53 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:44:52 PM PDT 24
Peak memory 215908 kb
Host smart-9617658e-0882-4274-be06-fb404a6d1053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781848027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1781848027
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.920557118
Short name T699
Test name
Test status
Simulation time 505026295 ps
CPU time 2.81 seconds
Started May 28 02:44:36 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 215944 kb
Host smart-afd40093-adf6-4d83-93ed-745d7f417a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920557118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.920557118
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1146765407
Short name T426
Test name
Test status
Simulation time 88639677 ps
CPU time 0.89 seconds
Started May 28 02:44:30 PM PDT 24
Finished May 28 02:44:42 PM PDT 24
Peak memory 205584 kb
Host smart-89f2866e-0cfc-4b8d-b290-4723af057640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146765407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1146765407
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3320576082
Short name T226
Test name
Test status
Simulation time 3570792517 ps
CPU time 6.81 seconds
Started May 28 02:44:46 PM PDT 24
Finished May 28 02:45:02 PM PDT 24
Peak memory 219880 kb
Host smart-3f2f9a1d-6839-465d-8c15-007fdd85e2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320576082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3320576082
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1142152407
Short name T574
Test name
Test status
Simulation time 41354087 ps
CPU time 0.75 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:50 PM PDT 24
Peak memory 204284 kb
Host smart-203ea785-8387-4a97-a284-96c78602e4c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142152407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1142152407
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3493594541
Short name T942
Test name
Test status
Simulation time 1276972206 ps
CPU time 2.02 seconds
Started May 28 02:44:54 PM PDT 24
Finished May 28 02:45:02 PM PDT 24
Peak memory 215668 kb
Host smart-e4d17d8e-63c4-48a8-9a56-f24783af5a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493594541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3493594541
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3561531138
Short name T432
Test name
Test status
Simulation time 20517014 ps
CPU time 0.77 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 205944 kb
Host smart-e41754bf-dae8-45ae-bc95-70b7c30bfbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561531138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3561531138
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1960045901
Short name T887
Test name
Test status
Simulation time 10225441282 ps
CPU time 90.96 seconds
Started May 28 02:44:43 PM PDT 24
Finished May 28 02:46:25 PM PDT 24
Peak memory 248816 kb
Host smart-efa9f9e6-373a-4a09-8de1-33a42bc6c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960045901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1960045901
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4215236697
Short name T294
Test name
Test status
Simulation time 182786284533 ps
CPU time 773.32 seconds
Started May 28 02:44:43 PM PDT 24
Finished May 28 02:57:47 PM PDT 24
Peak memory 273484 kb
Host smart-de4e60cf-860e-4118-9bee-57969f50ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215236697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4215236697
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.610083435
Short name T12
Test name
Test status
Simulation time 47887129491 ps
CPU time 226.97 seconds
Started May 28 02:44:39 PM PDT 24
Finished May 28 02:48:38 PM PDT 24
Peak memory 249084 kb
Host smart-aacda63c-3281-4941-9e15-31cfdbff9b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610083435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.610083435
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.225197966
Short name T306
Test name
Test status
Simulation time 1992223777 ps
CPU time 12.06 seconds
Started May 28 02:44:56 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 232392 kb
Host smart-463baa22-a9b2-474e-952f-375dcdec039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225197966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.225197966
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2643571620
Short name T884
Test name
Test status
Simulation time 125034241 ps
CPU time 2.26 seconds
Started May 28 02:44:45 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 220980 kb
Host smart-ace75e4b-ce68-4e72-b660-8b17588178c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643571620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2643571620
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2529979776
Short name T682
Test name
Test status
Simulation time 4733350350 ps
CPU time 33.77 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:45:36 PM PDT 24
Peak memory 217640 kb
Host smart-ea9dfc51-8673-4cc7-9490-ae17a7aec9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529979776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2529979776
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3219993848
Short name T614
Test name
Test status
Simulation time 42229786 ps
CPU time 0.99 seconds
Started May 28 02:44:50 PM PDT 24
Finished May 28 02:44:58 PM PDT 24
Peak memory 217468 kb
Host smart-7258e5cb-ec18-4d61-8611-fb336a95596f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219993848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3219993848
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1182312641
Short name T756
Test name
Test status
Simulation time 26608582325 ps
CPU time 10.93 seconds
Started May 28 02:44:55 PM PDT 24
Finished May 28 02:45:12 PM PDT 24
Peak memory 219820 kb
Host smart-595ef9d0-2290-488f-a23f-5ae6417c3a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182312641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1182312641
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3056378197
Short name T532
Test name
Test status
Simulation time 5395364792 ps
CPU time 18.29 seconds
Started May 28 02:44:48 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 232788 kb
Host smart-ae4167b9-d154-4f90-8a43-b03d56153826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056378197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3056378197
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.859862917
Short name T641
Test name
Test status
Simulation time 1538125337 ps
CPU time 6.22 seconds
Started May 28 02:44:40 PM PDT 24
Finished May 28 02:44:58 PM PDT 24
Peak memory 222636 kb
Host smart-1b29db12-8e35-4d58-9183-70bad5421215
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=859862917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.859862917
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.513843958
Short name T505
Test name
Test status
Simulation time 45778472 ps
CPU time 0.98 seconds
Started May 28 02:44:41 PM PDT 24
Finished May 28 02:44:53 PM PDT 24
Peak memory 205028 kb
Host smart-879d2541-d7be-45be-bcd0-3d9b290dc185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513843958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.513843958
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.491846462
Short name T961
Test name
Test status
Simulation time 610156855 ps
CPU time 4.12 seconds
Started May 28 02:44:41 PM PDT 24
Finished May 28 02:44:56 PM PDT 24
Peak memory 215916 kb
Host smart-298e68a5-3ad3-4a2f-847e-63ad31d63eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491846462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.491846462
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2826179061
Short name T1
Test name
Test status
Simulation time 3001310068 ps
CPU time 7.24 seconds
Started May 28 02:44:45 PM PDT 24
Finished May 28 02:45:02 PM PDT 24
Peak memory 215920 kb
Host smart-f77466b1-63ed-4162-96f3-dd4345dde80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826179061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2826179061
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2743065149
Short name T862
Test name
Test status
Simulation time 31299873 ps
CPU time 1.13 seconds
Started May 28 02:44:43 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 207132 kb
Host smart-21cb2284-0cb4-4344-8d01-83d962727ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743065149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2743065149
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.332087979
Short name T809
Test name
Test status
Simulation time 154957289 ps
CPU time 0.91 seconds
Started May 28 02:44:47 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 205316 kb
Host smart-2c9f36fc-59c7-4a11-a83a-b15a72a17a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332087979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.332087979
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2284880550
Short name T604
Test name
Test status
Simulation time 1143087821 ps
CPU time 6.17 seconds
Started May 28 02:44:39 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 232384 kb
Host smart-c2591efb-5c5d-4386-9109-f2a7f7e921a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284880550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2284880550
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4213248744
Short name T450
Test name
Test status
Simulation time 35185264 ps
CPU time 0.72 seconds
Started May 28 02:44:46 PM PDT 24
Finished May 28 02:44:56 PM PDT 24
Peak memory 205276 kb
Host smart-7b2c7b25-6731-47a9-a352-1f73f474e203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213248744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4213248744
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3466597681
Short name T717
Test name
Test status
Simulation time 742220301 ps
CPU time 3.68 seconds
Started May 28 02:44:39 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 224176 kb
Host smart-411c10e8-3525-46b6-aa5d-c12909696d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466597681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3466597681
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2660378823
Short name T701
Test name
Test status
Simulation time 19256127 ps
CPU time 0.8 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 206272 kb
Host smart-9a79e624-e379-4eda-82a1-2d4c67a687db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660378823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2660378823
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1388962160
Short name T255
Test name
Test status
Simulation time 154414885894 ps
CPU time 187.26 seconds
Started May 28 02:44:54 PM PDT 24
Finished May 28 02:48:07 PM PDT 24
Peak memory 241032 kb
Host smart-59866979-0462-411e-bf31-850040fad682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388962160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1388962160
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2337776523
Short name T726
Test name
Test status
Simulation time 69444698803 ps
CPU time 199.95 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 253880 kb
Host smart-ff322eb6-af2c-40b2-9fce-4153d3b5741d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337776523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2337776523
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2640424630
Short name T41
Test name
Test status
Simulation time 627281037 ps
CPU time 14.6 seconds
Started May 28 02:44:47 PM PDT 24
Finished May 28 02:45:11 PM PDT 24
Peak memory 248800 kb
Host smart-aa9fb7b3-757b-4f05-83d3-e382b699c19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640424630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2640424630
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2152801355
Short name T889
Test name
Test status
Simulation time 786628779 ps
CPU time 10.05 seconds
Started May 28 02:44:46 PM PDT 24
Finished May 28 02:45:05 PM PDT 24
Peak memory 233416 kb
Host smart-65acf4bb-53b8-4644-8bb1-42e36b2009ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152801355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2152801355
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3675690832
Short name T44
Test name
Test status
Simulation time 3413720481 ps
CPU time 10.34 seconds
Started May 28 02:44:40 PM PDT 24
Finished May 28 02:45:03 PM PDT 24
Peak memory 218424 kb
Host smart-9520d971-e2f1-4301-ba78-ee3323d39472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675690832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3675690832
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3924364824
Short name T729
Test name
Test status
Simulation time 14815240 ps
CPU time 1.06 seconds
Started May 28 02:44:48 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 216220 kb
Host smart-781f5254-1a17-415a-95cf-8ec2fd59f1f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924364824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3924364824
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1547432045
Short name T252
Test name
Test status
Simulation time 1929963183 ps
CPU time 7.99 seconds
Started May 28 02:45:01 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 218532 kb
Host smart-479bf409-6752-4343-82eb-cb6abbde3e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547432045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1547432045
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1501990333
Short name T950
Test name
Test status
Simulation time 5343935336 ps
CPU time 11.69 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:45:03 PM PDT 24
Peak memory 240608 kb
Host smart-3450b7eb-353e-4630-9c4f-7eb876e02d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501990333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1501990333
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3694195882
Short name T609
Test name
Test status
Simulation time 400692861 ps
CPU time 4.46 seconds
Started May 28 02:44:46 PM PDT 24
Finished May 28 02:45:00 PM PDT 24
Peak memory 218792 kb
Host smart-f8676456-f420-4ba1-8478-96e68f706748
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3694195882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3694195882
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.349944896
Short name T56
Test name
Test status
Simulation time 7437630632 ps
CPU time 34.07 seconds
Started May 28 02:44:42 PM PDT 24
Finished May 28 02:45:27 PM PDT 24
Peak memory 217656 kb
Host smart-9192e215-f859-4c02-b199-c4b2b8bbc435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349944896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.349944896
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.922975840
Short name T818
Test name
Test status
Simulation time 2544630546 ps
CPU time 3.31 seconds
Started May 28 02:44:48 PM PDT 24
Finished May 28 02:45:00 PM PDT 24
Peak memory 216032 kb
Host smart-82094f0d-9591-4bb6-bb42-8a290629e407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922975840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.922975840
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3720962120
Short name T677
Test name
Test status
Simulation time 488426663 ps
CPU time 1.07 seconds
Started May 28 02:44:52 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 206504 kb
Host smart-b445c182-d99a-4806-8cf3-d9160e928aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720962120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3720962120
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1667805829
Short name T121
Test name
Test status
Simulation time 207801272 ps
CPU time 2.82 seconds
Started May 28 02:44:44 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 215928 kb
Host smart-8fc8fa54-21db-4ff7-ab6c-8b02469da0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667805829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1667805829
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1783209967
Short name T388
Test name
Test status
Simulation time 25206550 ps
CPU time 0.84 seconds
Started May 28 02:44:39 PM PDT 24
Finished May 28 02:44:52 PM PDT 24
Peak memory 205304 kb
Host smart-1f891a67-2519-4a43-af34-492d02105484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783209967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1783209967
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1383675552
Short name T179
Test name
Test status
Simulation time 1961461092 ps
CPU time 11.3 seconds
Started May 28 02:44:38 PM PDT 24
Finished May 28 02:45:02 PM PDT 24
Peak memory 217944 kb
Host smart-342db12c-a7a2-4c96-ae04-46a825731264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383675552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1383675552
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2484662933
Short name T928
Test name
Test status
Simulation time 33011966 ps
CPU time 0.71 seconds
Started May 28 02:44:58 PM PDT 24
Finished May 28 02:45:04 PM PDT 24
Peak memory 204932 kb
Host smart-efb9799d-56fa-4106-ab01-0b941c6b1d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484662933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2484662933
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2945793325
Short name T649
Test name
Test status
Simulation time 35910246 ps
CPU time 2.14 seconds
Started May 28 02:44:45 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 218564 kb
Host smart-bb363200-cac2-4ba7-9b30-90d36d7b00d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945793325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2945793325
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3792160518
Short name T648
Test name
Test status
Simulation time 69805004 ps
CPU time 0.8 seconds
Started May 28 02:44:43 PM PDT 24
Finished May 28 02:44:55 PM PDT 24
Peak memory 206268 kb
Host smart-f5fab166-0292-4a7c-a05c-ab68a3dc7359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792160518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3792160518
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.202894200
Short name T290
Test name
Test status
Simulation time 53383654637 ps
CPU time 74.17 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:46:16 PM PDT 24
Peak memory 248680 kb
Host smart-79597c0c-09f5-4e4a-81c4-fb4f1d7cd9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202894200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.202894200
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2878733953
Short name T317
Test name
Test status
Simulation time 2095686275 ps
CPU time 52.31 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:45:50 PM PDT 24
Peak memory 253900 kb
Host smart-cdc8db32-091f-498f-a8b8-b93a00e61499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878733953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2878733953
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1272719216
Short name T956
Test name
Test status
Simulation time 2060428407 ps
CPU time 30.26 seconds
Started May 28 02:44:50 PM PDT 24
Finished May 28 02:45:28 PM PDT 24
Peak memory 224224 kb
Host smart-274c599e-cd28-44d1-88c8-d25fc1eb5b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272719216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1272719216
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.12541155
Short name T975
Test name
Test status
Simulation time 5825704863 ps
CPU time 25.5 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:45:28 PM PDT 24
Peak memory 224200 kb
Host smart-9a55c7fa-03e8-46c3-944a-b533bf7128b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12541155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.12541155
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2160326111
Short name T921
Test name
Test status
Simulation time 1883400510 ps
CPU time 8.48 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 219724 kb
Host smart-0db21b14-e7c3-44c6-adae-934b37845ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160326111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2160326111
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2427635178
Short name T930
Test name
Test status
Simulation time 197648569 ps
CPU time 5.08 seconds
Started May 28 02:44:50 PM PDT 24
Finished May 28 02:45:02 PM PDT 24
Peak memory 218384 kb
Host smart-9b20071e-44cb-40ad-938a-920054db1fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427635178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2427635178
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3199248131
Short name T909
Test name
Test status
Simulation time 45585592 ps
CPU time 0.95 seconds
Started May 28 02:44:42 PM PDT 24
Finished May 28 02:44:54 PM PDT 24
Peak memory 217448 kb
Host smart-45cb1a15-1252-447d-9f27-7d497d236619
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199248131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3199248131
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1187006532
Short name T14
Test name
Test status
Simulation time 7850679729 ps
CPU time 12.55 seconds
Started May 28 02:44:59 PM PDT 24
Finished May 28 02:45:17 PM PDT 24
Peak memory 233276 kb
Host smart-5b6d19f1-c1b9-48da-a726-63c3c531b694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187006532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1187006532
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3507147477
Short name T735
Test name
Test status
Simulation time 23303692031 ps
CPU time 17.09 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 236324 kb
Host smart-9f3185c9-f814-41dd-8c04-27961f8681bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507147477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3507147477
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.287578254
Short name T777
Test name
Test status
Simulation time 77178769 ps
CPU time 3.49 seconds
Started May 28 02:44:58 PM PDT 24
Finished May 28 02:45:06 PM PDT 24
Peak memory 222492 kb
Host smart-de601731-3dba-411f-b89a-45b6779ee951
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=287578254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.287578254
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1101828236
Short name T71
Test name
Test status
Simulation time 63190753915 ps
CPU time 183.73 seconds
Started May 28 02:44:58 PM PDT 24
Finished May 28 02:48:07 PM PDT 24
Peak memory 253312 kb
Host smart-a41ae186-e76a-49b1-8ef1-865327c2af82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101828236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1101828236
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2601143635
Short name T548
Test name
Test status
Simulation time 280564898 ps
CPU time 2.58 seconds
Started May 28 02:44:47 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 215908 kb
Host smart-827b7ba3-96d5-47bb-b0ee-07a492ddd435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601143635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2601143635
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4254168293
Short name T80
Test name
Test status
Simulation time 2567024923 ps
CPU time 5.38 seconds
Started May 28 02:44:47 PM PDT 24
Finished May 28 02:45:01 PM PDT 24
Peak memory 215868 kb
Host smart-548ed36c-2adb-4486-852b-092cb12e7661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254168293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4254168293
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1343000084
Short name T409
Test name
Test status
Simulation time 139275525 ps
CPU time 1.4 seconds
Started May 28 02:44:46 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 215872 kb
Host smart-c1aafc8f-bebe-4648-a058-f64104047fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343000084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1343000084
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3091398826
Short name T861
Test name
Test status
Simulation time 18779783 ps
CPU time 0.73 seconds
Started May 28 02:44:58 PM PDT 24
Finished May 28 02:45:04 PM PDT 24
Peak memory 205316 kb
Host smart-29eb2ef4-3ff9-47e9-b9db-b713917ece57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091398826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3091398826
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.818769515
Short name T465
Test name
Test status
Simulation time 4520440388 ps
CPU time 16.22 seconds
Started May 28 02:44:56 PM PDT 24
Finished May 28 02:45:18 PM PDT 24
Peak memory 218340 kb
Host smart-bc68c658-5c0d-4146-a44a-b13717129ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818769515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.818769515
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2964861858
Short name T764
Test name
Test status
Simulation time 47056093 ps
CPU time 0.75 seconds
Started May 28 02:44:54 PM PDT 24
Finished May 28 02:45:01 PM PDT 24
Peak memory 204896 kb
Host smart-8c537ebc-e9c4-431a-a367-367fd7362a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964861858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2964861858
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4078627769
Short name T710
Test name
Test status
Simulation time 77183437 ps
CPU time 2.84 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:45:00 PM PDT 24
Peak memory 217552 kb
Host smart-b6432df2-2aed-4dbc-8753-c80353b4ed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078627769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4078627769
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1288095400
Short name T691
Test name
Test status
Simulation time 14458547 ps
CPU time 0.79 seconds
Started May 28 02:44:45 PM PDT 24
Finished May 28 02:44:56 PM PDT 24
Peak memory 205836 kb
Host smart-f852b96a-9498-4597-b2d5-035ab226f200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288095400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1288095400
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3369340572
Short name T927
Test name
Test status
Simulation time 122318984630 ps
CPU time 147.39 seconds
Started May 28 02:44:46 PM PDT 24
Finished May 28 02:47:23 PM PDT 24
Peak memory 249732 kb
Host smart-e8f8e7b8-fd58-4252-bb6e-61b1ca209f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369340572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3369340572
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3955672217
Short name T129
Test name
Test status
Simulation time 23105292635 ps
CPU time 180.6 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 263416 kb
Host smart-c773eaf6-0a7d-4fc5-8d44-099d04b5815d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955672217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3955672217
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2855070170
Short name T17
Test name
Test status
Simulation time 18207101458 ps
CPU time 82.83 seconds
Started May 28 02:44:44 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 256460 kb
Host smart-85aefe72-33ab-4403-99ce-7144f25420a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855070170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2855070170
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3694234528
Short name T672
Test name
Test status
Simulation time 4346150357 ps
CPU time 11.71 seconds
Started May 28 02:45:02 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 234724 kb
Host smart-92ef7b35-c2c4-40db-8a23-bd0d03251969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694234528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3694234528
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2216367494
Short name T228
Test name
Test status
Simulation time 1119463861 ps
CPU time 6.22 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:45:09 PM PDT 24
Peak memory 218344 kb
Host smart-8c4b628f-e3a0-426c-9164-8abe0e7133fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216367494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2216367494
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3849044439
Short name T23
Test name
Test status
Simulation time 25868621 ps
CPU time 1.04 seconds
Started May 28 02:45:01 PM PDT 24
Finished May 28 02:45:07 PM PDT 24
Peak memory 216228 kb
Host smart-b78ae4a0-247e-4a75-b0d1-aab19150fb95
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849044439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3849044439
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2438213574
Short name T804
Test name
Test status
Simulation time 294671151 ps
CPU time 2.69 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:45:05 PM PDT 24
Peak memory 235004 kb
Host smart-70fde4b7-ba56-4abe-afa2-e7b17ba6b37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438213574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2438213574
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1362019259
Short name T522
Test name
Test status
Simulation time 92209509 ps
CPU time 3.38 seconds
Started May 28 02:45:02 PM PDT 24
Finished May 28 02:45:11 PM PDT 24
Peak memory 233820 kb
Host smart-60ad19a2-93ba-40a8-aee7-ec94213dea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362019259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1362019259
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2425155539
Short name T139
Test name
Test status
Simulation time 1775861132 ps
CPU time 9.36 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:45:07 PM PDT 24
Peak memory 219796 kb
Host smart-d2d7fbd2-86cc-435e-b5ba-9246222ff46a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2425155539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2425155539
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3642665987
Short name T131
Test name
Test status
Simulation time 61590670187 ps
CPU time 176.82 seconds
Started May 28 02:44:44 PM PDT 24
Finished May 28 02:47:51 PM PDT 24
Peak memory 240724 kb
Host smart-61b92bb1-8549-4610-b982-126140142f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642665987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3642665987
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.257128112
Short name T972
Test name
Test status
Simulation time 48149063607 ps
CPU time 13.68 seconds
Started May 28 02:45:02 PM PDT 24
Finished May 28 02:45:21 PM PDT 24
Peak memory 215984 kb
Host smart-b7be09fc-5667-4ea8-a3a1-772025b45bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257128112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.257128112
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1022770160
Short name T720
Test name
Test status
Simulation time 3619869812 ps
CPU time 4.93 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:45:03 PM PDT 24
Peak memory 215888 kb
Host smart-a1a29c82-5c43-421b-b338-7312440500e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022770160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1022770160
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3985686162
Short name T339
Test name
Test status
Simulation time 25150640 ps
CPU time 0.94 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 206420 kb
Host smart-8bf98cdd-42cb-4be9-b41f-b8200edb35a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985686162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3985686162
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.298274902
Short name T325
Test name
Test status
Simulation time 82404153 ps
CPU time 0.94 seconds
Started May 28 02:44:45 PM PDT 24
Finished May 28 02:44:56 PM PDT 24
Peak memory 205184 kb
Host smart-7b63d329-85e4-4538-a03c-e3c0b6e820ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298274902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.298274902
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.574735274
Short name T448
Test name
Test status
Simulation time 1019866419 ps
CPU time 8.23 seconds
Started May 28 02:44:40 PM PDT 24
Finished May 28 02:45:00 PM PDT 24
Peak memory 229244 kb
Host smart-fcb5abf6-b97f-4f1d-a5ce-e113ec717438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574735274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.574735274
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2022029671
Short name T740
Test name
Test status
Simulation time 35154188 ps
CPU time 0.71 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:45:06 PM PDT 24
Peak memory 204912 kb
Host smart-54e0465e-2478-45a7-a29e-157b2281fa03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022029671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2022029671
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3354438142
Short name T570
Test name
Test status
Simulation time 928201302 ps
CPU time 4.37 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:45:09 PM PDT 24
Peak memory 234992 kb
Host smart-1f605b8c-3fdd-4c7e-834f-f57599f389f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354438142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3354438142
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2404320410
Short name T500
Test name
Test status
Simulation time 21805438 ps
CPU time 0.8 seconds
Started May 28 02:44:40 PM PDT 24
Finished May 28 02:44:53 PM PDT 24
Peak memory 206256 kb
Host smart-c57bfae5-f886-40b4-b6a3-e3cc9cd64cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404320410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2404320410
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.656852365
Short name T74
Test name
Test status
Simulation time 38394469988 ps
CPU time 88.29 seconds
Started May 28 02:45:02 PM PDT 24
Finished May 28 02:46:36 PM PDT 24
Peak memory 250236 kb
Host smart-d4c297fb-5b17-4d36-bb43-6105008fb0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656852365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.656852365
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2602859117
Short name T210
Test name
Test status
Simulation time 1470023706 ps
CPU time 17.07 seconds
Started May 28 02:44:57 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 237584 kb
Host smart-85115070-416a-4cbb-9bec-8faa6a7dd42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602859117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2602859117
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2431288255
Short name T287
Test name
Test status
Simulation time 12730167880 ps
CPU time 180.56 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 265296 kb
Host smart-f45f18d5-f0c9-4c41-8569-22add8b5da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431288255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2431288255
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3601600049
Short name T305
Test name
Test status
Simulation time 765271189 ps
CPU time 10.5 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:22 PM PDT 24
Peak memory 233932 kb
Host smart-72a836a0-7552-4b3a-92df-a174017bcf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601600049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3601600049
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.268890275
Short name T318
Test name
Test status
Simulation time 41380892 ps
CPU time 2.74 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 232592 kb
Host smart-6ecf1564-fd02-4231-80e5-0cb3ebe769e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268890275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.268890275
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2430212538
Short name T175
Test name
Test status
Simulation time 9882075105 ps
CPU time 104.66 seconds
Started May 28 02:44:47 PM PDT 24
Finished May 28 02:46:41 PM PDT 24
Peak memory 230052 kb
Host smart-109009a0-2861-468b-bacd-6ede2630e8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430212538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2430212538
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2954436451
Short name T539
Test name
Test status
Simulation time 61741188 ps
CPU time 1.06 seconds
Started May 28 02:44:40 PM PDT 24
Finished May 28 02:44:53 PM PDT 24
Peak memory 216212 kb
Host smart-97c4706d-7e70-4500-a4c2-d3f329c65de9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954436451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2954436451
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4212178258
Short name T842
Test name
Test status
Simulation time 292543333 ps
CPU time 4.83 seconds
Started May 28 02:45:08 PM PDT 24
Finished May 28 02:45:17 PM PDT 24
Peak memory 232840 kb
Host smart-c9ca734c-d000-4f3b-bb9e-e342403c5b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212178258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4212178258
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3035475275
Short name T679
Test name
Test status
Simulation time 2683323016 ps
CPU time 3.95 seconds
Started May 28 02:44:48 PM PDT 24
Finished May 28 02:45:00 PM PDT 24
Peak memory 218244 kb
Host smart-89793e6f-b5a6-4c74-bed5-920852f298c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035475275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3035475275
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1086874634
Short name T435
Test name
Test status
Simulation time 458992797 ps
CPU time 5.12 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:45:10 PM PDT 24
Peak memory 221740 kb
Host smart-fd5b656f-ee9d-435a-b32e-9434b7ae4160
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1086874634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1086874634
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.982746225
Short name T750
Test name
Test status
Simulation time 3781836971 ps
CPU time 22.21 seconds
Started May 28 02:45:02 PM PDT 24
Finished May 28 02:45:30 PM PDT 24
Peak memory 216260 kb
Host smart-c0b7ac1f-3dde-4bf0-aad6-4627f7c89ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982746225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.982746225
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2232279640
Short name T803
Test name
Test status
Simulation time 818152006 ps
CPU time 1.25 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 206484 kb
Host smart-5af8547f-ff53-494b-809c-fd0bd6e7125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232279640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2232279640
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.69761262
Short name T590
Test name
Test status
Simulation time 770441067 ps
CPU time 3.6 seconds
Started May 28 02:44:50 PM PDT 24
Finished May 28 02:45:01 PM PDT 24
Peak memory 215868 kb
Host smart-d039c307-79d1-44e0-8f34-b36647c26dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69761262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.69761262
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.379220518
Short name T423
Test name
Test status
Simulation time 70964180 ps
CPU time 0.69 seconds
Started May 28 02:45:03 PM PDT 24
Finished May 28 02:45:09 PM PDT 24
Peak memory 205304 kb
Host smart-4906f392-4228-4849-80d9-84cc07e989ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379220518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.379220518
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2621792722
Short name T239
Test name
Test status
Simulation time 1452846454 ps
CPU time 4.43 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:45:02 PM PDT 24
Peak memory 236252 kb
Host smart-15d3cf6e-2234-4593-8f1b-a4896c581b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621792722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2621792722
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.739700449
Short name T365
Test name
Test status
Simulation time 27787005 ps
CPU time 0.72 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:35 PM PDT 24
Peak memory 204912 kb
Host smart-8fbe3e48-c520-456b-a4a1-92857025bd9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739700449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.739700449
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2315157318
Short name T496
Test name
Test status
Simulation time 3804749290 ps
CPU time 10.75 seconds
Started May 28 02:44:27 PM PDT 24
Finished May 28 02:44:49 PM PDT 24
Peak memory 238544 kb
Host smart-e28c55c0-0b28-4f85-8366-ee78e854569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315157318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2315157318
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.536137581
Short name T653
Test name
Test status
Simulation time 55543588 ps
CPU time 0.76 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:44:20 PM PDT 24
Peak memory 204780 kb
Host smart-d9d659e1-6923-41c8-9d26-1332dfe464ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536137581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.536137581
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3041369325
Short name T760
Test name
Test status
Simulation time 27736039941 ps
CPU time 95.46 seconds
Started May 28 02:44:15 PM PDT 24
Finished May 28 02:45:53 PM PDT 24
Peak memory 240604 kb
Host smart-3710d73f-ecd6-4a3e-b868-948004955ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041369325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3041369325
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2697531232
Short name T73
Test name
Test status
Simulation time 16451049715 ps
CPU time 129.91 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:46:45 PM PDT 24
Peak memory 250248 kb
Host smart-983c9d62-dc63-4955-8745-f7f963733f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697531232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2697531232
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1794578786
Short name T416
Test name
Test status
Simulation time 24012829123 ps
CPU time 31.87 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:45:06 PM PDT 24
Peak memory 232440 kb
Host smart-7dc705d5-c2b6-4ff5-a5d0-d33ef0b586d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794578786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1794578786
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1317851221
Short name T724
Test name
Test status
Simulation time 1715956306 ps
CPU time 18.92 seconds
Started May 28 02:44:14 PM PDT 24
Finished May 28 02:44:35 PM PDT 24
Peak memory 218284 kb
Host smart-112b8092-9b11-4ef9-8be3-9c94f36130ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317851221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1317851221
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2853369901
Short name T612
Test name
Test status
Simulation time 2134767651 ps
CPU time 7.4 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:44:28 PM PDT 24
Peak memory 218236 kb
Host smart-0e97a340-b283-4e18-941d-6cc653f4fae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853369901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2853369901
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.935979506
Short name T917
Test name
Test status
Simulation time 40113145 ps
CPU time 1.08 seconds
Started May 28 02:44:15 PM PDT 24
Finished May 28 02:44:19 PM PDT 24
Peak memory 216228 kb
Host smart-8c59e50b-7c0c-4178-baf5-9381c3bb7a15
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935979506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.935979506
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2184677728
Short name T85
Test name
Test status
Simulation time 1147151330 ps
CPU time 2.96 seconds
Started May 28 02:44:11 PM PDT 24
Finished May 28 02:44:16 PM PDT 24
Peak memory 232388 kb
Host smart-6da441a6-25fb-43b8-a7f6-286f59a711bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184677728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2184677728
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.311650201
Short name T452
Test name
Test status
Simulation time 227456066 ps
CPU time 4.1 seconds
Started May 28 02:44:19 PM PDT 24
Finished May 28 02:44:27 PM PDT 24
Peak memory 219220 kb
Host smart-14503ec1-e839-4700-975e-5076a36cab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311650201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.311650201
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3363289911
Short name T732
Test name
Test status
Simulation time 123347834 ps
CPU time 3.33 seconds
Started May 28 02:44:18 PM PDT 24
Finished May 28 02:44:25 PM PDT 24
Peak memory 222632 kb
Host smart-90bbeb1c-6ec4-4ce1-a702-b1f6d5f369c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3363289911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3363289911
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2137756752
Short name T60
Test name
Test status
Simulation time 217502637 ps
CPU time 1.06 seconds
Started May 28 02:44:20 PM PDT 24
Finished May 28 02:44:24 PM PDT 24
Peak memory 234724 kb
Host smart-6d98f1ce-2b67-44ef-bff6-12abf3dc1ad1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137756752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2137756752
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2579030643
Short name T783
Test name
Test status
Simulation time 180393537470 ps
CPU time 465.39 seconds
Started May 28 02:44:20 PM PDT 24
Finished May 28 02:52:09 PM PDT 24
Peak memory 272528 kb
Host smart-6f9202ae-31ae-42c9-ba98-8c7cf6d77a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579030643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2579030643
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3703947867
Short name T415
Test name
Test status
Simulation time 409851697 ps
CPU time 5.07 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:41 PM PDT 24
Peak memory 216096 kb
Host smart-b854d774-2c2d-4178-aee9-659bd1409448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703947867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3703947867
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2943978723
Short name T733
Test name
Test status
Simulation time 948351179 ps
CPU time 6.17 seconds
Started May 28 02:44:22 PM PDT 24
Finished May 28 02:44:32 PM PDT 24
Peak memory 215788 kb
Host smart-90b5b9a6-8d77-4258-9486-0643724bb079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943978723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2943978723
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.312257323
Short name T512
Test name
Test status
Simulation time 252921060 ps
CPU time 2.55 seconds
Started May 28 02:44:07 PM PDT 24
Finished May 28 02:44:11 PM PDT 24
Peak memory 216244 kb
Host smart-c122311c-d6f4-4344-95a4-b423294cbe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312257323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.312257323
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1758129181
Short name T120
Test name
Test status
Simulation time 49178161 ps
CPU time 0.79 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:29 PM PDT 24
Peak memory 205272 kb
Host smart-6dea0ba9-e683-458e-a5de-40dd785cfb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758129181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1758129181
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3188247496
Short name T514
Test name
Test status
Simulation time 2219673134 ps
CPU time 5.89 seconds
Started May 28 02:44:27 PM PDT 24
Finished May 28 02:44:44 PM PDT 24
Peak memory 227228 kb
Host smart-98695bd1-844c-49cd-be1d-8c3ec3adac12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188247496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3188247496
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1831666073
Short name T630
Test name
Test status
Simulation time 16016477 ps
CPU time 0.72 seconds
Started May 28 02:44:58 PM PDT 24
Finished May 28 02:45:04 PM PDT 24
Peak memory 204928 kb
Host smart-f8580ac1-a77e-4185-9132-60496c812376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831666073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1831666073
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3842409916
Short name T358
Test name
Test status
Simulation time 419336925 ps
CPU time 6.36 seconds
Started May 28 02:44:59 PM PDT 24
Finished May 28 02:45:10 PM PDT 24
Peak memory 218432 kb
Host smart-bfba14e2-a0bd-4ee6-9317-8c2106c5d7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842409916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3842409916
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1201981881
Short name T392
Test name
Test status
Simulation time 18062534 ps
CPU time 0.81 seconds
Started May 28 02:45:03 PM PDT 24
Finished May 28 02:45:09 PM PDT 24
Peak memory 205932 kb
Host smart-921329ca-a621-4410-86d3-c9b145a59017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201981881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1201981881
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.642739041
Short name T650
Test name
Test status
Simulation time 753698810 ps
CPU time 4.28 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 232728 kb
Host smart-24e349a1-d42f-4c19-a8cc-d03469d38400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642739041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.642739041
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3491943845
Short name T904
Test name
Test status
Simulation time 18276123382 ps
CPU time 138.27 seconds
Started May 28 02:44:52 PM PDT 24
Finished May 28 02:47:17 PM PDT 24
Peak memory 249148 kb
Host smart-d2f02fb2-c8a0-4995-8fbf-39d77d533270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491943845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3491943845
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4185674597
Short name T75
Test name
Test status
Simulation time 4925577205 ps
CPU time 92.66 seconds
Started May 28 02:44:50 PM PDT 24
Finished May 28 02:46:30 PM PDT 24
Peak memory 249908 kb
Host smart-7b3d2872-9c82-474e-af0a-3c986db06816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185674597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4185674597
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2566872179
Short name T725
Test name
Test status
Simulation time 753303358 ps
CPU time 6.11 seconds
Started May 28 02:44:59 PM PDT 24
Finished May 28 02:45:10 PM PDT 24
Peak memory 232376 kb
Host smart-6ef1efa9-cbfd-41c4-931c-ffaa6bbab792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566872179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2566872179
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.941766249
Short name T613
Test name
Test status
Simulation time 1784410458 ps
CPU time 15.03 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:26 PM PDT 24
Peak memory 218228 kb
Host smart-0ed23658-0c10-4f42-a1e1-352503b71179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941766249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.941766249
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2869227466
Short name T850
Test name
Test status
Simulation time 348384370 ps
CPU time 7.91 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 233436 kb
Host smart-e79713fb-5148-4b95-bdd6-210badf1e34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869227466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2869227466
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2342550981
Short name T269
Test name
Test status
Simulation time 768382307 ps
CPU time 6.07 seconds
Started May 28 02:45:01 PM PDT 24
Finished May 28 02:45:12 PM PDT 24
Peak memory 226964 kb
Host smart-a8ffe882-1f31-483a-a9e3-68eea0be77ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342550981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2342550981
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.648427308
Short name T537
Test name
Test status
Simulation time 9851861579 ps
CPU time 28.99 seconds
Started May 28 02:45:08 PM PDT 24
Finished May 28 02:45:41 PM PDT 24
Peak memory 245640 kb
Host smart-41ff7e27-b698-493a-bf01-adce44e1043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648427308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.648427308
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2861380163
Short name T523
Test name
Test status
Simulation time 7994998621 ps
CPU time 12.24 seconds
Started May 28 02:45:02 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 222128 kb
Host smart-527bff28-6ac4-454e-b834-797602c94f17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2861380163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2861380163
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2933080435
Short name T292
Test name
Test status
Simulation time 69361734903 ps
CPU time 175.13 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:48:00 PM PDT 24
Peak memory 249872 kb
Host smart-16048894-3a36-4c16-9eff-29fe6f193af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933080435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2933080435
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2154357410
Short name T639
Test name
Test status
Simulation time 34822936012 ps
CPU time 16.56 seconds
Started May 28 02:45:08 PM PDT 24
Finished May 28 02:45:29 PM PDT 24
Peak memory 215836 kb
Host smart-7e486619-99cb-4227-ab17-d6c72bc5efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154357410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2154357410
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3478879783
Short name T489
Test name
Test status
Simulation time 326558691 ps
CPU time 2.53 seconds
Started May 28 02:45:03 PM PDT 24
Finished May 28 02:45:11 PM PDT 24
Peak memory 215780 kb
Host smart-998ec044-4215-405e-b12b-1f10ee82e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478879783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3478879783
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.945890510
Short name T531
Test name
Test status
Simulation time 135896091 ps
CPU time 2.35 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:45:08 PM PDT 24
Peak memory 216288 kb
Host smart-aa67bcd1-add6-4f78-86d9-3e50fecdf530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945890510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.945890510
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4124718300
Short name T943
Test name
Test status
Simulation time 171174609 ps
CPU time 0.88 seconds
Started May 28 02:45:03 PM PDT 24
Finished May 28 02:45:09 PM PDT 24
Peak memory 205304 kb
Host smart-74a8336a-19c2-46d5-8b24-bf3a29cdfb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124718300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4124718300
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.968075019
Short name T232
Test name
Test status
Simulation time 9697441429 ps
CPU time 10.81 seconds
Started May 28 02:44:49 PM PDT 24
Finished May 28 02:45:08 PM PDT 24
Peak memory 240592 kb
Host smart-db873b2f-7bc0-4b1c-ad5f-1cb457b3a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968075019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.968075019
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2613690142
Short name T445
Test name
Test status
Simulation time 23281747 ps
CPU time 0.68 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:12 PM PDT 24
Peak memory 204300 kb
Host smart-64228bba-6c0f-40cb-a73b-32286e312b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613690142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2613690142
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2690351280
Short name T576
Test name
Test status
Simulation time 119203545 ps
CPU time 2.51 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 234136 kb
Host smart-4e682ced-3a0d-4e10-aaab-ea5c6c6a807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690351280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2690351280
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1534967170
Short name T122
Test name
Test status
Simulation time 25300545 ps
CPU time 0.74 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:12 PM PDT 24
Peak memory 206252 kb
Host smart-244dbb79-abba-44f4-9875-ced6bd30ecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534967170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1534967170
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1296327952
Short name T683
Test name
Test status
Simulation time 10022264005 ps
CPU time 65.54 seconds
Started May 28 02:44:49 PM PDT 24
Finished May 28 02:46:02 PM PDT 24
Peak memory 233888 kb
Host smart-8df054a9-e33f-4042-a888-081fac824fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296327952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1296327952
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4102253357
Short name T132
Test name
Test status
Simulation time 66721979054 ps
CPU time 151.09 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:47:36 PM PDT 24
Peak memory 256112 kb
Host smart-02de290a-2062-4d0d-9680-a3d459dc5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102253357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4102253357
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3161197365
Short name T66
Test name
Test status
Simulation time 2057620581 ps
CPU time 10.34 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:21 PM PDT 24
Peak memory 217060 kb
Host smart-09f3ae55-6038-427b-85c3-2d85e6e8eed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161197365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3161197365
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1205573849
Short name T310
Test name
Test status
Simulation time 122942615 ps
CPU time 5.55 seconds
Started May 28 02:44:59 PM PDT 24
Finished May 28 02:45:10 PM PDT 24
Peak memory 232420 kb
Host smart-c78a7208-f900-4b84-82a0-3faf0052fcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205573849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1205573849
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3539682362
Short name T247
Test name
Test status
Simulation time 151116866 ps
CPU time 3.86 seconds
Started May 28 02:45:02 PM PDT 24
Finished May 28 02:45:11 PM PDT 24
Peak memory 233304 kb
Host smart-9daaa2d3-5eb1-4367-893f-62491480f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539682362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3539682362
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1826048975
Short name T320
Test name
Test status
Simulation time 35061607 ps
CPU time 2.01 seconds
Started May 28 02:45:08 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 215708 kb
Host smart-5917ebb1-b560-4a0d-9b0c-1f2282815be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826048975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1826048975
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2000780874
Short name T935
Test name
Test status
Simulation time 6036690647 ps
CPU time 5.7 seconds
Started May 28 02:44:50 PM PDT 24
Finished May 28 02:45:03 PM PDT 24
Peak memory 216600 kb
Host smart-a97f5009-68c0-4cc9-8c07-1c348dbdc46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000780874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2000780874
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.578178650
Short name T502
Test name
Test status
Simulation time 3458594390 ps
CPU time 8.17 seconds
Started May 28 02:45:08 PM PDT 24
Finished May 28 02:45:21 PM PDT 24
Peak memory 237464 kb
Host smart-02aca347-67a7-4193-b691-fc18c9a023a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578178650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.578178650
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2501364162
Short name T383
Test name
Test status
Simulation time 957811804 ps
CPU time 6.98 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:45:12 PM PDT 24
Peak memory 219068 kb
Host smart-d3df1a66-ba02-43bc-b32c-a5e3189e2868
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2501364162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2501364162
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3942913789
Short name T39
Test name
Test status
Simulation time 39834082808 ps
CPU time 329.07 seconds
Started May 28 02:45:01 PM PDT 24
Finished May 28 02:50:35 PM PDT 24
Peak memory 254060 kb
Host smart-3ccd86c2-0356-4a5f-a6fb-770c6205cf73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942913789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3942913789
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.904318249
Short name T430
Test name
Test status
Simulation time 712580948 ps
CPU time 10.03 seconds
Started May 28 02:45:13 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 216164 kb
Host smart-dd240ba7-5bd5-42a8-9cc0-b88f9e85853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904318249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.904318249
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.842970255
Short name T357
Test name
Test status
Simulation time 988296060 ps
CPU time 5.65 seconds
Started May 28 02:44:52 PM PDT 24
Finished May 28 02:45:04 PM PDT 24
Peak memory 215808 kb
Host smart-64d5c221-96fe-4f27-b0f5-9291a56f9129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842970255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.842970255
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2350099996
Short name T556
Test name
Test status
Simulation time 37300741 ps
CPU time 0.77 seconds
Started May 28 02:45:09 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 205168 kb
Host smart-4633a77b-aa98-4a71-a459-f8619a8eee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350099996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2350099996
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2581768443
Short name T933
Test name
Test status
Simulation time 71342681 ps
CPU time 0.81 seconds
Started May 28 02:45:00 PM PDT 24
Finished May 28 02:45:06 PM PDT 24
Peak memory 205288 kb
Host smart-b3faca0e-f968-499d-ae57-1e2b118db1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581768443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2581768443
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1389981179
Short name T268
Test name
Test status
Simulation time 11273274443 ps
CPU time 13.44 seconds
Started May 28 02:45:01 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 219528 kb
Host smart-81fbeed8-544a-48ff-a8e5-a0c9636b66d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389981179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1389981179
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.514126577
Short name T565
Test name
Test status
Simulation time 14509542 ps
CPU time 0.7 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 204912 kb
Host smart-b7ebeaf9-4574-40be-92ca-f72506c0225e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514126577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.514126577
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3193256020
Short name T945
Test name
Test status
Simulation time 296343907 ps
CPU time 2.1 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:45:00 PM PDT 24
Peak memory 215776 kb
Host smart-fc31272e-c6be-44a1-8fd9-24b995da5c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193256020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3193256020
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3169098410
Short name T896
Test name
Test status
Simulation time 100238336 ps
CPU time 0.74 seconds
Started May 28 02:45:11 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 204752 kb
Host smart-99a586a6-e65a-4144-92e7-8c8355f55336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169098410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3169098410
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.154290964
Short name T837
Test name
Test status
Simulation time 25609363612 ps
CPU time 54.97 seconds
Started May 28 02:45:02 PM PDT 24
Finished May 28 02:46:02 PM PDT 24
Peak memory 235236 kb
Host smart-969e3be0-506a-4437-adbc-6c591a6931b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154290964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.154290964
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2687948193
Short name T222
Test name
Test status
Simulation time 21060830830 ps
CPU time 130.68 seconds
Started May 28 02:45:10 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 248772 kb
Host smart-2a462138-cea6-4a95-8844-dab88b260ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687948193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2687948193
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2558790934
Short name T661
Test name
Test status
Simulation time 27524215440 ps
CPU time 226.86 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:48:56 PM PDT 24
Peak memory 257084 kb
Host smart-93b04d19-25cc-4582-86d8-9b958b67282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558790934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2558790934
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.216644301
Short name T900
Test name
Test status
Simulation time 214964177 ps
CPU time 2.55 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:45:11 PM PDT 24
Peak memory 223640 kb
Host smart-c0a4457e-d67e-4bb7-bb8c-51d53e3293db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216644301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.216644301
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4235174343
Short name T491
Test name
Test status
Simulation time 364054130 ps
CPU time 2.96 seconds
Started May 28 02:44:59 PM PDT 24
Finished May 28 02:45:07 PM PDT 24
Peak memory 235092 kb
Host smart-9afe6126-023a-487a-a807-8e7ceeb04678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235174343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4235174343
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.289616431
Short name T730
Test name
Test status
Simulation time 322699165 ps
CPU time 6.48 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:16 PM PDT 24
Peak memory 218400 kb
Host smart-6de0f36b-dcf4-4c9c-a97a-13834b092c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289616431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.289616431
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.171072658
Short name T863
Test name
Test status
Simulation time 26823858258 ps
CPU time 22.34 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:45:32 PM PDT 24
Peak memory 247120 kb
Host smart-bc3e685a-341a-4953-930d-dd3b40aadccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171072658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.171072658
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1657701126
Short name T436
Test name
Test status
Simulation time 177776113 ps
CPU time 3.34 seconds
Started May 28 02:45:03 PM PDT 24
Finished May 28 02:45:12 PM PDT 24
Peak memory 218472 kb
Host smart-dc373548-16c5-4989-b380-e377474b0544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657701126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1657701126
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2895817049
Short name T515
Test name
Test status
Simulation time 1862197248 ps
CPU time 9.57 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:20 PM PDT 24
Peak memory 220028 kb
Host smart-58dedc76-396b-4146-9194-bc0f5c81bd60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2895817049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2895817049
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.362569349
Short name T311
Test name
Test status
Simulation time 14521430846 ps
CPU time 42.06 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 216256 kb
Host smart-b26bd794-a786-45e7-af8e-1e40f9322e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362569349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.362569349
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.110700570
Short name T697
Test name
Test status
Simulation time 579891406 ps
CPU time 4.54 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 215768 kb
Host smart-9c54b016-833b-45b5-a947-9ecc8e8c3184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110700570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.110700570
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1445841196
Short name T891
Test name
Test status
Simulation time 69181664 ps
CPU time 2.22 seconds
Started May 28 02:44:58 PM PDT 24
Finished May 28 02:45:06 PM PDT 24
Peak memory 215976 kb
Host smart-2714dc16-8cf0-4d02-b64e-1eb1830b08fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445841196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1445841196
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1680161049
Short name T569
Test name
Test status
Simulation time 17762800 ps
CPU time 0.67 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:45:10 PM PDT 24
Peak memory 204936 kb
Host smart-c24e60c2-9b4f-43ca-9489-016907235d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680161049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1680161049
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4269948573
Short name T765
Test name
Test status
Simulation time 4913076618 ps
CPU time 18.6 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:45:27 PM PDT 24
Peak memory 233192 kb
Host smart-2ecf4003-4ace-4c3c-8d5a-e311c61647b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269948573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4269948573
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1349950775
Short name T589
Test name
Test status
Simulation time 35750637 ps
CPU time 0.7 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:11 PM PDT 24
Peak memory 204232 kb
Host smart-bad91c0e-2bf5-4dba-a1b4-5504af9cd9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349950775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1349950775
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3637637634
Short name T361
Test name
Test status
Simulation time 91064862 ps
CPU time 2.65 seconds
Started May 28 02:45:16 PM PDT 24
Finished May 28 02:45:20 PM PDT 24
Peak memory 232944 kb
Host smart-91591d8f-ab0b-4626-833d-6a166e06175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637637634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3637637634
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2684259326
Short name T675
Test name
Test status
Simulation time 34325764 ps
CPU time 0.76 seconds
Started May 28 02:45:10 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 206116 kb
Host smart-78e647ea-c0a2-4553-936e-885e79df49a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684259326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2684259326
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2992103252
Short name T301
Test name
Test status
Simulation time 11025016881 ps
CPU time 73.2 seconds
Started May 28 02:45:16 PM PDT 24
Finished May 28 02:46:31 PM PDT 24
Peak memory 236460 kb
Host smart-2c7d6716-e27a-4a70-ba4d-c379586fb81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992103252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2992103252
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2343319749
Short name T192
Test name
Test status
Simulation time 2310001876 ps
CPU time 46.57 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:58 PM PDT 24
Peak memory 249008 kb
Host smart-52cc9ccd-183e-41c9-8878-4773a5e2bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343319749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2343319749
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1301392522
Short name T895
Test name
Test status
Simulation time 29503708 ps
CPU time 2.31 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 224196 kb
Host smart-02f38582-5f15-461b-a465-d4ff333c63cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301392522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1301392522
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3395849332
Short name T324
Test name
Test status
Simulation time 1800025399 ps
CPU time 5.51 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:17 PM PDT 24
Peak memory 218388 kb
Host smart-66afdb39-5910-42ce-85bc-2b796775e2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395849332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3395849332
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2720849892
Short name T815
Test name
Test status
Simulation time 2433805126 ps
CPU time 30.52 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:45:43 PM PDT 24
Peak memory 222952 kb
Host smart-fb73c357-639c-468d-84e4-89426f6a717c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720849892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2720849892
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2858354512
Short name T860
Test name
Test status
Simulation time 9615870445 ps
CPU time 15.01 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 240232 kb
Host smart-ecd249e4-d6e1-4a65-a527-98634c40df41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858354512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2858354512
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2974346182
Short name T755
Test name
Test status
Simulation time 1510967108 ps
CPU time 5.04 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 222092 kb
Host smart-14a3708e-e4d5-4668-ba87-932437281b26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2974346182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2974346182
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.664973865
Short name T560
Test name
Test status
Simulation time 100385536 ps
CPU time 0.99 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 206348 kb
Host smart-f9e51b97-4da6-4c1c-93e3-a982ab202d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664973865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.664973865
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3050529806
Short name T334
Test name
Test status
Simulation time 40316330 ps
CPU time 0.75 seconds
Started May 28 02:45:15 PM PDT 24
Finished May 28 02:45:17 PM PDT 24
Peak memory 205052 kb
Host smart-6439ebd3-14ad-4206-a88c-506be1594127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050529806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3050529806
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2191763383
Short name T319
Test name
Test status
Simulation time 11287219 ps
CPU time 0.68 seconds
Started May 28 02:44:51 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 204996 kb
Host smart-3bd189b3-aa6d-4588-ada4-20fbf72cb900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191763383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2191763383
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2171673493
Short name T754
Test name
Test status
Simulation time 279932855 ps
CPU time 2.6 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 215932 kb
Host smart-fe933eef-8d5e-4fb2-ad4f-e84886ec2374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171673493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2171673493
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3685901015
Short name T326
Test name
Test status
Simulation time 61744076 ps
CPU time 0.73 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 205312 kb
Host smart-57545388-9bc8-4784-8dd4-d13a41c1c1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685901015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3685901015
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2562175094
Short name T128
Test name
Test status
Simulation time 6859139877 ps
CPU time 7.47 seconds
Started May 28 02:45:16 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 218176 kb
Host smart-9f73e198-3c68-41ff-85b5-6142f4de968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562175094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2562175094
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3964698665
Short name T434
Test name
Test status
Simulation time 25085790 ps
CPU time 0.73 seconds
Started May 28 02:45:08 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 204244 kb
Host smart-beccfc57-9017-44e3-8e57-afb8e75c2cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964698665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3964698665
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.120743324
Short name T770
Test name
Test status
Simulation time 355297000 ps
CPU time 2.38 seconds
Started May 28 02:45:16 PM PDT 24
Finished May 28 02:45:20 PM PDT 24
Peak memory 216212 kb
Host smart-cac5150d-1263-4c0f-a960-8b858debf5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120743324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.120743324
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1366552696
Short name T344
Test name
Test status
Simulation time 31225453 ps
CPU time 0.8 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 205952 kb
Host smart-b028a14a-cd50-4393-b17d-5cfcc02d0d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366552696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1366552696
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.106525542
Short name T490
Test name
Test status
Simulation time 7223742013 ps
CPU time 69.35 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:46:21 PM PDT 24
Peak memory 251400 kb
Host smart-1384680a-7046-41fd-a26a-a24fa98482c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106525542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.106525542
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3850639385
Short name T662
Test name
Test status
Simulation time 73708472976 ps
CPU time 234.18 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 257104 kb
Host smart-867908bd-adc8-4c2c-929c-fbd7f8d0d4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850639385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3850639385
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2110283239
Short name T459
Test name
Test status
Simulation time 4419895542 ps
CPU time 38.01 seconds
Started May 28 02:45:09 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 248868 kb
Host smart-fcac05da-f34f-4857-a1db-4e7e59ec7fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110283239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2110283239
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3689877673
Short name T527
Test name
Test status
Simulation time 176256957 ps
CPU time 4.04 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 232412 kb
Host smart-3c17d499-0168-4734-ad30-0d5e44abcc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689877673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3689877673
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2872373590
Short name T970
Test name
Test status
Simulation time 2925345526 ps
CPU time 8.86 seconds
Started May 28 02:45:08 PM PDT 24
Finished May 28 02:45:21 PM PDT 24
Peak memory 235212 kb
Host smart-a2f3d8c5-e3f2-4ef4-b263-c6149570722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872373590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2872373590
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3324719247
Short name T575
Test name
Test status
Simulation time 248802668 ps
CPU time 2.48 seconds
Started May 28 02:45:16 PM PDT 24
Finished May 28 02:45:19 PM PDT 24
Peak memory 232404 kb
Host smart-12d8595d-75ac-4300-a322-8477b3583553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324719247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3324719247
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.847664788
Short name T248
Test name
Test status
Simulation time 11141912276 ps
CPU time 16.95 seconds
Started May 28 02:45:08 PM PDT 24
Finished May 28 02:45:30 PM PDT 24
Peak memory 234020 kb
Host smart-acea48ee-fc9f-40ec-9ac2-4c93fd0725a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847664788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.847664788
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1298152303
Short name T229
Test name
Test status
Simulation time 3318337823 ps
CPU time 11.28 seconds
Started May 28 02:45:12 PM PDT 24
Finished May 28 02:45:26 PM PDT 24
Peak memory 237200 kb
Host smart-9dde0a68-41e4-47aa-b5e6-680497c0dc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298152303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1298152303
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1303193142
Short name T137
Test name
Test status
Simulation time 774565059 ps
CPU time 3.39 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:15 PM PDT 24
Peak memory 222336 kb
Host smart-2906da1d-bc97-4569-bd10-3513cc0b0bf9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1303193142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1303193142
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3713747951
Short name T954
Test name
Test status
Simulation time 9902591732 ps
CPU time 187.77 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:48:18 PM PDT 24
Peak memory 255480 kb
Host smart-b429e27b-365a-455a-a8ac-9538ecd54d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713747951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3713747951
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4228794672
Short name T748
Test name
Test status
Simulation time 16565329 ps
CPU time 0.7 seconds
Started May 28 02:45:10 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 204980 kb
Host smart-dc70e8b8-496e-4274-a657-3d1491268a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228794672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4228794672
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2612632540
Short name T594
Test name
Test status
Simulation time 268978524 ps
CPU time 1.47 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 207208 kb
Host smart-77cf3640-9917-470b-9d70-3ceb5645a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612632540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2612632540
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1614750119
Short name T521
Test name
Test status
Simulation time 634351225 ps
CPU time 7.91 seconds
Started May 28 02:45:04 PM PDT 24
Finished May 28 02:45:18 PM PDT 24
Peak memory 216072 kb
Host smart-78b3e296-48d1-45fd-866a-61e4a4b12c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614750119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1614750119
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.650225500
Short name T640
Test name
Test status
Simulation time 125348073 ps
CPU time 1.02 seconds
Started May 28 02:45:16 PM PDT 24
Finished May 28 02:45:18 PM PDT 24
Peak memory 205292 kb
Host smart-def29f2f-aeab-43d0-85a0-0274640a3fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650225500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.650225500
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2272233752
Short name T340
Test name
Test status
Simulation time 5124952458 ps
CPU time 3.78 seconds
Started May 28 02:45:10 PM PDT 24
Finished May 28 02:45:18 PM PDT 24
Peak memory 218132 kb
Host smart-98016978-3daf-476b-8337-3a9ab8d933f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272233752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2272233752
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.283372438
Short name T553
Test name
Test status
Simulation time 81443496 ps
CPU time 0.76 seconds
Started May 28 02:45:22 PM PDT 24
Finished May 28 02:45:26 PM PDT 24
Peak memory 204924 kb
Host smart-5c00e4d0-8a74-4ef5-b4f7-f01e5c5924bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283372438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.283372438
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1263629680
Short name T955
Test name
Test status
Simulation time 682637993 ps
CPU time 3.83 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 218432 kb
Host smart-2138ce11-e372-49be-aff8-2a10724a1e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263629680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1263629680
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3710580787
Short name T495
Test name
Test status
Simulation time 15726985 ps
CPU time 0.74 seconds
Started May 28 02:45:09 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 205944 kb
Host smart-36c1f978-b23e-4164-bfda-d87ec87d689a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710580787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3710580787
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.995230514
Short name T441
Test name
Test status
Simulation time 7142530317 ps
CPU time 49.36 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 234800 kb
Host smart-2c14ee57-54ca-403c-a88e-abef840787b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995230514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.995230514
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1880423696
Short name T813
Test name
Test status
Simulation time 39179075215 ps
CPU time 201.25 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:48:44 PM PDT 24
Peak memory 251400 kb
Host smart-2efa332a-8635-44c7-a9ed-911d5f1a14d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880423696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1880423696
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.446619184
Short name T626
Test name
Test status
Simulation time 8421258145 ps
CPU time 32.08 seconds
Started May 28 02:45:09 PM PDT 24
Finished May 28 02:45:45 PM PDT 24
Peak memory 232452 kb
Host smart-308caca5-6cd1-4124-a131-48f02518deaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446619184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.446619184
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1129289648
Short name T190
Test name
Test status
Simulation time 724234827 ps
CPU time 3.97 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 219440 kb
Host smart-f462bcf5-dabd-4b96-b16e-2259aae9cec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129289648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1129289648
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3505506519
Short name T244
Test name
Test status
Simulation time 306213748 ps
CPU time 5.77 seconds
Started May 28 02:45:06 PM PDT 24
Finished May 28 02:45:17 PM PDT 24
Peak memory 233528 kb
Host smart-49ae6c97-44e2-477c-95ff-470e60cd8291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505506519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3505506519
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1277328265
Short name T254
Test name
Test status
Simulation time 2711956219 ps
CPU time 4.33 seconds
Started May 28 02:45:09 PM PDT 24
Finished May 28 02:45:17 PM PDT 24
Peak memory 234232 kb
Host smart-e0a25cb9-4164-4395-9ea5-2e5040d43e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277328265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1277328265
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2252264347
Short name T402
Test name
Test status
Simulation time 535757677 ps
CPU time 7.37 seconds
Started May 28 02:45:15 PM PDT 24
Finished May 28 02:45:24 PM PDT 24
Peak memory 228224 kb
Host smart-447c7b62-a559-4cf2-9cd7-dc6e03bd30ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252264347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2252264347
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1245425319
Short name T504
Test name
Test status
Simulation time 1263831721 ps
CPU time 9.18 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:20 PM PDT 24
Peak memory 220204 kb
Host smart-0f2eb8bb-5f69-48ff-bf80-62cb05eee4c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1245425319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1245425319
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4012025793
Short name T201
Test name
Test status
Simulation time 25473399799 ps
CPU time 115.96 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:47:22 PM PDT 24
Peak memory 265088 kb
Host smart-b78c30dc-da2e-4026-bc11-d5caea9fc501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012025793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4012025793
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4146942089
Short name T647
Test name
Test status
Simulation time 11757684016 ps
CPU time 33.96 seconds
Started May 28 02:45:14 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 215968 kb
Host smart-e0538692-0c98-4465-867e-daa6951e2931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146942089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4146942089
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3040909950
Short name T42
Test name
Test status
Simulation time 7103200393 ps
CPU time 10.05 seconds
Started May 28 02:45:13 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 215920 kb
Host smart-e6cf2b2a-63b3-42f3-a6b7-32491ebb37f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040909950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3040909950
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.712229070
Short name T11
Test name
Test status
Simulation time 18542735 ps
CPU time 0.75 seconds
Started May 28 02:45:07 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 205388 kb
Host smart-e9bc3d20-8c4d-49ab-ac16-cc3915d35a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712229070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.712229070
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2303341123
Short name T719
Test name
Test status
Simulation time 1289452281 ps
CPU time 0.89 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:11 PM PDT 24
Peak memory 205292 kb
Host smart-0b0c389c-621d-47e4-9f8e-b42e1d29c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303341123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2303341123
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3309607017
Short name T241
Test name
Test status
Simulation time 2063983484 ps
CPU time 2.97 seconds
Started May 28 02:45:05 PM PDT 24
Finished May 28 02:45:13 PM PDT 24
Peak memory 218744 kb
Host smart-3512cfe1-b084-4b9d-99a2-709909e56135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309607017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3309607017
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2940756887
Short name T438
Test name
Test status
Simulation time 14243593 ps
CPU time 0.75 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:24 PM PDT 24
Peak memory 204292 kb
Host smart-ca437acb-b795-469d-9c72-de13339f88dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940756887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2940756887
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2335684119
Short name T951
Test name
Test status
Simulation time 125776932 ps
CPU time 2.43 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 218200 kb
Host smart-228a1fb6-c32e-403e-9d70-c698eda38927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335684119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2335684119
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2171674054
Short name T696
Test name
Test status
Simulation time 53118948 ps
CPU time 0.75 seconds
Started May 28 02:45:17 PM PDT 24
Finished May 28 02:45:20 PM PDT 24
Peak memory 205952 kb
Host smart-0e57f0c0-1abd-4eee-a826-1e80d2c9cf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171674054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2171674054
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3357952186
Short name T4
Test name
Test status
Simulation time 13269731284 ps
CPU time 113.01 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:47:17 PM PDT 24
Peak memory 254020 kb
Host smart-8a37867a-09ab-449e-8d72-e732f020afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357952186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3357952186
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1982633572
Short name T727
Test name
Test status
Simulation time 1815677253 ps
CPU time 32.7 seconds
Started May 28 02:45:18 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 239524 kb
Host smart-d99646e8-7451-491c-9c33-45bee14dd3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982633572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1982633572
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1035487761
Short name T744
Test name
Test status
Simulation time 5020447836 ps
CPU time 25.21 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 232512 kb
Host smart-bd352e85-5be8-4135-819f-68687e83e4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035487761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1035487761
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2778812288
Short name T138
Test name
Test status
Simulation time 4310281912 ps
CPU time 12.5 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:45:34 PM PDT 24
Peak memory 240656 kb
Host smart-82fe9afc-c777-4cfc-888c-9f658c0bb5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778812288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2778812288
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2561911345
Short name T529
Test name
Test status
Simulation time 12543850791 ps
CPU time 28.47 seconds
Started May 28 02:45:19 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 221076 kb
Host smart-af2ccfc2-36cc-4e8e-bf2d-b689922c7a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561911345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2561911345
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4255373148
Short name T176
Test name
Test status
Simulation time 904217104 ps
CPU time 7.23 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:45:33 PM PDT 24
Peak memory 233976 kb
Host smart-75ae8e1b-87c7-486d-87fb-2e2ffffd448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255373148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4255373148
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.863757274
Short name T251
Test name
Test status
Simulation time 531424561 ps
CPU time 2.46 seconds
Started May 28 02:45:26 PM PDT 24
Finished May 28 02:45:30 PM PDT 24
Peak memory 224084 kb
Host smart-9b13db80-a210-44e8-be44-c0d73cb0711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863757274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.863757274
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.296238860
Short name T579
Test name
Test status
Simulation time 1535434759 ps
CPU time 6.53 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:45:29 PM PDT 24
Peak memory 218380 kb
Host smart-08371701-696f-4349-ab03-f9991ab13032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296238860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.296238860
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3039957690
Short name T10
Test name
Test status
Simulation time 224521469 ps
CPU time 4.88 seconds
Started May 28 02:45:18 PM PDT 24
Finished May 28 02:45:24 PM PDT 24
Peak memory 222496 kb
Host smart-5de10527-50fb-4f15-a21a-8f7f6ba50d77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3039957690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3039957690
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2177033989
Short name T51
Test name
Test status
Simulation time 725871934 ps
CPU time 1.29 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:26 PM PDT 24
Peak memory 207432 kb
Host smart-116edff2-4cbd-44bf-b65b-e8e079e4258a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177033989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2177033989
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1176791603
Short name T731
Test name
Test status
Simulation time 620981141 ps
CPU time 6.58 seconds
Started May 28 02:45:22 PM PDT 24
Finished May 28 02:45:31 PM PDT 24
Peak memory 218128 kb
Host smart-c296a349-40f8-4c91-87f0-126d6747663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176791603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1176791603
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2107241313
Short name T843
Test name
Test status
Simulation time 1911552536 ps
CPU time 6.1 seconds
Started May 28 02:45:18 PM PDT 24
Finished May 28 02:45:26 PM PDT 24
Peak memory 215784 kb
Host smart-bb4bc17f-4a8b-43f2-ac34-3f2c0a8acf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107241313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2107241313
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1215761243
Short name T395
Test name
Test status
Simulation time 115830441 ps
CPU time 1.43 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 215900 kb
Host smart-2f6f185e-5fba-4d32-b15d-1a78cf77f5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215761243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1215761243
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2313062914
Short name T375
Test name
Test status
Simulation time 168207275 ps
CPU time 0.85 seconds
Started May 28 02:45:26 PM PDT 24
Finished May 28 02:45:29 PM PDT 24
Peak memory 205256 kb
Host smart-b5521080-96c3-4f66-9c48-5c64a23daa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313062914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2313062914
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4227547890
Short name T607
Test name
Test status
Simulation time 185419650 ps
CPU time 2.15 seconds
Started May 28 02:45:24 PM PDT 24
Finished May 28 02:45:29 PM PDT 24
Peak memory 207528 kb
Host smart-b76e5c26-87b7-43c6-a96b-5b48e879d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227547890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4227547890
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2484057806
Short name T467
Test name
Test status
Simulation time 18239774 ps
CPU time 0.75 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 204292 kb
Host smart-4d0f0ad6-1238-4c2a-9818-a292e00177e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484057806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2484057806
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.124434412
Short name T542
Test name
Test status
Simulation time 32360592 ps
CPU time 0.75 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:45:27 PM PDT 24
Peak memory 204908 kb
Host smart-f2aec1a0-1e3e-4a21-babf-65868fa568fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124434412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.124434412
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1677291504
Short name T449
Test name
Test status
Simulation time 36555531854 ps
CPU time 271.36 seconds
Started May 28 02:45:22 PM PDT 24
Finished May 28 02:49:56 PM PDT 24
Peak memory 248816 kb
Host smart-75a080ec-a6f9-43e4-9086-31f8e6054535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677291504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1677291504
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3392880420
Short name T180
Test name
Test status
Simulation time 203877438891 ps
CPU time 450.6 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:52:53 PM PDT 24
Peak memory 255276 kb
Host smart-15c34e2b-eea5-4081-8cef-0b73378db73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392880420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3392880420
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2996439241
Short name T69
Test name
Test status
Simulation time 791345924 ps
CPU time 12.53 seconds
Started May 28 02:45:24 PM PDT 24
Finished May 28 02:45:39 PM PDT 24
Peak memory 240580 kb
Host smart-ddc48526-fd70-437e-9edd-5204e49c9981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996439241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2996439241
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.213821521
Short name T853
Test name
Test status
Simulation time 381088229 ps
CPU time 4.89 seconds
Started May 28 02:45:24 PM PDT 24
Finished May 28 02:45:32 PM PDT 24
Peak memory 233564 kb
Host smart-bcb47c43-f4f7-4b10-80bd-dac257c89da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213821521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.213821521
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2770735752
Short name T393
Test name
Test status
Simulation time 337916388 ps
CPU time 2.06 seconds
Started May 28 02:45:19 PM PDT 24
Finished May 28 02:45:23 PM PDT 24
Peak memory 215732 kb
Host smart-0093ff58-1a94-4816-bd8d-d6cbfa1d7d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770735752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2770735752
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2219872880
Short name T606
Test name
Test status
Simulation time 168433061 ps
CPU time 2.4 seconds
Started May 28 02:45:17 PM PDT 24
Finished May 28 02:45:21 PM PDT 24
Peak memory 233212 kb
Host smart-bd0d73d1-23ff-406d-911d-0d20e0c00181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219872880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2219872880
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1485033736
Short name T913
Test name
Test status
Simulation time 157129986 ps
CPU time 2.34 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 216388 kb
Host smart-f5ffa1d6-1e70-4831-932d-4d2a76f9b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485033736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1485033736
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1459223859
Short name T72
Test name
Test status
Simulation time 423427234 ps
CPU time 4.27 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:45:30 PM PDT 24
Peak memory 222320 kb
Host smart-2b7b15b8-a685-4edf-9f2f-8909a7acabb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1459223859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1459223859
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1011911033
Short name T894
Test name
Test status
Simulation time 87861093 ps
CPU time 1.35 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:45:28 PM PDT 24
Peak memory 206536 kb
Host smart-a9baf7be-2688-48f6-8f6c-1a2f48a16bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011911033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1011911033
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.377897988
Short name T78
Test name
Test status
Simulation time 8617603963 ps
CPU time 41.4 seconds
Started May 28 02:45:26 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 216004 kb
Host smart-426072b2-f1ef-424b-9f9e-f2d92742eee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377897988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.377897988
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3009775089
Short name T485
Test name
Test status
Simulation time 5920791384 ps
CPU time 9.81 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:33 PM PDT 24
Peak memory 215912 kb
Host smart-f6ef32c1-f602-400e-8b78-824a107255e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009775089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3009775089
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1309737294
Short name T857
Test name
Test status
Simulation time 202699058 ps
CPU time 3.97 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:27 PM PDT 24
Peak memory 215984 kb
Host smart-66bb2234-fff8-467c-87e2-33766e3fd84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309737294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1309737294
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.136123837
Short name T566
Test name
Test status
Simulation time 402986259 ps
CPU time 0.91 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 205240 kb
Host smart-bca5b7f7-30eb-44d9-af29-041fd6420baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136123837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.136123837
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2268927818
Short name T934
Test name
Test status
Simulation time 400317907 ps
CPU time 7.83 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:45:34 PM PDT 24
Peak memory 232400 kb
Host smart-f8d4607c-d75a-4ccd-82e1-3858bd84e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268927818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2268927818
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4129759126
Short name T506
Test name
Test status
Simulation time 30013686 ps
CPU time 0.72 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:43 PM PDT 24
Peak memory 205296 kb
Host smart-d39b0992-9dd6-4b5f-aed8-ff2774bae167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129759126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4129759126
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.675966821
Short name T949
Test name
Test status
Simulation time 6029876323 ps
CPU time 11.83 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:56 PM PDT 24
Peak memory 234076 kb
Host smart-a09d87a4-1964-47f9-ab89-620295291817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675966821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.675966821
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.671212204
Short name T421
Test name
Test status
Simulation time 16699884 ps
CPU time 0.76 seconds
Started May 28 02:45:20 PM PDT 24
Finished May 28 02:45:24 PM PDT 24
Peak memory 204924 kb
Host smart-a7ec26c0-34bd-42c6-af36-0672875f0a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671212204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.671212204
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3808960007
Short name T577
Test name
Test status
Simulation time 12983531566 ps
CPU time 61.02 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:46:51 PM PDT 24
Peak memory 253972 kb
Host smart-c39a45aa-d751-4a2e-816d-6516430a2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808960007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3808960007
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4118991228
Short name T605
Test name
Test status
Simulation time 13790425868 ps
CPU time 79.3 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:47:03 PM PDT 24
Peak memory 253108 kb
Host smart-30aa5784-9237-4df1-a789-40b94764d7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118991228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4118991228
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.337415407
Short name T454
Test name
Test status
Simulation time 1604489031 ps
CPU time 10.29 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:58 PM PDT 24
Peak memory 248976 kb
Host smart-dd4f1db1-844d-43ab-b323-fe62f284e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337415407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.337415407
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1885755988
Short name T472
Test name
Test status
Simulation time 30481126 ps
CPU time 2.11 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:45:28 PM PDT 24
Peak memory 215760 kb
Host smart-c361acca-7126-44ff-8891-a08733a0477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885755988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1885755988
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1481858664
Short name T845
Test name
Test status
Simulation time 117549707 ps
CPU time 2.48 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:50 PM PDT 24
Peak memory 221072 kb
Host smart-9e4d64df-b292-4bd0-940b-c37beb066eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481858664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1481858664
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.878477844
Short name T510
Test name
Test status
Simulation time 170328686 ps
CPU time 2.73 seconds
Started May 28 02:45:24 PM PDT 24
Finished May 28 02:45:30 PM PDT 24
Peak memory 232436 kb
Host smart-d30e113c-011c-4a1b-be51-fff5831ef4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878477844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.878477844
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1126914719
Short name T399
Test name
Test status
Simulation time 658166616 ps
CPU time 4.33 seconds
Started May 28 02:45:22 PM PDT 24
Finished May 28 02:45:30 PM PDT 24
Peak memory 235628 kb
Host smart-9d6f968e-08a5-43d3-a58a-b6d1cf24a45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126914719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1126914719
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3738990259
Short name T868
Test name
Test status
Simulation time 13097412510 ps
CPU time 13.36 seconds
Started May 28 02:45:37 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 220124 kb
Host smart-2e593eff-14af-4e5d-a086-c24a9e213b6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3738990259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3738990259
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.800518604
Short name T674
Test name
Test status
Simulation time 2761506992 ps
CPU time 51.27 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:46:39 PM PDT 24
Peak memory 248968 kb
Host smart-18395920-484a-45b9-8625-16ece5ebc971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800518604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.800518604
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2313895099
Short name T315
Test name
Test status
Simulation time 1695779537 ps
CPU time 10.23 seconds
Started May 28 02:45:23 PM PDT 24
Finished May 28 02:45:37 PM PDT 24
Peak memory 215912 kb
Host smart-2eadc619-391d-4a03-b980-19a01e009131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313895099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2313895099
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1326604411
Short name T859
Test name
Test status
Simulation time 603422338 ps
CPU time 2.8 seconds
Started May 28 02:45:19 PM PDT 24
Finished May 28 02:45:24 PM PDT 24
Peak memory 215604 kb
Host smart-ea9e01e7-ab8b-4f03-a899-940140349d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326604411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1326604411
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.170983660
Short name T458
Test name
Test status
Simulation time 353482115 ps
CPU time 3.07 seconds
Started May 28 02:45:24 PM PDT 24
Finished May 28 02:45:30 PM PDT 24
Peak memory 215988 kb
Host smart-bbdc230a-d0ef-4a7a-866f-3f83b65767cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170983660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.170983660
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2424144511
Short name T125
Test name
Test status
Simulation time 244891026 ps
CPU time 0.87 seconds
Started May 28 02:45:21 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 205280 kb
Host smart-9857986c-f13c-48a4-b93b-7fc4ec34afd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424144511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2424144511
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2473091784
Short name T844
Test name
Test status
Simulation time 4320180294 ps
CPU time 6.4 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 217080 kb
Host smart-1df269ca-0729-4b88-ad89-eb5ae14e35d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473091784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2473091784
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.97388076
Short name T336
Test name
Test status
Simulation time 12669952 ps
CPU time 0.7 seconds
Started May 28 02:45:38 PM PDT 24
Finished May 28 02:45:43 PM PDT 24
Peak memory 204296 kb
Host smart-78be904e-b833-4a76-91bf-861ce837cefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97388076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.97388076
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3312346732
Short name T901
Test name
Test status
Simulation time 80234746 ps
CPU time 2.73 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:46 PM PDT 24
Peak memory 218300 kb
Host smart-885469c7-1d98-484a-a4c8-aea26b7fd678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312346732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3312346732
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2633391933
Short name T342
Test name
Test status
Simulation time 20613578 ps
CPU time 0.82 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 205912 kb
Host smart-8422cb2c-fcc0-4b9b-aae7-55f1ea176076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633391933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2633391933
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.292204732
Short name T169
Test name
Test status
Simulation time 23265607189 ps
CPU time 66.88 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:46:54 PM PDT 24
Peak memory 248844 kb
Host smart-4c3a8ecf-7853-42ef-9f13-b776aaf1b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292204732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.292204732
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2304816318
Short name T628
Test name
Test status
Simulation time 73391362000 ps
CPU time 76.22 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:47:02 PM PDT 24
Peak memory 232520 kb
Host smart-6ba63077-7555-4e25-be02-4911c4dfd49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304816318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2304816318
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.921310712
Short name T698
Test name
Test status
Simulation time 1110249986 ps
CPU time 13.99 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 232392 kb
Host smart-9beecd08-97e0-4130-9bcf-ebd765c24d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921310712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.921310712
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1488299130
Short name T213
Test name
Test status
Simulation time 2227386522 ps
CPU time 3.1 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:48 PM PDT 24
Peak memory 218584 kb
Host smart-922e151f-1539-4be8-9cba-39a6011015c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488299130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1488299130
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3781519320
Short name T923
Test name
Test status
Simulation time 8212604397 ps
CPU time 19.23 seconds
Started May 28 02:45:37 PM PDT 24
Finished May 28 02:45:56 PM PDT 24
Peak memory 239476 kb
Host smart-c8d8a661-7be6-4f02-a162-8aef5e91b038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781519320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3781519320
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2100360687
Short name T286
Test name
Test status
Simulation time 17345254696 ps
CPU time 15.35 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 233276 kb
Host smart-2122e74e-fef8-4431-9b67-56bf6df9458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100360687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2100360687
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1895414001
Short name T912
Test name
Test status
Simulation time 2007523541 ps
CPU time 6.29 seconds
Started May 28 02:45:37 PM PDT 24
Finished May 28 02:45:44 PM PDT 24
Peak memory 218864 kb
Host smart-ac6568d0-57f7-418b-887b-8f839a4522f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895414001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1895414001
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2866524054
Short name T479
Test name
Test status
Simulation time 1012649741 ps
CPU time 6.7 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:50 PM PDT 24
Peak memory 219436 kb
Host smart-3596f5a4-a530-4589-8255-0fa350148fb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2866524054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2866524054
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1647578910
Short name T165
Test name
Test status
Simulation time 219605906 ps
CPU time 1.15 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:50 PM PDT 24
Peak memory 206228 kb
Host smart-d5a3e365-e4f1-429a-b72a-40d2d7583878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647578910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1647578910
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1457897817
Short name T457
Test name
Test status
Simulation time 7171989528 ps
CPU time 29.96 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 216052 kb
Host smart-12b52fdc-ac20-4e1d-b510-3f66537c7c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457897817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1457897817
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3751664420
Short name T840
Test name
Test status
Simulation time 274300512 ps
CPU time 1.44 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:48 PM PDT 24
Peak memory 207216 kb
Host smart-712a71f3-c398-4ff4-bd29-b228cb46739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751664420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3751664420
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.259476968
Short name T820
Test name
Test status
Simulation time 41682092 ps
CPU time 0.71 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:50 PM PDT 24
Peak memory 204956 kb
Host smart-034b7e19-cda4-4216-a951-496863f3d693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259476968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.259476968
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3614556537
Short name T709
Test name
Test status
Simulation time 61812953 ps
CPU time 0.82 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:48 PM PDT 24
Peak memory 205304 kb
Host smart-96673c0d-ec0d-4a3a-9bb6-dacb54edf8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614556537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3614556537
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4232669899
Short name T214
Test name
Test status
Simulation time 94355423899 ps
CPU time 23.26 seconds
Started May 28 02:45:38 PM PDT 24
Finished May 28 02:46:05 PM PDT 24
Peak memory 235324 kb
Host smart-b1fed27c-afd8-4332-93ce-6a80ddaa00a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232669899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4232669899
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3184837134
Short name T676
Test name
Test status
Simulation time 15982790 ps
CPU time 0.73 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:44:21 PM PDT 24
Peak memory 204260 kb
Host smart-c2c8f6fa-0836-400c-9755-ccd3e6389eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184837134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
184837134
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3706426532
Short name T275
Test name
Test status
Simulation time 407704603 ps
CPU time 4.06 seconds
Started May 28 02:44:14 PM PDT 24
Finished May 28 02:44:20 PM PDT 24
Peak memory 219668 kb
Host smart-611c09ae-5af1-4682-a061-83b1ab38afa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706426532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3706426532
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1233109224
Short name T654
Test name
Test status
Simulation time 126772177 ps
CPU time 0.79 seconds
Started May 28 02:44:14 PM PDT 24
Finished May 28 02:44:17 PM PDT 24
Peak memory 204912 kb
Host smart-24db6e40-2412-4104-b9b9-a72d85e7d4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233109224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1233109224
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1271277891
Short name T823
Test name
Test status
Simulation time 72452886582 ps
CPU time 513.86 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:52:54 PM PDT 24
Peak memory 255716 kb
Host smart-3a285220-a714-4512-8a04-1743f7a5cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271277891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1271277891
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.741810651
Short name T973
Test name
Test status
Simulation time 350112717 ps
CPU time 5.21 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:44:20 PM PDT 24
Peak memory 217152 kb
Host smart-0e829537-8260-4615-907e-2a5b05d25a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741810651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.741810651
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2269824818
Short name T751
Test name
Test status
Simulation time 5719955414 ps
CPU time 15.42 seconds
Started May 28 02:44:11 PM PDT 24
Finished May 28 02:44:29 PM PDT 24
Peak memory 217032 kb
Host smart-ade85531-a639-47f5-ace8-7fe4187e781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269824818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2269824818
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2827745326
Short name T552
Test name
Test status
Simulation time 233488210 ps
CPU time 7.77 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:44:22 PM PDT 24
Peak memory 232388 kb
Host smart-c9ef9726-4e92-43e0-90de-5e4d26012abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827745326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2827745326
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3004504274
Short name T462
Test name
Test status
Simulation time 193809749 ps
CPU time 3.15 seconds
Started May 28 02:44:13 PM PDT 24
Finished May 28 02:44:19 PM PDT 24
Peak memory 233432 kb
Host smart-c745081f-e63b-4d6c-9eb8-d4340ebd2469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004504274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3004504274
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.431169400
Short name T442
Test name
Test status
Simulation time 2680949619 ps
CPU time 20.47 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:49 PM PDT 24
Peak memory 238792 kb
Host smart-f25df6e0-b5e7-43d8-aed0-83a4754d748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431169400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.431169400
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1407776529
Short name T885
Test name
Test status
Simulation time 26914466 ps
CPU time 1.04 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:37 PM PDT 24
Peak memory 216224 kb
Host smart-4452c872-d0eb-457d-b774-ac9cc35b735f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407776529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1407776529
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3321661245
Short name T835
Test name
Test status
Simulation time 16352103235 ps
CPU time 10.74 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:44 PM PDT 24
Peak memory 233356 kb
Host smart-2f3f7add-448c-4573-84fc-7b8a5c52923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321661245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3321661245
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3903446054
Short name T811
Test name
Test status
Simulation time 14817862519 ps
CPU time 21.55 seconds
Started May 28 02:44:14 PM PDT 24
Finished May 28 02:44:38 PM PDT 24
Peak memory 223292 kb
Host smart-27da612b-cf35-4707-8451-f228e88acf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903446054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3903446054
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.878816462
Short name T482
Test name
Test status
Simulation time 8034946423 ps
CPU time 9.8 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 222684 kb
Host smart-16596be5-d991-4caf-bdf2-185d6f4223f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=878816462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.878816462
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3003384657
Short name T58
Test name
Test status
Simulation time 250207754 ps
CPU time 1.09 seconds
Started May 28 02:44:11 PM PDT 24
Finished May 28 02:44:15 PM PDT 24
Peak memory 234724 kb
Host smart-ee62912b-804a-4fe4-9535-c2daa5b033f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003384657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3003384657
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3930853799
Short name T704
Test name
Test status
Simulation time 7137511345 ps
CPU time 23.59 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:57 PM PDT 24
Peak memory 219464 kb
Host smart-6304670c-3043-4f4e-a493-576b584ce309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930853799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3930853799
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.867451435
Short name T847
Test name
Test status
Simulation time 385335248 ps
CPU time 2.42 seconds
Started May 28 02:44:17 PM PDT 24
Finished May 28 02:44:23 PM PDT 24
Peak memory 215644 kb
Host smart-d352792e-86bd-4266-bc73-c3abb45d88ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867451435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.867451435
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3434936339
Short name T354
Test name
Test status
Simulation time 25482016 ps
CPU time 1.14 seconds
Started May 28 02:44:18 PM PDT 24
Finished May 28 02:44:23 PM PDT 24
Peak memory 206844 kb
Host smart-8d818915-9fd3-4d26-90cb-d4ebb8e21e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434936339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3434936339
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1779286054
Short name T902
Test name
Test status
Simulation time 123218619 ps
CPU time 0.84 seconds
Started May 28 02:44:22 PM PDT 24
Finished May 28 02:44:26 PM PDT 24
Peak memory 205312 kb
Host smart-062eaff5-aa3d-4f1c-bcf0-eaa12ed8d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779286054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1779286054
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1488725433
Short name T638
Test name
Test status
Simulation time 14350188681 ps
CPU time 8.97 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:38 PM PDT 24
Peak memory 232388 kb
Host smart-17070663-c50c-4b83-8c3f-29b52e8ef1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488725433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1488725433
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.457701830
Short name T966
Test name
Test status
Simulation time 26088527 ps
CPU time 0.73 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:46 PM PDT 24
Peak memory 205224 kb
Host smart-42831551-e62a-43d1-a302-2606667c5c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457701830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.457701830
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2068214411
Short name T652
Test name
Test status
Simulation time 73675236 ps
CPU time 3.2 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 234000 kb
Host smart-c2d877cf-28d6-4949-b2c7-f70f8482a435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068214411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2068214411
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3437309385
Short name T558
Test name
Test status
Simulation time 23280147 ps
CPU time 0.76 seconds
Started May 28 02:45:38 PM PDT 24
Finished May 28 02:45:41 PM PDT 24
Peak memory 204916 kb
Host smart-fbcc91d2-86e3-4e59-94a9-895803fa5dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437309385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3437309385
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3045224974
Short name T922
Test name
Test status
Simulation time 2453234180 ps
CPU time 20.06 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:46:07 PM PDT 24
Peak memory 235876 kb
Host smart-c481bf04-1669-41c6-b9f4-e9e2541e58f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045224974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3045224974
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3721989805
Short name T240
Test name
Test status
Simulation time 3851509135 ps
CPU time 40.44 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:46:24 PM PDT 24
Peak memory 250916 kb
Host smart-96e166bd-8075-493d-846a-86455f3faba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721989805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3721989805
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3814189824
Short name T216
Test name
Test status
Simulation time 26994483031 ps
CPU time 288.99 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:50:37 PM PDT 24
Peak memory 255504 kb
Host smart-2678219e-7af3-4aea-9a0b-5253b7f67428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814189824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3814189824
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.369375110
Short name T911
Test name
Test status
Simulation time 4637008329 ps
CPU time 51.22 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:46:37 PM PDT 24
Peak memory 232408 kb
Host smart-4d219378-1977-427d-a31d-1fc7cfcedf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369375110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.369375110
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2334494390
Short name T583
Test name
Test status
Simulation time 1366019560 ps
CPU time 14.8 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:58 PM PDT 24
Peak memory 217992 kb
Host smart-2df013fd-328d-4033-874a-fb635933eea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334494390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2334494390
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1813579240
Short name T878
Test name
Test status
Simulation time 17229113556 ps
CPU time 18.31 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:46:06 PM PDT 24
Peak memory 240340 kb
Host smart-d109a114-f70c-4646-a7ad-cdbde3bfdef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813579240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1813579240
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1422189681
Short name T124
Test name
Test status
Simulation time 6262088370 ps
CPU time 18.06 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 228732 kb
Host smart-c7d48841-4ec6-41c0-b0b4-41c09b7f84f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422189681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1422189681
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2334009046
Short name T581
Test name
Test status
Simulation time 1912141587 ps
CPU time 11.82 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 227664 kb
Host smart-a3f5fe5e-0bf7-4e9f-bd1a-87dd0b3e935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334009046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2334009046
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3811046893
Short name T778
Test name
Test status
Simulation time 159470104 ps
CPU time 3.13 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:46 PM PDT 24
Peak memory 218532 kb
Host smart-46064825-33b7-4bc8-a3ae-50e85d44dd43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3811046893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3811046893
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.205025012
Short name T876
Test name
Test status
Simulation time 42670628 ps
CPU time 0.99 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:50 PM PDT 24
Peak memory 206108 kb
Host smart-68858c1b-589e-4806-9ddb-80d4fd223bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205025012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.205025012
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1861751004
Short name T394
Test name
Test status
Simulation time 367773553 ps
CPU time 2.74 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:45 PM PDT 24
Peak memory 216092 kb
Host smart-55c7d48a-c71e-4981-ad08-8fc6adb2a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861751004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1861751004
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.138869348
Short name T580
Test name
Test status
Simulation time 8692463601 ps
CPU time 23.71 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:46:14 PM PDT 24
Peak memory 215968 kb
Host smart-83f1d846-992f-4992-974b-010f10b2021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138869348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.138869348
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.448398656
Short name T832
Test name
Test status
Simulation time 31373076 ps
CPU time 0.75 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 205008 kb
Host smart-f679fff7-f671-4660-a36a-c72ae7a41bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448398656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.448398656
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3560063366
Short name T864
Test name
Test status
Simulation time 200319675 ps
CPU time 0.72 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:50 PM PDT 24
Peak memory 205348 kb
Host smart-48748acd-f9fc-4d41-9d8d-9bd8b1a8ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560063366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3560063366
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.495474871
Short name T663
Test name
Test status
Simulation time 24206691807 ps
CPU time 19.99 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 231588 kb
Host smart-c237f2c4-04e9-4d81-bd6f-7b7348fa8fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495474871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.495474871
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1059382185
Short name T333
Test name
Test status
Simulation time 24228048 ps
CPU time 0.72 seconds
Started May 28 02:45:44 PM PDT 24
Finished May 28 02:45:53 PM PDT 24
Peak memory 204148 kb
Host smart-65576ea2-4c87-43fd-bdd8-62d680980ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059382185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1059382185
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1538595152
Short name T633
Test name
Test status
Simulation time 99893662 ps
CPU time 2.34 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:53 PM PDT 24
Peak memory 233560 kb
Host smart-8d68fb84-2cec-402c-82d7-878d6a1aba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538595152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1538595152
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2281862664
Short name T518
Test name
Test status
Simulation time 30187752 ps
CPU time 0.75 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 204912 kb
Host smart-ed08735d-e877-447f-9b7c-bead42b17385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281862664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2281862664
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.275272232
Short name T898
Test name
Test status
Simulation time 56139012523 ps
CPU time 73.76 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:47:04 PM PDT 24
Peak memory 239904 kb
Host smart-5b14e6d2-13bb-4392-8ea0-460163475946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275272232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.275272232
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1122985334
Short name T831
Test name
Test status
Simulation time 427960718476 ps
CPU time 184.4 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:48:55 PM PDT 24
Peak memory 248936 kb
Host smart-f61f7b31-5429-425b-a137-61346cf68742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122985334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1122985334
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.686942671
Short name T284
Test name
Test status
Simulation time 19142753498 ps
CPU time 182.95 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:48:55 PM PDT 24
Peak memory 256232 kb
Host smart-8404064a-469f-441f-8a5d-71cb5e19ed04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686942671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.686942671
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1416139221
Short name T882
Test name
Test status
Simulation time 96242151 ps
CPU time 5.79 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:56 PM PDT 24
Peak memory 224160 kb
Host smart-e72241df-2fe8-4cd3-9467-697d47f9ec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416139221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1416139221
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.967948758
Short name T916
Test name
Test status
Simulation time 293780017 ps
CPU time 3.4 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 232820 kb
Host smart-aa900989-f0d1-4458-bc45-5428f8d24b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967948758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.967948758
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2874868089
Short name T568
Test name
Test status
Simulation time 36026453 ps
CPU time 2.48 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:50 PM PDT 24
Peak memory 220948 kb
Host smart-f46c72a3-ea1f-4715-bc90-bfc63e98695d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874868089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2874868089
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.4271838737
Short name T545
Test name
Test status
Simulation time 796856119 ps
CPU time 6.21 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 234892 kb
Host smart-8932f92d-972c-4842-9b92-ef862f0e299c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271838737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.4271838737
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.98916902
Short name T470
Test name
Test status
Simulation time 27882320593 ps
CPU time 14.95 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:46:03 PM PDT 24
Peak memory 234244 kb
Host smart-22cf8afe-f732-4819-bce4-f9805454d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98916902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.98916902
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3487124184
Short name T136
Test name
Test status
Simulation time 740661734 ps
CPU time 7.17 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:59 PM PDT 24
Peak memory 222592 kb
Host smart-ab622aa6-9c04-4f92-a410-3fee3f322165
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3487124184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3487124184
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.416736850
Short name T312
Test name
Test status
Simulation time 36629719951 ps
CPU time 44.25 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:46:35 PM PDT 24
Peak memory 215948 kb
Host smart-251d69b2-4d7a-4574-b61a-414a293c0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416736850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.416736850
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2468908936
Short name T525
Test name
Test status
Simulation time 9433121784 ps
CPU time 2.9 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 215912 kb
Host smart-2b54610f-1126-4fd9-acc3-6d557f141d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468908936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2468908936
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3282867584
Short name T678
Test name
Test status
Simulation time 183654235 ps
CPU time 2.57 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:48 PM PDT 24
Peak memory 215936 kb
Host smart-04321e1e-8bf9-4838-a0cc-e0dc135e99e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282867584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3282867584
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.25048612
Short name T370
Test name
Test status
Simulation time 49295071 ps
CPU time 0.8 seconds
Started May 28 02:45:38 PM PDT 24
Finished May 28 02:45:42 PM PDT 24
Peak memory 205328 kb
Host smart-810360cc-2ef8-45d2-ac22-c72209c13cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25048612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.25048612
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3066107071
Short name T586
Test name
Test status
Simulation time 3060851556 ps
CPU time 9.77 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:55 PM PDT 24
Peak memory 222948 kb
Host smart-54ff641f-b707-4669-a312-55a5f08d4139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066107071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3066107071
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2604319509
Short name T890
Test name
Test status
Simulation time 20813790 ps
CPU time 0.73 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 204140 kb
Host smart-a2f135de-c85b-45a8-86e3-3cc0740e8f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604319509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2604319509
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1381340511
Short name T475
Test name
Test status
Simulation time 135172499 ps
CPU time 2.24 seconds
Started May 28 02:45:44 PM PDT 24
Finished May 28 02:45:55 PM PDT 24
Peak memory 233672 kb
Host smart-87c9999f-553f-4bd0-bbba-970200bd04e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381340511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1381340511
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.571255559
Short name T870
Test name
Test status
Simulation time 44772470 ps
CPU time 0.72 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 204912 kb
Host smart-e14e2577-e490-4e68-b551-a694d08e6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571255559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.571255559
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1822565509
Short name T193
Test name
Test status
Simulation time 24481966224 ps
CPU time 201.05 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:49:13 PM PDT 24
Peak memory 264584 kb
Host smart-6282e06f-979f-4eab-b4e9-3147648f25e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822565509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1822565509
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1692934760
Short name T279
Test name
Test status
Simulation time 15709015510 ps
CPU time 97.51 seconds
Started May 28 02:45:45 PM PDT 24
Finished May 28 02:47:32 PM PDT 24
Peak memory 250964 kb
Host smart-e8c972bc-2ab6-4466-b44b-4645c934c628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692934760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1692934760
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2567215476
Short name T517
Test name
Test status
Simulation time 1901304174 ps
CPU time 36.68 seconds
Started May 28 02:45:44 PM PDT 24
Finished May 28 02:46:30 PM PDT 24
Peak memory 251540 kb
Host smart-b6b4731d-afd8-49eb-aecb-4098f5805d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567215476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2567215476
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2829573266
Short name T162
Test name
Test status
Simulation time 119679507 ps
CPU time 3.69 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:56 PM PDT 24
Peak memory 240616 kb
Host smart-0e778f47-64e7-4304-9851-c7094ff65e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829573266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2829573266
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2553294560
Short name T858
Test name
Test status
Simulation time 136393097 ps
CPU time 3.95 seconds
Started May 28 02:45:45 PM PDT 24
Finished May 28 02:45:58 PM PDT 24
Peak memory 234364 kb
Host smart-3dbc42d3-26db-4c9a-a555-99cb61b75886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553294560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2553294560
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.755704755
Short name T673
Test name
Test status
Simulation time 6392287304 ps
CPU time 80.86 seconds
Started May 28 02:45:45 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 220144 kb
Host smart-00b41f10-84bb-40ff-8ffe-42b32260555d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755704755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.755704755
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1815091546
Short name T418
Test name
Test status
Simulation time 11045263441 ps
CPU time 28.7 seconds
Started May 28 02:45:45 PM PDT 24
Finished May 28 02:46:23 PM PDT 24
Peak memory 240620 kb
Host smart-e397681a-686e-4bb6-9457-2e6dd05dad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815091546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1815091546
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3339734024
Short name T236
Test name
Test status
Simulation time 7213754605 ps
CPU time 4.16 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:55 PM PDT 24
Peak memory 218228 kb
Host smart-e89b056c-c6f5-4972-82f3-445c39792424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339734024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3339734024
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1903379080
Short name T554
Test name
Test status
Simulation time 2133776817 ps
CPU time 11.5 seconds
Started May 28 02:45:45 PM PDT 24
Finished May 28 02:46:06 PM PDT 24
Peak memory 218812 kb
Host smart-74c4a663-7324-41b0-9a64-28c738820e65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1903379080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1903379080
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.667417079
Short name T197
Test name
Test status
Simulation time 19860872180 ps
CPU time 235.25 seconds
Started May 28 02:45:45 PM PDT 24
Finished May 28 02:49:49 PM PDT 24
Peak memory 273468 kb
Host smart-25e5624c-fba4-4299-8046-b02fac59c8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667417079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.667417079
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4236957765
Short name T493
Test name
Test status
Simulation time 18787285295 ps
CPU time 27.69 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:46:20 PM PDT 24
Peak memory 216096 kb
Host smart-d718a83a-f6a8-47bb-89e9-32c9c6afa386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236957765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4236957765
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3476365851
Short name T849
Test name
Test status
Simulation time 7694348805 ps
CPU time 6.44 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:57 PM PDT 24
Peak memory 215852 kb
Host smart-9bbd76d1-b85c-4d04-838b-9562deee893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476365851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3476365851
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.694471583
Short name T424
Test name
Test status
Simulation time 944172146 ps
CPU time 2.64 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:55 PM PDT 24
Peak memory 215816 kb
Host smart-b44218b0-b37b-4066-b449-5865c7ac47be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694471583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.694471583
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3648490799
Short name T3
Test name
Test status
Simulation time 167660114 ps
CPU time 0.82 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 205276 kb
Host smart-8c218073-d925-467c-b394-b9d3d6d2cdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648490799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3648490799
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.583483299
Short name T327
Test name
Test status
Simulation time 131242701 ps
CPU time 2.12 seconds
Started May 28 02:45:44 PM PDT 24
Finished May 28 02:45:55 PM PDT 24
Peak memory 215760 kb
Host smart-4ee51a07-1e11-449d-9892-9e870a0d596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583483299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.583483299
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.660353080
Short name T779
Test name
Test status
Simulation time 37866183 ps
CPU time 0.71 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 204916 kb
Host smart-064f9f76-3d4f-4645-9467-9ac11927ebf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660353080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.660353080
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2449042447
Short name T822
Test name
Test status
Simulation time 193169317 ps
CPU time 5.84 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 220912 kb
Host smart-31971ae6-fa99-4eab-b2dc-2e17c9c664b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449042447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2449042447
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1714871104
Short name T598
Test name
Test status
Simulation time 37631711 ps
CPU time 0.78 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 205924 kb
Host smart-636b462b-7c56-4c73-b28e-00a8ef6959ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714871104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1714871104
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1388919723
Short name T405
Test name
Test status
Simulation time 1932516692 ps
CPU time 44.87 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:46:33 PM PDT 24
Peak memory 255844 kb
Host smart-46303379-1294-41ac-a92f-97d204d63970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388919723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1388919723
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2785144733
Short name T185
Test name
Test status
Simulation time 446581506167 ps
CPU time 699.71 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:57:30 PM PDT 24
Peak memory 255600 kb
Host smart-69d8543d-65c5-4f61-8ae5-88874f29e0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785144733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2785144733
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2387953033
Short name T608
Test name
Test status
Simulation time 4311875035 ps
CPU time 11.04 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:58 PM PDT 24
Peak memory 224272 kb
Host smart-aab24e5a-c949-463f-aefb-3ab849e993af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387953033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2387953033
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.972848249
Short name T231
Test name
Test status
Simulation time 2740346494 ps
CPU time 9.67 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:56 PM PDT 24
Peak memory 234736 kb
Host smart-64b7d948-1300-4dfe-bd4a-147de037fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972848249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.972848249
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1463219138
Short name T963
Test name
Test status
Simulation time 3206751400 ps
CPU time 22.41 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:46:11 PM PDT 24
Peak memory 246252 kb
Host smart-38f9ac20-4593-4f05-be26-80f9af054769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463219138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1463219138
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3748016639
Short name T272
Test name
Test status
Simulation time 26555675983 ps
CPU time 22.43 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:46:11 PM PDT 24
Peak memory 219588 kb
Host smart-04bd1bbe-10d3-4fe4-b1ae-735fa8f18118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748016639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3748016639
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2734214103
Short name T243
Test name
Test status
Simulation time 1826544712 ps
CPU time 6.03 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 233164 kb
Host smart-90cecf09-040f-4939-aa45-293aaf0976a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734214103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2734214103
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.254858774
Short name T377
Test name
Test status
Simulation time 391279102 ps
CPU time 4.86 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:53 PM PDT 24
Peak memory 222752 kb
Host smart-889446f6-6e82-4cf0-afe4-b51267632377
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=254858774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.254858774
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1474365996
Short name T867
Test name
Test status
Simulation time 2772741185 ps
CPU time 16.06 seconds
Started May 28 02:45:45 PM PDT 24
Finished May 28 02:46:10 PM PDT 24
Peak memory 215976 kb
Host smart-1559ebc7-663e-4b3a-b269-7d8fa5e9bba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474365996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1474365996
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2420541651
Short name T401
Test name
Test status
Simulation time 136273611 ps
CPU time 0.99 seconds
Started May 28 02:45:49 PM PDT 24
Finished May 28 02:45:59 PM PDT 24
Peak memory 205368 kb
Host smart-c5e96e56-8261-4654-8b3e-a185142cf85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420541651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2420541651
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.637373871
Short name T974
Test name
Test status
Simulation time 38189632 ps
CPU time 0.94 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 206656 kb
Host smart-8acd403c-a409-4a27-8812-17b8bd00d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637373871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.637373871
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3950901052
Short name T335
Test name
Test status
Simulation time 61614574 ps
CPU time 0.72 seconds
Started May 28 02:45:45 PM PDT 24
Finished May 28 02:45:55 PM PDT 24
Peak memory 205296 kb
Host smart-cb41d2a8-4b9e-4ebb-a9ea-d6e7ec086ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950901052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3950901052
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.849552465
Short name T622
Test name
Test status
Simulation time 2294614833 ps
CPU time 7.66 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:57 PM PDT 24
Peak memory 240324 kb
Host smart-60620597-07db-4e6f-8e5c-f92018899681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849552465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.849552465
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.269675746
Short name T481
Test name
Test status
Simulation time 41770335 ps
CPU time 0.69 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:53 PM PDT 24
Peak memory 204800 kb
Host smart-4c55e6a8-fccd-4c5b-a096-89f9575cf745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269675746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.269675746
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3111330762
Short name T374
Test name
Test status
Simulation time 224716631 ps
CPU time 3.44 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 234260 kb
Host smart-96044491-0cc9-481f-ba49-e27e33d5bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111330762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3111330762
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.602215028
Short name T406
Test name
Test status
Simulation time 67244962 ps
CPU time 0.79 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 205924 kb
Host smart-b5d03312-0474-4228-9176-3c848f21deca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602215028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.602215028
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1880058984
Short name T471
Test name
Test status
Simulation time 129971600 ps
CPU time 0.75 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 215440 kb
Host smart-26dd59f5-864c-4146-b028-ccec2874e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880058984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1880058984
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1109107339
Short name T184
Test name
Test status
Simulation time 79141976103 ps
CPU time 404.73 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:52:37 PM PDT 24
Peak memory 248892 kb
Host smart-39a8912c-3340-4d4d-a656-36b3fe5fb836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109107339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1109107339
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.732056636
Short name T47
Test name
Test status
Simulation time 3362928177 ps
CPU time 26.12 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 217388 kb
Host smart-8ea9e47e-9ad2-444f-af71-d0619914ece1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732056636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.732056636
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1314399405
Short name T968
Test name
Test status
Simulation time 5438031309 ps
CPU time 22.02 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:46:14 PM PDT 24
Peak memory 240632 kb
Host smart-52b3e31c-bea3-4672-83fd-1c3d6ad98b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314399405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1314399405
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1934865678
Short name T235
Test name
Test status
Simulation time 1558681409 ps
CPU time 16.59 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:46:02 PM PDT 24
Peak memory 218248 kb
Host smart-fcead37b-f984-4411-9fcb-cb0f7e61b447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934865678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1934865678
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2101289932
Short name T455
Test name
Test status
Simulation time 30033090 ps
CPU time 2.12 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:54 PM PDT 24
Peak memory 215704 kb
Host smart-2f33782e-76cc-4cfb-805f-e6d3a459bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101289932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2101289932
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2628503102
Short name T126
Test name
Test status
Simulation time 232943336 ps
CPU time 5.28 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:54 PM PDT 24
Peak memory 219688 kb
Host smart-bed684db-afc5-4a67-9948-67fa1deb4ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628503102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2628503102
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2445273751
Short name T530
Test name
Test status
Simulation time 65035475 ps
CPU time 2.96 seconds
Started May 28 02:45:41 PM PDT 24
Finished May 28 02:45:52 PM PDT 24
Peak memory 233360 kb
Host smart-c2da5ecd-d550-4dbf-9826-39f71f738ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445273751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2445273751
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2697485925
Short name T899
Test name
Test status
Simulation time 1060436406 ps
CPU time 8.05 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:59 PM PDT 24
Peak memory 219796 kb
Host smart-8b9f474f-ad57-4eb1-994e-152814510006
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2697485925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2697485925
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3659577909
Short name T805
Test name
Test status
Simulation time 116554423 ps
CPU time 0.95 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 205996 kb
Host smart-1081c89e-7e76-428f-866c-c84c65117f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659577909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3659577909
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3945626687
Short name T404
Test name
Test status
Simulation time 38234774 ps
CPU time 0.72 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:48 PM PDT 24
Peak memory 205064 kb
Host smart-a30441c8-cdb0-47ff-9f8a-438bfe75b9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945626687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3945626687
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4093756793
Short name T45
Test name
Test status
Simulation time 607660744 ps
CPU time 5.34 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:57 PM PDT 24
Peak memory 215788 kb
Host smart-966103ad-1818-468e-b6cc-327ce620ba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093756793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4093756793
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3596040764
Short name T414
Test name
Test status
Simulation time 59634741 ps
CPU time 0.91 seconds
Started May 28 02:45:40 PM PDT 24
Finished May 28 02:45:49 PM PDT 24
Peak memory 206788 kb
Host smart-1d88811d-706d-4002-a5a2-ac8bea16b194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596040764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3596040764
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4079406366
Short name T332
Test name
Test status
Simulation time 91167495 ps
CPU time 0.85 seconds
Started May 28 02:45:39 PM PDT 24
Finished May 28 02:45:44 PM PDT 24
Peak memory 205288 kb
Host smart-3773f774-9277-4cdf-b55f-ca191aa57e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079406366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4079406366
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1737965486
Short name T189
Test name
Test status
Simulation time 809778637 ps
CPU time 6.29 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:58 PM PDT 24
Peak memory 232380 kb
Host smart-ac253143-3a0e-4091-8f76-5940c21d482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737965486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1737965486
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.674198661
Short name T753
Test name
Test status
Simulation time 13725247 ps
CPU time 0.73 seconds
Started May 28 02:45:51 PM PDT 24
Finished May 28 02:46:00 PM PDT 24
Peak memory 204316 kb
Host smart-bb68d7e4-8543-477a-96d3-f0155689fcc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674198661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.674198661
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3709973095
Short name T420
Test name
Test status
Simulation time 419435194 ps
CPU time 5.25 seconds
Started May 28 02:45:51 PM PDT 24
Finished May 28 02:46:05 PM PDT 24
Peak memory 233012 kb
Host smart-e6117a09-c5f1-4dd1-9a14-3b3a02ef3a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709973095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3709973095
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2925969402
Short name T322
Test name
Test status
Simulation time 41099154 ps
CPU time 0.81 seconds
Started May 28 02:45:43 PM PDT 24
Finished May 28 02:45:53 PM PDT 24
Peak memory 205752 kb
Host smart-b1615cbf-59d1-4b45-8d6d-7c127cba1a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925969402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2925969402
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1361142447
Short name T643
Test name
Test status
Simulation time 1534843523 ps
CPU time 14.01 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:14 PM PDT 24
Peak memory 234392 kb
Host smart-c4ce01b4-d143-4a4c-8e09-bfbd8c55c589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361142447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1361142447
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.744514012
Short name T905
Test name
Test status
Simulation time 7195504101 ps
CPU time 89.36 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:47:30 PM PDT 24
Peak memory 248908 kb
Host smart-1e7e9df6-1dc8-4da2-b5bb-ceb6534664f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744514012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.744514012
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1926868544
Short name T288
Test name
Test status
Simulation time 5472531600 ps
CPU time 90.85 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:47:32 PM PDT 24
Peak memory 252364 kb
Host smart-e13cf253-bdc8-47a4-85ef-aa46d2a20bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926868544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1926868544
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.789612405
Short name T484
Test name
Test status
Simulation time 1807575011 ps
CPU time 4.38 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:05 PM PDT 24
Peak memory 232364 kb
Host smart-cc07345f-4f35-4eca-b33d-01414ca26a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789612405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.789612405
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.529231426
Short name T494
Test name
Test status
Simulation time 31131404192 ps
CPU time 24.48 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:46:25 PM PDT 24
Peak memory 224236 kb
Host smart-1537a737-e3a0-4a2c-8445-7ce1f1db380a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529231426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.529231426
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2859560144
Short name T480
Test name
Test status
Simulation time 700178314 ps
CPU time 7.99 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:08 PM PDT 24
Peak memory 218212 kb
Host smart-24e410bf-b003-4654-a468-10505c031c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859560144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2859560144
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3392507655
Short name T437
Test name
Test status
Simulation time 61079862 ps
CPU time 2.34 seconds
Started May 28 02:45:51 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 220980 kb
Host smart-9be6b1c2-09c7-4a4e-bf82-c218c44b5792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392507655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3392507655
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3792197019
Short name T233
Test name
Test status
Simulation time 12019892375 ps
CPU time 10.14 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:11 PM PDT 24
Peak memory 237860 kb
Host smart-ff042d44-416b-4328-a942-7f4a1f40199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792197019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3792197019
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3461298776
Short name T941
Test name
Test status
Simulation time 1274831725 ps
CPU time 14.75 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:18 PM PDT 24
Peak memory 219708 kb
Host smart-ecc0618c-528b-46d4-ad3e-0f9e89b31ba1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3461298776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3461298776
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.757698202
Short name T852
Test name
Test status
Simulation time 196660244 ps
CPU time 1.09 seconds
Started May 28 02:45:56 PM PDT 24
Finished May 28 02:46:05 PM PDT 24
Peak memory 206380 kb
Host smart-511c5682-c2ad-41e8-95e6-c1f041f05f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757698202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.757698202
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.44077703
Short name T488
Test name
Test status
Simulation time 1572199197 ps
CPU time 14.59 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:14 PM PDT 24
Peak memory 215940 kb
Host smart-3fc49f48-77b4-4328-bf6f-d41d2b5e34cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44077703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.44077703
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3051016286
Short name T16
Test name
Test status
Simulation time 12936838149 ps
CPU time 7.74 seconds
Started May 28 02:45:42 PM PDT 24
Finished May 28 02:45:59 PM PDT 24
Peak memory 215864 kb
Host smart-35316419-0ca8-47a9-8dd4-817765f1b2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051016286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3051016286
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.258624625
Short name T63
Test name
Test status
Simulation time 272779376 ps
CPU time 2.23 seconds
Started May 28 02:45:50 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 215896 kb
Host smart-52170c25-0b16-4700-ab69-df8ab550d465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258624625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.258624625
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.250954652
Short name T412
Test name
Test status
Simulation time 17322752 ps
CPU time 0.68 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:08 PM PDT 24
Peak memory 204960 kb
Host smart-6b61eef6-d9d8-499e-94e0-71e43060a420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250954652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.250954652
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2735107099
Short name T237
Test name
Test status
Simulation time 1484389345 ps
CPU time 4.04 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:11 PM PDT 24
Peak memory 219840 kb
Host smart-7af52bf9-9ae1-4bb4-8d3c-2e5a5a48ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735107099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2735107099
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3911666911
Short name T466
Test name
Test status
Simulation time 41893971 ps
CPU time 0.71 seconds
Started May 28 02:45:50 PM PDT 24
Finished May 28 02:45:59 PM PDT 24
Peak memory 205280 kb
Host smart-f7caaf1b-e18c-4433-9a99-fef9ee29b175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911666911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3911666911
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1742845472
Short name T390
Test name
Test status
Simulation time 121219280 ps
CPU time 2.31 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:46:03 PM PDT 24
Peak memory 232344 kb
Host smart-9de6e9b6-33f2-43a2-be0f-842db64ceff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742845472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1742845472
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.448530135
Short name T50
Test name
Test status
Simulation time 26805754 ps
CPU time 0.75 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 205880 kb
Host smart-7967834b-9eee-48bd-b3e7-f4ad105678ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448530135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.448530135
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3659551348
Short name T167
Test name
Test status
Simulation time 42037260029 ps
CPU time 146.59 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:48:26 PM PDT 24
Peak memory 248832 kb
Host smart-d5193569-7827-40c5-8d90-ee457dc38303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659551348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3659551348
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1329780727
Short name T308
Test name
Test status
Simulation time 249129074 ps
CPU time 7.02 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:46:12 PM PDT 24
Peak memory 232408 kb
Host smart-2e7caa2d-ccc0-486f-900b-b4839a3b5948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329780727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1329780727
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.226142479
Short name T267
Test name
Test status
Simulation time 224686330 ps
CPU time 4.16 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:46:05 PM PDT 24
Peak memory 218032 kb
Host smart-1b611c4d-9008-46fc-966d-cfa2d21f9bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226142479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.226142479
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3081789183
Short name T792
Test name
Test status
Simulation time 1095184247 ps
CPU time 13.94 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 222776 kb
Host smart-cdbc2807-012f-4169-83ab-f4c015bbc758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081789183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3081789183
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4222342703
Short name T6
Test name
Test status
Simulation time 107092513 ps
CPU time 2.55 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:10 PM PDT 24
Peak memory 218480 kb
Host smart-8eacfb50-afdf-4a45-99e1-f537095f8383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222342703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4222342703
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2860744627
Short name T879
Test name
Test status
Simulation time 5289296957 ps
CPU time 11.5 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:46:16 PM PDT 24
Peak memory 234960 kb
Host smart-1a3445a2-278a-4bb9-8d1e-44412ababf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860744627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2860744627
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3045655079
Short name T535
Test name
Test status
Simulation time 1213870743 ps
CPU time 6.92 seconds
Started May 28 02:45:51 PM PDT 24
Finished May 28 02:46:06 PM PDT 24
Peak memory 222584 kb
Host smart-463592c3-cdd5-4c49-879c-40278e807b68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3045655079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3045655079
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2725758098
Short name T182
Test name
Test status
Simulation time 25383141753 ps
CPU time 255.07 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:50:16 PM PDT 24
Peak memory 251952 kb
Host smart-704ef246-396a-4b7b-8de2-4cd0ee02ac30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725758098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2725758098
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1835644514
Short name T461
Test name
Test status
Simulation time 7704862894 ps
CPU time 11.09 seconds
Started May 28 02:45:56 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 216004 kb
Host smart-d5aed57a-4c6d-4987-a6a5-4b5eff78c093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835644514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1835644514
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.324770639
Short name T959
Test name
Test status
Simulation time 13868829950 ps
CPU time 12.96 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:46:14 PM PDT 24
Peak memory 215880 kb
Host smart-837f1e78-233a-48f7-9eb5-111cf12f232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324770639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.324770639
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2088545522
Short name T396
Test name
Test status
Simulation time 19017085 ps
CPU time 0.79 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 205368 kb
Host smart-670371aa-1d7e-49df-a074-7f14884ed7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088545522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2088545522
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3491505758
Short name T944
Test name
Test status
Simulation time 26547564 ps
CPU time 0.75 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 205312 kb
Host smart-edda57e1-0310-4d46-a950-952660aeaf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491505758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3491505758
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2199800279
Short name T230
Test name
Test status
Simulation time 18550713090 ps
CPU time 15.08 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:22 PM PDT 24
Peak memory 233868 kb
Host smart-a63a4d0c-fa58-49a6-84b8-b94373df8281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199800279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2199800279
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1390134265
Short name T715
Test name
Test status
Simulation time 43131167 ps
CPU time 0.72 seconds
Started May 28 02:45:56 PM PDT 24
Finished May 28 02:46:05 PM PDT 24
Peak memory 204924 kb
Host smart-6ed5ab2b-21ee-42ff-8254-64beb1294fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390134265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1390134265
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4182614039
Short name T926
Test name
Test status
Simulation time 469465141 ps
CPU time 6.21 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:13 PM PDT 24
Peak memory 218480 kb
Host smart-d30bbbca-1c65-4fde-889e-c7053be9893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182614039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4182614039
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2499142361
Short name T355
Test name
Test status
Simulation time 18290673 ps
CPU time 0.75 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:08 PM PDT 24
Peak memory 204908 kb
Host smart-46f33774-c17c-435e-8380-72279b784f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499142361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2499142361
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1245215619
Short name T258
Test name
Test status
Simulation time 8684322514 ps
CPU time 37.37 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:41 PM PDT 24
Peak memory 240576 kb
Host smart-c6c377f7-ff0f-4bf0-bc48-1a0354ecc8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245215619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1245215619
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3174180745
Short name T473
Test name
Test status
Simulation time 4466590005 ps
CPU time 16.5 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:20 PM PDT 24
Peak memory 216992 kb
Host smart-5b869d24-50a3-45d4-b29a-f427eef8f458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174180745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3174180745
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2222950834
Short name T578
Test name
Test status
Simulation time 42161783927 ps
CPU time 111.09 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 252288 kb
Host smart-8c732a9a-3c2e-4d17-9ed6-f67e8147e09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222950834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2222950834
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3045391784
Short name T391
Test name
Test status
Simulation time 1393405460 ps
CPU time 6.22 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:07 PM PDT 24
Peak memory 218248 kb
Host smart-1c1d953e-0a36-481c-86f3-6bfe3ac51724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045391784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3045391784
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3558520763
Short name T790
Test name
Test status
Simulation time 30920174872 ps
CPU time 34.78 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:35 PM PDT 24
Peak memory 218412 kb
Host smart-40314833-7670-42ab-af19-6784c01519d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558520763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3558520763
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.765037255
Short name T299
Test name
Test status
Simulation time 9512679899 ps
CPU time 29 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:46:34 PM PDT 24
Peak memory 248488 kb
Host smart-7011d320-970b-427b-b181-d518eb72d355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765037255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.765037255
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2106126103
Short name T161
Test name
Test status
Simulation time 1067085953 ps
CPU time 5.56 seconds
Started May 28 02:45:54 PM PDT 24
Finished May 28 02:46:07 PM PDT 24
Peak memory 218496 kb
Host smart-ba6885bd-93fe-4c9c-b561-3659dfbeffe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106126103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2106126103
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1543503064
Short name T768
Test name
Test status
Simulation time 158180994 ps
CPU time 3.85 seconds
Started May 28 02:45:51 PM PDT 24
Finished May 28 02:46:02 PM PDT 24
Peak memory 222632 kb
Host smart-63040007-b35f-4c8d-8fa2-da13092b26e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1543503064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1543503064
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1705159028
Short name T848
Test name
Test status
Simulation time 4426281700 ps
CPU time 27.78 seconds
Started May 28 02:45:51 PM PDT 24
Finished May 28 02:46:26 PM PDT 24
Peak memory 215956 kb
Host smart-606bc36b-9f3e-4dab-8103-2323a3d6700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705159028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1705159028
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3839970234
Short name T827
Test name
Test status
Simulation time 13317688 ps
CPU time 0.71 seconds
Started May 28 02:45:54 PM PDT 24
Finished May 28 02:46:02 PM PDT 24
Peak memory 204996 kb
Host smart-74257298-e0f2-4bf4-ba81-1abe06be4e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839970234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3839970234
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1247475963
Short name T596
Test name
Test status
Simulation time 79562323 ps
CPU time 1.25 seconds
Started May 28 02:45:52 PM PDT 24
Finished May 28 02:46:01 PM PDT 24
Peak memory 215864 kb
Host smart-b435b8df-7c15-4102-bb33-6b784d66ecb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247475963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1247475963
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3841085635
Short name T328
Test name
Test status
Simulation time 165233100 ps
CPU time 0.81 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:08 PM PDT 24
Peak memory 205296 kb
Host smart-d17f48e8-b19e-4f43-b8da-f61e1af09bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841085635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3841085635
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.4557843
Short name T413
Test name
Test status
Simulation time 205993046 ps
CPU time 2.45 seconds
Started May 28 02:45:56 PM PDT 24
Finished May 28 02:46:06 PM PDT 24
Peak memory 224072 kb
Host smart-ecbaf295-a541-45c9-8c7b-b3ca329a9e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4557843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4557843
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1939558940
Short name T398
Test name
Test status
Simulation time 12329380 ps
CPU time 0.76 seconds
Started May 28 02:45:54 PM PDT 24
Finished May 28 02:46:03 PM PDT 24
Peak memory 204296 kb
Host smart-a375a943-95f7-4b34-a92c-1b912569514c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939558940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1939558940
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3661822841
Short name T799
Test name
Test status
Simulation time 33133817 ps
CPU time 2.14 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 220820 kb
Host smart-420e2f80-91c2-4d97-b9bd-7dab4c96a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661822841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3661822841
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2988104605
Short name T544
Test name
Test status
Simulation time 54697385 ps
CPU time 0.85 seconds
Started May 28 02:45:56 PM PDT 24
Finished May 28 02:46:04 PM PDT 24
Peak memory 205932 kb
Host smart-0a9754f9-efc3-4056-b1f8-400f0d7fefda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988104605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2988104605
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3722555106
Short name T384
Test name
Test status
Simulation time 104424106 ps
CPU time 0.87 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 215524 kb
Host smart-18d9cf07-e464-4d21-846d-d31b999c3c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722555106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3722555106
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2738852899
Short name T875
Test name
Test status
Simulation time 73991037025 ps
CPU time 92.02 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:47:37 PM PDT 24
Peak memory 240228 kb
Host smart-385d0313-4e3d-4c45-8317-4139e0d9de60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738852899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2738852899
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3315284566
Short name T289
Test name
Test status
Simulation time 249766976436 ps
CPU time 316.11 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:51:21 PM PDT 24
Peak memory 257168 kb
Host smart-c2e4c53c-468b-4e4b-bb50-3d98f15cedf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315284566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3315284566
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2444771525
Short name T892
Test name
Test status
Simulation time 1565645848 ps
CPU time 13.77 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:21 PM PDT 24
Peak memory 234280 kb
Host smart-f5d7911d-22ee-4d3a-815b-a79f94e6732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444771525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2444771525
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2022908564
Short name T771
Test name
Test status
Simulation time 17466586525 ps
CPU time 16.91 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:24 PM PDT 24
Peak memory 220036 kb
Host smart-cbfd4008-0cdc-4e16-94da-99a2bd32ed84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022908564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2022908564
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3741054781
Short name T43
Test name
Test status
Simulation time 104336835 ps
CPU time 2.66 seconds
Started May 28 02:45:58 PM PDT 24
Finished May 28 02:46:08 PM PDT 24
Peak memory 233060 kb
Host smart-194c2ad7-0f3b-4bbd-b3f2-392b28352dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741054781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3741054781
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1909472145
Short name T209
Test name
Test status
Simulation time 5135661129 ps
CPU time 9.69 seconds
Started May 28 02:45:59 PM PDT 24
Finished May 28 02:46:16 PM PDT 24
Peak memory 232444 kb
Host smart-732cd971-b9b0-48e8-80cb-70f1fa9c5e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909472145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1909472145
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.733863714
Short name T246
Test name
Test status
Simulation time 3537414459 ps
CPU time 8 seconds
Started May 28 02:45:59 PM PDT 24
Finished May 28 02:46:14 PM PDT 24
Peak memory 233040 kb
Host smart-da0b2613-d17f-4af4-a629-2f645bcbc941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733863714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.733863714
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.168850771
Short name T624
Test name
Test status
Simulation time 284596573 ps
CPU time 3.32 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:06 PM PDT 24
Peak memory 219840 kb
Host smart-026b96f5-3138-47c8-8352-6cb14fffeb3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=168850771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.168850771
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1141630113
Short name T573
Test name
Test status
Simulation time 10604284030 ps
CPU time 35.29 seconds
Started May 28 02:45:58 PM PDT 24
Finished May 28 02:46:41 PM PDT 24
Peak memory 235932 kb
Host smart-5f585586-84a2-47e8-a309-b58848a108a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141630113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1141630113
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.839964381
Short name T703
Test name
Test status
Simulation time 27991607 ps
CPU time 0.73 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:04 PM PDT 24
Peak memory 205064 kb
Host smart-f4ae934c-8b32-4383-8c79-8a8baf73d02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839964381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.839964381
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.250402740
Short name T617
Test name
Test status
Simulation time 1255352105 ps
CPU time 4.69 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 216088 kb
Host smart-85f6a971-44b8-4a5e-af2a-a7939db2ddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250402740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.250402740
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.101933821
Short name T629
Test name
Test status
Simulation time 92686556 ps
CPU time 1 seconds
Started May 28 02:45:58 PM PDT 24
Finished May 28 02:46:06 PM PDT 24
Peak memory 205992 kb
Host smart-fb5d0752-c512-4bdf-b816-f8063f609c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101933821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.101933821
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1607343519
Short name T351
Test name
Test status
Simulation time 25755258 ps
CPU time 0.75 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:08 PM PDT 24
Peak memory 205296 kb
Host smart-deb6dd39-cf28-49ad-9d15-bd04e4a73274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607343519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1607343519
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1109318747
Short name T265
Test name
Test status
Simulation time 1812259713 ps
CPU time 5.86 seconds
Started May 28 02:45:58 PM PDT 24
Finished May 28 02:46:11 PM PDT 24
Peak memory 232292 kb
Host smart-fd1a3ddd-beed-4b1b-84f4-87d6fd164a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109318747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1109318747
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4103859260
Short name T762
Test name
Test status
Simulation time 41700341 ps
CPU time 0.71 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:04 PM PDT 24
Peak memory 204908 kb
Host smart-8e52a803-a659-4874-8c9f-dc29b6c2eb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103859260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4103859260
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1096284867
Short name T918
Test name
Test status
Simulation time 442281487 ps
CPU time 3.78 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:11 PM PDT 24
Peak memory 233452 kb
Host smart-84733b53-c434-4ff5-bc09-7d3cca4cddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096284867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1096284867
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1409764522
Short name T821
Test name
Test status
Simulation time 32551713 ps
CPU time 0.78 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:46:05 PM PDT 24
Peak memory 205940 kb
Host smart-f0deb72a-62b0-410f-bcbc-1809207ce794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409764522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1409764522
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2133445882
Short name T194
Test name
Test status
Simulation time 50225350918 ps
CPU time 77.69 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 253040 kb
Host smart-c40e270b-7d7b-4ce5-a7b9-78cf7ac9e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133445882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2133445882
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.938202649
Short name T188
Test name
Test status
Simulation time 19942130979 ps
CPU time 210.15 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:49:37 PM PDT 24
Peak memory 253036 kb
Host smart-4125e072-6602-4287-bc50-cfb1415c9eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938202649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.938202649
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1190600850
Short name T250
Test name
Test status
Simulation time 42139169454 ps
CPU time 100.85 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:47:48 PM PDT 24
Peak memory 248680 kb
Host smart-f2ad7d25-6a2c-45ad-b8e2-3e3bff2d164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190600850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1190600850
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1193412847
Short name T655
Test name
Test status
Simulation time 8107395797 ps
CPU time 26.53 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:35 PM PDT 24
Peak memory 240636 kb
Host smart-1e1bc17d-894f-44cc-aaa8-bf67e3a296b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193412847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1193412847
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.539340998
Short name T665
Test name
Test status
Simulation time 141112248 ps
CPU time 2.16 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:10 PM PDT 24
Peak memory 215728 kb
Host smart-6a24b9eb-f2a7-44a2-a6cb-89af8e220bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539340998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.539340998
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3351147464
Short name T814
Test name
Test status
Simulation time 6259935361 ps
CPU time 22.19 seconds
Started May 28 02:45:58 PM PDT 24
Finished May 28 02:46:27 PM PDT 24
Peak memory 240160 kb
Host smart-85edcb5f-b961-4a07-9681-da3e832df375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351147464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3351147464
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.803523636
Short name T690
Test name
Test status
Simulation time 986803281 ps
CPU time 5.17 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:08 PM PDT 24
Peak memory 233280 kb
Host smart-76530ff1-7c2d-405c-97bc-7708de31dbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803523636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.803523636
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.694477273
Short name T931
Test name
Test status
Simulation time 1296205845 ps
CPU time 8.07 seconds
Started May 28 02:45:53 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 237476 kb
Host smart-8d1f51ea-37d9-4809-9aa7-9f5178581358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694477273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.694477273
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.917123226
Short name T632
Test name
Test status
Simulation time 94294366 ps
CPU time 3.99 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:12 PM PDT 24
Peak memory 218776 kb
Host smart-ebc5612b-d991-4ede-9e2f-bf825d5d6577
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=917123226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.917123226
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.837451593
Short name T880
Test name
Test status
Simulation time 1034956030 ps
CPU time 8.88 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 215844 kb
Host smart-a4215e1c-2a71-4336-878f-476b40ff3057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837451593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.837451593
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3222653942
Short name T447
Test name
Test status
Simulation time 253245412 ps
CPU time 1.69 seconds
Started May 28 02:45:58 PM PDT 24
Finished May 28 02:46:07 PM PDT 24
Peak memory 207408 kb
Host smart-d23d4295-28ee-4fb0-a7ae-20ade6ed3073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222653942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3222653942
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2248561990
Short name T372
Test name
Test status
Simulation time 237284255 ps
CPU time 2.82 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:11 PM PDT 24
Peak memory 215992 kb
Host smart-a2154730-3ea1-4bbe-a641-16d3f069134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248561990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2248561990
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1455801803
Short name T362
Test name
Test status
Simulation time 80013562 ps
CPU time 0.79 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 205300 kb
Host smart-816cbec1-a545-4c66-987e-6d920ee53272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455801803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1455801803
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2158163383
Short name T429
Test name
Test status
Simulation time 5283118184 ps
CPU time 3.62 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:12 PM PDT 24
Peak memory 233740 kb
Host smart-28600572-709a-4441-82c4-cc92b6a54303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158163383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2158163383
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.879704400
Short name T915
Test name
Test status
Simulation time 15936605 ps
CPU time 0.76 seconds
Started May 28 02:44:20 PM PDT 24
Finished May 28 02:44:24 PM PDT 24
Peak memory 205264 kb
Host smart-a8fde221-494c-4a65-b4b4-3fc799c2f389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879704400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.879704400
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2939089558
Short name T82
Test name
Test status
Simulation time 128234083 ps
CPU time 3.62 seconds
Started May 28 02:44:22 PM PDT 24
Finished May 28 02:44:30 PM PDT 24
Peak memory 233476 kb
Host smart-e6d93c95-9d8f-4a84-8be9-c0cb0dbd206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939089558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2939089558
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1473760334
Short name T947
Test name
Test status
Simulation time 71781015 ps
CPU time 0.78 seconds
Started May 28 02:44:15 PM PDT 24
Finished May 28 02:44:19 PM PDT 24
Peak memory 205960 kb
Host smart-79bb1e6c-0362-4e48-9b0d-be976f8c766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473760334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1473760334
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.122975880
Short name T28
Test name
Test status
Simulation time 37346295689 ps
CPU time 190.76 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:47:31 PM PDT 24
Peak memory 255332 kb
Host smart-9f03278c-a7c8-4698-8bc9-7a1d4fc9f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122975880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.122975880
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.827086693
Short name T759
Test name
Test status
Simulation time 6837407372 ps
CPU time 29.4 seconds
Started May 28 02:44:17 PM PDT 24
Finished May 28 02:44:50 PM PDT 24
Peak memory 235844 kb
Host smart-2ea82c50-2fb8-43b5-8ca7-77ef894b4f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827086693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.827086693
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2491492401
Short name T34
Test name
Test status
Simulation time 13764205451 ps
CPU time 78.05 seconds
Started May 28 02:44:27 PM PDT 24
Finished May 28 02:45:56 PM PDT 24
Peak memory 253568 kb
Host smart-ea135a54-9db9-4e75-a5fc-004a67bc9cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491492401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2491492401
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.353875018
Short name T757
Test name
Test status
Simulation time 231908394 ps
CPU time 2.45 seconds
Started May 28 02:44:21 PM PDT 24
Finished May 28 02:44:27 PM PDT 24
Peak memory 232364 kb
Host smart-4c83390a-a045-47ac-86e6-6c332b684ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353875018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.353875018
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1741965080
Short name T559
Test name
Test status
Simulation time 11818291969 ps
CPU time 23.37 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:45:00 PM PDT 24
Peak memory 233732 kb
Host smart-cf1191d3-773b-4f7f-b337-318f0f91ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741965080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1741965080
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.429973903
Short name T769
Test name
Test status
Simulation time 170762178 ps
CPU time 2.36 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:41 PM PDT 24
Peak memory 216652 kb
Host smart-a54fa8c7-f5a1-4865-a09d-2a92ed4b53a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429973903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.429973903
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3981962824
Short name T872
Test name
Test status
Simulation time 17506591 ps
CPU time 1.02 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:44:21 PM PDT 24
Peak memory 216192 kb
Host smart-1fcdf5fe-28a7-4074-862a-4928bf10d120
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981962824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3981962824
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2629590267
Short name T256
Test name
Test status
Simulation time 4534289367 ps
CPU time 16.94 seconds
Started May 28 02:44:19 PM PDT 24
Finished May 28 02:44:39 PM PDT 24
Peak memory 231348 kb
Host smart-f6d226d2-48f7-4b24-8df8-9b0d8b103c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629590267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2629590267
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2972528711
Short name T155
Test name
Test status
Simulation time 70727806 ps
CPU time 2.11 seconds
Started May 28 02:44:21 PM PDT 24
Finished May 28 02:44:26 PM PDT 24
Peak memory 215712 kb
Host smart-bc0c4a3f-03a9-4168-843d-e75b69fd4738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972528711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2972528711
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.637409342
Short name T410
Test name
Test status
Simulation time 231025853 ps
CPU time 4.6 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:34 PM PDT 24
Peak memory 222524 kb
Host smart-bdf72680-d014-40f1-a8f2-0a0679059731
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=637409342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.637409342
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.177163622
Short name T59
Test name
Test status
Simulation time 38750892 ps
CPU time 0.98 seconds
Started May 28 02:44:20 PM PDT 24
Finished May 28 02:44:24 PM PDT 24
Peak memory 234716 kb
Host smart-a80f47be-0d55-4915-8123-b2d09f71f095
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177163622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.177163622
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1264901550
Short name T298
Test name
Test status
Simulation time 20789565468 ps
CPU time 378.37 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:50:47 PM PDT 24
Peak memory 285708 kb
Host smart-6556c5de-00d4-4ab9-96d6-eca668d20e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264901550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1264901550
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1198353245
Short name T582
Test name
Test status
Simulation time 2021750652 ps
CPU time 15.96 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:44:36 PM PDT 24
Peak memory 215908 kb
Host smart-c16cc2d2-ab7b-4923-9d39-33dc4c5a73a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198353245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1198353245
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1923183421
Short name T356
Test name
Test status
Simulation time 13731986744 ps
CPU time 9.86 seconds
Started May 28 02:44:20 PM PDT 24
Finished May 28 02:44:33 PM PDT 24
Peak memory 215896 kb
Host smart-8d911f65-9024-4f63-9536-344e88119b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923183421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1923183421
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.363364515
Short name T397
Test name
Test status
Simulation time 257612826 ps
CPU time 2.72 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:44:23 PM PDT 24
Peak memory 215908 kb
Host smart-6daddad3-6dfc-45fa-8fe7-009b67cf12b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363364515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.363364515
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.275754417
Short name T360
Test name
Test status
Simulation time 30709350 ps
CPU time 0.79 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:30 PM PDT 24
Peak memory 205320 kb
Host smart-4bce8002-ceae-4a89-96b9-8306d5194fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275754417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.275754417
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2167332661
Short name T752
Test name
Test status
Simulation time 2697654526 ps
CPU time 12.38 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:46 PM PDT 24
Peak memory 236948 kb
Host smart-3932ab4a-f74a-4730-a4c7-ee4579f91c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167332661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2167332661
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1033868019
Short name T967
Test name
Test status
Simulation time 12774161 ps
CPU time 0.71 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:04 PM PDT 24
Peak memory 205240 kb
Host smart-750b6824-db1a-4100-9ad5-9b670480281c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033868019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1033868019
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1449905629
Short name T446
Test name
Test status
Simulation time 159325658 ps
CPU time 3.79 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:07 PM PDT 24
Peak memory 218384 kb
Host smart-384fcf7a-284e-463a-b49e-9a1c6347290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449905629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1449905629
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.921895073
Short name T444
Test name
Test status
Simulation time 42413956 ps
CPU time 0.79 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:04 PM PDT 24
Peak memory 206260 kb
Host smart-37707d81-d3b5-414a-bf0a-d98d32fe7dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921895073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.921895073
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1055467619
Short name T692
Test name
Test status
Simulation time 12917227255 ps
CPU time 89.12 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 237944 kb
Host smart-a8d549be-6019-448c-9bbd-db3b6418c5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055467619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1055467619
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.636452449
Short name T712
Test name
Test status
Simulation time 3021338151 ps
CPU time 21.78 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:46:26 PM PDT 24
Peak memory 217308 kb
Host smart-57444498-83af-442c-8955-386db60e8126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636452449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.636452449
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2618814145
Short name T379
Test name
Test status
Simulation time 4022324388 ps
CPU time 11.97 seconds
Started May 28 02:45:48 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 238452 kb
Host smart-0e92029e-0900-470f-aa84-29b47e92e751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618814145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2618814145
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.439754298
Short name T341
Test name
Test status
Simulation time 2193150044 ps
CPU time 6.97 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 218440 kb
Host smart-4ba569df-2648-42c7-a693-283fc8cb7f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439754298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.439754298
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.924864725
Short name T871
Test name
Test status
Simulation time 7868110842 ps
CPU time 22.35 seconds
Started May 28 02:45:51 PM PDT 24
Finished May 28 02:46:21 PM PDT 24
Peak memory 218256 kb
Host smart-edcc2a4f-9ab7-4d67-896b-98ce757b4d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924864725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.924864725
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1143132615
Short name T507
Test name
Test status
Simulation time 458041607 ps
CPU time 3.16 seconds
Started May 28 02:45:51 PM PDT 24
Finished May 28 02:46:03 PM PDT 24
Peak memory 218096 kb
Host smart-fa4ef811-9617-4b23-8ee4-b220000e7234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143132615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1143132615
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3488897661
Short name T207
Test name
Test status
Simulation time 996558680 ps
CPU time 8.15 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 238968 kb
Host smart-724bc47c-f1fe-484e-a866-14f49d7c5822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488897661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3488897661
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2131879120
Short name T965
Test name
Test status
Simulation time 452975385 ps
CPU time 4.22 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 220120 kb
Host smart-107c5e09-f388-43c7-8d16-f9f28f36a890
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131879120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2131879120
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2610582667
Short name T695
Test name
Test status
Simulation time 3741435901 ps
CPU time 16.46 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:23 PM PDT 24
Peak memory 215988 kb
Host smart-94873bab-17cc-46a6-a32c-f19f48a2f15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610582667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2610582667
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4041530047
Short name T841
Test name
Test status
Simulation time 2694208000 ps
CPU time 7.68 seconds
Started May 28 02:45:57 PM PDT 24
Finished May 28 02:46:12 PM PDT 24
Peak memory 215928 kb
Host smart-faf6d0e0-18a4-45c4-a8ca-9b2b829ed912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041530047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4041530047
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3123690452
Short name T571
Test name
Test status
Simulation time 126063866 ps
CPU time 4.91 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 216064 kb
Host smart-748c5bf9-8d84-4a90-aabb-c066fc08295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123690452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3123690452
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2829820318
Short name T746
Test name
Test status
Simulation time 28556210 ps
CPU time 0.81 seconds
Started May 28 02:45:56 PM PDT 24
Finished May 28 02:46:04 PM PDT 24
Peak memory 205320 kb
Host smart-32bfa49e-ad5b-4d47-89d1-043b1ae18ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829820318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2829820318
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3029237638
Short name T526
Test name
Test status
Simulation time 151495784 ps
CPU time 2.76 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:10 PM PDT 24
Peak memory 224216 kb
Host smart-b3e4cb42-6b05-4fa2-a2d0-63d4c6927a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029237638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3029237638
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1966835452
Short name T886
Test name
Test status
Simulation time 23114063 ps
CPU time 0.72 seconds
Started May 28 02:46:11 PM PDT 24
Finished May 28 02:46:18 PM PDT 24
Peak memory 204908 kb
Host smart-3e7abf55-5206-4683-9dbc-b6ff3a8d7f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966835452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1966835452
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.483931209
Short name T758
Test name
Test status
Simulation time 126910950 ps
CPU time 2.6 seconds
Started May 28 02:46:08 PM PDT 24
Finished May 28 02:46:16 PM PDT 24
Peak memory 218268 kb
Host smart-75ddeece-1c46-4971-a6fb-b7bad11e798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483931209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.483931209
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.96427618
Short name T159
Test name
Test status
Simulation time 87169390 ps
CPU time 0.78 seconds
Started May 28 02:45:59 PM PDT 24
Finished May 28 02:46:07 PM PDT 24
Peak memory 205764 kb
Host smart-6fb76627-736d-4265-829b-4501a1f172aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96427618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.96427618
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.353472940
Short name T866
Test name
Test status
Simulation time 4327977341 ps
CPU time 42.42 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:55 PM PDT 24
Peak memory 248856 kb
Host smart-ce434a98-9dd4-4764-a7e3-ac35f2f5af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353472940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.353472940
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.620190709
Short name T562
Test name
Test status
Simulation time 10990682828 ps
CPU time 75.38 seconds
Started May 28 02:46:08 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 252308 kb
Host smart-0e58d49a-dee5-4786-a70f-282a63e3a616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620190709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.620190709
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.901755253
Short name T277
Test name
Test status
Simulation time 42275154541 ps
CPU time 127.72 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 263164 kb
Host smart-9291d5e7-92ae-4942-96ba-89baa4b2f165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901755253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.901755253
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1597515044
Short name T302
Test name
Test status
Simulation time 345909725 ps
CPU time 7.88 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:20 PM PDT 24
Peak memory 232380 kb
Host smart-cfd6de8a-8024-4b18-bfad-1fec84430432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597515044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1597515044
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2746506810
Short name T929
Test name
Test status
Simulation time 3053854699 ps
CPU time 14.21 seconds
Started May 28 02:45:55 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 233320 kb
Host smart-e46b8cf3-9225-4ca9-b0ed-39881bda33a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746506810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2746506810
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2944148469
Short name T95
Test name
Test status
Simulation time 933749133 ps
CPU time 11.22 seconds
Started May 28 02:46:07 PM PDT 24
Finished May 28 02:46:24 PM PDT 24
Peak memory 236004 kb
Host smart-0ca7c82d-adeb-4f4a-a8c1-965de55bf689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944148469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2944148469
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1183217098
Short name T373
Test name
Test status
Simulation time 5369216840 ps
CPU time 20.87 seconds
Started May 28 02:45:58 PM PDT 24
Finished May 28 02:46:26 PM PDT 24
Peak memory 232672 kb
Host smart-2120f3c2-a508-4b68-aed5-7ccc788b00be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183217098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1183217098
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3434793139
Short name T851
Test name
Test status
Simulation time 12580527271 ps
CPU time 5.15 seconds
Started May 28 02:45:58 PM PDT 24
Finished May 28 02:46:10 PM PDT 24
Peak memory 224068 kb
Host smart-9eff893f-8a88-4416-bcb5-25dacfcd601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434793139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3434793139
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2340014281
Short name T798
Test name
Test status
Simulation time 7412239097 ps
CPU time 11.74 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:24 PM PDT 24
Peak memory 222288 kb
Host smart-3b99520f-f4ac-44be-87a8-9020cad8c7d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2340014281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2340014281
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.775292256
Short name T464
Test name
Test status
Simulation time 4765457096 ps
CPU time 42.74 seconds
Started May 28 02:46:05 PM PDT 24
Finished May 28 02:46:53 PM PDT 24
Peak memory 256168 kb
Host smart-d7f5d333-ba7b-4033-9350-85b27276129c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775292256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.775292256
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.4235696162
Short name T157
Test name
Test status
Simulation time 5013445465 ps
CPU time 23.48 seconds
Started May 28 02:45:59 PM PDT 24
Finished May 28 02:46:29 PM PDT 24
Peak memory 219764 kb
Host smart-e634ce3a-69ea-49bf-9c37-576e425fbc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235696162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.4235696162
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2377592356
Short name T368
Test name
Test status
Simulation time 5821359217 ps
CPU time 9.13 seconds
Started May 28 02:46:00 PM PDT 24
Finished May 28 02:46:16 PM PDT 24
Peak memory 215928 kb
Host smart-4b2a12d9-f700-4fdd-90ad-6896fbb5b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377592356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2377592356
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3774435324
Short name T371
Test name
Test status
Simulation time 28970393 ps
CPU time 1.17 seconds
Started May 28 02:46:01 PM PDT 24
Finished May 28 02:46:09 PM PDT 24
Peak memory 215916 kb
Host smart-07b638c2-63ce-4743-bdac-368a658daa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774435324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3774435324
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.925837384
Short name T766
Test name
Test status
Simulation time 78821101 ps
CPU time 0.87 seconds
Started May 28 02:45:59 PM PDT 24
Finished May 28 02:46:06 PM PDT 24
Peak memory 205316 kb
Host smart-d793ce4a-2acf-434c-a5a8-5685c590b5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925837384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.925837384
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4109347754
Short name T722
Test name
Test status
Simulation time 7707384005 ps
CPU time 15.89 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:28 PM PDT 24
Peak memory 233396 kb
Host smart-55387203-c08d-4d0b-bcdf-61d5fd3dffaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109347754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4109347754
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3544391834
Short name T738
Test name
Test status
Simulation time 35258106 ps
CPU time 0.69 seconds
Started May 28 02:46:08 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 204860 kb
Host smart-af61d31f-ebe6-45d1-85e5-f82dab189a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544391834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3544391834
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1117476864
Short name T761
Test name
Test status
Simulation time 514353717 ps
CPU time 6.64 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:25 PM PDT 24
Peak memory 234212 kb
Host smart-e099af5c-c8f0-429d-824a-5724cfecea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117476864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1117476864
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2537501217
Short name T721
Test name
Test status
Simulation time 63685768 ps
CPU time 0.76 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:13 PM PDT 24
Peak memory 205936 kb
Host smart-ade08cea-b9ae-4928-9ebc-5b2120ab60e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537501217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2537501217
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2358910520
Short name T592
Test name
Test status
Simulation time 35877525 ps
CPU time 0.78 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:46:16 PM PDT 24
Peak memory 215288 kb
Host smart-7df6b736-d44e-4cac-82df-6f2ce669331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358910520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2358910520
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.961845511
Short name T681
Test name
Test status
Simulation time 7323205420 ps
CPU time 118.02 seconds
Started May 28 02:46:05 PM PDT 24
Finished May 28 02:48:09 PM PDT 24
Peak memory 253040 kb
Host smart-9760fd52-2d05-449d-85a0-446f3ca08adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961845511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.961845511
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1175009337
Short name T739
Test name
Test status
Simulation time 14172578712 ps
CPU time 89.08 seconds
Started May 28 02:46:11 PM PDT 24
Finished May 28 02:47:46 PM PDT 24
Peak memory 248392 kb
Host smart-134ae081-fd1a-4775-9c84-580f2731c627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175009337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1175009337
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1727259987
Short name T353
Test name
Test status
Simulation time 300953567 ps
CPU time 6.53 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:19 PM PDT 24
Peak memory 232428 kb
Host smart-80f2cb27-caf1-4e08-85fa-cf626f9228a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727259987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1727259987
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3966247822
Short name T508
Test name
Test status
Simulation time 122993547 ps
CPU time 2.4 seconds
Started May 28 02:46:07 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 220888 kb
Host smart-26205557-96ec-4223-a80f-cbb9d4ce29ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966247822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3966247822
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1204762587
Short name T274
Test name
Test status
Simulation time 4954365901 ps
CPU time 5.78 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:18 PM PDT 24
Peak memory 234616 kb
Host smart-08e907a1-6abc-43c1-adfa-ca77117fb0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204762587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1204762587
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3949945910
Short name T215
Test name
Test status
Simulation time 6192887569 ps
CPU time 12.48 seconds
Started May 28 02:46:08 PM PDT 24
Finished May 28 02:46:26 PM PDT 24
Peak memory 232852 kb
Host smart-2c039292-da9f-43a1-9349-e716d5032375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949945910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3949945910
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1676446898
Short name T498
Test name
Test status
Simulation time 1323156174 ps
CPU time 4.94 seconds
Started May 28 02:46:10 PM PDT 24
Finished May 28 02:46:21 PM PDT 24
Peak memory 224108 kb
Host smart-6660fc65-4b70-4e08-8554-9717d75045cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676446898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1676446898
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2495857084
Short name T33
Test name
Test status
Simulation time 1014433433 ps
CPU time 5 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 222476 kb
Host smart-de144fec-a26e-4325-8f8e-b596f443b826
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2495857084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2495857084
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2021048670
Short name T547
Test name
Test status
Simulation time 62728433822 ps
CPU time 174.27 seconds
Started May 28 02:46:08 PM PDT 24
Finished May 28 02:49:08 PM PDT 24
Peak memory 248988 kb
Host smart-5d0ec7c1-912d-4423-ab2c-8691692019b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021048670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2021048670
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2382916544
Short name T723
Test name
Test status
Simulation time 5100712281 ps
CPU time 3.9 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:46:19 PM PDT 24
Peak memory 216024 kb
Host smart-bda5c0e9-8d3a-4a2d-8752-bfee58778ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382916544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2382916544
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3573921984
Short name T411
Test name
Test status
Simulation time 11377607 ps
CPU time 0.71 seconds
Started May 28 02:46:05 PM PDT 24
Finished May 28 02:46:12 PM PDT 24
Peak memory 204988 kb
Host smart-abb6af79-1578-4379-a382-b927d35d03fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573921984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3573921984
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4278999653
Short name T680
Test name
Test status
Simulation time 79699217 ps
CPU time 1.53 seconds
Started May 28 02:46:07 PM PDT 24
Finished May 28 02:46:14 PM PDT 24
Peak memory 207548 kb
Host smart-d23367cc-452b-4bcc-87c9-d691dbe30039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278999653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4278999653
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2643305067
Short name T708
Test name
Test status
Simulation time 169001035 ps
CPU time 1.03 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 205300 kb
Host smart-a167a248-6594-4aa2-8c2a-8531743517e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643305067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2643305067
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3336263224
Short name T658
Test name
Test status
Simulation time 215874283 ps
CPU time 2.91 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:21 PM PDT 24
Peak memory 217864 kb
Host smart-42e74afb-feea-414d-b162-44836a00ef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336263224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3336263224
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2123372702
Short name T54
Test name
Test status
Simulation time 37289993 ps
CPU time 0.75 seconds
Started May 28 02:46:05 PM PDT 24
Finished May 28 02:46:12 PM PDT 24
Peak memory 204292 kb
Host smart-56e357b5-274a-4484-ab73-08648b47e7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123372702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2123372702
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4112327869
Short name T551
Test name
Test status
Simulation time 45430751 ps
CPU time 2.71 seconds
Started May 28 02:46:15 PM PDT 24
Finished May 28 02:46:24 PM PDT 24
Peak memory 233060 kb
Host smart-5016480b-7e61-4676-9750-3fe4d0dc749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112327869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4112327869
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4159338293
Short name T478
Test name
Test status
Simulation time 55741635 ps
CPU time 0.76 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:19 PM PDT 24
Peak memory 204884 kb
Host smart-873dc292-df8e-4a80-97cb-33e1aee5c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159338293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4159338293
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1910762328
Short name T300
Test name
Test status
Simulation time 90486369792 ps
CPU time 334.43 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:51:50 PM PDT 24
Peak memory 255176 kb
Host smart-b5d5d20a-9ff2-44ee-8425-709f36b554c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910762328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1910762328
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.773873858
Short name T160
Test name
Test status
Simulation time 7770364769 ps
CPU time 90.52 seconds
Started May 28 02:46:07 PM PDT 24
Finished May 28 02:47:44 PM PDT 24
Peak memory 233504 kb
Host smart-5eb594cc-e406-4751-8b3b-372b7c4059a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773873858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.773873858
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3282703348
Short name T211
Test name
Test status
Simulation time 99116536346 ps
CPU time 204.19 seconds
Started May 28 02:46:05 PM PDT 24
Finished May 28 02:49:36 PM PDT 24
Peak memory 251344 kb
Host smart-fe048459-f99b-47c9-9c6b-bdd743af5988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282703348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3282703348
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2332357530
Short name T705
Test name
Test status
Simulation time 209243202 ps
CPU time 6.03 seconds
Started May 28 02:46:05 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 236268 kb
Host smart-4644c00c-6ee0-4d7c-8158-ced8399503ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332357530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2332357530
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3595558108
Short name T220
Test name
Test status
Simulation time 1289551731 ps
CPU time 11.28 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:23 PM PDT 24
Peak memory 233436 kb
Host smart-86fa4d2b-19da-4a01-8727-c1f56e621bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595558108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3595558108
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3777366300
Short name T567
Test name
Test status
Simulation time 53823493 ps
CPU time 2.47 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 218388 kb
Host smart-f8416d7c-1230-4b58-bb8b-1c5ff65144b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777366300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3777366300
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2829017846
Short name T249
Test name
Test status
Simulation time 17743096114 ps
CPU time 12.2 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:46:27 PM PDT 24
Peak memory 224216 kb
Host smart-addb6cfd-9ca6-41b4-a63b-e05c05184489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829017846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2829017846
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.133497680
Short name T469
Test name
Test status
Simulation time 107818787 ps
CPU time 2.35 seconds
Started May 28 02:46:07 PM PDT 24
Finished May 28 02:46:15 PM PDT 24
Peak memory 218124 kb
Host smart-71bc8472-8e96-43ab-8831-866eb1be4301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133497680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.133497680
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3299619783
Short name T135
Test name
Test status
Simulation time 379868852 ps
CPU time 4.17 seconds
Started May 28 02:46:07 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 219780 kb
Host smart-898d90fe-2518-4f76-beb7-4363ef505715
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299619783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3299619783
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.490485312
Short name T924
Test name
Test status
Simulation time 19096910483 ps
CPU time 110.53 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:48:05 PM PDT 24
Peak memory 256032 kb
Host smart-201ff091-4e81-4f96-81d0-4c6e5daea8fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490485312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.490485312
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1520192398
Short name T386
Test name
Test status
Simulation time 1085124146 ps
CPU time 8.23 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:21 PM PDT 24
Peak memory 215960 kb
Host smart-0df7baec-ca04-4ded-b675-db66946a5d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520192398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1520192398
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1434714994
Short name T834
Test name
Test status
Simulation time 2408618908 ps
CPU time 5.87 seconds
Started May 28 02:46:13 PM PDT 24
Finished May 28 02:46:26 PM PDT 24
Peak memory 215892 kb
Host smart-a10743fd-26d9-4874-a639-e47482ed9d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434714994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1434714994
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3085121271
Short name T363
Test name
Test status
Simulation time 14131444 ps
CPU time 0.74 seconds
Started May 28 02:46:05 PM PDT 24
Finished May 28 02:46:12 PM PDT 24
Peak memory 204972 kb
Host smart-b16d8384-4cb4-4100-90a6-8d2d832b7445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085121271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3085121271
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.39587204
Short name T602
Test name
Test status
Simulation time 62887643 ps
CPU time 0.76 seconds
Started May 28 02:46:07 PM PDT 24
Finished May 28 02:46:14 PM PDT 24
Peak memory 205332 kb
Host smart-8a3455dd-fe4a-4b88-a723-3434317a5998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39587204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.39587204
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1570310554
Short name T958
Test name
Test status
Simulation time 102308919 ps
CPU time 3 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:22 PM PDT 24
Peak memory 218344 kb
Host smart-7094141e-d641-4699-928c-dd37bc5d3300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570310554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1570310554
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4061309549
Short name T456
Test name
Test status
Simulation time 18425554 ps
CPU time 0.79 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:46:16 PM PDT 24
Peak memory 204760 kb
Host smart-d1bf16c2-7b5a-4143-a918-22d57da2f025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061309549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4061309549
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2888468222
Short name T789
Test name
Test status
Simulation time 507017899 ps
CPU time 8.81 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:27 PM PDT 24
Peak memory 219680 kb
Host smart-efb7a939-6b06-401f-ba56-74582db919aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888468222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2888468222
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.946229643
Short name T376
Test name
Test status
Simulation time 68523114 ps
CPU time 0.73 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:13 PM PDT 24
Peak memory 204892 kb
Host smart-b26f055d-ca8e-4cda-9028-31de2b2dba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946229643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.946229643
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2843316095
Short name T802
Test name
Test status
Simulation time 66995607634 ps
CPU time 119.94 seconds
Started May 28 02:46:13 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 249856 kb
Host smart-ebce4094-913e-416c-a954-4f3d8637e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843316095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2843316095
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3090799884
Short name T40
Test name
Test status
Simulation time 36930036654 ps
CPU time 332.61 seconds
Started May 28 02:46:13 PM PDT 24
Finished May 28 02:51:52 PM PDT 24
Peak memory 265440 kb
Host smart-ea00d287-9c31-4029-ac38-403c97e4c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090799884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3090799884
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3971555113
Short name T794
Test name
Test status
Simulation time 75318370943 ps
CPU time 246.69 seconds
Started May 28 02:46:11 PM PDT 24
Finished May 28 02:50:24 PM PDT 24
Peak memory 248584 kb
Host smart-66dce210-41e1-4007-b777-ed6acec018c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971555113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3971555113
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2111438215
Short name T623
Test name
Test status
Simulation time 144030637 ps
CPU time 2.6 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:20 PM PDT 24
Peak memory 232372 kb
Host smart-242a1a92-c1e2-41e6-8795-0324f1864799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111438215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2111438215
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2443111143
Short name T321
Test name
Test status
Simulation time 122895506 ps
CPU time 2.78 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:21 PM PDT 24
Peak memory 235076 kb
Host smart-44e59812-8129-4e76-ab0f-f22c499fd858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443111143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2443111143
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1383653584
Short name T259
Test name
Test status
Simulation time 1224854279 ps
CPU time 7.3 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:25 PM PDT 24
Peak memory 224160 kb
Host smart-3c75c683-76ed-4af7-991a-f79266a5c502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383653584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1383653584
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3621900825
Short name T86
Test name
Test status
Simulation time 731525745 ps
CPU time 4.46 seconds
Started May 28 02:46:11 PM PDT 24
Finished May 28 02:46:22 PM PDT 24
Peak memory 234132 kb
Host smart-d0c1ac5d-3179-4e04-a203-1e1b32199da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621900825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3621900825
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1005894986
Short name T198
Test name
Test status
Simulation time 8900121600 ps
CPU time 8.44 seconds
Started May 28 02:46:15 PM PDT 24
Finished May 28 02:46:31 PM PDT 24
Peak memory 218256 kb
Host smart-6a9e4df6-50ba-465a-8067-d7a1225da31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005894986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1005894986
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.176077763
Short name T939
Test name
Test status
Simulation time 659167262 ps
CPU time 3.66 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:46:19 PM PDT 24
Peak memory 218896 kb
Host smart-1bbbfbca-6fa1-412d-a1c3-68a047edcab6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=176077763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.176077763
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3146056454
Short name T314
Test name
Test status
Simulation time 21677748033 ps
CPU time 120.68 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 248912 kb
Host smart-7a3f6fd7-fa73-4988-bb90-09f68c9c87b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146056454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3146056454
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.150109010
Short name T702
Test name
Test status
Simulation time 2092497967 ps
CPU time 12.9 seconds
Started May 28 02:46:09 PM PDT 24
Finished May 28 02:46:27 PM PDT 24
Peak memory 218700 kb
Host smart-1374f991-59a6-479b-b926-ba3f6e9ddb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150109010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.150109010
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.541917858
Short name T427
Test name
Test status
Simulation time 480768626 ps
CPU time 1.13 seconds
Started May 28 02:46:06 PM PDT 24
Finished May 28 02:46:13 PM PDT 24
Peak memory 207172 kb
Host smart-57c7d8a4-731a-4d91-8b09-00a724925e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541917858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.541917858
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2995313411
Short name T689
Test name
Test status
Simulation time 854604605 ps
CPU time 1.66 seconds
Started May 28 02:46:10 PM PDT 24
Finished May 28 02:46:17 PM PDT 24
Peak memory 215900 kb
Host smart-ada48de4-b9bc-4305-9bd2-d08b3f561ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995313411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2995313411
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2602957225
Short name T742
Test name
Test status
Simulation time 75709843 ps
CPU time 0.79 seconds
Started May 28 02:46:13 PM PDT 24
Finished May 28 02:46:21 PM PDT 24
Peak memory 205304 kb
Host smart-3e872afc-cec3-4a38-ba00-0795d3ee7767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602957225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2602957225
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2380584350
Short name T224
Test name
Test status
Simulation time 2565221571 ps
CPU time 6 seconds
Started May 28 02:46:14 PM PDT 24
Finished May 28 02:46:26 PM PDT 24
Peak memory 229792 kb
Host smart-cf497f4b-a2c7-4b41-92b4-b5a0b8e5ac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380584350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2380584350
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.895069697
Short name T474
Test name
Test status
Simulation time 14735784 ps
CPU time 0.73 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:33 PM PDT 24
Peak memory 204292 kb
Host smart-cc01d56e-75d5-4a96-be46-f004fd68eed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895069697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.895069697
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1457725335
Short name T369
Test name
Test status
Simulation time 1251000801 ps
CPU time 6.3 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:39 PM PDT 24
Peak memory 235844 kb
Host smart-64b3d1cb-aad3-472a-9936-1cd0ff6d7552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457725335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1457725335
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.718666552
Short name T563
Test name
Test status
Simulation time 212343925 ps
CPU time 0.77 seconds
Started May 28 02:46:12 PM PDT 24
Finished May 28 02:46:19 PM PDT 24
Peak memory 206268 kb
Host smart-21ef0477-6015-4e84-80a3-44c4119e782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718666552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.718666552
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2379934608
Short name T460
Test name
Test status
Simulation time 13271043 ps
CPU time 0.76 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:33 PM PDT 24
Peak memory 215380 kb
Host smart-0c759011-5e90-42cb-80c3-adbf7ec17395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379934608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2379934608
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2289378996
Short name T711
Test name
Test status
Simulation time 7723883488 ps
CPU time 71.52 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:47:39 PM PDT 24
Peak memory 239980 kb
Host smart-9f97b08d-7cc4-4d1d-93a8-1316ed0835d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289378996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2289378996
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1318166108
Short name T528
Test name
Test status
Simulation time 26468500554 ps
CPU time 280.24 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:51:13 PM PDT 24
Peak memory 264672 kb
Host smart-ba524a3c-49bc-4ad1-85c8-db268cdc1cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318166108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1318166108
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1411001117
Short name T767
Test name
Test status
Simulation time 21274907933 ps
CPU time 18.6 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:51 PM PDT 24
Peak memory 232396 kb
Host smart-6a21541f-9b1c-42cb-b684-2259fce78160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411001117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1411001117
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1555901219
Short name T257
Test name
Test status
Simulation time 142470761 ps
CPU time 4.12 seconds
Started May 28 02:46:15 PM PDT 24
Finished May 28 02:46:27 PM PDT 24
Peak memory 232792 kb
Host smart-f130723f-460b-40da-bc1d-facd156a593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555901219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1555901219
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3905279184
Short name T914
Test name
Test status
Simulation time 5197532630 ps
CPU time 19.05 seconds
Started May 28 02:46:16 PM PDT 24
Finished May 28 02:46:42 PM PDT 24
Peak memory 240120 kb
Host smart-4fe40446-af84-4e71-88e1-b503c110780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905279184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3905279184
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1903378493
Short name T293
Test name
Test status
Simulation time 9923409276 ps
CPU time 12.83 seconds
Started May 28 02:46:15 PM PDT 24
Finished May 28 02:46:36 PM PDT 24
Peak memory 232456 kb
Host smart-de4401c9-fe9f-4306-abc6-8b2b4bdbd39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903378493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1903378493
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.470891424
Short name T597
Test name
Test status
Simulation time 821066782 ps
CPU time 3.18 seconds
Started May 28 02:46:16 PM PDT 24
Finished May 28 02:46:26 PM PDT 24
Peak memory 217656 kb
Host smart-f91c8437-3300-4563-bd1e-374887795a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470891424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.470891424
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1787715219
Short name T636
Test name
Test status
Simulation time 4374928194 ps
CPU time 12.51 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:44 PM PDT 24
Peak memory 218732 kb
Host smart-3d923cc4-fb47-4679-aff0-c284e05b9f2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1787715219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1787715219
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.831892129
Short name T203
Test name
Test status
Simulation time 401002583321 ps
CPU time 891.73 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 03:01:24 PM PDT 24
Peak memory 273440 kb
Host smart-df969afa-2c9e-4c26-864d-997dc5bec54b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831892129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.831892129
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4151694720
Short name T501
Test name
Test status
Simulation time 1668162011 ps
CPU time 9.2 seconds
Started May 28 02:46:10 PM PDT 24
Finished May 28 02:46:25 PM PDT 24
Peak memory 215912 kb
Host smart-dc1e0c63-8eb8-4227-aa0a-e94891b18ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151694720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4151694720
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.335902468
Short name T785
Test name
Test status
Simulation time 6708357176 ps
CPU time 18.97 seconds
Started May 28 02:46:15 PM PDT 24
Finished May 28 02:46:41 PM PDT 24
Peak memory 215888 kb
Host smart-064547fe-4a30-4b3d-919e-5961152a4e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335902468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.335902468
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3247264718
Short name T316
Test name
Test status
Simulation time 34964450 ps
CPU time 1.02 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:46:28 PM PDT 24
Peak memory 206524 kb
Host smart-5205873f-a101-4eb6-979e-e4940cf552bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247264718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3247264718
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1900865845
Short name T664
Test name
Test status
Simulation time 112352505 ps
CPU time 0.85 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:46:29 PM PDT 24
Peak memory 205216 kb
Host smart-6e184cb9-29f1-4207-8363-ccabb59c46bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900865845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1900865845
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2183777698
Short name T688
Test name
Test status
Simulation time 1827922544 ps
CPU time 8.28 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:46:36 PM PDT 24
Peak memory 233800 kb
Host smart-7dbddec5-690c-4e1e-9352-f40818fa1b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183777698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2183777698
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3413739448
Short name T817
Test name
Test status
Simulation time 23141098 ps
CPU time 0.72 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:49 PM PDT 24
Peak memory 204292 kb
Host smart-d7b7883d-6073-43fb-8b95-07e18a3b5967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413739448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3413739448
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2286023015
Short name T84
Test name
Test status
Simulation time 653720991 ps
CPU time 3.31 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:46:32 PM PDT 24
Peak memory 219608 kb
Host smart-bb792549-1d83-4db8-8c3c-1062069d31c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286023015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2286023015
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2897049945
Short name T627
Test name
Test status
Simulation time 50939809 ps
CPU time 0.74 seconds
Started May 28 02:46:19 PM PDT 24
Finished May 28 02:46:32 PM PDT 24
Peak memory 205944 kb
Host smart-af7f9ca9-75cd-405a-9886-526508b73966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897049945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2897049945
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.925467230
Short name T338
Test name
Test status
Simulation time 18476293 ps
CPU time 0.81 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:46:28 PM PDT 24
Peak memory 215440 kb
Host smart-e15f1259-3298-46eb-8225-d75f16188965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925467230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.925467230
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.756748303
Short name T227
Test name
Test status
Simulation time 4441650391 ps
CPU time 29.64 seconds
Started May 28 02:46:19 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 252836 kb
Host smart-1f39384f-f986-4175-b1ea-2d60deeb8a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756748303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.756748303
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.929493065
Short name T199
Test name
Test status
Simulation time 189201578457 ps
CPU time 338.01 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:52:06 PM PDT 24
Peak memory 258668 kb
Host smart-e022a695-44c3-4359-b38c-b5dcbfe56f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929493065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.929493065
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4152305885
Short name T309
Test name
Test status
Simulation time 1987714510 ps
CPU time 8.76 seconds
Started May 28 02:46:24 PM PDT 24
Finished May 28 02:46:49 PM PDT 24
Peak memory 232408 kb
Host smart-5295f075-8ef1-4137-8754-f89318defa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152305885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4152305885
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3276366247
Short name T387
Test name
Test status
Simulation time 211681837 ps
CPU time 4.46 seconds
Started May 28 02:46:19 PM PDT 24
Finished May 28 02:46:34 PM PDT 24
Peak memory 233028 kb
Host smart-1543ca68-a794-4a6a-9431-e754b0a236b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276366247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3276366247
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2194919061
Short name T883
Test name
Test status
Simulation time 648849846 ps
CPU time 3.19 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:52 PM PDT 24
Peak memory 232384 kb
Host smart-7d49b727-0a9f-42c6-82af-9c4de604cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194919061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2194919061
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3293539738
Short name T285
Test name
Test status
Simulation time 90641302162 ps
CPU time 13.46 seconds
Started May 28 02:46:13 PM PDT 24
Finished May 28 02:46:33 PM PDT 24
Peak memory 225252 kb
Host smart-f5b6c33f-8207-4e5c-b3e8-caf420e36479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293539738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3293539738
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2626229338
Short name T773
Test name
Test status
Simulation time 41695855625 ps
CPU time 35.47 seconds
Started May 28 02:46:13 PM PDT 24
Finished May 28 02:46:55 PM PDT 24
Peak memory 218964 kb
Host smart-57daa0d3-0849-409c-b39d-8e3acc4eacba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626229338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2626229338
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3316519794
Short name T953
Test name
Test status
Simulation time 920153535 ps
CPU time 7 seconds
Started May 28 02:46:24 PM PDT 24
Finished May 28 02:46:47 PM PDT 24
Peak memory 218428 kb
Host smart-5057e361-cb31-4655-84e3-87861aed9236
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3316519794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3316519794
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3294304304
Short name T151
Test name
Test status
Simulation time 42015715617 ps
CPU time 348.23 seconds
Started May 28 02:46:28 PM PDT 24
Finished May 28 02:52:32 PM PDT 24
Peak memory 253004 kb
Host smart-c27c9119-da9f-4227-86ff-5f3b3b4f2176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294304304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3294304304
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3363626105
Short name T451
Test name
Test status
Simulation time 5334591430 ps
CPU time 22.25 seconds
Started May 28 02:46:19 PM PDT 24
Finished May 28 02:46:54 PM PDT 24
Peak memory 216244 kb
Host smart-d7b961e8-8ad1-4a5e-a1a3-be3ba2636721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363626105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3363626105
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2783859356
Short name T359
Test name
Test status
Simulation time 11090915919 ps
CPU time 14.16 seconds
Started May 28 02:46:19 PM PDT 24
Finished May 28 02:46:44 PM PDT 24
Peak memory 215904 kb
Host smart-64aca8dd-755c-4ab5-9193-9dc986b1e659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783859356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2783859356
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3217737175
Short name T856
Test name
Test status
Simulation time 13006436 ps
CPU time 0.74 seconds
Started May 28 02:46:13 PM PDT 24
Finished May 28 02:46:20 PM PDT 24
Peak memory 205032 kb
Host smart-18c62cb7-a614-4fb4-866b-da585a6b3b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217737175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3217737175
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.488084906
Short name T601
Test name
Test status
Simulation time 68181172 ps
CPU time 0.83 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:46:29 PM PDT 24
Peak memory 205304 kb
Host smart-5f6c5e6e-0c75-4af7-9885-a790932f1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488084906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.488084906
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3369455992
Short name T538
Test name
Test status
Simulation time 1509162622 ps
CPU time 5.76 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:46:55 PM PDT 24
Peak memory 219820 kb
Host smart-95ccec8a-e746-4000-b9d4-3ccaec38f33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369455992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3369455992
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.69350007
Short name T671
Test name
Test status
Simulation time 28207414 ps
CPU time 0.72 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:46:50 PM PDT 24
Peak memory 204840 kb
Host smart-589ada0c-606c-41be-bcc3-89d55d3ab5a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69350007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.69350007
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.103481080
Short name T238
Test name
Test status
Simulation time 612687704 ps
CPU time 9.74 seconds
Started May 28 02:46:16 PM PDT 24
Finished May 28 02:46:34 PM PDT 24
Peak memory 218220 kb
Host smart-57ec465f-168a-47c9-870a-d58bc9656713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103481080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.103481080
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1739606007
Short name T400
Test name
Test status
Simulation time 41286921 ps
CPU time 0.72 seconds
Started May 28 02:46:24 PM PDT 24
Finished May 28 02:46:40 PM PDT 24
Peak memory 204884 kb
Host smart-459a821c-398d-4322-aa4e-1ac175a2ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739606007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1739606007
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4022579429
Short name T810
Test name
Test status
Simulation time 13666085580 ps
CPU time 107.92 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 248840 kb
Host smart-e6715236-7a56-4e87-a9d5-f9940925654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022579429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4022579429
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4187229268
Short name T296
Test name
Test status
Simulation time 27832690812 ps
CPU time 251.77 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:51:01 PM PDT 24
Peak memory 264696 kb
Host smart-4cd5ce14-0106-48dc-a474-849cde2cb891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187229268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4187229268
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.506006547
Short name T280
Test name
Test status
Simulation time 12593950980 ps
CPU time 79.61 seconds
Started May 28 02:46:17 PM PDT 24
Finished May 28 02:47:47 PM PDT 24
Peak memory 250408 kb
Host smart-f4c34951-602e-445a-bd7a-e2cc05706149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506006547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.506006547
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.934670221
Short name T830
Test name
Test status
Simulation time 961955750 ps
CPU time 3.39 seconds
Started May 28 02:46:27 PM PDT 24
Finished May 28 02:46:46 PM PDT 24
Peak memory 232396 kb
Host smart-2cbbd514-1340-4c77-8d68-84b945de8156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934670221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.934670221
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4195559515
Short name T829
Test name
Test status
Simulation time 471669217 ps
CPU time 3.57 seconds
Started May 28 02:46:17 PM PDT 24
Finished May 28 02:46:30 PM PDT 24
Peak memory 232876 kb
Host smart-12b4a51a-348b-4b1d-a00f-1d328dc9404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195559515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4195559515
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3453077155
Short name T910
Test name
Test status
Simulation time 41719406314 ps
CPU time 30.3 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:47:19 PM PDT 24
Peak memory 218096 kb
Host smart-4e2b20fd-49b0-43be-b99d-c039cfd317fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453077155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3453077155
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.847164254
Short name T776
Test name
Test status
Simulation time 13530509387 ps
CPU time 4.62 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:46:32 PM PDT 24
Peak memory 233056 kb
Host smart-ba2e8d4b-14aa-455b-a8c0-a8fba007c453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847164254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.847164254
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2967107944
Short name T196
Test name
Test status
Simulation time 6152316280 ps
CPU time 15.6 seconds
Started May 28 02:46:28 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 218448 kb
Host smart-b166f4c9-4cc4-49d5-b354-0fac782f19d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967107944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2967107944
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1757169892
Short name T141
Test name
Test status
Simulation time 925112208 ps
CPU time 10.38 seconds
Started May 28 02:46:19 PM PDT 24
Finished May 28 02:46:41 PM PDT 24
Peak memory 222072 kb
Host smart-358dbc95-8c7d-44b1-a181-1ccd95e7da32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1757169892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1757169892
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1305541533
Short name T946
Test name
Test status
Simulation time 38537866486 ps
CPU time 252.12 seconds
Started May 28 02:46:17 PM PDT 24
Finished May 28 02:50:38 PM PDT 24
Peak memory 248844 kb
Host smart-4ad3b752-8aeb-4b8a-8a0e-c99f2466b866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305541533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1305541533
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3647589353
Short name T499
Test name
Test status
Simulation time 18250265966 ps
CPU time 24.52 seconds
Started May 28 02:46:33 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 215980 kb
Host smart-b65963b0-0097-40fa-b9d4-1c9e17f8575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647589353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3647589353
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.993291525
Short name T877
Test name
Test status
Simulation time 1172966328 ps
CPU time 6.15 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:46:55 PM PDT 24
Peak memory 215804 kb
Host smart-dfd054be-7b41-4e7b-b304-fdb9fa743a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993291525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.993291525
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.747802344
Short name T541
Test name
Test status
Simulation time 853501983 ps
CPU time 3.01 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:35 PM PDT 24
Peak memory 215908 kb
Host smart-ea93c0f6-d3d6-4450-8667-5def14f01782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747802344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.747802344
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3393368065
Short name T443
Test name
Test status
Simulation time 60369671 ps
CPU time 0.89 seconds
Started May 28 02:46:17 PM PDT 24
Finished May 28 02:46:27 PM PDT 24
Peak memory 205272 kb
Host smart-0dd3630a-a287-4ba2-a349-6c4380555f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393368065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3393368065
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3125935265
Short name T65
Test name
Test status
Simulation time 5551238345 ps
CPU time 17.74 seconds
Started May 28 02:46:28 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 234088 kb
Host smart-2bbd0630-29c4-45c0-85e9-a672011199d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125935265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3125935265
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.979202749
Short name T425
Test name
Test status
Simulation time 26344669 ps
CPU time 0.7 seconds
Started May 28 02:46:26 PM PDT 24
Finished May 28 02:46:42 PM PDT 24
Peak memory 204912 kb
Host smart-59ae3a0a-cb10-4cee-bfbc-39e8170fc23c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979202749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.979202749
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2286789794
Short name T938
Test name
Test status
Simulation time 321303667 ps
CPU time 4.18 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:53 PM PDT 24
Peak memory 233860 kb
Host smart-386cabf7-ba41-439a-b54e-5a635c8d0cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286789794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2286789794
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2570293691
Short name T428
Test name
Test status
Simulation time 196385594 ps
CPU time 0.78 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:46:50 PM PDT 24
Peak memory 206228 kb
Host smart-40708188-54e6-465d-8566-6eff381b31c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570293691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2570293691
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1653109724
Short name T166
Test name
Test status
Simulation time 49524172743 ps
CPU time 196.66 seconds
Started May 28 02:46:24 PM PDT 24
Finished May 28 02:49:57 PM PDT 24
Peak memory 249612 kb
Host smart-1e06fc2e-686c-45c2-b124-476ee613d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653109724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1653109724
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2760321554
Short name T795
Test name
Test status
Simulation time 5620917785 ps
CPU time 79.43 seconds
Started May 28 02:46:24 PM PDT 24
Finished May 28 02:47:59 PM PDT 24
Peak memory 256048 kb
Host smart-efc464a6-827a-46dd-8e3b-d45099747d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760321554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2760321554
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.4087220927
Short name T278
Test name
Test status
Simulation time 22226371431 ps
CPU time 68.18 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:47:56 PM PDT 24
Peak memory 252292 kb
Host smart-9064a066-7344-451c-87cc-28b3ce98ea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087220927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.4087220927
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3851427060
Short name T140
Test name
Test status
Simulation time 10029097866 ps
CPU time 10.84 seconds
Started May 28 02:46:26 PM PDT 24
Finished May 28 02:46:53 PM PDT 24
Peak memory 240660 kb
Host smart-d5ba06dc-f6f7-4c4b-b1a9-b3739c1d9a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851427060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3851427060
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2001954543
Short name T543
Test name
Test status
Simulation time 8700697715 ps
CPU time 15.88 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:47:05 PM PDT 24
Peak memory 234168 kb
Host smart-0eb0048f-5a25-46bd-a4ae-c11af3f2d019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001954543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2001954543
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1170327130
Short name T349
Test name
Test status
Simulation time 62397317 ps
CPU time 2.53 seconds
Started May 28 02:46:17 PM PDT 24
Finished May 28 02:46:28 PM PDT 24
Peak memory 221004 kb
Host smart-ec7b5095-4f20-4ed4-a047-97bcb02ef8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170327130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1170327130
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.727526608
Short name T253
Test name
Test status
Simulation time 3342517747 ps
CPU time 5.28 seconds
Started May 28 02:46:16 PM PDT 24
Finished May 28 02:46:30 PM PDT 24
Peak memory 233332 kb
Host smart-44b7d654-2ba0-4747-bba9-070d466b58d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727526608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.727526608
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2772734747
Short name T273
Test name
Test status
Simulation time 3332377058 ps
CPU time 4.93 seconds
Started May 28 02:46:19 PM PDT 24
Finished May 28 02:46:35 PM PDT 24
Peak memory 218328 kb
Host smart-20b1451e-0d88-43c3-9f4b-810c827d403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772734747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2772734747
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2245314773
Short name T486
Test name
Test status
Simulation time 1929842141 ps
CPU time 15.83 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:47:04 PM PDT 24
Peak memory 220040 kb
Host smart-33442d64-d28f-4b03-a8c4-f3d3f2d4fdef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2245314773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2245314773
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2093735841
Short name T550
Test name
Test status
Simulation time 22189164218 ps
CPU time 30.39 seconds
Started May 28 02:46:28 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 216004 kb
Host smart-b8012fa9-f749-423a-9a77-b66fc146eae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093735841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2093735841
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2895528651
Short name T156
Test name
Test status
Simulation time 2694093136 ps
CPU time 6.32 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:39 PM PDT 24
Peak memory 215864 kb
Host smart-df57575e-7c01-402f-bc86-f6f20cd3a4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895528651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2895528651
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1917675659
Short name T329
Test name
Test status
Simulation time 66735212 ps
CPU time 0.66 seconds
Started May 28 02:46:28 PM PDT 24
Finished May 28 02:46:45 PM PDT 24
Peak memory 204980 kb
Host smart-5de9b697-5961-4b46-b1e2-93d15326a877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917675659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1917675659
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1665520719
Short name T713
Test name
Test status
Simulation time 47733234 ps
CPU time 0.82 seconds
Started May 28 02:46:17 PM PDT 24
Finished May 28 02:46:27 PM PDT 24
Peak memory 205324 kb
Host smart-287b4182-54e2-4a1c-9381-d1e8828c487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665520719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1665520719
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1430389585
Short name T509
Test name
Test status
Simulation time 3198045221 ps
CPU time 7.75 seconds
Started May 28 02:46:18 PM PDT 24
Finished May 28 02:46:35 PM PDT 24
Peak memory 235180 kb
Host smart-e96656ec-7306-4bc5-aa9a-12954388b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430389585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1430389585
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.744765599
Short name T52
Test name
Test status
Simulation time 28431243 ps
CPU time 0.71 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:46:48 PM PDT 24
Peak memory 204788 kb
Host smart-83fafaa1-65da-4ec3-ad19-63f7471fd486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744765599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.744765599
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3294879094
Short name T549
Test name
Test status
Simulation time 752871424 ps
CPU time 6.1 seconds
Started May 28 02:46:26 PM PDT 24
Finished May 28 02:46:48 PM PDT 24
Peak memory 234048 kb
Host smart-226b5e3d-cebf-4c47-8c2a-1f812bb6a9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294879094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3294879094
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2470775917
Short name T536
Test name
Test status
Simulation time 65946714 ps
CPU time 0.78 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:46:50 PM PDT 24
Peak memory 206264 kb
Host smart-56d61cda-adbb-4a88-a31d-fdae2d0b8bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470775917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2470775917
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.360893120
Short name T191
Test name
Test status
Simulation time 129495323144 ps
CPU time 141.3 seconds
Started May 28 02:46:22 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 248800 kb
Host smart-20f0562e-42a9-41e3-a3ce-871b3d499cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360893120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.360893120
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.437119938
Short name T833
Test name
Test status
Simulation time 2226389695 ps
CPU time 52.65 seconds
Started May 28 02:46:22 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 241272 kb
Host smart-f18e6dfb-5300-4c66-82af-1e988545f843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437119938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.437119938
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.901113027
Short name T476
Test name
Test status
Simulation time 908272990 ps
CPU time 20.42 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:54 PM PDT 24
Peak memory 250268 kb
Host smart-280a1849-6ae3-4bf4-8b37-242cae26405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901113027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.901113027
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2214871040
Short name T218
Test name
Test status
Simulation time 78448477 ps
CPU time 3.02 seconds
Started May 28 02:46:22 PM PDT 24
Finished May 28 02:46:40 PM PDT 24
Peak memory 232412 kb
Host smart-47cabaaa-d9b0-4e8a-84a1-4ffd9ec07c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214871040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2214871040
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3451212813
Short name T263
Test name
Test status
Simulation time 729448029 ps
CPU time 5.77 seconds
Started May 28 02:46:21 PM PDT 24
Finished May 28 02:46:40 PM PDT 24
Peak memory 233236 kb
Host smart-49bc80fb-c1fd-4d5d-b23f-410931548a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451212813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3451212813
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1469567566
Short name T385
Test name
Test status
Simulation time 1120845630 ps
CPU time 4.67 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:46:54 PM PDT 24
Peak memory 233936 kb
Host smart-a2221062-05df-4106-9855-59926341e43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469567566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1469567566
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3076791304
Short name T793
Test name
Test status
Simulation time 6608237186 ps
CPU time 19.58 seconds
Started May 28 02:46:27 PM PDT 24
Finished May 28 02:47:02 PM PDT 24
Peak memory 234820 kb
Host smart-b0f0bdbd-5c29-41e6-837f-c42ce71bc497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076791304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3076791304
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.51336736
Short name T48
Test name
Test status
Simulation time 1057618549 ps
CPU time 4.66 seconds
Started May 28 02:46:27 PM PDT 24
Finished May 28 02:46:47 PM PDT 24
Peak memory 226712 kb
Host smart-89b0e0c4-154a-421c-b30d-81a9ea821ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51336736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.51336736
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3577196393
Short name T646
Test name
Test status
Simulation time 2333390521 ps
CPU time 13.23 seconds
Started May 28 02:46:20 PM PDT 24
Finished May 28 02:46:46 PM PDT 24
Peak memory 221540 kb
Host smart-ac0e5a13-6cff-462e-a610-7d965beaed48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3577196393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3577196393
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.933946524
Short name T149
Test name
Test status
Simulation time 6639108330 ps
CPU time 94.57 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 250736 kb
Host smart-f1776d65-8d02-479e-b555-13ebab5611dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933946524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.933946524
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4287425831
Short name T347
Test name
Test status
Simulation time 1592628535 ps
CPU time 3 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:46:53 PM PDT 24
Peak memory 215908 kb
Host smart-a98d8d3e-4b67-49de-9cff-21c071a71ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287425831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4287425831
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1665308155
Short name T534
Test name
Test status
Simulation time 4067984172 ps
CPU time 3.12 seconds
Started May 28 02:46:28 PM PDT 24
Finished May 28 02:46:46 PM PDT 24
Peak memory 215888 kb
Host smart-8782f519-fa5d-4faf-832a-6bb36344f8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665308155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1665308155
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2591668163
Short name T440
Test name
Test status
Simulation time 198589839 ps
CPU time 3.12 seconds
Started May 28 02:46:22 PM PDT 24
Finished May 28 02:46:40 PM PDT 24
Peak memory 215880 kb
Host smart-14afede8-8efa-49ce-b51e-dedafbb0c763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591668163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2591668163
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.528263551
Short name T846
Test name
Test status
Simulation time 100915346 ps
CPU time 0.87 seconds
Started May 28 02:46:26 PM PDT 24
Finished May 28 02:46:42 PM PDT 24
Peak memory 205300 kb
Host smart-175bf604-89ea-4e40-8cfd-162447e777c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528263551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.528263551
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1488156731
Short name T270
Test name
Test status
Simulation time 160362057 ps
CPU time 2.83 seconds
Started May 28 02:46:26 PM PDT 24
Finished May 28 02:46:45 PM PDT 24
Peak memory 224152 kb
Host smart-db0dc607-8cff-4b0c-88eb-fa88a5c09236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488156731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1488156731
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3176061770
Short name T619
Test name
Test status
Simulation time 36788430 ps
CPU time 0.72 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:44:46 PM PDT 24
Peak memory 204236 kb
Host smart-5a054f29-8909-4483-9892-d9bf82787a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176061770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
176061770
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3457880257
Short name T591
Test name
Test status
Simulation time 487054218 ps
CPU time 2.87 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:35 PM PDT 24
Peak memory 218220 kb
Host smart-a01a3a5c-44e9-49cf-8772-ba347c52e3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457880257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3457880257
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.238321257
Short name T520
Test name
Test status
Simulation time 17056729 ps
CPU time 0.8 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:31 PM PDT 24
Peak memory 205936 kb
Host smart-5f24b91a-4bdb-4747-a93e-c6f6c5c4621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238321257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.238321257
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.28934031
Short name T195
Test name
Test status
Simulation time 142630299966 ps
CPU time 316.87 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:49:54 PM PDT 24
Peak memory 253240 kb
Host smart-02bc054e-8a02-4bf2-b28a-2a49d12a52d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28934031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.28934031
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3436265260
Short name T67
Test name
Test status
Simulation time 21188663970 ps
CPU time 43.95 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:45:14 PM PDT 24
Peak memory 236300 kb
Host smart-39a72d15-627f-4d69-ab13-ecc074ef3acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436265260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3436265260
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2260900880
Short name T775
Test name
Test status
Simulation time 13330213643 ps
CPU time 42.73 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:45:10 PM PDT 24
Peak memory 233128 kb
Host smart-7c876112-5a86-426e-947a-0a38757a147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260900880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2260900880
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3382354816
Short name T439
Test name
Test status
Simulation time 1021776813 ps
CPU time 3.81 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:35 PM PDT 24
Peak memory 233212 kb
Host smart-7455c8e9-896a-4779-bf75-75805efe15c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382354816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3382354816
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3194071799
Short name T888
Test name
Test status
Simulation time 1416684386 ps
CPU time 18.6 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 233932 kb
Host smart-8bcb9397-59a9-40d7-a1e9-8194faad7537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194071799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3194071799
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.4188306365
Short name T24
Test name
Test status
Simulation time 95386936 ps
CPU time 1.04 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:30 PM PDT 24
Peak memory 216224 kb
Host smart-f4234bc0-2a16-4d0c-ab7c-1afdd37095a3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188306365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.4188306365
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1273689508
Short name T516
Test name
Test status
Simulation time 229904194 ps
CPU time 2.4 seconds
Started May 28 02:44:22 PM PDT 24
Finished May 28 02:44:28 PM PDT 24
Peak memory 220628 kb
Host smart-80be87a3-433c-4ca3-b5a6-fbbc11ff0a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273689508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1273689508
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3912391661
Short name T208
Test name
Test status
Simulation time 331719675 ps
CPU time 5.27 seconds
Started May 28 02:44:20 PM PDT 24
Finished May 28 02:44:29 PM PDT 24
Peak memory 239200 kb
Host smart-45b2b0cb-8223-4554-bb52-48c9c4d4b5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912391661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3912391661
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2227910741
Short name T389
Test name
Test status
Simulation time 14331840626 ps
CPU time 6.29 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:46 PM PDT 24
Peak memory 218508 kb
Host smart-a60d6b2c-3722-4b43-a9ee-563a99d18bb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2227910741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2227910741
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2208256633
Short name T153
Test name
Test status
Simulation time 9475414074 ps
CPU time 72.77 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:45:46 PM PDT 24
Peak memory 248964 kb
Host smart-d45f3b4c-55ad-46a2-a072-fec4fd56bffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208256633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2208256633
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3371013902
Short name T668
Test name
Test status
Simulation time 1329667501 ps
CPU time 13.18 seconds
Started May 28 02:44:27 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 215964 kb
Host smart-a96ad448-78e4-492f-a1b2-52eee456af9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371013902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3371013902
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.496233312
Short name T600
Test name
Test status
Simulation time 2338960536 ps
CPU time 5.06 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:44:45 PM PDT 24
Peak memory 215868 kb
Host smart-e86363f7-d9c9-49b1-b682-acd3db9e85a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496233312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.496233312
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2255827784
Short name T685
Test name
Test status
Simulation time 153778387 ps
CPU time 1.45 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:29 PM PDT 24
Peak memory 216052 kb
Host smart-400a0dd3-88b9-4d8a-a7ca-a64ff8ec15db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255827784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2255827784
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2413799717
Short name T791
Test name
Test status
Simulation time 139485525 ps
CPU time 1.08 seconds
Started May 28 02:44:20 PM PDT 24
Finished May 28 02:44:24 PM PDT 24
Peak memory 206316 kb
Host smart-96f8cf0a-de3f-40ca-9cf2-2826cb54521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413799717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2413799717
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2503857357
Short name T564
Test name
Test status
Simulation time 1100270732 ps
CPU time 3.61 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 219264 kb
Host smart-8bb1c3cf-8ebb-47bd-b2d1-2526929cc521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503857357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2503857357
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3480008296
Short name T893
Test name
Test status
Simulation time 12404047 ps
CPU time 0.68 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:30 PM PDT 24
Peak memory 205124 kb
Host smart-f7bc869f-1d3c-4361-8402-6481059d8e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480008296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
480008296
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2648336889
Short name T422
Test name
Test status
Simulation time 455941627 ps
CPU time 5.74 seconds
Started May 28 02:44:15 PM PDT 24
Finished May 28 02:44:24 PM PDT 24
Peak memory 234108 kb
Host smart-73050e0a-dc17-4dbb-8ecc-f94b5b02063c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648336889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2648336889
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2504337453
Short name T46
Test name
Test status
Simulation time 27866633 ps
CPU time 0.79 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:44:46 PM PDT 24
Peak memory 205884 kb
Host smart-8f22c721-8b82-4955-a8d2-59351ca30a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504337453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2504337453
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1314369614
Short name T225
Test name
Test status
Simulation time 50873119832 ps
CPU time 324.69 seconds
Started May 28 02:44:15 PM PDT 24
Finished May 28 02:49:43 PM PDT 24
Peak memory 256920 kb
Host smart-cb382540-2401-477e-9732-5e5f06714a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314369614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1314369614
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3403052105
Short name T873
Test name
Test status
Simulation time 38140782487 ps
CPU time 363.91 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:50:18 PM PDT 24
Peak memory 249000 kb
Host smart-6351b7b9-8a57-4527-ab5c-55bd2b34b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403052105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3403052105
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.374627878
Short name T962
Test name
Test status
Simulation time 618590353 ps
CPU time 13.34 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:48 PM PDT 24
Peak memory 238832 kb
Host smart-6dc4cbcc-fb4c-4c07-810a-9ffde4d79fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374627878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.374627878
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3321580831
Short name T714
Test name
Test status
Simulation time 78310480 ps
CPU time 2.64 seconds
Started May 28 02:44:18 PM PDT 24
Finished May 28 02:44:24 PM PDT 24
Peak memory 234948 kb
Host smart-d7ac011b-9dd2-4896-ba5d-b0a911557320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321580831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3321580831
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2415105418
Short name T706
Test name
Test status
Simulation time 2339538407 ps
CPU time 8.43 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:38 PM PDT 24
Peak memory 218248 kb
Host smart-f6f53fd3-44b4-408d-8fef-2d61add325a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415105418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2415105418
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.953541678
Short name T588
Test name
Test status
Simulation time 97557793 ps
CPU time 1.05 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:44:46 PM PDT 24
Peak memory 217400 kb
Host smart-fb4559e7-7341-435e-89d3-2adfcca3334a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953541678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.953541678
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1072922133
Short name T511
Test name
Test status
Simulation time 31330944816 ps
CPU time 11.68 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 232740 kb
Host smart-7776dc6b-c2f9-401a-b42c-bdfa08aa8e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072922133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1072922133
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1846275897
Short name T634
Test name
Test status
Simulation time 205177320 ps
CPU time 2.93 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:35 PM PDT 24
Peak memory 232392 kb
Host smart-a4b1af9a-7d35-4e2a-8704-5ff3affac5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846275897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1846275897
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1495699547
Short name T417
Test name
Test status
Simulation time 1267810428 ps
CPU time 8.43 seconds
Started May 28 02:44:16 PM PDT 24
Finished May 28 02:44:28 PM PDT 24
Peak memory 222600 kb
Host smart-97e1a739-73c2-46d7-9e39-a1c817af7557
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1495699547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1495699547
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2883986812
Short name T64
Test name
Test status
Simulation time 210960415 ps
CPU time 1.03 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:28 PM PDT 24
Peak memory 206296 kb
Host smart-81241d30-005b-4e79-ba56-316164dedcca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883986812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2883986812
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2930013529
Short name T453
Test name
Test status
Simulation time 6555320073 ps
CPU time 7.17 seconds
Started May 28 02:44:36 PM PDT 24
Finished May 28 02:44:56 PM PDT 24
Peak memory 215988 kb
Host smart-a656c8d4-0754-44a0-a04a-f42e923bf966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930013529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2930013529
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3729727510
Short name T728
Test name
Test status
Simulation time 6097716411 ps
CPU time 10.1 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:44:58 PM PDT 24
Peak memory 215832 kb
Host smart-a6567b56-1070-42a8-8cad-33001a62409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729727510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3729727510
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3521366628
Short name T366
Test name
Test status
Simulation time 88378973 ps
CPU time 1.19 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:30 PM PDT 24
Peak memory 215912 kb
Host smart-0b4e4c8b-eb91-4207-b155-b923c379ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521366628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3521366628
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1975770403
Short name T364
Test name
Test status
Simulation time 27309606 ps
CPU time 0.79 seconds
Started May 28 02:44:34 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 205260 kb
Host smart-9694f7a0-0fa4-4312-811e-208c8aaebdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975770403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1975770403
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1261386660
Short name T202
Test name
Test status
Simulation time 5208526364 ps
CPU time 18.39 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:50 PM PDT 24
Peak memory 233216 kb
Host smart-0e2ca47b-6265-46ce-859f-e37296426726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261386660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1261386660
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1250672814
Short name T8
Test name
Test status
Simulation time 161119416 ps
CPU time 0.72 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:37 PM PDT 24
Peak memory 204288 kb
Host smart-b7a1511e-47b6-4c9c-8dd0-cd500cbcd9b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250672814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
250672814
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2695360884
Short name T749
Test name
Test status
Simulation time 430166759 ps
CPU time 6.09 seconds
Started May 28 02:44:21 PM PDT 24
Finished May 28 02:44:31 PM PDT 24
Peak memory 218284 kb
Host smart-7b4f128a-a636-4e27-be8c-797e02683e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695360884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2695360884
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3270567824
Short name T615
Test name
Test status
Simulation time 49006478 ps
CPU time 0.73 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:35 PM PDT 24
Peak memory 204912 kb
Host smart-1c2aa1ed-b851-4e15-924f-1d4bb1190cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270567824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3270567824
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2086675611
Short name T693
Test name
Test status
Simulation time 2812283759 ps
CPU time 48.46 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:45:25 PM PDT 24
Peak memory 254412 kb
Host smart-bdba3204-e627-4622-a71b-229a5a076160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086675611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2086675611
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2905199835
Short name T70
Test name
Test status
Simulation time 18013236214 ps
CPU time 192.02 seconds
Started May 28 02:44:19 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 252184 kb
Host smart-4a2ecaaf-c203-4cdd-b500-25c5367679ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905199835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2905199835
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.879138087
Short name T130
Test name
Test status
Simulation time 49143845356 ps
CPU time 505.12 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:52:53 PM PDT 24
Peak memory 250360 kb
Host smart-64b07f2f-a4e0-4ba5-90de-9fc010529593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879138087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
879138087
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3775238928
Short name T221
Test name
Test status
Simulation time 112646858 ps
CPU time 3.44 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 224192 kb
Host smart-af8f1887-0427-40aa-acd5-b4a4a361f99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775238928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3775238928
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1929064583
Short name T936
Test name
Test status
Simulation time 524870169 ps
CPU time 4.41 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:38 PM PDT 24
Peak memory 233444 kb
Host smart-cc6fd5fc-a710-43cb-a3e0-1740342d4948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929064583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1929064583
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2913555605
Short name T533
Test name
Test status
Simulation time 2168497133 ps
CPU time 23.21 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:59 PM PDT 24
Peak memory 224192 kb
Host smart-ebd692f7-ef89-4b2c-a6ba-4d528bcd0dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913555605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2913555605
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.501673208
Short name T684
Test name
Test status
Simulation time 71619371 ps
CPU time 1 seconds
Started May 28 02:44:17 PM PDT 24
Finished May 28 02:44:22 PM PDT 24
Peak memory 216232 kb
Host smart-acc8e866-31f8-40d9-aad7-cfb2db814373
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501673208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.501673208
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3079191722
Short name T177
Test name
Test status
Simulation time 1649410113 ps
CPU time 8.32 seconds
Started May 28 02:44:17 PM PDT 24
Finished May 28 02:44:29 PM PDT 24
Peak memory 224176 kb
Host smart-0f101324-d90e-4477-97a6-fc00f8ec1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079191722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3079191722
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3960407553
Short name T266
Test name
Test status
Simulation time 1650565601 ps
CPU time 5.75 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:39 PM PDT 24
Peak memory 228324 kb
Host smart-a6a746bf-2047-43f1-9665-b3e5ba9f4d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960407553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3960407553
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2284086246
Short name T483
Test name
Test status
Simulation time 4745249077 ps
CPU time 4.63 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:33 PM PDT 24
Peak memory 218860 kb
Host smart-6186882e-9378-4b43-af9b-cfd86b6f1d0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2284086246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2284086246
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.547613146
Short name T152
Test name
Test status
Simulation time 171010389 ps
CPU time 1.02 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:30 PM PDT 24
Peak memory 206364 kb
Host smart-009d0461-6259-4344-b4c0-85bdc6a038a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547613146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.547613146
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.757466449
Short name T350
Test name
Test status
Simulation time 246810244 ps
CPU time 3.44 seconds
Started May 28 02:44:17 PM PDT 24
Finished May 28 02:44:24 PM PDT 24
Peak memory 215940 kb
Host smart-b9c7a64c-921b-4805-8a10-7af9556632b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757466449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.757466449
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3651752434
Short name T343
Test name
Test status
Simulation time 507228265 ps
CPU time 4.31 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:44:33 PM PDT 24
Peak memory 216144 kb
Host smart-4a06f317-f412-42de-8e75-a67ad9893f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651752434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3651752434
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4001496642
Short name T782
Test name
Test status
Simulation time 19641250 ps
CPU time 0.75 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:44:15 PM PDT 24
Peak memory 205324 kb
Host smart-5edd905d-0285-42a5-9e83-da86ecea6436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001496642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4001496642
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2612784975
Short name T666
Test name
Test status
Simulation time 30063535 ps
CPU time 0.9 seconds
Started May 28 02:44:12 PM PDT 24
Finished May 28 02:44:15 PM PDT 24
Peak memory 205320 kb
Host smart-696f1061-c190-479a-8bf7-e0e4342aa847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612784975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2612784975
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.326097563
Short name T642
Test name
Test status
Simulation time 669917385 ps
CPU time 6.09 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 218184 kb
Host smart-a4ae21d7-6c65-4a43-afb6-893928198161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326097563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.326097563
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1940956725
Short name T463
Test name
Test status
Simulation time 178653582 ps
CPU time 0.7 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:44:41 PM PDT 24
Peak memory 204908 kb
Host smart-081b3ec2-8d77-4581-b0ab-d83b4cf49f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940956725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
940956725
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1887618093
Short name T635
Test name
Test status
Simulation time 322154022 ps
CPU time 3.19 seconds
Started May 28 02:44:24 PM PDT 24
Finished May 28 02:44:34 PM PDT 24
Peak memory 218548 kb
Host smart-a68e9480-5eff-4955-a000-4960bfc54b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887618093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1887618093
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4120969151
Short name T800
Test name
Test status
Simulation time 32852498 ps
CPU time 0.8 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:38 PM PDT 24
Peak memory 205928 kb
Host smart-cc0775e5-500d-4c95-bfec-7d7b084badd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120969151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4120969151
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.911924802
Short name T295
Test name
Test status
Simulation time 73661832326 ps
CPU time 475.57 seconds
Started May 28 02:44:23 PM PDT 24
Finished May 28 02:52:23 PM PDT 24
Peak memory 252596 kb
Host smart-66acf545-7dc0-46a4-a4e0-5dc54b301276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911924802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.911924802
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.37120743
Short name T18
Test name
Test status
Simulation time 8034048204 ps
CPU time 28.24 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:45:01 PM PDT 24
Peak memory 217092 kb
Host smart-5c74b24b-bb19-412c-8959-3a946af2d951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37120743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.37120743
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2729599748
Short name T957
Test name
Test status
Simulation time 10083840724 ps
CPU time 105.85 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:46:19 PM PDT 24
Peak memory 264000 kb
Host smart-9081c243-3bf2-4442-b4ae-c03b752e0d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729599748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2729599748
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3299056972
Short name T686
Test name
Test status
Simulation time 121646730 ps
CPU time 3.7 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 232348 kb
Host smart-489eaf00-e802-45c1-9cbd-e707768b1d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299056972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3299056972
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3833001129
Short name T694
Test name
Test status
Simulation time 2191422180 ps
CPU time 21.03 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:45:01 PM PDT 24
Peak memory 234272 kb
Host smart-c509d043-d376-461b-8483-4891907a482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833001129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3833001129
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3792206611
Short name T836
Test name
Test status
Simulation time 6609201045 ps
CPU time 56.73 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:45:38 PM PDT 24
Peak memory 236404 kb
Host smart-9020b195-daf0-4ac5-b651-9d0a39c2f493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792206611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3792206611
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3628030752
Short name T599
Test name
Test status
Simulation time 487494749 ps
CPU time 1.08 seconds
Started May 28 02:44:30 PM PDT 24
Finished May 28 02:44:43 PM PDT 24
Peak memory 216172 kb
Host smart-1362759b-4467-4167-9036-4b2e9d2d24bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628030752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3628030752
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3962485801
Short name T7
Test name
Test status
Simulation time 279893257 ps
CPU time 3.08 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 235928 kb
Host smart-e8416107-4525-43de-8c5c-fe175f9067a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962485801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3962485801
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3695127113
Short name T700
Test name
Test status
Simulation time 13238915180 ps
CPU time 11.35 seconds
Started May 28 02:44:27 PM PDT 24
Finished May 28 02:44:50 PM PDT 24
Peak memory 218844 kb
Host smart-3423f3b5-c72b-4b23-8ab2-34d6748398cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695127113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3695127113
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2645668923
Short name T660
Test name
Test status
Simulation time 1574406826 ps
CPU time 10.11 seconds
Started May 28 02:44:27 PM PDT 24
Finished May 28 02:44:48 PM PDT 24
Peak memory 222244 kb
Host smart-4a1d4a14-e913-4f31-b002-ff1d0bb16b1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2645668923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2645668923
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.499326446
Short name T940
Test name
Test status
Simulation time 141301111827 ps
CPU time 409.13 seconds
Started May 28 02:44:29 PM PDT 24
Finished May 28 02:51:31 PM PDT 24
Peak memory 268812 kb
Host smart-48c0eaa1-2fe1-4f22-8079-8b1cc07bf54c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499326446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.499326446
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2379947468
Short name T838
Test name
Test status
Simulation time 9320044265 ps
CPU time 45.6 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:45:20 PM PDT 24
Peak memory 216032 kb
Host smart-6cfc225c-33c9-49dd-a4d8-901a0cf97cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379947468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2379947468
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1651585844
Short name T855
Test name
Test status
Simulation time 6726002097 ps
CPU time 5.31 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:41 PM PDT 24
Peak memory 215912 kb
Host smart-2d6bde41-b712-44c4-90e0-1522e631dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651585844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1651585844
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1215209024
Short name T741
Test name
Test status
Simulation time 39266660 ps
CPU time 0.69 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 204936 kb
Host smart-0d7163e5-475e-4ab4-9b7e-58e908957faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215209024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1215209024
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4087124206
Short name T346
Test name
Test status
Simulation time 14411653 ps
CPU time 0.69 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 205284 kb
Host smart-a25859f4-c726-41c5-ab5c-c5524904e152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087124206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4087124206
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1014108773
Short name T781
Test name
Test status
Simulation time 154831002 ps
CPU time 2.59 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 218528 kb
Host smart-a3ab4536-3484-4c63-8ea1-327339947621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014108773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1014108773
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3516190463
Short name T932
Test name
Test status
Simulation time 45564110 ps
CPU time 0.67 seconds
Started May 28 02:44:30 PM PDT 24
Finished May 28 02:44:43 PM PDT 24
Peak memory 204916 kb
Host smart-764b047f-cc8b-4c74-8e16-68bc41845bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516190463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
516190463
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.573114473
Short name T245
Test name
Test status
Simulation time 274229512 ps
CPU time 2.98 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:44:48 PM PDT 24
Peak memory 232988 kb
Host smart-6d287cc0-19b0-4501-b940-aee58dcb2099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573114473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.573114473
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1307705654
Short name T920
Test name
Test status
Simulation time 14591207 ps
CPU time 0.75 seconds
Started May 28 02:44:31 PM PDT 24
Finished May 28 02:44:43 PM PDT 24
Peak memory 205924 kb
Host smart-796e6f6b-905a-4825-a957-d1e4137c9329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307705654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1307705654
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3635640327
Short name T200
Test name
Test status
Simulation time 2245767173 ps
CPU time 26.67 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:45:03 PM PDT 24
Peak memory 240156 kb
Host smart-b0547a87-925f-4950-8a77-e2339e5a8461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635640327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3635640327
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1826245461
Short name T907
Test name
Test status
Simulation time 9266020593 ps
CPU time 70.42 seconds
Started May 28 02:44:33 PM PDT 24
Finished May 28 02:45:56 PM PDT 24
Peak memory 251852 kb
Host smart-ad85f8e2-9602-4e66-8bd9-45ce291e7986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826245461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1826245461
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2023915177
Short name T297
Test name
Test status
Simulation time 8353677720 ps
CPU time 123.19 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:46:47 PM PDT 24
Peak memory 255092 kb
Host smart-5df9d34b-e8e8-4336-9bb9-595a1b8dc863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023915177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2023915177
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2922526675
Short name T960
Test name
Test status
Simulation time 3300793790 ps
CPU time 15.33 seconds
Started May 28 02:44:31 PM PDT 24
Finished May 28 02:44:58 PM PDT 24
Peak memory 233556 kb
Host smart-0163bd1d-afad-4d8d-b48b-0c3dacf7db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922526675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2922526675
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3434423668
Short name T908
Test name
Test status
Simulation time 21561302286 ps
CPU time 40.21 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:45:18 PM PDT 24
Peak memory 219400 kb
Host smart-4ddd59a6-f2e8-4363-8470-a3075cfd267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434423668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3434423668
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1862211826
Short name T477
Test name
Test status
Simulation time 88330121 ps
CPU time 1.07 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:47 PM PDT 24
Peak memory 216228 kb
Host smart-f4fd55a7-5e20-49a5-aea8-b8f5d8fb84cf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862211826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1862211826
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2763255685
Short name T656
Test name
Test status
Simulation time 113019363 ps
CPU time 2.2 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:39 PM PDT 24
Peak memory 220564 kb
Host smart-787271dd-75d5-4170-a5b4-97e3830fc763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763255685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2763255685
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3453274602
Short name T262
Test name
Test status
Simulation time 2869115088 ps
CPU time 7.35 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:46 PM PDT 24
Peak memory 218712 kb
Host smart-ce368559-463a-459d-b0cb-c33aaec61487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453274602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3453274602
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.298212670
Short name T572
Test name
Test status
Simulation time 79751350 ps
CPU time 3.65 seconds
Started May 28 02:44:37 PM PDT 24
Finished May 28 02:44:53 PM PDT 24
Peak memory 218372 kb
Host smart-2252eac9-c480-4553-a3d5-56465aeaf764
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298212670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.298212670
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2872246556
Short name T282
Test name
Test status
Simulation time 41302167172 ps
CPU time 163.83 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:47:21 PM PDT 24
Peak memory 265296 kb
Host smart-3dc4eba8-5ebf-41ed-a13b-18707593aa5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872246556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2872246556
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.855779341
Short name T747
Test name
Test status
Simulation time 6412891575 ps
CPU time 6.16 seconds
Started May 28 02:44:26 PM PDT 24
Finished May 28 02:44:43 PM PDT 24
Peak memory 215908 kb
Host smart-a8a8f424-18eb-40db-9ce1-d2bafae6f67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855779341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.855779341
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.817015452
Short name T737
Test name
Test status
Simulation time 717489956 ps
CPU time 1.59 seconds
Started May 28 02:44:32 PM PDT 24
Finished May 28 02:44:45 PM PDT 24
Peak memory 207288 kb
Host smart-71f2e9e4-3037-43d1-91ef-35eaf2c96c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817015452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.817015452
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2520099900
Short name T796
Test name
Test status
Simulation time 17020884 ps
CPU time 0.85 seconds
Started May 28 02:44:25 PM PDT 24
Finished May 28 02:44:34 PM PDT 24
Peak memory 206696 kb
Host smart-72a83aba-9835-4828-9776-aa1b57a0c368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520099900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2520099900
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3679085264
Short name T497
Test name
Test status
Simulation time 45112313 ps
CPU time 0.7 seconds
Started May 28 02:44:28 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 205312 kb
Host smart-25d3affe-0950-4b8a-b835-8b68c0cd2ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679085264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3679085264
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1428616926
Short name T734
Test name
Test status
Simulation time 654763097 ps
CPU time 3.2 seconds
Started May 28 02:44:35 PM PDT 24
Finished May 28 02:44:51 PM PDT 24
Peak memory 217100 kb
Host smart-d9d7ced7-4daa-43ba-86c0-cdaccee993fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428616926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1428616926
Directory /workspace/9.spi_device_upload/latest
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