Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3555212	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3894076

1

T1

1

T2

553

T3

1851

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4217617	1			T1	1		T2	1		T3	1949
values[0x0]	1613617	1			T1	6		T2	317		T3	461
values[0x1]	1618054	1			T1	6		T2	356		T3	428

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2521890	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4927398

1

T1

2

T2

589

T3

2036

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27906	1			T3	15		T6	6		T7	157
valid_sources[0x01]	29409	1			T3	10		T4	3		T6	9
valid_sources[0x02]	28139	1			T2	1		T3	10		T4	1
valid_sources[0x03]	23916	1			T3	6		T4	7		T6	6
valid_sources[0x04]	31598	1			T2	4		T3	4		T4	1
valid_sources[0x05]	27745	1			T2	2		T3	17		T4	1
valid_sources[0x06]	28192	1			T3	12		T4	13		T6	7
valid_sources[0x07]	27469	1			T2	4		T3	17		T4	2
valid_sources[0x08]	26142	1			T3	9		T6	8		T7	118
valid_sources[0x09]	28133	1			T3	5		T6	4		T7	139
valid_sources[0x0a]	27479	1			T3	8		T6	6		T7	114
valid_sources[0x0b]	25635	1			T3	16		T6	9		T7	125
valid_sources[0x0c]	29351	1			T3	4		T4	5		T6	3
valid_sources[0x0d]	31368	1			T2	2		T3	12		T4	9
valid_sources[0x0e]	26018	1			T2	6		T3	10		T4	3
valid_sources[0x0f]	28030	1			T3	6		T4	5		T6	9
valid_sources[0x10]	29359	1			T3	6		T4	2		T6	2
valid_sources[0x11]	26814	1			T2	8		T3	18		T6	2
valid_sources[0x12]	27709	1			T3	7		T4	3		T6	3
valid_sources[0x13]	25108	1			T3	11		T4	1		T6	8
valid_sources[0x14]	35292	1			T3	11		T4	1		T6	7
valid_sources[0x15]	25060	1			T2	1		T3	9		T6	1
valid_sources[0x16]	27284	1			T3	14		T6	4		T7	124
valid_sources[0x17]	32424	1			T2	2		T3	15		T6	3
valid_sources[0x18]	27335	1			T3	6		T6	5		T7	123
valid_sources[0x19]	27021	1			T3	8		T4	2		T6	5
valid_sources[0x1a]	29358	1			T3	14		T4	2		T6	6
valid_sources[0x1b]	27837	1			T3	11		T6	11		T7	105
valid_sources[0x1c]	26072	1			T3	5		T4	7		T7	122
valid_sources[0x1d]	29969	1			T3	14		T4	6		T6	7
valid_sources[0x1e]	31832	1			T3	6		T4	6		T6	3
valid_sources[0x1f]	30807	1			T3	9		T6	3		T7	135
valid_sources[0x20]	26060	1			T3	18		T4	17		T6	9
valid_sources[0x21]	27182	1			T2	2		T3	8		T4	3
valid_sources[0x22]	28573	1			T3	7		T4	1		T6	8
valid_sources[0x23]	25405	1			T2	1		T3	8		T4	1
valid_sources[0x24]	28348	1			T3	12		T4	16		T6	5
valid_sources[0x25]	27156	1			T3	9		T6	3		T7	123
valid_sources[0x26]	29084	1			T2	12		T3	17		T4	3
valid_sources[0x27]	27428	1			T3	7		T6	8		T7	122
valid_sources[0x28]	26417	1			T3	11		T6	3		T7	111
valid_sources[0x29]	31798	1			T2	5		T3	8		T6	3
valid_sources[0x2a]	31767	1			T2	10		T3	7		T6	10
valid_sources[0x2b]	28554	1			T2	9		T3	9		T4	4
valid_sources[0x2c]	28060	1			T2	4		T3	6		T4	3
valid_sources[0x2d]	32846	1			T3	11		T4	2		T6	5
valid_sources[0x2e]	27217	1			T2	6		T3	5		T6	8
valid_sources[0x2f]	29475	1			T3	27		T4	1		T6	11
valid_sources[0x30]	28559	1			T2	2		T3	13		T4	2
valid_sources[0x31]	29013	1			T3	9		T6	4		T7	133
valid_sources[0x32]	30582	1			T2	6		T3	6		T6	11
valid_sources[0x33]	25226	1			T3	6		T6	3		T7	121
valid_sources[0x34]	28009	1			T3	5		T6	6		T7	123
valid_sources[0x35]	26800	1			T2	10		T3	7		T6	3
valid_sources[0x36]	31650	1			T3	8		T4	14		T6	4
valid_sources[0x37]	26703	1			T3	12		T4	3		T6	5
valid_sources[0x38]	26688	1			T3	15		T4	3		T6	4
valid_sources[0x39]	30385	1			T3	18		T4	2		T6	4
valid_sources[0x3a]	28672	1			T3	17		T4	2		T6	2
valid_sources[0x3b]	28331	1			T3	15		T6	9		T7	135
valid_sources[0x3c]	31504	1			T3	14		T4	1		T6	5
valid_sources[0x3d]	31100	1			T3	5		T4	1		T6	5
valid_sources[0x3e]	29503	1			T3	12		T4	6		T6	12
valid_sources[0x3f]	29002	1			T2	14		T3	13		T6	8
valid_sources[0x40]	31328	1			T2	26		T3	10		T4	4
valid_sources[0x41]	32176	1			T3	12		T6	7		T7	120
valid_sources[0x42]	30303	1			T2	1		T3	8		T4	1
valid_sources[0x43]	26569	1			T3	17		T6	6		T7	131
valid_sources[0x44]	32476	1			T3	19		T6	2		T7	126
valid_sources[0x45]	27824	1			T3	11		T4	4		T6	2
valid_sources[0x46]	28291	1			T2	2		T3	6		T4	3
valid_sources[0x47]	30041	1			T2	1		T3	7		T4	4
valid_sources[0x48]	27660	1			T2	7		T3	11		T4	1
valid_sources[0x49]	28334	1			T2	34		T3	11		T6	4
valid_sources[0x4a]	26963	1			T2	4		T3	11		T4	3
valid_sources[0x4b]	32925	1			T3	14		T6	2		T7	139
valid_sources[0x4c]	27675	1			T3	12		T4	6		T6	3
valid_sources[0x4d]	26308	1			T2	20		T3	8		T4	3
valid_sources[0x4e]	28065	1			T2	9		T3	12		T4	4
valid_sources[0x4f]	30298	1			T3	7		T6	2		T7	119
valid_sources[0x50]	25398	1			T3	11		T6	6		T7	131
valid_sources[0x51]	30210	1			T3	11		T4	2		T6	5
valid_sources[0x52]	78788	1			T2	10		T3	7		T6	6
valid_sources[0x53]	28593	1			T3	11		T4	4		T6	11
valid_sources[0x54]	32770	1			T3	11		T6	5		T7	109
valid_sources[0x55]	37335	1			T3	7		T4	6		T6	6
valid_sources[0x56]	24746	1			T2	1		T3	8		T4	1
valid_sources[0x57]	30744	1			T2	13		T3	24		T4	6
valid_sources[0x58]	25923	1			T2	22		T3	20		T4	2
valid_sources[0x59]	30747	1			T3	5		T4	7		T6	6
valid_sources[0x5a]	29316	1			T2	5		T3	12		T6	3
valid_sources[0x5b]	28039	1			T2	5		T3	11		T6	7
valid_sources[0x5c]	30201	1			T2	3		T3	20		T4	1
valid_sources[0x5d]	28245	1			T2	2		T3	17		T6	6
valid_sources[0x5e]	28817	1			T3	9		T4	3		T6	8
valid_sources[0x5f]	30798	1			T2	2		T3	14		T6	6
valid_sources[0x60]	28335	1			T3	8		T4	1		T6	9
valid_sources[0x61]	27949	1			T2	2		T3	9		T4	4
valid_sources[0x62]	25640	1			T3	9		T4	9		T6	9
valid_sources[0x63]	26651	1			T2	1		T3	11		T4	6
valid_sources[0x64]	30992	1			T3	8		T4	2		T6	6
valid_sources[0x65]	26472	1			T2	7		T3	9		T4	2
valid_sources[0x66]	28227	1			T3	11		T6	3		T7	103
valid_sources[0x67]	29707	1			T2	3		T3	18		T4	2
valid_sources[0x68]	32492	1			T3	8		T6	7		T7	91
valid_sources[0x69]	31947	1			T3	19		T6	4		T7	133
valid_sources[0x6a]	26829	1			T3	14		T6	5		T7	146
valid_sources[0x6b]	27228	1			T3	13		T4	4		T6	4
valid_sources[0x6c]	33842	1			T3	6		T4	7		T6	6
valid_sources[0x6d]	31144	1			T3	18		T4	1		T6	9
valid_sources[0x6e]	26883	1			T2	3		T3	15		T6	3
valid_sources[0x6f]	31719	1			T2	2		T3	15		T4	2
valid_sources[0x70]	28306	1			T3	7		T4	3		T6	3
valid_sources[0x71]	31073	1			T2	2		T3	10		T4	3
valid_sources[0x72]	27310	1			T3	12		T4	1		T6	5
valid_sources[0x73]	33582	1			T2	4		T3	9		T6	11
valid_sources[0x74]	30280	1			T3	18		T4	1		T6	4
valid_sources[0x75]	27167	1			T3	11		T4	4		T6	11
valid_sources[0x76]	27928	1			T2	1		T3	11		T4	3
valid_sources[0x77]	26879	1			T3	10		T6	4		T7	127
valid_sources[0x78]	26734	1			T3	9		T4	2		T6	6
valid_sources[0x79]	35287	1			T3	8		T4	3		T6	4
valid_sources[0x7a]	29190	1			T3	9		T5	451		T6	10
valid_sources[0x7b]	30373	1			T3	8		T6	12		T7	113
valid_sources[0x7c]	26889	1			T3	11		T4	1		T6	9
valid_sources[0x7d]	25556	1			T2	3		T3	4		T6	7
valid_sources[0x7e]	25795	1			T3	14		T6	3		T7	110
valid_sources[0x7f]	27251	1			T3	6		T6	6		T7	112
valid_sources[0x80]	27299	1			T2	2		T3	9		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

993178

1

T2

1

T3

972

T4

77

values[0x0]

all_enables

biggest_size

1460918

1

T1

1

T2

267

T3

458

values[0x1]

all_enables

biggest_size

1439980

1

T2

285

T3

421

T4

25