Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3572048

1

T1

12

T2

121

T3

987

full_word

3892912

1

T1

1

T2

553

T3

1851

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7464540	1			T1	13		T2	674		T3	2838
auto[TlIntgErrCmd]	120	1			T97	3		T98	4		T99	9
auto[TlIntgErrData]	144	1			T97	5		T98	6		T99	11
auto[TlIntgErrBoth]	156	1			T97	2		T98	10		T99	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4218986

1

T1

1

T2

1

T3

1949

auto[1]

3245974

1

T1

12

T2

673

T3

889

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3225538	1			T1	1		T3	977		T4	383
auto[TlIntgErrNone]	partial	auto[1]	346123	1			T1	11		T2	121		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	993245	1			T2	1		T3	972		T4	77
auto[TlIntgErrNone]	full_word	auto[1]	2899634	1			T1	1		T2	552		T3	879
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T97	1		T98	2		T99	6
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T97	2		T98	1		T99	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T98	1		T99	1		T175	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T173	1		T175	1		T177	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T97	4		T98	3		T99	5
auto[TlIntgErrData]	partial	auto[1]	62	1			T97	1		T98	1		T99	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T98	1		T99	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T98	1		T173	2		T174	1
auto[TlIntgErrBoth]	partial	auto[0]	71	1			T98	3		T99	6		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T97	2		T98	6		T99	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T99	1		T178	2		T179	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T98	1		T180	1		T176	2