Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	389149085	2428992	0	0
DepthKnown_A	389149085	389018473	0	0
RvalidKnown_A	389149085	389018473	0	0
WreadyKnown_A	389149085	389018473	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	2428992	0	0
T3	120724	1663	0	0
T4	11317	0	0	0
T5	75692	1663	0	0
T6	17991	832	0	0
T7	881388	17463	0	0
T8	552635	1668	0	0
T9	12841	1663	0	0
T10	3103	0	0	0
T11	969271	0	0	0
T12	442078	6655	0	0
T13	0	7496	0	0
T14	0	832	0	0
T15	0	11645	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	389149085	2599767	0	0
DepthKnown_A	389149085	389018473	0	0
RvalidKnown_A	389149085	389018473	0	0
WreadyKnown_A	389149085	389018473	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	2599767	0	0
T3	120724	832	0	0
T4	11317	0	0	0
T5	75692	832	0	0
T6	17991	832	0	0
T7	881388	9984	0	0
T8	552635	838	0	0
T9	12841	832	0	0
T10	3103	0	0	0
T11	969271	0	0	0
T12	442078	5824	0	0
T13	0	7993	0	0
T14	0	832	0	0
T15	0	9152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	389149085	161044	0	0
DepthKnown_A	389149085	389018473	0	0
RvalidKnown_A	389149085	389018473	0	0
WreadyKnown_A	389149085	389018473	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	161044	0	0
T4	11317	73	0	0
T5	75692	0	0	0
T6	17991	0	0	0
T7	881388	1371	0	0
T8	552635	193	0	0
T9	12841	0	0	0
T10	3103	11	0	0
T11	969271	959	0	0
T12	442078	1328	0	0
T13	707886	256	0	0
T15	0	520	0	0
T17	0	43	0	0
T24	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	389149085	363274	0	0
DepthKnown_A	389149085	389018473	0	0
RvalidKnown_A	389149085	389018473	0	0
WreadyKnown_A	389149085	389018473	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	363274	0	0
T4	11317	73	0	0
T5	75692	0	0	0
T6	17991	0	0	0
T7	881388	1367	0	0
T8	552635	654	0	0
T9	12841	0	0	0
T10	3103	11	0	0
T11	969271	4185	0	0
T12	442078	1327	0	0
T13	707886	930	0	0
T15	0	520	0	0
T17	0	43	0	0
T24	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	389149085	6098669	0	0
DepthKnown_A	389149085	389018473	0	0
RvalidKnown_A	389149085	389018473	0	0
WreadyKnown_A	389149085	389018473	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	6098669	0	0
T1	1071	13	0	0
T2	401134	674	0	0
T3	120724	2006	0	0
T4	11317	505	0	0
T5	75692	4046	0	0
T6	17991	581	0	0
T7	881388	19870	0	0
T8	552635	10541	0	0
T9	12841	442	0	0
T10	3103	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	389149085	13420016	0	0
DepthKnown_A	389149085	389018473	0	0
RvalidKnown_A	389149085	389018473	0	0
WreadyKnown_A	389149085	389018473	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	13420016	0	0
T1	1071	13	0	0
T2	401134	674	0	0
T3	120724	2006	0	0
T4	11317	505	0	0
T5	75692	4046	0	0
T6	17991	581	0	0
T7	881388	19676	0	0
T8	552635	30645	0	0
T9	12841	442	0	0
T10	3103	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389149085	389018473	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0