Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Unreachable
1	1	Covered	T4,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T12
1	0	Covered	T7,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T7,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	641878573	512970217	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	641878573	3103006	0	0
GntImpliesValid_A	641878573	3103006	0	0
GrantKnown_A	641878573	512970217	0	0
IdxKnown_A	641878573	512970217	0	0
IndexIsCorrect_A	641878573	3103006	0	0
LockArbDecision_A	641878573	0	0	0
NoReadyValidNoGrant_A	641878573	0	0	0
ReadyAndValidImplyGrant_A	641878573	3103006	0	0
ReqAndReadyImplyGrant_A	641878573	3103006	0	0
ReqImpliesValid_A	641878573	3103006	0	0
ReqStaysHighUntilGranted0_M	641878573	0	0	0
RoundRobin_A	641878573	7	0	926
ValidKnown_A	641878573	512970217	0	0
gen_data_port_assertion.DataFlow_A	641878573	3103006	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	512970217	0	0
T1	1071	1015	0	0
T2	482236	478233	0	0
T3	167744	144179	0	0
T4	20539	15365	0	0
T5	104616	90061	0	0
T6	52393	34630	0	0
T7	2428302	1643960	0	0
T8	737527	643717	0	0
T9	71105	41141	0	0
T10	6527	4752	0	0
T11	241518	114416	0	0
T12	761717	754031	0	0
T13	0	226818	0	0
T14	0	22716	0	0
T15	0	895402	0	0
T16	0	28936	0	0
T17	0	2672	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	3103006	0	0
T3	120724	832	0	0
T4	15928	435	0	0
T5	90154	832	0	0
T6	35192	832	0	0
T7	2428302	20538	0	0
T8	737527	2028	0	0
T9	71105	832	0	0
T10	6527	102	0	0
T11	1210789	8207	0	0
T12	1965512	18279	0	0
T13	457238	3305	0	0
T14	23014	0	0	0
T15	897248	8682	0	0
T17	0	198	0	0
T24	0	82	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T43	0	102	0	0
T44	0	356	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	3103006	0	0
T3	120724	832	0	0
T4	15928	435	0	0
T5	90154	832	0	0
T6	35192	832	0	0
T7	2428302	20538	0	0
T8	737527	2028	0	0
T9	71105	832	0	0
T10	6527	102	0	0
T11	1210789	8207	0	0
T12	1965512	18279	0	0
T13	457238	3305	0	0
T14	23014	0	0	0
T15	897248	8682	0	0
T17	0	198	0	0
T24	0	82	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T43	0	102	0	0
T44	0	356	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	512970217	0	0
T1	1071	1015	0	0
T2	482236	478233	0	0
T3	167744	144179	0	0
T4	20539	15365	0	0
T5	104616	90061	0	0
T6	52393	34630	0	0
T7	2428302	1643960	0	0
T8	737527	643717	0	0
T9	71105	41141	0	0
T10	6527	4752	0	0
T11	241518	114416	0	0
T12	761717	754031	0	0
T13	0	226818	0	0
T14	0	22716	0	0
T15	0	895402	0	0
T16	0	28936	0	0
T17	0	2672	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	512970217	0	0
T1	1071	1015	0	0
T2	482236	478233	0	0
T3	167744	144179	0	0
T4	20539	15365	0	0
T5	104616	90061	0	0
T6	52393	34630	0	0
T7	2428302	1643960	0	0
T8	737527	643717	0	0
T9	71105	41141	0	0
T10	6527	4752	0	0
T11	241518	114416	0	0
T12	761717	754031	0	0
T13	0	226818	0	0
T14	0	22716	0	0
T15	0	895402	0	0
T16	0	28936	0	0
T17	0	2672	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	3103006	0	0
T3	120724	832	0	0
T4	15928	435	0	0
T5	90154	832	0	0
T6	35192	832	0	0
T7	2428302	20538	0	0
T8	737527	2028	0	0
T9	71105	832	0	0
T10	6527	102	0	0
T11	1210789	8207	0	0
T12	1965512	18279	0	0
T13	457238	3305	0	0
T14	23014	0	0	0
T15	897248	8682	0	0
T17	0	198	0	0
T24	0	82	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T43	0	102	0	0
T44	0	356	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	3103006	0	0
T3	120724	832	0	0
T4	15928	435	0	0
T5	90154	832	0	0
T6	35192	832	0	0
T7	2428302	20538	0	0
T8	737527	2028	0	0
T9	71105	832	0	0
T10	6527	102	0	0
T11	1210789	8207	0	0
T12	1965512	18279	0	0
T13	457238	3305	0	0
T14	23014	0	0	0
T15	897248	8682	0	0
T17	0	198	0	0
T24	0	82	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T43	0	102	0	0
T44	0	356	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	3103006	0	0
T3	120724	832	0	0
T4	15928	435	0	0
T5	90154	832	0	0
T6	35192	832	0	0
T7	2428302	20538	0	0
T8	737527	2028	0	0
T9	71105	832	0	0
T10	6527	102	0	0
T11	1210789	8207	0	0
T12	1965512	18279	0	0
T13	457238	3305	0	0
T14	23014	0	0	0
T15	897248	8682	0	0
T17	0	198	0	0
T24	0	82	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T43	0	102	0	0
T44	0	356	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	3103006	0	0
T3	120724	832	0	0
T4	15928	435	0	0
T5	90154	832	0	0
T6	35192	832	0	0
T7	2428302	20538	0	0
T8	737527	2028	0	0
T9	71105	832	0	0
T10	6527	102	0	0
T11	1210789	8207	0	0
T12	1965512	18279	0	0
T13	457238	3305	0	0
T14	23014	0	0	0
T15	897248	8682	0	0
T17	0	198	0	0
T24	0	82	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T43	0	102	0	0
T44	0	356	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	7	0	926
T34	240712	1	0	1
T35	969207	0	0	1
T36	246098	0	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	393737	0	0	1
T52	69700	0	0	1
T53	27847	0	0	1
T54	239349	0	0	1
T55	162007	0	0	1
T56	1315	0	0	1
T57	8417	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	512970217	0	0
T1	1071	1015	0	0
T2	482236	478233	0	0
T3	167744	144179	0	0
T4	20539	15365	0	0
T5	104616	90061	0	0
T6	52393	34630	0	0
T7	2428302	1643960	0	0
T8	737527	643717	0	0
T9	71105	41141	0	0
T10	6527	4752	0	0
T11	241518	114416	0	0
T12	761717	754031	0	0
T13	0	226818	0	0
T14	0	22716	0	0
T15	0	895402	0	0
T16	0	28936	0	0
T17	0	2672	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	641878573	3103006	0	0
T3	120724	832	0	0
T4	15928	435	0	0
T5	90154	832	0	0
T6	35192	832	0	0
T7	2428302	20538	0	0
T8	737527	2028	0	0
T9	71105	832	0	0
T10	6527	102	0	0
T11	1210789	8207	0	0
T12	1965512	18279	0	0
T13	457238	3305	0	0
T14	23014	0	0	0
T15	897248	8682	0	0
T17	0	198	0	0
T24	0	82	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T43	0	102	0	0
T44	0	356	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Unreachable
1	1	Covered	T4,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	127510485	29430257	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	127510485	648413	0	0
GntImpliesValid_A	127510485	648413	0	0
GrantKnown_A	127510485	29430257	0	0
IdxKnown_A	127510485	29430257	0	0
IndexIsCorrect_A	127510485	648413	0	0
LockArbDecision_A	127510485	0	0	0
NoReadyValidNoGrant_A	127510485	0	0	0
ReadyAndValidImplyGrant_A	127510485	648413	0	0
ReqAndReadyImplyGrant_A	127510485	648413	0	0
ReqImpliesValid_A	127510485	648413	0	0
ReqStaysHighUntilGranted0_M	127510485	0	0	0
RoundRobin_A	127510485	0	0	0
ValidKnown_A	127510485	29430257	0	0
gen_data_port_assertion.DataFlow_A	127510485	648413	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	29430257	0	0
T2	81102	77184	0	0
T3	23510	0	0	0
T4	4611	4120	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	226448	0	0
T8	92446	19824	0	0
T9	29132	0	0	0
T10	1712	1712	0	0
T11	120759	114416	0	0
T12	0	319160	0	0
T15	0	19120	0	0
T16	0	28936	0	0
T17	0	2672	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	648413	0	0
T4	4611	328	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	5764	0	0
T8	92446	884	0	0
T9	29132	0	0	0
T10	1712	68	0	0
T11	120759	5562	0	0
T12	761717	5660	0	0
T13	228619	0	0	0
T15	0	355	0	0
T17	0	198	0	0
T24	0	82	0	0
T43	0	102	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	648413	0	0
T4	4611	328	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	5764	0	0
T8	92446	884	0	0
T9	29132	0	0	0
T10	1712	68	0	0
T11	120759	5562	0	0
T12	761717	5660	0	0
T13	228619	0	0	0
T15	0	355	0	0
T17	0	198	0	0
T24	0	82	0	0
T43	0	102	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	29430257	0	0
T2	81102	77184	0	0
T3	23510	0	0	0
T4	4611	4120	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	226448	0	0
T8	92446	19824	0	0
T9	29132	0	0	0
T10	1712	1712	0	0
T11	120759	114416	0	0
T12	0	319160	0	0
T15	0	19120	0	0
T16	0	28936	0	0
T17	0	2672	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	29430257	0	0
T2	81102	77184	0	0
T3	23510	0	0	0
T4	4611	4120	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	226448	0	0
T8	92446	19824	0	0
T9	29132	0	0	0
T10	1712	1712	0	0
T11	120759	114416	0	0
T12	0	319160	0	0
T15	0	19120	0	0
T16	0	28936	0	0
T17	0	2672	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	648413	0	0
T4	4611	328	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	5764	0	0
T8	92446	884	0	0
T9	29132	0	0	0
T10	1712	68	0	0
T11	120759	5562	0	0
T12	761717	5660	0	0
T13	228619	0	0	0
T15	0	355	0	0
T17	0	198	0	0
T24	0	82	0	0
T43	0	102	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	648413	0	0
T4	4611	328	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	5764	0	0
T8	92446	884	0	0
T9	29132	0	0	0
T10	1712	68	0	0
T11	120759	5562	0	0
T12	761717	5660	0	0
T13	228619	0	0	0
T15	0	355	0	0
T17	0	198	0	0
T24	0	82	0	0
T43	0	102	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	648413	0	0
T4	4611	328	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	5764	0	0
T8	92446	884	0	0
T9	29132	0	0	0
T10	1712	68	0	0
T11	120759	5562	0	0
T12	761717	5660	0	0
T13	228619	0	0	0
T15	0	355	0	0
T17	0	198	0	0
T24	0	82	0	0
T43	0	102	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	648413	0	0
T4	4611	328	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	5764	0	0
T8	92446	884	0	0
T9	29132	0	0	0
T10	1712	68	0	0
T11	120759	5562	0	0
T12	761717	5660	0	0
T13	228619	0	0	0
T15	0	355	0	0
T17	0	198	0	0
T24	0	82	0	0
T43	0	102	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	29430257	0	0
T2	81102	77184	0	0
T3	23510	0	0	0
T4	4611	4120	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	226448	0	0
T8	92446	19824	0	0
T9	29132	0	0	0
T10	1712	1712	0	0
T11	120759	114416	0	0
T12	0	319160	0	0
T15	0	19120	0	0
T16	0	28936	0	0
T17	0	2672	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	648413	0	0
T4	4611	328	0	0
T5	14462	0	0	0
T6	17201	0	0	0
T7	773457	5764	0	0
T8	92446	884	0	0
T9	29132	0	0	0
T10	1712	68	0	0
T11	120759	5562	0	0
T12	761717	5660	0	0
T13	228619	0	0	0
T15	0	355	0	0
T17	0	198	0	0
T24	0	82	0	0
T43	0	102	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T12
1	0	Covered	T7,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T7,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T12
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	127510485	96767759	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	127510485	491091	0	0
GntImpliesValid_A	127510485	491091	0	0
GrantKnown_A	127510485	96767759	0	0
IdxKnown_A	127510485	96767759	0	0
IndexIsCorrect_A	127510485	491091	0	0
LockArbDecision_A	127510485	0	0	0
NoReadyValidNoGrant_A	127510485	0	0	0
ReadyAndValidImplyGrant_A	127510485	491091	0	0
ReqAndReadyImplyGrant_A	127510485	491091	0	0
ReqImpliesValid_A	127510485	491091	0	0
ReqStaysHighUntilGranted0_M	127510485	0	0	0
RoundRobin_A	127510485	0	0	0
ValidKnown_A	127510485	96767759	0	0
gen_data_port_assertion.DataFlow_A	127510485	491091	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	96767759	0	0
T3	23510	23510	0	0
T4	4611	0	0	0
T5	14462	14462	0	0
T6	17201	16704	0	0
T7	773457	536208	0	0
T8	92446	71341	0	0
T9	29132	28350	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	434871	0	0
T13	0	226818	0	0
T14	0	22716	0	0
T15	0	876282	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	491091	0	0
T7	773457	1827	0	0
T8	92446	2	0	0
T9	29132	0	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	3931	0	0
T13	228619	3305	0	0
T14	23014	0	0	0
T15	897248	8327	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T44	0	356	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	491091	0	0
T7	773457	1827	0	0
T8	92446	2	0	0
T9	29132	0	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	3931	0	0
T13	228619	3305	0	0
T14	23014	0	0	0
T15	897248	8327	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T44	0	356	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	96767759	0	0
T3	23510	23510	0	0
T4	4611	0	0	0
T5	14462	14462	0	0
T6	17201	16704	0	0
T7	773457	536208	0	0
T8	92446	71341	0	0
T9	29132	28350	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	434871	0	0
T13	0	226818	0	0
T14	0	22716	0	0
T15	0	876282	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	96767759	0	0
T3	23510	23510	0	0
T4	4611	0	0	0
T5	14462	14462	0	0
T6	17201	16704	0	0
T7	773457	536208	0	0
T8	92446	71341	0	0
T9	29132	28350	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	434871	0	0
T13	0	226818	0	0
T14	0	22716	0	0
T15	0	876282	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	491091	0	0
T7	773457	1827	0	0
T8	92446	2	0	0
T9	29132	0	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	3931	0	0
T13	228619	3305	0	0
T14	23014	0	0	0
T15	897248	8327	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T44	0	356	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	491091	0	0
T7	773457	1827	0	0
T8	92446	2	0	0
T9	29132	0	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	3931	0	0
T13	228619	3305	0	0
T14	23014	0	0	0
T15	897248	8327	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T44	0	356	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	491091	0	0
T7	773457	1827	0	0
T8	92446	2	0	0
T9	29132	0	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	3931	0	0
T13	228619	3305	0	0
T14	23014	0	0	0
T15	897248	8327	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T44	0	356	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	491091	0	0
T7	773457	1827	0	0
T8	92446	2	0	0
T9	29132	0	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	3931	0	0
T13	228619	3305	0	0
T14	23014	0	0	0
T15	897248	8327	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T44	0	356	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	96767759	0	0
T3	23510	23510	0	0
T4	4611	0	0	0
T5	14462	14462	0	0
T6	17201	16704	0	0
T7	773457	536208	0	0
T8	92446	71341	0	0
T9	29132	28350	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	434871	0	0
T13	0	226818	0	0
T14	0	22716	0	0
T15	0	876282	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127510485	491091	0	0
T7	773457	1827	0	0
T8	92446	2	0	0
T9	29132	0	0	0
T10	1712	0	0	0
T11	120759	0	0	0
T12	761717	3931	0	0
T13	228619	3305	0	0
T14	23014	0	0	0
T15	897248	8327	0	0
T27	0	6209	0	0
T29	0	3035	0	0
T30	29311	0	0	0
T31	0	8	0	0
T42	0	3230	0	0
T44	0	356	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386857603	386772201	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	386857603	1963502	0	0
GntImpliesValid_A	386857603	1963502	0	0
GrantKnown_A	386857603	386772201	0	0
IdxKnown_A	386857603	386772201	0	0
IndexIsCorrect_A	386857603	1963502	0	0
LockArbDecision_A	386857603	0	0	0
NoReadyValidNoGrant_A	386857603	0	0	0
ReadyAndValidImplyGrant_A	386857603	1963502	0	0
ReqAndReadyImplyGrant_A	386857603	1963502	0	0
ReqImpliesValid_A	386857603	1963502	0	0
ReqStaysHighUntilGranted0_M	386857603	0	0	0
RoundRobin_A	386857603	7	0	926
ValidKnown_A	386857603	386772201	0	0
gen_data_port_assertion.DataFlow_A	386857603	1963502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	386772201	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	1963502	0	0
T3	120724	832	0	0
T4	11317	107	0	0
T5	75692	832	0	0
T6	17991	832	0	0
T7	881388	12947	0	0
T8	552635	1142	0	0
T9	12841	832	0	0
T10	3103	34	0	0
T11	969271	2645	0	0
T12	442078	8688	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	1963502	0	0
T3	120724	832	0	0
T4	11317	107	0	0
T5	75692	832	0	0
T6	17991	832	0	0
T7	881388	12947	0	0
T8	552635	1142	0	0
T9	12841	832	0	0
T10	3103	34	0	0
T11	969271	2645	0	0
T12	442078	8688	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	386772201	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	386772201	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	1963502	0	0
T3	120724	832	0	0
T4	11317	107	0	0
T5	75692	832	0	0
T6	17991	832	0	0
T7	881388	12947	0	0
T8	552635	1142	0	0
T9	12841	832	0	0
T10	3103	34	0	0
T11	969271	2645	0	0
T12	442078	8688	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	1963502	0	0
T3	120724	832	0	0
T4	11317	107	0	0
T5	75692	832	0	0
T6	17991	832	0	0
T7	881388	12947	0	0
T8	552635	1142	0	0
T9	12841	832	0	0
T10	3103	34	0	0
T11	969271	2645	0	0
T12	442078	8688	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	1963502	0	0
T3	120724	832	0	0
T4	11317	107	0	0
T5	75692	832	0	0
T6	17991	832	0	0
T7	881388	12947	0	0
T8	552635	1142	0	0
T9	12841	832	0	0
T10	3103	34	0	0
T11	969271	2645	0	0
T12	442078	8688	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	1963502	0	0
T3	120724	832	0	0
T4	11317	107	0	0
T5	75692	832	0	0
T6	17991	832	0	0
T7	881388	12947	0	0
T8	552635	1142	0	0
T9	12841	832	0	0
T10	3103	34	0	0
T11	969271	2645	0	0
T12	442078	8688	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	7	0	926
T34	240712	1	0	1
T35	969207	0	0	1
T36	246098	0	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	393737	0	0	1
T52	69700	0	0	1
T53	27847	0	0	1
T54	239349	0	0	1
T55	162007	0	0	1
T56	1315	0	0	1
T57	8417	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	386772201	0	0
T1	1071	1015	0	0
T2	401134	401049	0	0
T3	120724	120669	0	0
T4	11317	11245	0	0
T5	75692	75599	0	0
T6	17991	17926	0	0
T7	881388	881304	0	0
T8	552635	552552	0	0
T9	12841	12791	0	0
T10	3103	3040	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386857603	1963502	0	0
T3	120724	832	0	0
T4	11317	107	0	0
T5	75692	832	0	0
T6	17991	832	0	0
T7	881388	12947	0	0
T8	552635	1142	0	0
T9	12841	832	0	0
T10	3103	34	0	0
T11	969271	2645	0	0
T12	442078	8688	0	0