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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.11 98.35 94.20 98.61 89.36 97.23 95.82 99.20


Total test records in report: 1101
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T826 /workspace/coverage/default/23.spi_device_stress_all.2562508977 May 30 01:18:00 PM PDT 24 May 30 01:19:15 PM PDT 24 3532968279 ps
T827 /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1707903327 May 30 01:18:52 PM PDT 24 May 30 01:24:38 PM PDT 24 113253661500 ps
T828 /workspace/coverage/default/28.spi_device_csb_read.1636142708 May 30 01:18:07 PM PDT 24 May 30 01:18:10 PM PDT 24 40888644 ps
T829 /workspace/coverage/default/11.spi_device_upload.1180972907 May 30 01:17:03 PM PDT 24 May 30 01:17:09 PM PDT 24 1731151294 ps
T830 /workspace/coverage/default/38.spi_device_csb_read.57382985 May 30 01:18:37 PM PDT 24 May 30 01:18:39 PM PDT 24 27545990 ps
T831 /workspace/coverage/default/7.spi_device_tpm_sts_read.1244518681 May 30 01:16:41 PM PDT 24 May 30 01:16:43 PM PDT 24 40046872 ps
T206 /workspace/coverage/default/44.spi_device_stress_all.906362538 May 30 01:19:06 PM PDT 24 May 30 01:21:42 PM PDT 24 19981476845 ps
T832 /workspace/coverage/default/41.spi_device_tpm_rw.3252968351 May 30 01:18:55 PM PDT 24 May 30 01:18:59 PM PDT 24 827317503 ps
T833 /workspace/coverage/default/10.spi_device_csb_read.2550475250 May 30 01:16:50 PM PDT 24 May 30 01:16:51 PM PDT 24 18179818 ps
T834 /workspace/coverage/default/1.spi_device_alert_test.3569621637 May 30 01:16:20 PM PDT 24 May 30 01:16:21 PM PDT 24 42629588 ps
T835 /workspace/coverage/default/41.spi_device_intercept.355075836 May 30 01:18:53 PM PDT 24 May 30 01:19:02 PM PDT 24 301217201 ps
T836 /workspace/coverage/default/23.spi_device_alert_test.20565024 May 30 01:17:57 PM PDT 24 May 30 01:17:59 PM PDT 24 27749327 ps
T837 /workspace/coverage/default/14.spi_device_alert_test.2937592646 May 30 01:17:26 PM PDT 24 May 30 01:17:28 PM PDT 24 14172617 ps
T838 /workspace/coverage/default/11.spi_device_tpm_all.1142419151 May 30 01:16:55 PM PDT 24 May 30 01:17:14 PM PDT 24 6402476627 ps
T839 /workspace/coverage/default/30.spi_device_csb_read.3136964965 May 30 01:18:07 PM PDT 24 May 30 01:18:10 PM PDT 24 152121318 ps
T840 /workspace/coverage/default/3.spi_device_read_buffer_direct.1487050748 May 30 01:16:22 PM PDT 24 May 30 01:16:31 PM PDT 24 1279742173 ps
T841 /workspace/coverage/default/26.spi_device_intercept.3576709418 May 30 01:18:01 PM PDT 24 May 30 01:18:07 PM PDT 24 209028329 ps
T842 /workspace/coverage/default/6.spi_device_tpm_sts_read.246807369 May 30 01:16:37 PM PDT 24 May 30 01:16:38 PM PDT 24 67554915 ps
T843 /workspace/coverage/default/40.spi_device_tpm_sts_read.2272823247 May 30 01:18:52 PM PDT 24 May 30 01:18:54 PM PDT 24 61969760 ps
T844 /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2690246467 May 30 01:17:43 PM PDT 24 May 30 01:17:52 PM PDT 24 1204971896 ps
T845 /workspace/coverage/default/14.spi_device_stress_all.2097206612 May 30 01:17:23 PM PDT 24 May 30 01:19:14 PM PDT 24 7245172843 ps
T846 /workspace/coverage/default/12.spi_device_tpm_all.2446783668 May 30 01:17:03 PM PDT 24 May 30 01:17:14 PM PDT 24 6684547704 ps
T847 /workspace/coverage/default/0.spi_device_flash_all.2698788351 May 30 01:16:23 PM PDT 24 May 30 01:17:11 PM PDT 24 36731619138 ps
T848 /workspace/coverage/default/37.spi_device_tpm_sts_read.2148698710 May 30 01:18:37 PM PDT 24 May 30 01:18:39 PM PDT 24 40979426 ps
T292 /workspace/coverage/default/6.spi_device_stress_all.1659932863 May 30 01:16:40 PM PDT 24 May 30 01:20:19 PM PDT 24 101963244948 ps
T849 /workspace/coverage/default/4.spi_device_csb_read.3025062024 May 30 01:16:24 PM PDT 24 May 30 01:16:27 PM PDT 24 28552216 ps
T850 /workspace/coverage/default/27.spi_device_tpm_rw.3571740978 May 30 01:18:06 PM PDT 24 May 30 01:18:11 PM PDT 24 2047612885 ps
T851 /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3855157457 May 30 01:18:29 PM PDT 24 May 30 01:19:00 PM PDT 24 46584392277 ps
T852 /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.418381786 May 30 01:17:45 PM PDT 24 May 30 01:17:54 PM PDT 24 2993503804 ps
T853 /workspace/coverage/default/25.spi_device_mailbox.3050413551 May 30 01:17:56 PM PDT 24 May 30 01:18:15 PM PDT 24 1489883771 ps
T854 /workspace/coverage/default/36.spi_device_csb_read.2704156050 May 30 01:18:35 PM PDT 24 May 30 01:18:36 PM PDT 24 27139677 ps
T855 /workspace/coverage/default/1.spi_device_mailbox.1013722129 May 30 01:16:19 PM PDT 24 May 30 01:16:22 PM PDT 24 30854376 ps
T856 /workspace/coverage/default/8.spi_device_tpm_sts_read.3784511245 May 30 01:16:39 PM PDT 24 May 30 01:16:41 PM PDT 24 455549528 ps
T303 /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2598623644 May 30 01:17:02 PM PDT 24 May 30 01:17:58 PM PDT 24 20701642740 ps
T857 /workspace/coverage/default/19.spi_device_tpm_rw.1746413704 May 30 01:17:42 PM PDT 24 May 30 01:17:45 PM PDT 24 232777708 ps
T858 /workspace/coverage/default/21.spi_device_pass_cmd_filtering.667712189 May 30 01:17:42 PM PDT 24 May 30 01:17:47 PM PDT 24 1730092084 ps
T859 /workspace/coverage/default/45.spi_device_upload.1531193911 May 30 01:19:07 PM PDT 24 May 30 01:19:11 PM PDT 24 363024683 ps
T860 /workspace/coverage/default/14.spi_device_tpm_all.697453516 May 30 01:17:04 PM PDT 24 May 30 01:17:26 PM PDT 24 14876936373 ps
T861 /workspace/coverage/default/28.spi_device_tpm_sts_read.3729538748 May 30 01:18:04 PM PDT 24 May 30 01:18:07 PM PDT 24 570089439 ps
T862 /workspace/coverage/default/22.spi_device_csb_read.2980192193 May 30 01:17:45 PM PDT 24 May 30 01:17:47 PM PDT 24 38755970 ps
T863 /workspace/coverage/default/2.spi_device_mem_parity.4059785490 May 30 01:16:23 PM PDT 24 May 30 01:16:26 PM PDT 24 46727658 ps
T864 /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3323516244 May 30 01:16:24 PM PDT 24 May 30 01:16:32 PM PDT 24 1880042437 ps
T865 /workspace/coverage/default/9.spi_device_alert_test.3680425714 May 30 01:16:52 PM PDT 24 May 30 01:16:54 PM PDT 24 16292465 ps
T866 /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.233951823 May 30 01:18:24 PM PDT 24 May 30 01:18:30 PM PDT 24 3823573853 ps
T867 /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3394257807 May 30 01:19:17 PM PDT 24 May 30 01:19:22 PM PDT 24 1715105072 ps
T868 /workspace/coverage/default/22.spi_device_flash_mode.3116281695 May 30 01:17:45 PM PDT 24 May 30 01:17:55 PM PDT 24 2154605972 ps
T869 /workspace/coverage/default/36.spi_device_flash_all.664763764 May 30 01:18:38 PM PDT 24 May 30 01:19:07 PM PDT 24 23004680790 ps
T269 /workspace/coverage/default/45.spi_device_flash_all.1927549746 May 30 01:19:05 PM PDT 24 May 30 01:20:26 PM PDT 24 3516040496 ps
T870 /workspace/coverage/default/45.spi_device_cfg_cmd.2256425799 May 30 01:19:11 PM PDT 24 May 30 01:19:15 PM PDT 24 439565177 ps
T871 /workspace/coverage/default/9.spi_device_cfg_cmd.32509783 May 30 01:16:52 PM PDT 24 May 30 01:16:56 PM PDT 24 121870420 ps
T70 /workspace/coverage/default/3.spi_device_sec_cm.3483447528 May 30 01:16:21 PM PDT 24 May 30 01:16:24 PM PDT 24 127476468 ps
T872 /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.392904714 May 30 01:16:51 PM PDT 24 May 30 01:16:55 PM PDT 24 178471169 ps
T873 /workspace/coverage/default/20.spi_device_tpm_all.2063576365 May 30 01:17:42 PM PDT 24 May 30 01:17:54 PM PDT 24 2180944306 ps
T874 /workspace/coverage/default/37.spi_device_upload.491557506 May 30 01:18:36 PM PDT 24 May 30 01:18:44 PM PDT 24 2205819234 ps
T875 /workspace/coverage/default/38.spi_device_cfg_cmd.1591658646 May 30 01:18:39 PM PDT 24 May 30 01:18:43 PM PDT 24 682281158 ps
T876 /workspace/coverage/default/29.spi_device_upload.2359919479 May 30 01:18:07 PM PDT 24 May 30 01:18:11 PM PDT 24 804520414 ps
T877 /workspace/coverage/default/29.spi_device_intercept.322364218 May 30 01:18:08 PM PDT 24 May 30 01:18:15 PM PDT 24 518108226 ps
T878 /workspace/coverage/default/5.spi_device_tpm_all.1248530564 May 30 01:16:35 PM PDT 24 May 30 01:16:37 PM PDT 24 38857663 ps
T879 /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2598794301 May 30 01:18:54 PM PDT 24 May 30 01:19:00 PM PDT 24 404299208 ps
T880 /workspace/coverage/default/7.spi_device_mem_parity.749604809 May 30 01:16:39 PM PDT 24 May 30 01:16:42 PM PDT 24 353883218 ps
T881 /workspace/coverage/default/28.spi_device_flash_mode.825994688 May 30 01:18:05 PM PDT 24 May 30 01:18:09 PM PDT 24 517282779 ps
T882 /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2603709618 May 30 01:17:43 PM PDT 24 May 30 01:17:49 PM PDT 24 9097073848 ps
T883 /workspace/coverage/default/37.spi_device_csb_read.2772962957 May 30 01:18:36 PM PDT 24 May 30 01:18:37 PM PDT 24 35896277 ps
T884 /workspace/coverage/default/34.spi_device_tpm_sts_read.3234739563 May 30 01:18:23 PM PDT 24 May 30 01:18:25 PM PDT 24 52710687 ps
T885 /workspace/coverage/default/39.spi_device_tpm_sts_read.628378920 May 30 01:18:37 PM PDT 24 May 30 01:18:40 PM PDT 24 173954305 ps
T886 /workspace/coverage/default/42.spi_device_mailbox.1134804060 May 30 01:18:56 PM PDT 24 May 30 01:19:16 PM PDT 24 8839362106 ps
T308 /workspace/coverage/default/48.spi_device_flash_and_tpm.2923417140 May 30 01:19:18 PM PDT 24 May 30 01:32:47 PM PDT 24 76722171962 ps
T887 /workspace/coverage/default/20.spi_device_alert_test.1353707172 May 30 01:17:44 PM PDT 24 May 30 01:17:47 PM PDT 24 51491121 ps
T888 /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3585741367 May 30 01:17:41 PM PDT 24 May 30 01:18:02 PM PDT 24 61916675914 ps
T889 /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.591913086 May 30 01:18:23 PM PDT 24 May 30 01:18:31 PM PDT 24 2401896489 ps
T301 /workspace/coverage/default/39.spi_device_flash_all.1491467026 May 30 01:18:52 PM PDT 24 May 30 01:19:30 PM PDT 24 2617319541 ps
T890 /workspace/coverage/default/32.spi_device_tpm_all.1469487502 May 30 01:18:17 PM PDT 24 May 30 01:18:30 PM PDT 24 848262023 ps
T891 /workspace/coverage/default/0.spi_device_mailbox.3313824757 May 30 01:16:06 PM PDT 24 May 30 01:16:49 PM PDT 24 4115495448 ps
T892 /workspace/coverage/default/0.spi_device_cfg_cmd.3939495567 May 30 01:16:22 PM PDT 24 May 30 01:16:30 PM PDT 24 10845500575 ps
T893 /workspace/coverage/default/36.spi_device_stress_all.3833920563 May 30 01:18:41 PM PDT 24 May 30 01:24:34 PM PDT 24 39479450375 ps
T293 /workspace/coverage/default/18.spi_device_flash_and_tpm.3208499746 May 30 01:17:21 PM PDT 24 May 30 01:18:54 PM PDT 24 8035228968 ps
T894 /workspace/coverage/default/34.spi_device_mailbox.3574115069 May 30 01:18:30 PM PDT 24 May 30 01:19:18 PM PDT 24 6116541558 ps
T895 /workspace/coverage/default/11.spi_device_flash_and_tpm.2221209250 May 30 01:17:02 PM PDT 24 May 30 01:18:21 PM PDT 24 6716125169 ps
T896 /workspace/coverage/default/37.spi_device_flash_and_tpm.329521533 May 30 01:18:37 PM PDT 24 May 30 01:20:56 PM PDT 24 24375076350 ps
T897 /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1033230507 May 30 01:18:53 PM PDT 24 May 30 01:18:58 PM PDT 24 352703495 ps
T898 /workspace/coverage/default/24.spi_device_cfg_cmd.631712136 May 30 01:18:00 PM PDT 24 May 30 01:18:07 PM PDT 24 243074942 ps
T899 /workspace/coverage/default/28.spi_device_flash_all.837703515 May 30 01:18:08 PM PDT 24 May 30 01:19:59 PM PDT 24 56713534329 ps
T900 /workspace/coverage/default/26.spi_device_flash_mode.1510642456 May 30 01:17:58 PM PDT 24 May 30 01:18:05 PM PDT 24 373428022 ps
T901 /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1331907705 May 30 01:19:10 PM PDT 24 May 30 01:19:51 PM PDT 24 5560365011 ps
T902 /workspace/coverage/default/26.spi_device_flash_all.1682949969 May 30 01:18:04 PM PDT 24 May 30 01:18:57 PM PDT 24 22357672540 ps
T903 /workspace/coverage/default/27.spi_device_pass_cmd_filtering.370259805 May 30 01:18:00 PM PDT 24 May 30 01:18:05 PM PDT 24 261170838 ps
T904 /workspace/coverage/default/46.spi_device_pass_cmd_filtering.758017699 May 30 01:19:08 PM PDT 24 May 30 01:19:14 PM PDT 24 390180173 ps
T905 /workspace/coverage/default/17.spi_device_flash_and_tpm.19762255 May 30 01:17:20 PM PDT 24 May 30 01:19:14 PM PDT 24 65437659743 ps
T906 /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3483972413 May 30 01:16:23 PM PDT 24 May 30 01:16:29 PM PDT 24 538592474 ps
T907 /workspace/coverage/default/49.spi_device_cfg_cmd.1097805812 May 30 01:19:21 PM PDT 24 May 30 01:19:26 PM PDT 24 129535993 ps
T908 /workspace/coverage/default/11.spi_device_stress_all.2773055002 May 30 01:17:05 PM PDT 24 May 30 01:22:02 PM PDT 24 89227853815 ps
T909 /workspace/coverage/default/1.spi_device_flash_all.1469431789 May 30 01:16:21 PM PDT 24 May 30 01:17:25 PM PDT 24 4985960934 ps
T910 /workspace/coverage/default/39.spi_device_mailbox.553799287 May 30 01:18:35 PM PDT 24 May 30 01:19:02 PM PDT 24 4420133057 ps
T911 /workspace/coverage/default/8.spi_device_stress_all.1244189384 May 30 01:16:49 PM PDT 24 May 30 01:21:13 PM PDT 24 20165041538 ps
T912 /workspace/coverage/default/30.spi_device_intercept.1596499169 May 30 01:18:09 PM PDT 24 May 30 01:18:14 PM PDT 24 143539300 ps
T913 /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.589308638 May 30 01:18:56 PM PDT 24 May 30 01:19:00 PM PDT 24 133210211 ps
T914 /workspace/coverage/default/7.spi_device_read_buffer_direct.3243310412 May 30 01:16:40 PM PDT 24 May 30 01:16:51 PM PDT 24 2805696390 ps
T915 /workspace/coverage/default/7.spi_device_alert_test.99421605 May 30 01:16:42 PM PDT 24 May 30 01:16:45 PM PDT 24 22145866 ps
T916 /workspace/coverage/default/13.spi_device_flash_and_tpm.1245058855 May 30 01:17:06 PM PDT 24 May 30 01:17:47 PM PDT 24 6246422033 ps
T917 /workspace/coverage/default/1.spi_device_cfg_cmd.2261485905 May 30 01:16:22 PM PDT 24 May 30 01:16:28 PM PDT 24 423799722 ps
T918 /workspace/coverage/default/9.spi_device_mailbox.133754266 May 30 01:16:51 PM PDT 24 May 30 01:17:06 PM PDT 24 2944236214 ps
T919 /workspace/coverage/default/46.spi_device_csb_read.3560162548 May 30 01:19:06 PM PDT 24 May 30 01:19:08 PM PDT 24 43154623 ps
T920 /workspace/coverage/default/32.spi_device_flash_all.2610200502 May 30 01:18:20 PM PDT 24 May 30 01:18:22 PM PDT 24 30025163 ps
T921 /workspace/coverage/default/33.spi_device_cfg_cmd.2982861700 May 30 01:18:26 PM PDT 24 May 30 01:18:30 PM PDT 24 213458615 ps
T922 /workspace/coverage/default/30.spi_device_mailbox.793455741 May 30 01:18:11 PM PDT 24 May 30 01:18:45 PM PDT 24 7304056063 ps
T923 /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.721975057 May 30 01:17:21 PM PDT 24 May 30 01:17:23 PM PDT 24 20402462 ps
T924 /workspace/coverage/default/9.spi_device_read_buffer_direct.2770384627 May 30 01:16:51 PM PDT 24 May 30 01:17:05 PM PDT 24 3918119091 ps
T925 /workspace/coverage/default/49.spi_device_alert_test.2346867654 May 30 01:19:19 PM PDT 24 May 30 01:19:22 PM PDT 24 43629759 ps
T926 /workspace/coverage/default/38.spi_device_flash_and_tpm.1383705525 May 30 01:18:38 PM PDT 24 May 30 01:21:03 PM PDT 24 39306408967 ps
T273 /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3310516293 May 30 01:16:38 PM PDT 24 May 30 01:21:16 PM PDT 24 131960784045 ps
T927 /workspace/coverage/default/20.spi_device_flash_all.3206239324 May 30 01:17:43 PM PDT 24 May 30 01:21:38 PM PDT 24 140153291056 ps
T928 /workspace/coverage/default/10.spi_device_flash_all.3936649639 May 30 01:16:55 PM PDT 24 May 30 01:17:34 PM PDT 24 13178283291 ps
T213 /workspace/coverage/default/33.spi_device_stress_all.3209717516 May 30 01:18:28 PM PDT 24 May 30 01:23:19 PM PDT 24 59735510777 ps
T929 /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3154395579 May 30 01:18:54 PM PDT 24 May 30 01:19:05 PM PDT 24 1908116483 ps
T930 /workspace/coverage/default/7.spi_device_mailbox.1600078224 May 30 01:16:41 PM PDT 24 May 30 01:17:01 PM PDT 24 7370884918 ps
T931 /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2239910637 May 30 01:18:28 PM PDT 24 May 30 01:18:33 PM PDT 24 1058914465 ps
T932 /workspace/coverage/default/47.spi_device_upload.3810803558 May 30 01:19:08 PM PDT 24 May 30 01:19:28 PM PDT 24 7834686711 ps
T933 /workspace/coverage/default/25.spi_device_flash_and_tpm.794599023 May 30 01:17:55 PM PDT 24 May 30 01:22:05 PM PDT 24 26571367709 ps
T288 /workspace/coverage/default/18.spi_device_stress_all.70142767 May 30 01:17:19 PM PDT 24 May 30 01:18:53 PM PDT 24 33063974436 ps
T934 /workspace/coverage/default/34.spi_device_tpm_all.2190228523 May 30 01:18:30 PM PDT 24 May 30 01:18:44 PM PDT 24 12520483149 ps
T935 /workspace/coverage/default/47.spi_device_flash_mode.1045914414 May 30 01:19:07 PM PDT 24 May 30 01:19:13 PM PDT 24 573117844 ps
T290 /workspace/coverage/default/13.spi_device_stress_all.1820444887 May 30 01:17:01 PM PDT 24 May 30 01:24:30 PM PDT 24 174889328195 ps
T936 /workspace/coverage/default/7.spi_device_tpm_all.3738850186 May 30 01:16:42 PM PDT 24 May 30 01:16:51 PM PDT 24 3852665609 ps
T937 /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.382774004 May 30 01:17:05 PM PDT 24 May 30 01:17:10 PM PDT 24 744230724 ps
T938 /workspace/coverage/default/28.spi_device_mailbox.1997103460 May 30 01:18:05 PM PDT 24 May 30 01:18:25 PM PDT 24 2600908715 ps
T939 /workspace/coverage/default/47.spi_device_alert_test.2150526053 May 30 01:19:18 PM PDT 24 May 30 01:19:20 PM PDT 24 14622746 ps
T940 /workspace/coverage/default/6.spi_device_flash_mode.3657080223 May 30 01:16:40 PM PDT 24 May 30 01:17:51 PM PDT 24 5463682288 ps
T941 /workspace/coverage/default/37.spi_device_read_buffer_direct.2905505220 May 30 01:18:38 PM PDT 24 May 30 01:18:51 PM PDT 24 2014201304 ps
T942 /workspace/coverage/default/18.spi_device_read_buffer_direct.2015049539 May 30 01:17:28 PM PDT 24 May 30 01:17:38 PM PDT 24 754163709 ps
T943 /workspace/coverage/default/35.spi_device_cfg_cmd.2251865961 May 30 01:18:36 PM PDT 24 May 30 01:18:43 PM PDT 24 2813177785 ps
T944 /workspace/coverage/default/27.spi_device_flash_mode.590155163 May 30 01:18:05 PM PDT 24 May 30 01:18:23 PM PDT 24 18957670411 ps
T945 /workspace/coverage/default/17.spi_device_tpm_all.666852947 May 30 01:17:25 PM PDT 24 May 30 01:17:56 PM PDT 24 21124815684 ps
T946 /workspace/coverage/default/15.spi_device_upload.4014640513 May 30 01:17:23 PM PDT 24 May 30 01:17:31 PM PDT 24 9933388524 ps
T947 /workspace/coverage/default/41.spi_device_flash_mode.1940734231 May 30 01:18:54 PM PDT 24 May 30 01:19:00 PM PDT 24 739088730 ps
T287 /workspace/coverage/default/37.spi_device_stress_all.312087398 May 30 01:18:36 PM PDT 24 May 30 01:24:05 PM PDT 24 24503310572 ps
T294 /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2403676848 May 30 01:19:18 PM PDT 24 May 30 01:29:41 PM PDT 24 308932178021 ps
T948 /workspace/coverage/default/27.spi_device_upload.1112176372 May 30 01:18:06 PM PDT 24 May 30 01:18:19 PM PDT 24 11454201097 ps
T949 /workspace/coverage/default/2.spi_device_flash_mode.3083476950 May 30 01:16:24 PM PDT 24 May 30 01:16:59 PM PDT 24 17665427833 ps
T950 /workspace/coverage/default/11.spi_device_alert_test.4015461611 May 30 01:17:05 PM PDT 24 May 30 01:17:07 PM PDT 24 12010632 ps
T951 /workspace/coverage/default/25.spi_device_read_buffer_direct.458250606 May 30 01:18:02 PM PDT 24 May 30 01:18:07 PM PDT 24 586025912 ps
T952 /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3059582015 May 30 01:18:27 PM PDT 24 May 30 01:18:31 PM PDT 24 279196374 ps
T953 /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.344854972 May 30 01:18:41 PM PDT 24 May 30 01:18:49 PM PDT 24 921507367 ps
T954 /workspace/coverage/default/46.spi_device_tpm_rw.1675745881 May 30 01:19:10 PM PDT 24 May 30 01:19:13 PM PDT 24 34064626 ps
T955 /workspace/coverage/default/17.spi_device_alert_test.2580798041 May 30 01:17:22 PM PDT 24 May 30 01:17:24 PM PDT 24 30461519 ps
T956 /workspace/coverage/default/24.spi_device_intercept.1981722711 May 30 01:17:59 PM PDT 24 May 30 01:18:03 PM PDT 24 320412927 ps
T957 /workspace/coverage/default/19.spi_device_upload.2040157078 May 30 01:17:43 PM PDT 24 May 30 01:17:49 PM PDT 24 2916383045 ps
T140 /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.495577493 May 30 01:18:07 PM PDT 24 May 30 01:21:36 PM PDT 24 20499316657 ps
T958 /workspace/coverage/default/26.spi_device_cfg_cmd.1961084105 May 30 01:17:55 PM PDT 24 May 30 01:17:58 PM PDT 24 60602234 ps
T959 /workspace/coverage/default/29.spi_device_tpm_sts_read.1243812886 May 30 01:18:01 PM PDT 24 May 30 01:18:03 PM PDT 24 13325433 ps
T960 /workspace/coverage/default/14.spi_device_mailbox.3077008806 May 30 01:17:20 PM PDT 24 May 30 01:17:26 PM PDT 24 454299926 ps
T961 /workspace/coverage/default/41.spi_device_flash_all.4213099790 May 30 01:18:54 PM PDT 24 May 30 01:20:50 PM PDT 24 14778048782 ps
T962 /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1683700834 May 30 01:18:37 PM PDT 24 May 30 01:19:30 PM PDT 24 6349208926 ps
T963 /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1651795210 May 30 01:18:09 PM PDT 24 May 30 01:18:15 PM PDT 24 257556739 ps
T964 /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1919199726 May 30 01:17:44 PM PDT 24 May 30 01:17:54 PM PDT 24 4873986596 ps
T305 /workspace/coverage/default/26.spi_device_stress_all.1944990458 May 30 01:17:57 PM PDT 24 May 30 01:19:49 PM PDT 24 31765221837 ps
T965 /workspace/coverage/default/27.spi_device_stress_all.2378713260 May 30 01:17:59 PM PDT 24 May 30 01:18:01 PM PDT 24 47852029 ps
T966 /workspace/coverage/default/18.spi_device_tpm_sts_read.1710766871 May 30 01:17:22 PM PDT 24 May 30 01:17:24 PM PDT 24 37525913 ps
T967 /workspace/coverage/default/12.spi_device_upload.4204269685 May 30 01:17:06 PM PDT 24 May 30 01:17:23 PM PDT 24 3900354354 ps
T968 /workspace/coverage/default/20.spi_device_intercept.3130720793 May 30 01:17:43 PM PDT 24 May 30 01:18:05 PM PDT 24 8336889470 ps
T969 /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1627992780 May 30 01:17:19 PM PDT 24 May 30 01:17:34 PM PDT 24 3762978410 ps
T970 /workspace/coverage/default/49.spi_device_tpm_rw.2631159288 May 30 01:19:19 PM PDT 24 May 30 01:19:21 PM PDT 24 192618436 ps
T971 /workspace/coverage/default/7.spi_device_cfg_cmd.4218320970 May 30 01:16:41 PM PDT 24 May 30 01:16:46 PM PDT 24 1351868640 ps
T972 /workspace/coverage/default/47.spi_device_tpm_sts_read.4157188400 May 30 01:19:10 PM PDT 24 May 30 01:19:13 PM PDT 24 323038730 ps
T296 /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.17348034 May 30 01:17:43 PM PDT 24 May 30 01:19:08 PM PDT 24 4040789033 ps
T973 /workspace/coverage/default/2.spi_device_flash_all.3458322372 May 30 01:16:25 PM PDT 24 May 30 01:16:57 PM PDT 24 12205522457 ps
T974 /workspace/coverage/default/42.spi_device_flash_and_tpm.608538385 May 30 01:18:56 PM PDT 24 May 30 01:20:06 PM PDT 24 6894107103 ps
T975 /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2731113822 May 30 01:18:38 PM PDT 24 May 30 01:18:46 PM PDT 24 1432502381 ps
T976 /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2323937021 May 30 01:18:08 PM PDT 24 May 30 01:18:15 PM PDT 24 628666871 ps
T977 /workspace/coverage/default/4.spi_device_upload.3535543895 May 30 01:16:24 PM PDT 24 May 30 01:16:28 PM PDT 24 189921855 ps
T978 /workspace/coverage/default/12.spi_device_stress_all.2780742691 May 30 01:17:05 PM PDT 24 May 30 01:17:07 PM PDT 24 34421636 ps
T979 /workspace/coverage/default/6.spi_device_intercept.1958358806 May 30 01:16:37 PM PDT 24 May 30 01:17:05 PM PDT 24 2663155272 ps
T980 /workspace/coverage/default/25.spi_device_tpm_sts_read.860695271 May 30 01:17:58 PM PDT 24 May 30 01:18:00 PM PDT 24 241376273 ps
T50 /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2960233714 May 30 01:17:43 PM PDT 24 May 30 01:21:56 PM PDT 24 45283563172 ps
T981 /workspace/coverage/default/47.spi_device_intercept.877903023 May 30 01:19:15 PM PDT 24 May 30 01:19:19 PM PDT 24 201152331 ps
T982 /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2747937944 May 30 01:17:44 PM PDT 24 May 30 01:17:51 PM PDT 24 407593295 ps
T983 /workspace/coverage/default/20.spi_device_flash_and_tpm.4153980974 May 30 01:17:46 PM PDT 24 May 30 01:18:01 PM PDT 24 1682815915 ps
T119 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1145627819 May 30 01:09:00 PM PDT 24 May 30 01:09:03 PM PDT 24 74126466 ps
T93 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.123566139 May 30 01:08:59 PM PDT 24 May 30 01:09:02 PM PDT 24 470932180 ps
T147 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1357387909 May 30 01:09:06 PM PDT 24 May 30 01:09:15 PM PDT 24 566410269 ps
T120 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.548923137 May 30 01:09:17 PM PDT 24 May 30 01:09:20 PM PDT 24 82911997 ps
T94 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3985430826 May 30 01:09:14 PM PDT 24 May 30 01:09:19 PM PDT 24 484029225 ps
T984 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3763457407 May 30 01:09:10 PM PDT 24 May 30 01:09:12 PM PDT 24 55891384 ps
T95 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1419210812 May 30 01:09:14 PM PDT 24 May 30 01:09:19 PM PDT 24 471961528 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3720500719 May 30 01:08:58 PM PDT 24 May 30 01:09:09 PM PDT 24 640324791 ps
T122 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3212586092 May 30 01:09:10 PM PDT 24 May 30 01:09:13 PM PDT 24 131440877 ps
T985 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2050965523 May 30 01:09:14 PM PDT 24 May 30 01:09:15 PM PDT 24 134087366 ps
T986 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3538710374 May 30 01:08:56 PM PDT 24 May 30 01:08:58 PM PDT 24 40619170 ps
T96 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3800200080 May 30 01:09:00 PM PDT 24 May 30 01:09:03 PM PDT 24 32623367 ps
T987 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.722860573 May 30 01:08:56 PM PDT 24 May 30 01:09:12 PM PDT 24 217534690 ps
T141 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3925313205 May 30 01:08:59 PM PDT 24 May 30 01:09:03 PM PDT 24 328595348 ps
T123 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3839355832 May 30 01:09:09 PM PDT 24 May 30 01:09:13 PM PDT 24 404721560 ps
T124 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.882711696 May 30 01:08:58 PM PDT 24 May 30 01:09:01 PM PDT 24 423316649 ps
T142 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3869397776 May 30 01:09:06 PM PDT 24 May 30 01:09:11 PM PDT 24 154124697 ps
T988 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3996870848 May 30 01:09:03 PM PDT 24 May 30 01:09:08 PM PDT 24 593472125 ps
T989 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2202615165 May 30 01:09:06 PM PDT 24 May 30 01:09:08 PM PDT 24 13215156 ps
T990 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3958809281 May 30 01:09:05 PM PDT 24 May 30 01:09:09 PM PDT 24 361733608 ps
T125 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3064586396 May 30 01:09:00 PM PDT 24 May 30 01:09:03 PM PDT 24 32813474 ps
T97 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3918333496 May 30 01:09:00 PM PDT 24 May 30 01:09:09 PM PDT 24 210347436 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3178559339 May 30 01:08:59 PM PDT 24 May 30 01:09:02 PM PDT 24 32728975 ps
T991 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.30040620 May 30 01:09:06 PM PDT 24 May 30 01:09:09 PM PDT 24 51913960 ps
T98 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.47493828 May 30 01:08:58 PM PDT 24 May 30 01:09:15 PM PDT 24 5691917696 ps
T992 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3994427456 May 30 01:08:57 PM PDT 24 May 30 01:08:59 PM PDT 24 12748575 ps
T993 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1150890722 May 30 01:08:59 PM PDT 24 May 30 01:09:27 PM PDT 24 4840471973 ps
T100 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2775200211 May 30 01:09:09 PM PDT 24 May 30 01:09:14 PM PDT 24 133367051 ps
T99 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1207598085 May 30 01:08:58 PM PDT 24 May 30 01:09:22 PM PDT 24 827580368 ps
T994 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3103244176 May 30 01:09:16 PM PDT 24 May 30 01:09:18 PM PDT 24 20769075 ps
T995 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3006777902 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 11689050 ps
T115 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.989215342 May 30 01:09:18 PM PDT 24 May 30 01:09:23 PM PDT 24 165477653 ps
T116 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2617551747 May 30 01:09:10 PM PDT 24 May 30 01:09:14 PM PDT 24 911254980 ps
T996 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.150670208 May 30 01:09:15 PM PDT 24 May 30 01:09:17 PM PDT 24 114546702 ps
T110 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1236926938 May 30 01:09:17 PM PDT 24 May 30 01:09:20 PM PDT 24 35417975 ps
T997 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.60855862 May 30 01:09:16 PM PDT 24 May 30 01:09:18 PM PDT 24 53304959 ps
T117 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1457074294 May 30 01:09:10 PM PDT 24 May 30 01:09:19 PM PDT 24 1217375955 ps
T998 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2134607645 May 30 01:09:15 PM PDT 24 May 30 01:09:17 PM PDT 24 43035620 ps
T999 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1026895758 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 32285490 ps
T105 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.329784509 May 30 01:09:00 PM PDT 24 May 30 01:09:05 PM PDT 24 60992527 ps
T1000 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3315775016 May 30 01:09:02 PM PDT 24 May 30 01:09:04 PM PDT 24 20649756 ps
T173 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2790756009 May 30 01:09:06 PM PDT 24 May 30 01:09:21 PM PDT 24 2795848415 ps
T1001 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3749841228 May 30 01:08:59 PM PDT 24 May 30 01:09:03 PM PDT 24 376990876 ps
T1002 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.470677128 May 30 01:09:07 PM PDT 24 May 30 01:09:09 PM PDT 24 44357724 ps
T129 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1847318850 May 30 01:09:00 PM PDT 24 May 30 01:09:39 PM PDT 24 7208304191 ps
T1003 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.995432711 May 30 01:09:09 PM PDT 24 May 30 01:09:11 PM PDT 24 248948485 ps
T148 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.370174107 May 30 01:08:56 PM PDT 24 May 30 01:08:59 PM PDT 24 164523226 ps
T1004 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1438837621 May 30 01:09:09 PM PDT 24 May 30 01:09:13 PM PDT 24 326125408 ps
T127 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3124639608 May 30 01:09:01 PM PDT 24 May 30 01:09:18 PM PDT 24 762208487 ps
T1005 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2553030033 May 30 01:09:16 PM PDT 24 May 30 01:09:18 PM PDT 24 36698801 ps
T113 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1192583720 May 30 01:09:11 PM PDT 24 May 30 01:09:15 PM PDT 24 560430225 ps
T1006 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.285309773 May 30 01:09:07 PM PDT 24 May 30 01:09:09 PM PDT 24 318136856 ps
T1007 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3824742172 May 30 01:08:58 PM PDT 24 May 30 01:09:03 PM PDT 24 118778412 ps
T1008 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.660001183 May 30 01:09:11 PM PDT 24 May 30 01:09:13 PM PDT 24 13568168 ps
T1009 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.176894080 May 30 01:09:20 PM PDT 24 May 30 01:09:23 PM PDT 24 29546605 ps
T106 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3402366799 May 30 01:09:09 PM PDT 24 May 30 01:09:14 PM PDT 24 183527038 ps
T107 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1818670812 May 30 01:09:15 PM PDT 24 May 30 01:09:21 PM PDT 24 68310541 ps
T109 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3812870082 May 30 01:09:16 PM PDT 24 May 30 01:09:21 PM PDT 24 518021661 ps
T1010 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3168305257 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 38847862 ps
T101 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1573878489 May 30 01:09:06 PM PDT 24 May 30 01:09:08 PM PDT 24 90700088 ps
T128 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2721373254 May 30 01:09:15 PM PDT 24 May 30 01:09:19 PM PDT 24 109670400 ps
T1011 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2551205482 May 30 01:09:02 PM PDT 24 May 30 01:09:05 PM PDT 24 13733573 ps
T1012 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3937974485 May 30 01:09:00 PM PDT 24 May 30 01:09:02 PM PDT 24 26072417 ps
T149 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4067135451 May 30 01:08:58 PM PDT 24 May 30 01:09:08 PM PDT 24 1603612948 ps
T103 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1129265420 May 30 01:09:00 PM PDT 24 May 30 01:09:03 PM PDT 24 49521909 ps
T1013 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.286042319 May 30 01:09:14 PM PDT 24 May 30 01:09:16 PM PDT 24 16134092 ps
T130 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2398479442 May 30 01:08:58 PM PDT 24 May 30 01:09:07 PM PDT 24 373058944 ps
T81 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2709069432 May 30 01:08:58 PM PDT 24 May 30 01:09:01 PM PDT 24 118486970 ps
T151 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.584152486 May 30 01:09:01 PM PDT 24 May 30 01:09:04 PM PDT 24 99567067 ps
T1014 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.532320983 May 30 01:09:05 PM PDT 24 May 30 01:09:07 PM PDT 24 34144885 ps
T1015 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2563121788 May 30 01:09:06 PM PDT 24 May 30 01:09:10 PM PDT 24 46824117 ps
T150 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3256228658 May 30 01:09:02 PM PDT 24 May 30 01:09:05 PM PDT 24 227814489 ps
T1016 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.475200946 May 30 01:09:12 PM PDT 24 May 30 01:09:15 PM PDT 24 43417500 ps
T1017 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.975196455 May 30 01:09:12 PM PDT 24 May 30 01:09:16 PM PDT 24 58787243 ps
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