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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.11 98.35 94.20 98.61 89.36 97.23 95.82 99.20


Total test records in report: 1101
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T131 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2757764613 May 30 01:08:59 PM PDT 24 May 30 01:09:02 PM PDT 24 55005179 ps
T1018 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1824953174 May 30 01:09:20 PM PDT 24 May 30 01:09:22 PM PDT 24 15523442 ps
T1019 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1518782173 May 30 01:09:14 PM PDT 24 May 30 01:09:15 PM PDT 24 18075007 ps
T174 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1372408272 May 30 01:09:17 PM PDT 24 May 30 01:09:42 PM PDT 24 911255138 ps
T82 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4020254524 May 30 01:09:01 PM PDT 24 May 30 01:09:03 PM PDT 24 115440368 ps
T1020 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2231392714 May 30 01:09:00 PM PDT 24 May 30 01:09:02 PM PDT 24 26265498 ps
T1021 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3614800302 May 30 01:09:16 PM PDT 24 May 30 01:09:18 PM PDT 24 11981773 ps
T104 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2706485525 May 30 01:09:01 PM PDT 24 May 30 01:09:05 PM PDT 24 107343233 ps
T1022 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.723516170 May 30 01:09:05 PM PDT 24 May 30 01:09:08 PM PDT 24 29085648 ps
T1023 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1386795370 May 30 01:09:02 PM PDT 24 May 30 01:09:06 PM PDT 24 47039944 ps
T1024 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4043876702 May 30 01:08:57 PM PDT 24 May 30 01:09:33 PM PDT 24 2436973249 ps
T175 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2172403444 May 30 01:08:59 PM PDT 24 May 30 01:09:18 PM PDT 24 564756737 ps
T1025 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2341678272 May 30 01:09:02 PM PDT 24 May 30 01:09:06 PM PDT 24 168430909 ps
T1026 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4043491867 May 30 01:09:07 PM PDT 24 May 30 01:09:10 PM PDT 24 151129849 ps
T1027 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1854566060 May 30 01:09:19 PM PDT 24 May 30 01:09:22 PM PDT 24 121617386 ps
T1028 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2294618289 May 30 01:08:57 PM PDT 24 May 30 01:09:00 PM PDT 24 19024328 ps
T1029 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1347499423 May 30 01:09:05 PM PDT 24 May 30 01:09:08 PM PDT 24 91556794 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2766025622 May 30 01:09:02 PM PDT 24 May 30 01:09:05 PM PDT 24 49603351 ps
T180 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3759728871 May 30 01:09:10 PM PDT 24 May 30 01:09:19 PM PDT 24 665058689 ps
T1031 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1665620139 May 30 01:09:00 PM PDT 24 May 30 01:09:02 PM PDT 24 11647816 ps
T1032 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4206804103 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 16882807 ps
T102 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2639775734 May 30 01:08:58 PM PDT 24 May 30 01:09:03 PM PDT 24 57175555 ps
T108 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2020015337 May 30 01:09:10 PM PDT 24 May 30 01:09:14 PM PDT 24 459381760 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2906504329 May 30 01:09:02 PM PDT 24 May 30 01:09:16 PM PDT 24 1236701897 ps
T1034 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3371897823 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 17628041 ps
T1035 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.293593578 May 30 01:09:18 PM PDT 24 May 30 01:09:20 PM PDT 24 64970053 ps
T1036 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1043106443 May 30 01:09:19 PM PDT 24 May 30 01:09:21 PM PDT 24 49975961 ps
T1037 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1674093656 May 30 01:09:00 PM PDT 24 May 30 01:09:03 PM PDT 24 85236339 ps
T1038 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.227632648 May 30 01:09:14 PM PDT 24 May 30 01:09:19 PM PDT 24 132269328 ps
T114 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3658515555 May 30 01:09:19 PM PDT 24 May 30 01:09:24 PM PDT 24 111871256 ps
T1039 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4268587813 May 30 01:09:07 PM PDT 24 May 30 01:09:12 PM PDT 24 134655149 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3212649569 May 30 01:09:06 PM PDT 24 May 30 01:09:07 PM PDT 24 14900865 ps
T1041 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.18610187 May 30 01:09:19 PM PDT 24 May 30 01:09:21 PM PDT 24 38065889 ps
T1042 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3067878856 May 30 01:09:15 PM PDT 24 May 30 01:09:17 PM PDT 24 18642607 ps
T1043 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.401702584 May 30 01:08:58 PM PDT 24 May 30 01:09:02 PM PDT 24 26353104 ps
T1044 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3673547689 May 30 01:09:13 PM PDT 24 May 30 01:09:15 PM PDT 24 14976754 ps
T1045 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3637282625 May 30 01:09:20 PM PDT 24 May 30 01:09:22 PM PDT 24 118619155 ps
T1046 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2086179296 May 30 01:09:15 PM PDT 24 May 30 01:09:17 PM PDT 24 23498254 ps
T1047 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.361970336 May 30 01:08:58 PM PDT 24 May 30 01:09:02 PM PDT 24 151594738 ps
T176 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2671340603 May 30 01:09:06 PM PDT 24 May 30 01:09:23 PM PDT 24 2932982289 ps
T83 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1217391831 May 30 01:09:01 PM PDT 24 May 30 01:09:04 PM PDT 24 114395488 ps
T1048 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1069791174 May 30 01:09:08 PM PDT 24 May 30 01:09:12 PM PDT 24 106731345 ps
T1049 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.294430121 May 30 01:09:14 PM PDT 24 May 30 01:09:16 PM PDT 24 12697920 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.255773911 May 30 01:09:11 PM PDT 24 May 30 01:09:15 PM PDT 24 141829566 ps
T1051 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2333439787 May 30 01:09:13 PM PDT 24 May 30 01:09:16 PM PDT 24 28022150 ps
T1052 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3640786963 May 30 01:09:08 PM PDT 24 May 30 01:09:11 PM PDT 24 52433302 ps
T1053 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2013148086 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 41440392 ps
T1054 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2750524032 May 30 01:09:20 PM PDT 24 May 30 01:09:22 PM PDT 24 28464181 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2781090195 May 30 01:09:02 PM PDT 24 May 30 01:09:05 PM PDT 24 359589322 ps
T1056 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1467238125 May 30 01:08:58 PM PDT 24 May 30 01:09:18 PM PDT 24 1002144547 ps
T111 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1726575781 May 30 01:09:08 PM PDT 24 May 30 01:09:13 PM PDT 24 52803572 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.765604458 May 30 01:09:01 PM PDT 24 May 30 01:09:03 PM PDT 24 12191359 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1036325239 May 30 01:09:07 PM PDT 24 May 30 01:09:11 PM PDT 24 196017818 ps
T1059 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4257912851 May 30 01:09:11 PM PDT 24 May 30 01:09:13 PM PDT 24 37686178 ps
T1060 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1051439112 May 30 01:09:00 PM PDT 24 May 30 01:09:04 PM PDT 24 169557892 ps
T1061 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3718576819 May 30 01:09:09 PM PDT 24 May 30 01:09:12 PM PDT 24 97200144 ps
T1062 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4055713430 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 44211040 ps
T1063 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3090496284 May 30 01:09:13 PM PDT 24 May 30 01:09:28 PM PDT 24 2016465137 ps
T84 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3750538237 May 30 01:09:05 PM PDT 24 May 30 01:09:07 PM PDT 24 41809934 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3800953675 May 30 01:08:59 PM PDT 24 May 30 01:09:09 PM PDT 24 112531093 ps
T1065 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2853507710 May 30 01:09:08 PM PDT 24 May 30 01:09:16 PM PDT 24 399633987 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2642163569 May 30 01:09:03 PM PDT 24 May 30 01:09:05 PM PDT 24 87256292 ps
T1067 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3440999570 May 30 01:09:09 PM PDT 24 May 30 01:09:11 PM PDT 24 41773250 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3213488998 May 30 01:09:10 PM PDT 24 May 30 01:09:12 PM PDT 24 11707827 ps
T1069 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1327667153 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 44850679 ps
T177 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.159845315 May 30 01:09:15 PM PDT 24 May 30 01:09:36 PM PDT 24 830981213 ps
T1070 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2325372835 May 30 01:09:05 PM PDT 24 May 30 01:09:07 PM PDT 24 81721175 ps
T1071 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1812758280 May 30 01:09:08 PM PDT 24 May 30 01:09:12 PM PDT 24 34643700 ps
T1072 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.883870587 May 30 01:09:14 PM PDT 24 May 30 01:09:29 PM PDT 24 561498035 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2936896956 May 30 01:08:59 PM PDT 24 May 30 01:09:02 PM PDT 24 107819926 ps
T1074 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2431772445 May 30 01:09:09 PM PDT 24 May 30 01:09:11 PM PDT 24 28019634 ps
T1075 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3227523530 May 30 01:09:02 PM PDT 24 May 30 01:09:05 PM PDT 24 290803640 ps
T1076 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4169186188 May 30 01:09:10 PM PDT 24 May 30 01:09:18 PM PDT 24 218852282 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2602452568 May 30 01:09:16 PM PDT 24 May 30 01:09:19 PM PDT 24 19549916 ps
T1078 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.557397395 May 30 01:09:13 PM PDT 24 May 30 01:09:14 PM PDT 24 12118629 ps
T178 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.525793863 May 30 01:09:17 PM PDT 24 May 30 01:09:38 PM PDT 24 303910972 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1011168975 May 30 01:08:56 PM PDT 24 May 30 01:09:00 PM PDT 24 200612501 ps
T1080 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2011688734 May 30 01:09:15 PM PDT 24 May 30 01:09:17 PM PDT 24 17378126 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2988943489 May 30 01:08:55 PM PDT 24 May 30 01:09:01 PM PDT 24 446114532 ps
T179 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2097639501 May 30 01:09:14 PM PDT 24 May 30 01:09:32 PM PDT 24 297297348 ps
T1081 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.587058314 May 30 01:09:10 PM PDT 24 May 30 01:09:14 PM PDT 24 96871004 ps
T1082 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3925621269 May 30 01:09:01 PM PDT 24 May 30 01:09:04 PM PDT 24 25308563 ps
T1083 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3219229025 May 30 01:09:13 PM PDT 24 May 30 01:09:15 PM PDT 24 117634334 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2287041185 May 30 01:08:58 PM PDT 24 May 30 01:09:01 PM PDT 24 148590738 ps
T1085 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2398409590 May 30 01:09:12 PM PDT 24 May 30 01:09:16 PM PDT 24 758277318 ps
T1086 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3540172994 May 30 01:08:58 PM PDT 24 May 30 01:09:34 PM PDT 24 1093775526 ps
T1087 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3350982276 May 30 01:08:56 PM PDT 24 May 30 01:09:13 PM PDT 24 554820876 ps
T1088 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.678554505 May 30 01:09:10 PM PDT 24 May 30 01:09:12 PM PDT 24 68479723 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3770705678 May 30 01:09:05 PM PDT 24 May 30 01:09:23 PM PDT 24 326082886 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4236738625 May 30 01:09:06 PM PDT 24 May 30 01:09:09 PM PDT 24 101153043 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2899342172 May 30 01:09:00 PM PDT 24 May 30 01:09:02 PM PDT 24 30496721 ps
T1092 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1025608247 May 30 01:09:14 PM PDT 24 May 30 01:09:16 PM PDT 24 23315226 ps
T1093 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3453477125 May 30 01:09:06 PM PDT 24 May 30 01:09:07 PM PDT 24 102227328 ps
T1094 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3105553243 May 30 01:09:07 PM PDT 24 May 30 01:09:11 PM PDT 24 168779254 ps
T1095 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3803908163 May 30 01:09:08 PM PDT 24 May 30 01:09:11 PM PDT 24 98642174 ps
T1096 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2148074999 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 18164096 ps
T1097 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1477076159 May 30 01:09:13 PM PDT 24 May 30 01:09:14 PM PDT 24 23729544 ps
T1098 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1673927728 May 30 01:08:57 PM PDT 24 May 30 01:09:00 PM PDT 24 25527522 ps
T1099 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.891710193 May 30 01:09:13 PM PDT 24 May 30 01:09:15 PM PDT 24 34186227 ps
T1100 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.819408481 May 30 01:09:17 PM PDT 24 May 30 01:09:19 PM PDT 24 36157589 ps
T1101 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2002332777 May 30 01:09:01 PM PDT 24 May 30 01:09:04 PM PDT 24 77823274 ps

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1033305577
Short name T7
Test name
Test status
Simulation time 8813905558 ps
CPU time 140.05 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 273380 kb
Host smart-f93319c9-8bbd-4d20-a08f-07b571ada1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033305577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1033305577
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2194041188
Short name T12
Test name
Test status
Simulation time 6056058329 ps
CPU time 86.91 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:19:33 PM PDT 24
Peak memory 250676 kb
Host smart-1b4fed05-c928-45c8-aa0a-786d17ddf165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194041188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2194041188
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1094064064
Short name T34
Test name
Test status
Simulation time 160476044755 ps
CPU time 294.65 seconds
Started May 30 01:16:26 PM PDT 24
Finished May 30 01:21:22 PM PDT 24
Peak memory 266272 kb
Host smart-2929e3a5-80b1-4fd5-950f-1636e771dc76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094064064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1094064064
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.47493828
Short name T98
Test name
Test status
Simulation time 5691917696 ps
CPU time 15.38 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 215604 kb
Host smart-309f4dce-f6e1-476f-aded-469a0d22d6f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47493828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_t
l_intg_err.47493828
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.571728682
Short name T18
Test name
Test status
Simulation time 1078169177889 ps
CPU time 937.9 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:34:33 PM PDT 24
Peak memory 273496 kb
Host smart-ab3240b8-a4d2-460e-801d-9ace14a04569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571728682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.571728682
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3574860830
Short name T66
Test name
Test status
Simulation time 45642422 ps
CPU time 0.74 seconds
Started May 30 01:16:07 PM PDT 24
Finished May 30 01:16:09 PM PDT 24
Peak memory 215664 kb
Host smart-97b2a808-3d40-46e9-9898-e0b1ed6bf6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574860830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3574860830
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.836305252
Short name T158
Test name
Test status
Simulation time 564097743133 ps
CPU time 730.99 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:29:58 PM PDT 24
Peak memory 283032 kb
Host smart-ab670db7-d3b2-4390-a668-9833266e8aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836305252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.836305252
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.532381477
Short name T27
Test name
Test status
Simulation time 49692809895 ps
CPU time 358.89 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:24:11 PM PDT 24
Peak memory 253384 kb
Host smart-c9aa52a3-b95a-4df4-849a-4fb679685477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532381477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.532381477
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2891281623
Short name T152
Test name
Test status
Simulation time 5547680507 ps
CPU time 90.69 seconds
Started May 30 01:16:39 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 264568 kb
Host smart-9a9d0c69-2bc2-414d-bb78-89a573a860d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891281623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2891281623
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2775200211
Short name T100
Test name
Test status
Simulation time 133367051 ps
CPU time 4.23 seconds
Started May 30 01:09:09 PM PDT 24
Finished May 30 01:09:14 PM PDT 24
Peak memory 215556 kb
Host smart-b9f51c1b-b439-4cfa-a4fa-2b43287d07cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775200211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
775200211
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3699584690
Short name T63
Test name
Test status
Simulation time 116941070 ps
CPU time 1.3 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:26 PM PDT 24
Peak memory 235516 kb
Host smart-3360dc6b-ad54-44f4-9aa0-99a236800401
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699584690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3699584690
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.983871967
Short name T167
Test name
Test status
Simulation time 85892525704 ps
CPU time 433.81 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:26:33 PM PDT 24
Peak memory 264696 kb
Host smart-e8e25667-8cda-46fe-a70f-0224d4c48430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983871967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.983871967
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3214330807
Short name T143
Test name
Test status
Simulation time 892436169 ps
CPU time 16.89 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:36 PM PDT 24
Peak memory 240540 kb
Host smart-b3fd8b21-a701-4528-b72a-42ac504d7654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214330807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3214330807
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1076295749
Short name T191
Test name
Test status
Simulation time 52460090182 ps
CPU time 146.66 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:20:36 PM PDT 24
Peak memory 248880 kb
Host smart-9ef8e5e7-c56e-4b6e-aa2d-db767bde729d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076295749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1076295749
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1145627819
Short name T119
Test name
Test status
Simulation time 74126466 ps
CPU time 1.97 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 215572 kb
Host smart-a4a2138c-8cab-4ba7-9ab6-9690c65f1ee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145627819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
145627819
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.324047936
Short name T45
Test name
Test status
Simulation time 17204979510 ps
CPU time 124.34 seconds
Started May 30 01:16:54 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 262256 kb
Host smart-c0035275-6c67-4b5e-8308-ded6c365dd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324047936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.324047936
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.900221505
Short name T164
Test name
Test status
Simulation time 36354076281 ps
CPU time 335.42 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:24:34 PM PDT 24
Peak memory 256124 kb
Host smart-d48ab4db-c69a-4328-b649-826f6a3d5384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900221505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.900221505
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1604800089
Short name T23
Test name
Test status
Simulation time 28238060 ps
CPU time 0.98 seconds
Started May 30 01:16:54 PM PDT 24
Finished May 30 01:16:57 PM PDT 24
Peak memory 217400 kb
Host smart-aacea149-a0fa-4590-81fe-a9b1e70a58ac
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604800089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1604800089
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3711083379
Short name T15
Test name
Test status
Simulation time 52483029460 ps
CPU time 94.15 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:20:12 PM PDT 24
Peak memory 264748 kb
Host smart-865b0e24-5d6b-4e7d-81e8-2277f02dab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711083379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3711083379
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3073423369
Short name T253
Test name
Test status
Simulation time 178140695259 ps
CPU time 387.8 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:25:08 PM PDT 24
Peak memory 265312 kb
Host smart-6c02fbaa-808e-41ca-adb8-85e8a9b89071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073423369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3073423369
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2801488490
Short name T31
Test name
Test status
Simulation time 27435337334 ps
CPU time 203.81 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:20:48 PM PDT 24
Peak memory 238600 kb
Host smart-3c3ba8e1-a071-4da9-ab13-509f0cf16a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801488490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2801488490
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.70142767
Short name T288
Test name
Test status
Simulation time 33063974436 ps
CPU time 92.51 seconds
Started May 30 01:17:19 PM PDT 24
Finished May 30 01:18:53 PM PDT 24
Peak memory 248864 kb
Host smart-72f34494-bedc-46bf-9fdc-e94ac31a1f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70142767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress
_all.70142767
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2824226185
Short name T205
Test name
Test status
Simulation time 15073294809 ps
CPU time 235.15 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:23:03 PM PDT 24
Peak memory 271800 kb
Host smart-5b58646f-a968-496d-bc0e-e162c4d1e594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824226185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2824226185
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2097206612
Short name T845
Test name
Test status
Simulation time 7245172843 ps
CPU time 110.07 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:19:14 PM PDT 24
Peak memory 256232 kb
Host smart-55b62087-7bce-427d-801b-cfe18bccc9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097206612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2097206612
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3099706540
Short name T61
Test name
Test status
Simulation time 49349847 ps
CPU time 0.77 seconds
Started May 30 01:17:24 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 205304 kb
Host smart-2db41083-2411-4684-8de7-d2232fb5e3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099706540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3099706540
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2225586722
Short name T41
Test name
Test status
Simulation time 214527024 ps
CPU time 8.87 seconds
Started May 30 01:18:40 PM PDT 24
Finished May 30 01:18:50 PM PDT 24
Peak memory 224148 kb
Host smart-e6d0be8e-4653-4c64-9bc5-75ab99a8362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225586722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2225586722
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.352100025
Short name T220
Test name
Test status
Simulation time 273351650938 ps
CPU time 592.43 seconds
Started May 30 01:16:54 PM PDT 24
Finished May 30 01:26:48 PM PDT 24
Peak memory 250480 kb
Host smart-fab1eb87-6c41-4023-982f-c3c2ef29d854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352100025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.352100025
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.973921569
Short name T42
Test name
Test status
Simulation time 6841201665 ps
CPU time 93.89 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:19:02 PM PDT 24
Peak memory 248852 kb
Host smart-5dc318e5-91f1-47b5-9e36-fe9e2ee4c0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973921569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.973921569
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3208499746
Short name T293
Test name
Test status
Simulation time 8035228968 ps
CPU time 91.75 seconds
Started May 30 01:17:21 PM PDT 24
Finished May 30 01:18:54 PM PDT 24
Peak memory 263896 kb
Host smart-9fd68109-c36d-44d5-8749-64c2998dde69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208499746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3208499746
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2988943489
Short name T112
Test name
Test status
Simulation time 446114532 ps
CPU time 4.71 seconds
Started May 30 01:08:55 PM PDT 24
Finished May 30 01:09:01 PM PDT 24
Peak memory 215596 kb
Host smart-1df93430-b4a6-4d19-8f1d-43ca5f35ecb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988943489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
988943489
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2172403444
Short name T175
Test name
Test status
Simulation time 564756737 ps
CPU time 17.71 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:18 PM PDT 24
Peak memory 215880 kb
Host smart-ae85df9f-be7f-477e-9671-97160e09e435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172403444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2172403444
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1641806127
Short name T200
Test name
Test status
Simulation time 29808661330 ps
CPU time 208.58 seconds
Started May 30 01:18:04 PM PDT 24
Finished May 30 01:21:35 PM PDT 24
Peak memory 248804 kb
Host smart-e35ace1d-8380-493a-8f7d-c9e1f4c6140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641806127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1641806127
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3781164921
Short name T234
Test name
Test status
Simulation time 8482866096 ps
CPU time 68.34 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:17:33 PM PDT 24
Peak memory 254136 kb
Host smart-69432345-96f8-4742-b18a-b9b44485f12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781164921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3781164921
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2768449293
Short name T36
Test name
Test status
Simulation time 24609882945 ps
CPU time 247.03 seconds
Started May 30 01:17:29 PM PDT 24
Finished May 30 01:21:37 PM PDT 24
Peak memory 254648 kb
Host smart-3633c2f4-7650-462e-aa4f-c3412312bc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768449293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2768449293
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1076803327
Short name T44
Test name
Test status
Simulation time 2461013018 ps
CPU time 46.63 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:18:34 PM PDT 24
Peak memory 248900 kb
Host smart-5b02b1bc-e017-4ed4-806e-9b40691d79d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076803327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1076803327
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3209717516
Short name T213
Test name
Test status
Simulation time 59735510777 ps
CPU time 289.47 seconds
Started May 30 01:18:28 PM PDT 24
Finished May 30 01:23:19 PM PDT 24
Peak memory 251440 kb
Host smart-63f20526-b50d-48d0-8ef9-6475348575f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209717516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3209717516
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3502117037
Short name T58
Test name
Test status
Simulation time 41119882 ps
CPU time 0.96 seconds
Started May 30 01:17:25 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 206184 kb
Host smart-c36f0df1-c2b8-4d22-b5b5-cb2ee672827a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502117037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3502117037
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4128092687
Short name T232
Test name
Test status
Simulation time 89686202028 ps
CPU time 311.68 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:21:53 PM PDT 24
Peak memory 240648 kb
Host smart-044a8a59-1bd7-4fe3-a4ff-24ec8bcb7e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128092687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4128092687
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.707955892
Short name T202
Test name
Test status
Simulation time 7428745489 ps
CPU time 116.92 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:20:53 PM PDT 24
Peak memory 256564 kb
Host smart-a19ba02f-3c7d-4f03-99d5-42b33e7afe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707955892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.707955892
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.357800789
Short name T243
Test name
Test status
Simulation time 234006402043 ps
CPU time 569.24 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:28:38 PM PDT 24
Peak memory 255008 kb
Host smart-ef728ef2-2836-43a1-8683-7222ca661b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357800789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.357800789
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.169751883
Short name T90
Test name
Test status
Simulation time 10035202192 ps
CPU time 14.37 seconds
Started May 30 01:17:21 PM PDT 24
Finished May 30 01:17:37 PM PDT 24
Peak memory 234216 kb
Host smart-f7abeee3-f3b4-478e-9eb2-25ad3e7615c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169751883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.169751883
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1653650083
Short name T26
Test name
Test status
Simulation time 477778595 ps
CPU time 3.7 seconds
Started May 30 01:18:03 PM PDT 24
Finished May 30 01:18:08 PM PDT 24
Peak memory 234812 kb
Host smart-da8786ac-bff2-4b47-bb84-2712cab879c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653650083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1653650083
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.401702584
Short name T1043
Test name
Test status
Simulation time 26353104 ps
CPU time 1.64 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 215556 kb
Host smart-bff30f6c-e683-41a4-b910-843d97d5c31d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401702584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.401702584
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2097639501
Short name T179
Test name
Test status
Simulation time 297297348 ps
CPU time 16.49 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:32 PM PDT 24
Peak memory 215492 kb
Host smart-dbb86246-04b0-40c6-882b-c2110032a86b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097639501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2097639501
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1214663967
Short name T587
Test name
Test status
Simulation time 428752786 ps
CPU time 6.59 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:11 PM PDT 24
Peak memory 248840 kb
Host smart-89c34784-e778-42ac-94b2-64da79851298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214663967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1214663967
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1820444887
Short name T290
Test name
Test status
Simulation time 174889328195 ps
CPU time 447.54 seconds
Started May 30 01:17:01 PM PDT 24
Finished May 30 01:24:30 PM PDT 24
Peak memory 266480 kb
Host smart-9a2453be-4db1-45c9-b470-78a5ce8ddd04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820444887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1820444887
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2611404917
Short name T267
Test name
Test status
Simulation time 125901097 ps
CPU time 2.87 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:24 PM PDT 24
Peak memory 216444 kb
Host smart-e8c05a61-37c2-4a37-b593-bcfd7c390573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611404917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2611404917
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2401730784
Short name T207
Test name
Test status
Simulation time 11064550204 ps
CPU time 22.39 seconds
Started May 30 01:17:40 PM PDT 24
Finished May 30 01:18:04 PM PDT 24
Peak memory 253372 kb
Host smart-ddc8f023-6199-401f-86b8-2b4348a91c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401730784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2401730784
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.17348034
Short name T296
Test name
Test status
Simulation time 4040789033 ps
CPU time 83.15 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:19:08 PM PDT 24
Peak memory 265220 kb
Host smart-fce1eb2f-4514-4f52-8a7e-828c37e5bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17348034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.17348034
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3473464533
Short name T182
Test name
Test status
Simulation time 25366884458 ps
CPU time 193.78 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:21:02 PM PDT 24
Peak memory 254092 kb
Host smart-a17bbc7c-e351-47c6-9f1a-fdf494cd25c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473464533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3473464533
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3639482899
Short name T203
Test name
Test status
Simulation time 56598955741 ps
CPU time 82.09 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:19:23 PM PDT 24
Peak memory 253536 kb
Host smart-fd3d330c-9296-4111-a139-c8390e292b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639482899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3639482899
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1944990458
Short name T305
Test name
Test status
Simulation time 31765221837 ps
CPU time 111.02 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:19:49 PM PDT 24
Peak memory 272868 kb
Host smart-a8a9798b-b150-40fb-8d59-5270cc03dc58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944990458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1944990458
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2136084221
Short name T315
Test name
Test status
Simulation time 599944693 ps
CPU time 9.25 seconds
Started May 30 01:18:24 PM PDT 24
Finished May 30 01:18:35 PM PDT 24
Peak memory 248652 kb
Host smart-f363b599-29fe-4062-b02e-9ff929b295b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136084221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2136084221
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4000281213
Short name T49
Test name
Test status
Simulation time 15866832183 ps
CPU time 46.6 seconds
Started May 30 01:18:40 PM PDT 24
Finished May 30 01:19:29 PM PDT 24
Peak memory 248960 kb
Host smart-b230ebf0-dbcb-4157-ae99-4fa519989d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000281213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4000281213
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.312087398
Short name T287
Test name
Test status
Simulation time 24503310572 ps
CPU time 328.39 seconds
Started May 30 01:18:36 PM PDT 24
Finished May 30 01:24:05 PM PDT 24
Peak memory 270640 kb
Host smart-5198938a-1ebf-4405-b924-853951ee6c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312087398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.312087398
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2071758261
Short name T199
Test name
Test status
Simulation time 79936259076 ps
CPU time 275.74 seconds
Started May 30 01:19:04 PM PDT 24
Finished May 30 01:23:41 PM PDT 24
Peak memory 248732 kb
Host smart-7b71c159-818a-4157-b568-eaf25f85a04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071758261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2071758261
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.806033685
Short name T271
Test name
Test status
Simulation time 242051739699 ps
CPU time 503.08 seconds
Started May 30 01:19:14 PM PDT 24
Finished May 30 01:27:38 PM PDT 24
Peak memory 256408 kb
Host smart-187001e0-0622-47ad-8b9c-4f8fdebe831d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806033685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.806033685
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1217391831
Short name T83
Test name
Test status
Simulation time 114395488 ps
CPU time 1.16 seconds
Started May 30 01:09:01 PM PDT 24
Finished May 30 01:09:04 PM PDT 24
Peak memory 207360 kb
Host smart-e2bddcb1-189d-4663-bf1f-7a3818d2defb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217391831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1217391831
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3720500719
Short name T121
Test name
Test status
Simulation time 640324791 ps
CPU time 8.76 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:09 PM PDT 24
Peak memory 215524 kb
Host smart-9e07f224-8533-4aff-8db1-16cc22a75058
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720500719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3720500719
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3540172994
Short name T1086
Test name
Test status
Simulation time 1093775526 ps
CPU time 34.54 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:34 PM PDT 24
Peak memory 207356 kb
Host smart-1d3fc092-0432-4a75-bb87-911a1a8e3b36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540172994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3540172994
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1011168975
Short name T1079
Test name
Test status
Simulation time 200612501 ps
CPU time 3.01 seconds
Started May 30 01:08:56 PM PDT 24
Finished May 30 01:09:00 PM PDT 24
Peak memory 217876 kb
Host smart-1db37658-38c7-4bb3-896e-77bf68482526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011168975 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1011168975
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.370174107
Short name T148
Test name
Test status
Simulation time 164523226 ps
CPU time 1.37 seconds
Started May 30 01:08:56 PM PDT 24
Finished May 30 01:08:59 PM PDT 24
Peak memory 207288 kb
Host smart-34f8c2e5-6f08-4696-8913-e5b53e1f4954
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370174107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.370174107
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2899342172
Short name T1091
Test name
Test status
Simulation time 30496721 ps
CPU time 0.75 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 203744 kb
Host smart-cf5338e3-cd43-4dac-8162-c1797f6789d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899342172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
899342172
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2287041185
Short name T1084
Test name
Test status
Simulation time 148590738 ps
CPU time 1.37 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:01 PM PDT 24
Peak memory 215472 kb
Host smart-5aa729fc-327b-45dc-a739-e46f17f1f59d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287041185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2287041185
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3994427456
Short name T992
Test name
Test status
Simulation time 12748575 ps
CPU time 0.64 seconds
Started May 30 01:08:57 PM PDT 24
Finished May 30 01:08:59 PM PDT 24
Peak memory 203552 kb
Host smart-833fc09e-2324-4e2a-aa06-4ae0120dd356
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994427456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3994427456
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3824742172
Short name T1007
Test name
Test status
Simulation time 118778412 ps
CPU time 2.95 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 215504 kb
Host smart-d0cb74b4-5f37-48bf-bcad-910cffbd7184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824742172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3824742172
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4067135451
Short name T149
Test name
Test status
Simulation time 1603612948 ps
CPU time 8.45 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:08 PM PDT 24
Peak memory 216052 kb
Host smart-8fbc698e-6bd1-4ec2-ab4c-99b83120b05c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067135451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4067135451
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.722860573
Short name T987
Test name
Test status
Simulation time 217534690 ps
CPU time 14.78 seconds
Started May 30 01:08:56 PM PDT 24
Finished May 30 01:09:12 PM PDT 24
Peak memory 207212 kb
Host smart-9ffc5005-b8e7-4a39-b988-e7ae60566295
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722860573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.722860573
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1150890722
Short name T993
Test name
Test status
Simulation time 4840471973 ps
CPU time 26.28 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:27 PM PDT 24
Peak memory 207396 kb
Host smart-08913d31-435d-496f-b007-b8869748c263
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150890722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1150890722
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2709069432
Short name T81
Test name
Test status
Simulation time 118486970 ps
CPU time 1.14 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:01 PM PDT 24
Peak memory 207284 kb
Host smart-bbd89fb3-61b3-4c24-86a0-d1e59770a3b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709069432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2709069432
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3800953675
Short name T1064
Test name
Test status
Simulation time 112531093 ps
CPU time 3.9 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:09 PM PDT 24
Peak memory 217952 kb
Host smart-29173901-17f2-4894-86e9-236144a089ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800953675 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3800953675
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1665620139
Short name T1031
Test name
Test status
Simulation time 11647816 ps
CPU time 0.73 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 204012 kb
Host smart-3c4f5970-288f-4684-bfee-b562b0eeb2d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665620139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
665620139
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3178559339
Short name T126
Test name
Test status
Simulation time 32728975 ps
CPU time 1.37 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 215556 kb
Host smart-cc52f1a1-4240-455c-a31b-5dc31bce9db0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178559339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3178559339
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2231392714
Short name T1020
Test name
Test status
Simulation time 26265498 ps
CPU time 0.65 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 203636 kb
Host smart-4a17e504-9cc6-4910-b4cb-057b0b710668
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231392714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2231392714
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3256228658
Short name T150
Test name
Test status
Simulation time 227814489 ps
CPU time 1.75 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:05 PM PDT 24
Peak memory 207228 kb
Host smart-59b4f6c4-c8c8-479e-978a-015756d8d28f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256228658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3256228658
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2639775734
Short name T102
Test name
Test status
Simulation time 57175555 ps
CPU time 3.35 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 216740 kb
Host smart-93143b8d-a6de-4994-956c-482446051e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639775734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
639775734
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.584152486
Short name T151
Test name
Test status
Simulation time 99567067 ps
CPU time 1.71 seconds
Started May 30 01:09:01 PM PDT 24
Finished May 30 01:09:04 PM PDT 24
Peak memory 216704 kb
Host smart-48a4a2eb-fa79-4378-8781-724d75ea1c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584152486 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.584152486
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3925621269
Short name T1082
Test name
Test status
Simulation time 25308563 ps
CPU time 1.55 seconds
Started May 30 01:09:01 PM PDT 24
Finished May 30 01:09:04 PM PDT 24
Peak memory 207256 kb
Host smart-a59755d2-8adf-4961-ae3f-dc40857f56b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925621269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3925621269
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2325372835
Short name T1070
Test name
Test status
Simulation time 81721175 ps
CPU time 0.73 seconds
Started May 30 01:09:05 PM PDT 24
Finished May 30 01:09:07 PM PDT 24
Peak memory 203700 kb
Host smart-75e1b3cf-edaa-4ff6-affe-cc394b479efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325372835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2325372835
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.30040620
Short name T991
Test name
Test status
Simulation time 51913960 ps
CPU time 1.62 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:09 PM PDT 24
Peak memory 216728 kb
Host smart-81ab8ace-e0ff-4df7-aa05-d201174d94b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30040620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sp
i_device_same_csr_outstanding.30040620
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1573878489
Short name T101
Test name
Test status
Simulation time 90700088 ps
CPU time 1.63 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:08 PM PDT 24
Peak memory 215624 kb
Host smart-0c6b95b5-5593-434d-a813-b70496210146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573878489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1573878489
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1457074294
Short name T117
Test name
Test status
Simulation time 1217375955 ps
CPU time 7.98 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 216008 kb
Host smart-f11ebcd6-6fb1-48cd-88eb-fd6975b45b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457074294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1457074294
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.255773911
Short name T1050
Test name
Test status
Simulation time 141829566 ps
CPU time 2.87 seconds
Started May 30 01:09:11 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 217392 kb
Host smart-072791f2-ed54-4100-8c70-26ace0c0a795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255773911 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.255773911
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.723516170
Short name T1022
Test name
Test status
Simulation time 29085648 ps
CPU time 1.9 seconds
Started May 30 01:09:05 PM PDT 24
Finished May 30 01:09:08 PM PDT 24
Peak memory 215516 kb
Host smart-c185c85a-e8dc-4df8-b482-3c3b2fec798a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723516170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.723516170
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2202615165
Short name T989
Test name
Test status
Simulation time 13215156 ps
CPU time 0.73 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:08 PM PDT 24
Peak memory 204000 kb
Host smart-bcfaffb2-3656-4b97-aec6-48be67e92a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202615165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2202615165
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2936896956
Short name T1073
Test name
Test status
Simulation time 107819926 ps
CPU time 1.83 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 215384 kb
Host smart-dd3d280d-df08-43ca-96c4-0417810e9433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936896956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2936896956
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2002332777
Short name T1101
Test name
Test status
Simulation time 77823274 ps
CPU time 1.61 seconds
Started May 30 01:09:01 PM PDT 24
Finished May 30 01:09:04 PM PDT 24
Peak memory 216624 kb
Host smart-27bcb28b-b356-4b72-bd1b-39b09ad35c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002332777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2002332777
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4169186188
Short name T1076
Test name
Test status
Simulation time 218852282 ps
CPU time 7.09 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:18 PM PDT 24
Peak memory 215556 kb
Host smart-f68d7236-0ab5-4aaf-ab7d-db653a942609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169186188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4169186188
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3803908163
Short name T1095
Test name
Test status
Simulation time 98642174 ps
CPU time 2.69 seconds
Started May 30 01:09:08 PM PDT 24
Finished May 30 01:09:11 PM PDT 24
Peak memory 216780 kb
Host smart-f8c9253c-c8ba-4cc9-9cda-e9982b6f16eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803908163 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3803908163
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3105553243
Short name T1094
Test name
Test status
Simulation time 168779254 ps
CPU time 2.53 seconds
Started May 30 01:09:07 PM PDT 24
Finished May 30 01:09:11 PM PDT 24
Peak memory 215548 kb
Host smart-cdebd774-316d-4a90-9fa8-6690e1493078
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105553243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3105553243
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3453477125
Short name T1093
Test name
Test status
Simulation time 102227328 ps
CPU time 0.71 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:07 PM PDT 24
Peak memory 203988 kb
Host smart-04f6825b-c367-45eb-bd5a-67cea5f6bc07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453477125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3453477125
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2563121788
Short name T1015
Test name
Test status
Simulation time 46824117 ps
CPU time 2.92 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:10 PM PDT 24
Peak memory 215548 kb
Host smart-c5ce4b82-5af1-47d4-88c8-020bab4402ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563121788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2563121788
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.123566139
Short name T93
Test name
Test status
Simulation time 470932180 ps
CPU time 1.97 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 215724 kb
Host smart-2842aa60-1d7e-4817-8e8c-89cb97ad35c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123566139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.123566139
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2790756009
Short name T173
Test name
Test status
Simulation time 2795848415 ps
CPU time 14.02 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:21 PM PDT 24
Peak memory 215420 kb
Host smart-1affdabc-3e1b-4d64-bad9-e1f67ab0b819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790756009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2790756009
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1069791174
Short name T1048
Test name
Test status
Simulation time 106731345 ps
CPU time 2.61 seconds
Started May 30 01:09:08 PM PDT 24
Finished May 30 01:09:12 PM PDT 24
Peak memory 215456 kb
Host smart-95535741-f770-4279-9cf8-dbede8b8c0c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069791174 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1069791174
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3212586092
Short name T122
Test name
Test status
Simulation time 131440877 ps
CPU time 2.01 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:13 PM PDT 24
Peak memory 215412 kb
Host smart-e6af2024-35d7-4957-a6aa-ceffdf7222c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212586092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3212586092
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.678554505
Short name T1088
Test name
Test status
Simulation time 68479723 ps
CPU time 0.69 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:12 PM PDT 24
Peak memory 203576 kb
Host smart-24dc4e1c-6f51-4c3c-8f0a-a334062b1b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678554505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.678554505
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3925313205
Short name T141
Test name
Test status
Simulation time 328595348 ps
CPU time 2.1 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 215500 kb
Host smart-06f383f1-c7aa-48e3-9872-abe30f7a94ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925313205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3925313205
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4268587813
Short name T1039
Test name
Test status
Simulation time 134655149 ps
CPU time 3.79 seconds
Started May 30 01:09:07 PM PDT 24
Finished May 30 01:09:12 PM PDT 24
Peak memory 215628 kb
Host smart-33795595-cd7d-403b-a175-043b4f901cce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268587813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4268587813
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2671340603
Short name T176
Test name
Test status
Simulation time 2932982289 ps
CPU time 15.75 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:23 PM PDT 24
Peak memory 223792 kb
Host smart-12432e49-7fcc-4c60-a356-a47d52d9257e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671340603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2671340603
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2617551747
Short name T116
Test name
Test status
Simulation time 911254980 ps
CPU time 2.9 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:14 PM PDT 24
Peak memory 216504 kb
Host smart-1f04f93c-2309-40b0-acec-6697510e4768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617551747 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2617551747
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3958809281
Short name T990
Test name
Test status
Simulation time 361733608 ps
CPU time 2.59 seconds
Started May 30 01:09:05 PM PDT 24
Finished May 30 01:09:09 PM PDT 24
Peak memory 215516 kb
Host smart-392c14c6-6dfb-4bda-a4ad-9945d90c5df6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958809281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3958809281
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2431772445
Short name T1074
Test name
Test status
Simulation time 28019634 ps
CPU time 0.71 seconds
Started May 30 01:09:09 PM PDT 24
Finished May 30 01:09:11 PM PDT 24
Peak memory 203884 kb
Host smart-91680869-b92d-4745-9fff-c6f8551fbac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431772445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2431772445
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.995432711
Short name T1003
Test name
Test status
Simulation time 248948485 ps
CPU time 1.73 seconds
Started May 30 01:09:09 PM PDT 24
Finished May 30 01:09:11 PM PDT 24
Peak memory 215380 kb
Host smart-af9f2e8f-6e4d-4d08-86c2-acf8abc5bf11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995432711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.995432711
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3402366799
Short name T106
Test name
Test status
Simulation time 183527038 ps
CPU time 4.42 seconds
Started May 30 01:09:09 PM PDT 24
Finished May 30 01:09:14 PM PDT 24
Peak memory 215480 kb
Host smart-d2f6363f-766e-410e-afaa-41766fd35e16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402366799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3402366799
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2853507710
Short name T1065
Test name
Test status
Simulation time 399633987 ps
CPU time 6.19 seconds
Started May 30 01:09:08 PM PDT 24
Finished May 30 01:09:16 PM PDT 24
Peak memory 216456 kb
Host smart-7c349bb8-893d-464e-bf5b-a3f46a2a98d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853507710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2853507710
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.989215342
Short name T115
Test name
Test status
Simulation time 165477653 ps
CPU time 4.07 seconds
Started May 30 01:09:18 PM PDT 24
Finished May 30 01:09:23 PM PDT 24
Peak memory 217500 kb
Host smart-0be6ac12-79e3-44a9-b50b-4b45e1787020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989215342 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.989215342
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.548923137
Short name T120
Test name
Test status
Simulation time 82911997 ps
CPU time 2.25 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:20 PM PDT 24
Peak memory 215564 kb
Host smart-d9a20732-7e03-436c-a5bd-defa5c92f89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548923137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.548923137
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.150670208
Short name T996
Test name
Test status
Simulation time 114546702 ps
CPU time 0.76 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:09:17 PM PDT 24
Peak memory 203724 kb
Host smart-9d526268-4f13-4f48-a43d-739c8df59d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150670208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.150670208
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3219229025
Short name T1083
Test name
Test status
Simulation time 117634334 ps
CPU time 1.94 seconds
Started May 30 01:09:13 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 207332 kb
Host smart-0469c988-947f-44fe-afa5-a3b0c9d77cd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219229025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3219229025
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3800200080
Short name T96
Test name
Test status
Simulation time 32623367 ps
CPU time 2.12 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 207460 kb
Host smart-dabd8b0e-121f-4f34-bb49-80a892e80573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800200080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3800200080
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3090496284
Short name T1063
Test name
Test status
Simulation time 2016465137 ps
CPU time 13.93 seconds
Started May 30 01:09:13 PM PDT 24
Finished May 30 01:09:28 PM PDT 24
Peak memory 215540 kb
Host smart-8d40fc6a-41b7-4d1a-bebc-679ce7598866
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090496284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3090496284
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.227632648
Short name T1038
Test name
Test status
Simulation time 132269328 ps
CPU time 3.99 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 217212 kb
Host smart-38f2316b-43e8-44b1-8023-8ea2ae3c4521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227632648 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.227632648
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.176894080
Short name T1009
Test name
Test status
Simulation time 29546605 ps
CPU time 2.06 seconds
Started May 30 01:09:20 PM PDT 24
Finished May 30 01:09:23 PM PDT 24
Peak memory 220100 kb
Host smart-f0e1c6be-3e76-42cc-9304-81be635a0d00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176894080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.176894080
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3103244176
Short name T994
Test name
Test status
Simulation time 20769075 ps
CPU time 0.75 seconds
Started May 30 01:09:16 PM PDT 24
Finished May 30 01:09:18 PM PDT 24
Peak memory 203716 kb
Host smart-abb22cb5-7952-4176-8fbf-46194193d194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103244176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3103244176
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.475200946
Short name T1016
Test name
Test status
Simulation time 43417500 ps
CPU time 2.89 seconds
Started May 30 01:09:12 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 215732 kb
Host smart-373057b8-2c70-4aee-beb6-2e92d92b145b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475200946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.475200946
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3658515555
Short name T114
Test name
Test status
Simulation time 111871256 ps
CPU time 3.19 seconds
Started May 30 01:09:19 PM PDT 24
Finished May 30 01:09:24 PM PDT 24
Peak memory 215800 kb
Host smart-10b61641-9e7b-4915-a98c-87113a271ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658515555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3658515555
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1372408272
Short name T174
Test name
Test status
Simulation time 911255138 ps
CPU time 22.88 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:42 PM PDT 24
Peak memory 216164 kb
Host smart-cd754e03-6e10-4333-bf5b-8adb780b1432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372408272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1372408272
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3985430826
Short name T94
Test name
Test status
Simulation time 484029225 ps
CPU time 3.78 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 217620 kb
Host smart-9e3c4759-46ab-438a-b4cc-49f0728b1f28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985430826 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3985430826
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2721373254
Short name T128
Test name
Test status
Simulation time 109670400 ps
CPU time 2.59 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 215404 kb
Host smart-1a57bd46-eee1-4371-98ff-4c029e236e5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721373254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2721373254
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1043106443
Short name T1036
Test name
Test status
Simulation time 49975961 ps
CPU time 0.69 seconds
Started May 30 01:09:19 PM PDT 24
Finished May 30 01:09:21 PM PDT 24
Peak memory 203640 kb
Host smart-a9040969-e155-42d8-b12a-69c99210e966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043106443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1043106443
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1854566060
Short name T1027
Test name
Test status
Simulation time 121617386 ps
CPU time 1.75 seconds
Started May 30 01:09:19 PM PDT 24
Finished May 30 01:09:22 PM PDT 24
Peak memory 215400 kb
Host smart-4744b43c-7aa6-4ebf-b6a5-e4ca553f3911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854566060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1854566060
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3812870082
Short name T109
Test name
Test status
Simulation time 518021661 ps
CPU time 3.33 seconds
Started May 30 01:09:16 PM PDT 24
Finished May 30 01:09:21 PM PDT 24
Peak memory 215520 kb
Host smart-bda3ef8b-3bc1-47f4-9bcf-88f838ab2751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812870082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3812870082
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1419210812
Short name T95
Test name
Test status
Simulation time 471961528 ps
CPU time 3.6 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 216672 kb
Host smart-cc28a4c8-d109-4f89-a1b4-1005bee1622a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419210812 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1419210812
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2602452568
Short name T1077
Test name
Test status
Simulation time 19549916 ps
CPU time 1.26 seconds
Started May 30 01:09:16 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 215540 kb
Host smart-b45f9e63-3a9a-4e82-ba14-e0ab2b4a9964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602452568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2602452568
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.293593578
Short name T1035
Test name
Test status
Simulation time 64970053 ps
CPU time 0.76 seconds
Started May 30 01:09:18 PM PDT 24
Finished May 30 01:09:20 PM PDT 24
Peak memory 203912 kb
Host smart-ae364908-bedd-43e2-8832-4eae7927341e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293593578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.293593578
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.975196455
Short name T1017
Test name
Test status
Simulation time 58787243 ps
CPU time 3.85 seconds
Started May 30 01:09:12 PM PDT 24
Finished May 30 01:09:16 PM PDT 24
Peak memory 215464 kb
Host smart-ac2ab2f8-1ba5-4689-8991-026c6feb9d6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975196455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.975196455
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1236926938
Short name T110
Test name
Test status
Simulation time 35417975 ps
CPU time 2.01 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:20 PM PDT 24
Peak memory 215616 kb
Host smart-5b19eaa9-fe33-4484-8006-50e527286c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236926938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1236926938
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.525793863
Short name T178
Test name
Test status
Simulation time 303910972 ps
CPU time 19.75 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:38 PM PDT 24
Peak memory 215512 kb
Host smart-dc4f98fc-998f-474f-bbca-ea603a651e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525793863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.525793863
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2333439787
Short name T1051
Test name
Test status
Simulation time 28022150 ps
CPU time 1.96 seconds
Started May 30 01:09:13 PM PDT 24
Finished May 30 01:09:16 PM PDT 24
Peak memory 216700 kb
Host smart-ba9c26be-b064-4a78-b727-5e843c99aefd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333439787 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2333439787
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.18610187
Short name T1041
Test name
Test status
Simulation time 38065889 ps
CPU time 1.26 seconds
Started May 30 01:09:19 PM PDT 24
Finished May 30 01:09:21 PM PDT 24
Peak memory 207228 kb
Host smart-df80b462-73da-4534-86b0-8b04b00b1137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18610187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.18610187
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2013148086
Short name T1053
Test name
Test status
Simulation time 41440392 ps
CPU time 0.74 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203640 kb
Host smart-c540a6ab-ed34-4af4-a3ed-c756d5dde72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013148086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2013148086
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2398409590
Short name T1085
Test name
Test status
Simulation time 758277318 ps
CPU time 3.72 seconds
Started May 30 01:09:12 PM PDT 24
Finished May 30 01:09:16 PM PDT 24
Peak memory 215496 kb
Host smart-be0fea9a-34f8-4bc5-816c-1ea8d1647170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398409590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2398409590
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1818670812
Short name T107
Test name
Test status
Simulation time 68310541 ps
CPU time 4.5 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:09:21 PM PDT 24
Peak memory 215640 kb
Host smart-134cec4c-3614-4bbf-98b7-af280b27afca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818670812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1818670812
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.159845315
Short name T177
Test name
Test status
Simulation time 830981213 ps
CPU time 19.03 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:09:36 PM PDT 24
Peak memory 215760 kb
Host smart-57d270d9-e536-485b-ac75-edd6afcc23ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159845315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.159845315
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2398479442
Short name T130
Test name
Test status
Simulation time 373058944 ps
CPU time 7.93 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:07 PM PDT 24
Peak memory 207324 kb
Host smart-2ce96fd0-cc22-4db6-af2a-b2305920f232
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398479442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2398479442
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4043876702
Short name T1024
Test name
Test status
Simulation time 2436973249 ps
CPU time 34.55 seconds
Started May 30 01:08:57 PM PDT 24
Finished May 30 01:09:33 PM PDT 24
Peak memory 207356 kb
Host smart-1aaff3b4-02f6-48cd-a840-815cade2f4f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043876702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4043876702
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2642163569
Short name T1066
Test name
Test status
Simulation time 87256292 ps
CPU time 0.94 seconds
Started May 30 01:09:03 PM PDT 24
Finished May 30 01:09:05 PM PDT 24
Peak memory 206992 kb
Host smart-b8985c34-7640-43d8-a14a-d65b3e09701d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642163569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2642163569
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.361970336
Short name T1047
Test name
Test status
Simulation time 151594738 ps
CPU time 2.74 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 217100 kb
Host smart-61a332a2-c89f-440f-8b56-35d25f486572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361970336 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.361970336
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2757764613
Short name T131
Test name
Test status
Simulation time 55005179 ps
CPU time 1.85 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 207140 kb
Host smart-e30409f6-013b-4729-9367-9c418808e621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757764613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
757764613
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3538710374
Short name T986
Test name
Test status
Simulation time 40619170 ps
CPU time 0.7 seconds
Started May 30 01:08:56 PM PDT 24
Finished May 30 01:08:58 PM PDT 24
Peak memory 204028 kb
Host smart-e90be7fe-cf13-4073-b6fa-b12da0cfe5eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538710374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
538710374
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2294618289
Short name T1028
Test name
Test status
Simulation time 19024328 ps
CPU time 1.27 seconds
Started May 30 01:08:57 PM PDT 24
Finished May 30 01:09:00 PM PDT 24
Peak memory 215564 kb
Host smart-6d6cc673-7448-41bd-b5d8-34010549a365
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294618289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2294618289
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3937974485
Short name T1012
Test name
Test status
Simulation time 26072417 ps
CPU time 0.66 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:02 PM PDT 24
Peak memory 203744 kb
Host smart-ad57298b-931c-4c58-99ee-61e63c526886
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937974485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3937974485
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1386795370
Short name T1023
Test name
Test status
Simulation time 47039944 ps
CPU time 2.8 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:06 PM PDT 24
Peak memory 215512 kb
Host smart-f2fc86eb-4c9a-4adc-abb9-49050033f5cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386795370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1386795370
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1129265420
Short name T103
Test name
Test status
Simulation time 49521909 ps
CPU time 1.76 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 215724 kb
Host smart-9a20c29f-6451-4f67-a5a2-89c2e1b4536a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129265420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
129265420
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1207598085
Short name T99
Test name
Test status
Simulation time 827580368 ps
CPU time 21.85 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:22 PM PDT 24
Peak memory 216012 kb
Host smart-159a9229-19bf-47e1-9388-710722ddda4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207598085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1207598085
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.286042319
Short name T1013
Test name
Test status
Simulation time 16134092 ps
CPU time 0.77 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:16 PM PDT 24
Peak memory 203696 kb
Host smart-8cc2b5bf-c157-4596-a221-d1a47c70b432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286042319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.286042319
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4206804103
Short name T1032
Test name
Test status
Simulation time 16882807 ps
CPU time 0.81 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203716 kb
Host smart-a5ab571d-4cc2-4330-90cd-5e47e4670f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206804103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4206804103
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3673547689
Short name T1044
Test name
Test status
Simulation time 14976754 ps
CPU time 0.76 seconds
Started May 30 01:09:13 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 203612 kb
Host smart-8c3d109f-01fb-4cf6-aafa-fbe70c6261bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673547689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3673547689
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1026895758
Short name T999
Test name
Test status
Simulation time 32285490 ps
CPU time 0.76 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203924 kb
Host smart-c43e6c99-2913-446c-b91b-aa992e8af113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026895758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1026895758
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.60855862
Short name T997
Test name
Test status
Simulation time 53304959 ps
CPU time 0.73 seconds
Started May 30 01:09:16 PM PDT 24
Finished May 30 01:09:18 PM PDT 24
Peak memory 203748 kb
Host smart-1208307b-87bb-4e93-8e35-dd3cea6a0f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60855862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.60855862
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2148074999
Short name T1096
Test name
Test status
Simulation time 18164096 ps
CPU time 0.75 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 204016 kb
Host smart-68da8673-debf-4ddc-bfac-cabadf23ac69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148074999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2148074999
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3067878856
Short name T1042
Test name
Test status
Simulation time 18642607 ps
CPU time 0.75 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:09:17 PM PDT 24
Peak memory 203708 kb
Host smart-7d6f0239-430f-47ce-bfe7-fa610f339ae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067878856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3067878856
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3614800302
Short name T1021
Test name
Test status
Simulation time 11981773 ps
CPU time 0.8 seconds
Started May 30 01:09:16 PM PDT 24
Finished May 30 01:09:18 PM PDT 24
Peak memory 203772 kb
Host smart-dcdb828a-223d-4486-917b-bed7950c43cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614800302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3614800302
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1477076159
Short name T1097
Test name
Test status
Simulation time 23729544 ps
CPU time 0.7 seconds
Started May 30 01:09:13 PM PDT 24
Finished May 30 01:09:14 PM PDT 24
Peak memory 203912 kb
Host smart-0670ce2b-f613-4607-8194-5406ca2e3e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477076159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1477076159
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3763457407
Short name T984
Test name
Test status
Simulation time 55891384 ps
CPU time 0.69 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:12 PM PDT 24
Peak memory 203692 kb
Host smart-ae04e344-960d-447f-80db-b1859f92e4f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763457407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3763457407
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3124639608
Short name T127
Test name
Test status
Simulation time 762208487 ps
CPU time 15.48 seconds
Started May 30 01:09:01 PM PDT 24
Finished May 30 01:09:18 PM PDT 24
Peak memory 215564 kb
Host smart-eaac1285-3c18-470b-9218-8e95f48ee66d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124639608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3124639608
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2906504329
Short name T1033
Test name
Test status
Simulation time 1236701897 ps
CPU time 13.1 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:16 PM PDT 24
Peak memory 207224 kb
Host smart-8a2bbb18-6222-4dc4-b870-a46f80da9716
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906504329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2906504329
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4020254524
Short name T82
Test name
Test status
Simulation time 115440368 ps
CPU time 1.2 seconds
Started May 30 01:09:01 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 207188 kb
Host smart-20bdfa51-dd40-40bb-bf25-7fdd1075576f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020254524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4020254524
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2766025622
Short name T1030
Test name
Test status
Simulation time 49603351 ps
CPU time 1.8 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:05 PM PDT 24
Peak memory 216680 kb
Host smart-f1f03ebf-0496-4962-ad6b-d3d68d0e6956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766025622 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2766025622
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2781090195
Short name T1055
Test name
Test status
Simulation time 359589322 ps
CPU time 2.18 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:05 PM PDT 24
Peak memory 215528 kb
Host smart-d2ebb690-60af-4311-b939-2600b27d9f04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781090195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
781090195
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3315775016
Short name T1000
Test name
Test status
Simulation time 20649756 ps
CPU time 0.71 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:04 PM PDT 24
Peak memory 203664 kb
Host smart-3136c8d2-191e-48b2-b1ff-446b87a861cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315775016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
315775016
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3064586396
Short name T125
Test name
Test status
Simulation time 32813474 ps
CPU time 1.32 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 215608 kb
Host smart-210738e1-0897-4ec0-89bb-0615d46e9784
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064586396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3064586396
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.765604458
Short name T1057
Test name
Test status
Simulation time 12191359 ps
CPU time 0.7 seconds
Started May 30 01:09:01 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 203612 kb
Host smart-88d4f33a-d120-420b-b935-44c445d72511
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765604458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.765604458
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2341678272
Short name T1025
Test name
Test status
Simulation time 168430909 ps
CPU time 2.81 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:06 PM PDT 24
Peak memory 215396 kb
Host smart-99c8ed09-e66e-4c83-85be-7d1b3cb42452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341678272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2341678272
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.329784509
Short name T105
Test name
Test status
Simulation time 60992527 ps
CPU time 3.57 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:05 PM PDT 24
Peak memory 215596 kb
Host smart-aa858945-2f80-4caf-b155-d6b3ee91b9c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329784509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.329784509
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3350982276
Short name T1087
Test name
Test status
Simulation time 554820876 ps
CPU time 15.7 seconds
Started May 30 01:08:56 PM PDT 24
Finished May 30 01:09:13 PM PDT 24
Peak memory 215564 kb
Host smart-32d0c889-7af0-4b99-a8b9-01c4bf4fb856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350982276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3350982276
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.660001183
Short name T1008
Test name
Test status
Simulation time 13568168 ps
CPU time 0.72 seconds
Started May 30 01:09:11 PM PDT 24
Finished May 30 01:09:13 PM PDT 24
Peak memory 203692 kb
Host smart-454b6c73-2ad0-43ce-80bc-d058573ce89f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660001183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.660001183
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3168305257
Short name T1010
Test name
Test status
Simulation time 38847862 ps
CPU time 0.75 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203772 kb
Host smart-5f443f8b-8135-4161-9ec1-8f206dd530da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168305257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3168305257
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2086179296
Short name T1046
Test name
Test status
Simulation time 23498254 ps
CPU time 0.72 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:09:17 PM PDT 24
Peak memory 203992 kb
Host smart-f1a9683a-a4d9-4092-9798-35359f059443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086179296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2086179296
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.557397395
Short name T1078
Test name
Test status
Simulation time 12118629 ps
CPU time 0.7 seconds
Started May 30 01:09:13 PM PDT 24
Finished May 30 01:09:14 PM PDT 24
Peak memory 203724 kb
Host smart-571b7e4f-db8b-41fc-9a97-e8af496ee886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557397395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.557397395
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1327667153
Short name T1069
Test name
Test status
Simulation time 44850679 ps
CPU time 0.7 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203716 kb
Host smart-acbc1e6d-fe57-433e-aa8f-f8b4dba578ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327667153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1327667153
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.891710193
Short name T1099
Test name
Test status
Simulation time 34186227 ps
CPU time 0.73 seconds
Started May 30 01:09:13 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 203716 kb
Host smart-bb8540ac-28ab-4575-9a60-a30b4b2b6ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891710193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.891710193
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2134607645
Short name T998
Test name
Test status
Simulation time 43035620 ps
CPU time 0.76 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:09:17 PM PDT 24
Peak memory 203912 kb
Host smart-a73c8247-38eb-4116-a42b-c8884e0158a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134607645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2134607645
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3637282625
Short name T1045
Test name
Test status
Simulation time 118619155 ps
CPU time 0.72 seconds
Started May 30 01:09:20 PM PDT 24
Finished May 30 01:09:22 PM PDT 24
Peak memory 203668 kb
Host smart-b59a4893-173d-4077-b558-f1bb9940c902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637282625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3637282625
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3371897823
Short name T1034
Test name
Test status
Simulation time 17628041 ps
CPU time 0.78 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203708 kb
Host smart-8e532ff5-953e-4ab9-a3fd-83ac0ecd5eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371897823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3371897823
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.294430121
Short name T1049
Test name
Test status
Simulation time 12697920 ps
CPU time 0.73 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:16 PM PDT 24
Peak memory 203700 kb
Host smart-13390b72-9331-4823-b382-2b21bd22a559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294430121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.294430121
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1357387909
Short name T147
Test name
Test status
Simulation time 566410269 ps
CPU time 8.35 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 206988 kb
Host smart-3f653a88-dd8b-42b3-98d3-dacc50c16101
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357387909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1357387909
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1847318850
Short name T129
Test name
Test status
Simulation time 7208304191 ps
CPU time 37.49 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:39 PM PDT 24
Peak memory 207384 kb
Host smart-020364c8-dabe-406f-b33e-8ab3d6fd91d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847318850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1847318850
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3750538237
Short name T84
Test name
Test status
Simulation time 41809934 ps
CPU time 1.41 seconds
Started May 30 01:09:05 PM PDT 24
Finished May 30 01:09:07 PM PDT 24
Peak memory 216460 kb
Host smart-aeafbdb2-87df-46a4-b16f-4d23e6356ea2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750538237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3750538237
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1036325239
Short name T1058
Test name
Test status
Simulation time 196017818 ps
CPU time 3.38 seconds
Started May 30 01:09:07 PM PDT 24
Finished May 30 01:09:11 PM PDT 24
Peak memory 217960 kb
Host smart-f124ef72-fdc8-42fd-95dc-9d68c03ec814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036325239 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1036325239
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4236738625
Short name T1090
Test name
Test status
Simulation time 101153043 ps
CPU time 1.81 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:09 PM PDT 24
Peak memory 215552 kb
Host smart-ef974ea8-aa51-4221-943c-2060575196e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236738625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
236738625
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3213488998
Short name T1068
Test name
Test status
Simulation time 11707827 ps
CPU time 0.68 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:12 PM PDT 24
Peak memory 203676 kb
Host smart-0599bf04-85b4-41bd-a893-1fc16ffc88df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213488998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
213488998
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1347499423
Short name T1029
Test name
Test status
Simulation time 91556794 ps
CPU time 2.14 seconds
Started May 30 01:09:05 PM PDT 24
Finished May 30 01:09:08 PM PDT 24
Peak memory 215572 kb
Host smart-f92b95e8-4562-4578-881c-9226adc80ba0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347499423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1347499423
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.532320983
Short name T1014
Test name
Test status
Simulation time 34144885 ps
CPU time 0.68 seconds
Started May 30 01:09:05 PM PDT 24
Finished May 30 01:09:07 PM PDT 24
Peak memory 203576 kb
Host smart-0899b884-5f49-44d6-b452-753115d9250b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532320983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.532320983
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3869397776
Short name T142
Test name
Test status
Simulation time 154124697 ps
CPU time 4.06 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:11 PM PDT 24
Peak memory 215324 kb
Host smart-2023aa47-412c-4ec1-84f0-776d6ec2aa0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869397776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3869397776
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2706485525
Short name T104
Test name
Test status
Simulation time 107343233 ps
CPU time 2.07 seconds
Started May 30 01:09:01 PM PDT 24
Finished May 30 01:09:05 PM PDT 24
Peak memory 215612 kb
Host smart-026ca962-883e-4269-b2c2-ab515f5d9076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706485525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
706485525
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3918333496
Short name T97
Test name
Test status
Simulation time 210347436 ps
CPU time 6.94 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:09 PM PDT 24
Peak memory 215520 kb
Host smart-75259644-081f-4924-8d5d-b0573480a087
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918333496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3918333496
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1824953174
Short name T1018
Test name
Test status
Simulation time 15523442 ps
CPU time 0.77 seconds
Started May 30 01:09:20 PM PDT 24
Finished May 30 01:09:22 PM PDT 24
Peak memory 204020 kb
Host smart-53d1d7d7-f897-41e6-b271-52fbecc2d14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824953174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1824953174
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.819408481
Short name T1100
Test name
Test status
Simulation time 36157589 ps
CPU time 0.71 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203640 kb
Host smart-7c1d760c-31bd-4781-be31-fde9091fc385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819408481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.819408481
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1025608247
Short name T1092
Test name
Test status
Simulation time 23315226 ps
CPU time 0.74 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:16 PM PDT 24
Peak memory 204000 kb
Host smart-cf5540e6-5b42-4c6e-a1c2-d5ade0e7ef7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025608247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1025608247
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4055713430
Short name T1062
Test name
Test status
Simulation time 44211040 ps
CPU time 0.73 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203692 kb
Host smart-87754c02-5b64-4258-9c7a-e33657143d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055713430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4055713430
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2750524032
Short name T1054
Test name
Test status
Simulation time 28464181 ps
CPU time 0.74 seconds
Started May 30 01:09:20 PM PDT 24
Finished May 30 01:09:22 PM PDT 24
Peak memory 203780 kb
Host smart-69d41fed-b5d8-461c-9323-edb99d5a81dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750524032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2750524032
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3006777902
Short name T995
Test name
Test status
Simulation time 11689050 ps
CPU time 0.73 seconds
Started May 30 01:09:17 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 203944 kb
Host smart-be4e9bb5-a133-41dd-a196-5699cc97ae90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006777902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3006777902
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1518782173
Short name T1019
Test name
Test status
Simulation time 18075007 ps
CPU time 0.76 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 203740 kb
Host smart-9d88b6f2-e0a1-451e-985d-d85a6da526f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518782173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1518782173
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2553030033
Short name T1005
Test name
Test status
Simulation time 36698801 ps
CPU time 0.68 seconds
Started May 30 01:09:16 PM PDT 24
Finished May 30 01:09:18 PM PDT 24
Peak memory 203708 kb
Host smart-24fde7c8-a455-40a9-a329-ffa976827da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553030033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2553030033
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2050965523
Short name T985
Test name
Test status
Simulation time 134087366 ps
CPU time 0.73 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 203648 kb
Host smart-9be5465e-1a7c-4c66-961f-0a0853697018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050965523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2050965523
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2011688734
Short name T1080
Test name
Test status
Simulation time 17378126 ps
CPU time 0.76 seconds
Started May 30 01:09:15 PM PDT 24
Finished May 30 01:09:17 PM PDT 24
Peak memory 203752 kb
Host smart-e91a9eed-287e-4af5-addb-ce274351525c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011688734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2011688734
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.285309773
Short name T1006
Test name
Test status
Simulation time 318136856 ps
CPU time 1.94 seconds
Started May 30 01:09:07 PM PDT 24
Finished May 30 01:09:09 PM PDT 24
Peak memory 216696 kb
Host smart-3129b053-9bbf-47ec-9a92-7cd6e854be3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285309773 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.285309773
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.882711696
Short name T124
Test name
Test status
Simulation time 423316649 ps
CPU time 1.31 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:01 PM PDT 24
Peak memory 207228 kb
Host smart-43654c27-33de-4e05-b46c-9c7cfc9549b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882711696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.882711696
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1673927728
Short name T1098
Test name
Test status
Simulation time 25527522 ps
CPU time 0.73 seconds
Started May 30 01:08:57 PM PDT 24
Finished May 30 01:09:00 PM PDT 24
Peak memory 203652 kb
Host smart-d26645dd-1b8c-4d45-b974-cb534b5bca27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673927728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
673927728
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4043491867
Short name T1026
Test name
Test status
Simulation time 151129849 ps
CPU time 1.88 seconds
Started May 30 01:09:07 PM PDT 24
Finished May 30 01:09:10 PM PDT 24
Peak memory 215544 kb
Host smart-66760059-683a-44f8-b20b-f8b12d449530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043491867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4043491867
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.470677128
Short name T1002
Test name
Test status
Simulation time 44357724 ps
CPU time 1.5 seconds
Started May 30 01:09:07 PM PDT 24
Finished May 30 01:09:09 PM PDT 24
Peak memory 215532 kb
Host smart-016c3881-70f6-425d-a3d9-7d7ad1dca02f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470677128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.470677128
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1467238125
Short name T1056
Test name
Test status
Simulation time 1002144547 ps
CPU time 18.4 seconds
Started May 30 01:08:58 PM PDT 24
Finished May 30 01:09:18 PM PDT 24
Peak memory 215428 kb
Host smart-1b222456-8f02-4244-8c0b-b0e8dbbf420f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467238125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1467238125
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.587058314
Short name T1081
Test name
Test status
Simulation time 96871004 ps
CPU time 3.15 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:14 PM PDT 24
Peak memory 216580 kb
Host smart-066aac28-cc87-4c64-b7d7-ddf6c924fe17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587058314 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.587058314
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3839355832
Short name T123
Test name
Test status
Simulation time 404721560 ps
CPU time 2.61 seconds
Started May 30 01:09:09 PM PDT 24
Finished May 30 01:09:13 PM PDT 24
Peak memory 215440 kb
Host smart-b6b74dda-02bc-4554-91b2-eae10b403b18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839355832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
839355832
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4257912851
Short name T1059
Test name
Test status
Simulation time 37686178 ps
CPU time 0.75 seconds
Started May 30 01:09:11 PM PDT 24
Finished May 30 01:09:13 PM PDT 24
Peak memory 203720 kb
Host smart-29ebccfb-152b-4774-a3fa-72a225f65e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257912851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
257912851
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3640786963
Short name T1052
Test name
Test status
Simulation time 52433302 ps
CPU time 1.81 seconds
Started May 30 01:09:08 PM PDT 24
Finished May 30 01:09:11 PM PDT 24
Peak memory 207044 kb
Host smart-da766f4a-941d-4d7a-b6d1-f58fb8d630b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640786963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3640786963
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3770705678
Short name T1089
Test name
Test status
Simulation time 326082886 ps
CPU time 16.8 seconds
Started May 30 01:09:05 PM PDT 24
Finished May 30 01:09:23 PM PDT 24
Peak memory 215540 kb
Host smart-f984f1c7-991f-445b-a803-3a12f021ab62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770705678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3770705678
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1438837621
Short name T1004
Test name
Test status
Simulation time 326125408 ps
CPU time 2.88 seconds
Started May 30 01:09:09 PM PDT 24
Finished May 30 01:09:13 PM PDT 24
Peak memory 217820 kb
Host smart-e75428c0-9226-4b4a-aa3d-af232720d210
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438837621 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1438837621
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1812758280
Short name T1071
Test name
Test status
Simulation time 34643700 ps
CPU time 2.28 seconds
Started May 30 01:09:08 PM PDT 24
Finished May 30 01:09:12 PM PDT 24
Peak memory 215564 kb
Host smart-5b34c1e8-5de3-4ac8-932d-5a7ff96a7ef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812758280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
812758280
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2551205482
Short name T1011
Test name
Test status
Simulation time 13733573 ps
CPU time 0.8 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:05 PM PDT 24
Peak memory 203720 kb
Host smart-feeb2b4b-da5a-4d25-8aef-12ded585d0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551205482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
551205482
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3749841228
Short name T1001
Test name
Test status
Simulation time 376990876 ps
CPU time 2.74 seconds
Started May 30 01:08:59 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 215544 kb
Host smart-97fc10c3-fb54-46d5-b082-5a2200b12ea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749841228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3749841228
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3759728871
Short name T180
Test name
Test status
Simulation time 665058689 ps
CPU time 8.63 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:19 PM PDT 24
Peak memory 215728 kb
Host smart-8d0d5fb5-a110-4185-92fd-74c0bba59e5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759728871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3759728871
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1192583720
Short name T113
Test name
Test status
Simulation time 560430225 ps
CPU time 2.78 seconds
Started May 30 01:09:11 PM PDT 24
Finished May 30 01:09:15 PM PDT 24
Peak memory 218088 kb
Host smart-bb31c58e-1380-4542-96b4-b8f5d894ad60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192583720 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1192583720
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3227523530
Short name T1075
Test name
Test status
Simulation time 290803640 ps
CPU time 1.95 seconds
Started May 30 01:09:02 PM PDT 24
Finished May 30 01:09:05 PM PDT 24
Peak memory 215552 kb
Host smart-d85ebee0-fd7d-4d2c-9c1a-746eedc36489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227523530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
227523530
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3212649569
Short name T1040
Test name
Test status
Simulation time 14900865 ps
CPU time 0.73 seconds
Started May 30 01:09:06 PM PDT 24
Finished May 30 01:09:07 PM PDT 24
Peak memory 203780 kb
Host smart-5ddb9771-39cb-46f3-9964-8dada7ad0ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212649569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
212649569
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1051439112
Short name T1060
Test name
Test status
Simulation time 169557892 ps
CPU time 2.75 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:04 PM PDT 24
Peak memory 215588 kb
Host smart-38f9dd0b-b5e9-426e-a761-83ba5f204469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051439112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1051439112
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2020015337
Short name T108
Test name
Test status
Simulation time 459381760 ps
CPU time 3.27 seconds
Started May 30 01:09:10 PM PDT 24
Finished May 30 01:09:14 PM PDT 24
Peak memory 215584 kb
Host smart-ad34b8f2-8262-4a40-8fc9-60ec56c290a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020015337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
020015337
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1674093656
Short name T1037
Test name
Test status
Simulation time 85236339 ps
CPU time 1.6 seconds
Started May 30 01:09:00 PM PDT 24
Finished May 30 01:09:03 PM PDT 24
Peak memory 215672 kb
Host smart-ec2fda32-cc3a-4fed-8013-1d1fe8a8e7ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674093656 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1674093656
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3718576819
Short name T1061
Test name
Test status
Simulation time 97200144 ps
CPU time 2.57 seconds
Started May 30 01:09:09 PM PDT 24
Finished May 30 01:09:12 PM PDT 24
Peak memory 215496 kb
Host smart-9e8b6bb6-8db0-4897-868f-064c95048791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718576819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
718576819
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3440999570
Short name T1067
Test name
Test status
Simulation time 41773250 ps
CPU time 0.7 seconds
Started May 30 01:09:09 PM PDT 24
Finished May 30 01:09:11 PM PDT 24
Peak memory 203648 kb
Host smart-15db3955-bb88-4b6b-9f55-468fdf19ab27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440999570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
440999570
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3996870848
Short name T988
Test name
Test status
Simulation time 593472125 ps
CPU time 4.04 seconds
Started May 30 01:09:03 PM PDT 24
Finished May 30 01:09:08 PM PDT 24
Peak memory 215516 kb
Host smart-c034e500-d1ee-404e-b799-5615e103831e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996870848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3996870848
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1726575781
Short name T111
Test name
Test status
Simulation time 52803572 ps
CPU time 3.83 seconds
Started May 30 01:09:08 PM PDT 24
Finished May 30 01:09:13 PM PDT 24
Peak memory 215664 kb
Host smart-60c3c2ce-064e-41a2-96aa-a8c20a432c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726575781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
726575781
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.883870587
Short name T1072
Test name
Test status
Simulation time 561498035 ps
CPU time 14.08 seconds
Started May 30 01:09:14 PM PDT 24
Finished May 30 01:09:29 PM PDT 24
Peak memory 215556 kb
Host smart-916b0bcb-56eb-4aef-8803-b1131672c0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883870587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.883870587
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.167611766
Short name T469
Test name
Test status
Simulation time 50742941 ps
CPU time 0.7 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:16:23 PM PDT 24
Peak memory 204780 kb
Host smart-051ab6e1-c658-4827-9119-c925743a3f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167611766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.167611766
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3939495567
Short name T892
Test name
Test status
Simulation time 10845500575 ps
CPU time 5.94 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:30 PM PDT 24
Peak memory 219644 kb
Host smart-abebcaa5-a6bc-428e-84ec-5464234495fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939495567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3939495567
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1595053087
Short name T789
Test name
Test status
Simulation time 100579364 ps
CPU time 0.73 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:08 PM PDT 24
Peak memory 204904 kb
Host smart-1761425b-44c4-4170-8d6a-ecd2e09ceb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595053087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1595053087
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2698788351
Short name T847
Test name
Test status
Simulation time 36731619138 ps
CPU time 46.21 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:17:11 PM PDT 24
Peak memory 240612 kb
Host smart-9f7761ba-9271-4ada-acce-9b089a90f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698788351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2698788351
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2916929470
Short name T133
Test name
Test status
Simulation time 120512783392 ps
CPU time 174.95 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:19:19 PM PDT 24
Peak memory 239504 kb
Host smart-43c6f475-21ea-44bd-9c03-8378fc0679eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916929470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2916929470
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3739684545
Short name T525
Test name
Test status
Simulation time 70054515641 ps
CPU time 133.48 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:18:39 PM PDT 24
Peak memory 249704 kb
Host smart-0eba31f4-3b0e-4aad-b83b-131223a3659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739684545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3739684545
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3035739488
Short name T561
Test name
Test status
Simulation time 464981084 ps
CPU time 4.09 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:25 PM PDT 24
Peak memory 232344 kb
Host smart-ca0c925b-eaa8-4500-9014-d1fded61ac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035739488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3035739488
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4004998886
Short name T448
Test name
Test status
Simulation time 13091441790 ps
CPU time 26.95 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:35 PM PDT 24
Peak memory 233420 kb
Host smart-de0f94db-68db-4308-b3b7-37e842f1d184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004998886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4004998886
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3313824757
Short name T891
Test name
Test status
Simulation time 4115495448 ps
CPU time 41.57 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:49 PM PDT 24
Peak memory 240652 kb
Host smart-8d3cc1ef-4e8e-4278-b888-220b9049afde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313824757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3313824757
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3118138427
Short name T804
Test name
Test status
Simulation time 51281022 ps
CPU time 1.08 seconds
Started May 30 01:16:08 PM PDT 24
Finished May 30 01:16:11 PM PDT 24
Peak memory 216220 kb
Host smart-5d82d6ac-77ee-4830-9394-b05efa3db2d9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118138427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3118138427
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4202268325
Short name T760
Test name
Test status
Simulation time 4202629515 ps
CPU time 8.87 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:16 PM PDT 24
Peak memory 234952 kb
Host smart-5849085f-b798-4971-ae07-dd7bdb919a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202268325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4202268325
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1158391111
Short name T533
Test name
Test status
Simulation time 7091971197 ps
CPU time 11.89 seconds
Started May 30 01:16:10 PM PDT 24
Finished May 30 01:16:23 PM PDT 24
Peak memory 219384 kb
Host smart-b55ebf70-7c03-4ea2-8006-8314e5dc903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158391111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1158391111
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.793396893
Short name T713
Test name
Test status
Simulation time 597078772 ps
CPU time 4.67 seconds
Started May 30 01:16:19 PM PDT 24
Finished May 30 01:16:25 PM PDT 24
Peak memory 218904 kb
Host smart-161c5c26-f917-495b-8729-b2f15d670c61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793396893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.793396893
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2389855356
Short name T163
Test name
Test status
Simulation time 10898318845 ps
CPU time 138.2 seconds
Started May 30 01:16:19 PM PDT 24
Finished May 30 01:18:38 PM PDT 24
Peak memory 249872 kb
Host smart-d9d4ebda-15c3-4eb8-a4d7-a014fba19b26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389855356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2389855356
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2400469180
Short name T391
Test name
Test status
Simulation time 12663776 ps
CPU time 0.74 seconds
Started May 30 01:16:10 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 205020 kb
Host smart-6cc6c703-562b-4604-94f3-f52749e9b30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400469180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2400469180
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.953469813
Short name T512
Test name
Test status
Simulation time 2245787528 ps
CPU time 4.27 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 215896 kb
Host smart-df6623bc-5a66-400c-854f-f8285cd7183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953469813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.953469813
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2399597809
Short name T10
Test name
Test status
Simulation time 44999494 ps
CPU time 1.04 seconds
Started May 30 01:16:06 PM PDT 24
Finished May 30 01:16:09 PM PDT 24
Peak memory 206812 kb
Host smart-6f5d3389-3d41-4b68-99f9-268123be9311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399597809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2399597809
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.759506595
Short name T795
Test name
Test status
Simulation time 40915823 ps
CPU time 0.89 seconds
Started May 30 01:16:07 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 205292 kb
Host smart-3ed5422f-704c-461e-8f5f-452f4a77eeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759506595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.759506595
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.126046412
Short name T646
Test name
Test status
Simulation time 1194482725 ps
CPU time 5.5 seconds
Started May 30 01:16:05 PM PDT 24
Finished May 30 01:16:12 PM PDT 24
Peak memory 218252 kb
Host smart-5320d2dc-935a-4264-b64d-5ce38a310e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126046412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.126046412
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3569621637
Short name T834
Test name
Test status
Simulation time 42629588 ps
CPU time 0.73 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:21 PM PDT 24
Peak memory 204852 kb
Host smart-bdea9ab1-1166-4a1d-9a95-0a56e51f7734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569621637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
569621637
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2261485905
Short name T917
Test name
Test status
Simulation time 423799722 ps
CPU time 4.12 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:28 PM PDT 24
Peak memory 233656 kb
Host smart-767ee36a-4766-47ef-9a37-064d2c83578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261485905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2261485905
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.409345391
Short name T332
Test name
Test status
Simulation time 18541572 ps
CPU time 0.8 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:21 PM PDT 24
Peak memory 206256 kb
Host smart-f670ae50-26d0-44fd-8e41-1dd61704a2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409345391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.409345391
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1469431789
Short name T909
Test name
Test status
Simulation time 4985960934 ps
CPU time 63.03 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:17:25 PM PDT 24
Peak memory 248820 kb
Host smart-a50c247b-96da-427f-a0c4-0b3252c012d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469431789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1469431789
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2320148904
Short name T680
Test name
Test status
Simulation time 587638022269 ps
CPU time 362.86 seconds
Started May 30 01:16:19 PM PDT 24
Finished May 30 01:22:23 PM PDT 24
Peak memory 250996 kb
Host smart-73d6d1d3-9a4e-4c68-b271-c3cf6eac5962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320148904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2320148904
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2144960477
Short name T692
Test name
Test status
Simulation time 12849300533 ps
CPU time 34.18 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:17:00 PM PDT 24
Peak memory 224368 kb
Host smart-ecc9b3fa-8cb9-4bad-bf27-2985a56fcfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144960477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2144960477
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3848725181
Short name T708
Test name
Test status
Simulation time 2356947585 ps
CPU time 22.91 seconds
Started May 30 01:16:18 PM PDT 24
Finished May 30 01:16:42 PM PDT 24
Peak memory 219144 kb
Host smart-0da1a981-bc53-40c7-9c11-687125039fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848725181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3848725181
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1013722129
Short name T855
Test name
Test status
Simulation time 30854376 ps
CPU time 2.45 seconds
Started May 30 01:16:19 PM PDT 24
Finished May 30 01:16:22 PM PDT 24
Peak memory 221164 kb
Host smart-6df45820-57d0-4dea-9ece-d3b13ad9f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013722129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1013722129
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2361085766
Short name T711
Test name
Test status
Simulation time 24603138 ps
CPU time 1.07 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:27 PM PDT 24
Peak memory 216200 kb
Host smart-784fd109-d1b9-43a4-8580-15f8ce9ad2db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361085766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2361085766
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1079041336
Short name T694
Test name
Test status
Simulation time 1284942202 ps
CPU time 5.41 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:28 PM PDT 24
Peak memory 233400 kb
Host smart-13d4b50c-7c46-4a4b-be92-da253e612853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079041336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1079041336
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.206581561
Short name T455
Test name
Test status
Simulation time 1968652325 ps
CPU time 8.6 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:32 PM PDT 24
Peak memory 218440 kb
Host smart-2881b61b-055e-4a92-ab23-9def9c221c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206581561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.206581561
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1849173608
Short name T783
Test name
Test status
Simulation time 1002116294 ps
CPU time 9.77 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:33 PM PDT 24
Peak memory 218976 kb
Host smart-339f9da2-3ddd-4f6f-ae4a-3cedd795a263
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1849173608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1849173608
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1994926119
Short name T69
Test name
Test status
Simulation time 345829551 ps
CPU time 1.16 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:27 PM PDT 24
Peak memory 234712 kb
Host smart-0a05bc16-07ca-47f5-8e4e-ab55e808ae6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994926119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1994926119
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4218502895
Short name T319
Test name
Test status
Simulation time 28906429513 ps
CPU time 21.43 seconds
Started May 30 01:16:18 PM PDT 24
Finished May 30 01:16:40 PM PDT 24
Peak memory 215920 kb
Host smart-28d73d9b-b1fe-4d0e-b83c-cbd65c4874e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218502895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4218502895
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.172416863
Short name T441
Test name
Test status
Simulation time 17963959802 ps
CPU time 12.95 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:34 PM PDT 24
Peak memory 215988 kb
Host smart-41c88153-921c-475e-801f-4102c160475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172416863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.172416863
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4168967901
Short name T43
Test name
Test status
Simulation time 23015437 ps
CPU time 1.24 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:26 PM PDT 24
Peak memory 215864 kb
Host smart-5fc608c8-7a7a-42f9-a6f9-f891f151e797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168967901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4168967901
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1601709067
Short name T416
Test name
Test status
Simulation time 70903656 ps
CPU time 0.76 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:22 PM PDT 24
Peak memory 205244 kb
Host smart-c45c4dba-7f42-4d25-854b-00f8dafba0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601709067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1601709067
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2309830466
Short name T225
Test name
Test status
Simulation time 152484971 ps
CPU time 2.31 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:28 PM PDT 24
Peak memory 215900 kb
Host smart-c3385ecf-d60b-4b81-b7e3-52963dee0106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309830466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2309830466
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.804989651
Short name T686
Test name
Test status
Simulation time 11939627 ps
CPU time 0.71 seconds
Started May 30 01:16:53 PM PDT 24
Finished May 30 01:16:55 PM PDT 24
Peak memory 204916 kb
Host smart-7efb5b09-a9a9-4a85-8471-9ec4f754da21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804989651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.804989651
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3110467469
Short name T489
Test name
Test status
Simulation time 300013517 ps
CPU time 2.42 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:16:56 PM PDT 24
Peak memory 218340 kb
Host smart-e0e5e3c1-d81b-4375-8a6e-119c301710f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110467469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3110467469
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2550475250
Short name T833
Test name
Test status
Simulation time 18179818 ps
CPU time 0.75 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 204900 kb
Host smart-e8e4ced9-510f-4678-873d-0a5d5b4791ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550475250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2550475250
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3936649639
Short name T928
Test name
Test status
Simulation time 13178283291 ps
CPU time 36.77 seconds
Started May 30 01:16:55 PM PDT 24
Finished May 30 01:17:34 PM PDT 24
Peak memory 250724 kb
Host smart-9914d6cc-2b72-4604-9b0f-295eb8d16516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936649639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3936649639
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1040660403
Short name T440
Test name
Test status
Simulation time 3797827391 ps
CPU time 11.5 seconds
Started May 30 01:16:54 PM PDT 24
Finished May 30 01:17:06 PM PDT 24
Peak memory 232472 kb
Host smart-58a95d29-cf40-408d-9267-2f716ea7dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040660403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1040660403
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3909638486
Short name T204
Test name
Test status
Simulation time 1988417638 ps
CPU time 4.38 seconds
Started May 30 01:16:53 PM PDT 24
Finished May 30 01:16:59 PM PDT 24
Peak memory 216484 kb
Host smart-10033e68-2da2-4287-a7eb-6bad48b8cb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909638486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3909638486
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1363841223
Short name T498
Test name
Test status
Simulation time 151713722 ps
CPU time 3.12 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:16:55 PM PDT 24
Peak memory 224180 kb
Host smart-d93115be-98ae-4eed-b6bf-fb636b6b294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363841223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1363841223
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4128021372
Short name T777
Test name
Test status
Simulation time 3516895570 ps
CPU time 4.18 seconds
Started May 30 01:16:53 PM PDT 24
Finished May 30 01:16:58 PM PDT 24
Peak memory 218448 kb
Host smart-6772cf01-6042-4a0f-b529-67fa2f534e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128021372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4128021372
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2629798513
Short name T283
Test name
Test status
Simulation time 9191574786 ps
CPU time 8.22 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:17:01 PM PDT 24
Peak memory 233288 kb
Host smart-3ddf0118-e257-4fef-9a7c-b12e95d4bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629798513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2629798513
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.757920901
Short name T613
Test name
Test status
Simulation time 1206784185 ps
CPU time 5.09 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:16:58 PM PDT 24
Peak memory 222536 kb
Host smart-d9bd5f04-4357-4ca1-8e8d-67f872141852
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=757920901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.757920901
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.379138416
Short name T697
Test name
Test status
Simulation time 122724695431 ps
CPU time 157.45 seconds
Started May 30 01:16:55 PM PDT 24
Finished May 30 01:19:34 PM PDT 24
Peak memory 249932 kb
Host smart-81e1d7b6-a795-4270-ba8a-e4f057fee2e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379138416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.379138416
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1568662199
Short name T328
Test name
Test status
Simulation time 35632404 ps
CPU time 0.71 seconds
Started May 30 01:16:49 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 204968 kb
Host smart-2ef00445-c758-43ff-b048-3464709b9e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568662199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1568662199
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.987678021
Short name T807
Test name
Test status
Simulation time 1292290543 ps
CPU time 7.2 seconds
Started May 30 01:16:55 PM PDT 24
Finished May 30 01:17:04 PM PDT 24
Peak memory 215768 kb
Host smart-d3af5927-e44a-47e8-8ad2-233e45819ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987678021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.987678021
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3203850735
Short name T597
Test name
Test status
Simulation time 54412099 ps
CPU time 2.09 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:16:54 PM PDT 24
Peak memory 215896 kb
Host smart-b4abf8fa-144f-415a-bd37-78085c1f1181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203850735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3203850735
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1221561117
Short name T703
Test name
Test status
Simulation time 161817740 ps
CPU time 0.94 seconds
Started May 30 01:16:49 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 206304 kb
Host smart-5c874700-4b0f-4625-9bd1-d937bcc5c30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221561117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1221561117
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.982633345
Short name T419
Test name
Test status
Simulation time 2044887422 ps
CPU time 5.83 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:17:00 PM PDT 24
Peak memory 233796 kb
Host smart-ebdfafb3-05e3-447e-873f-6075c477794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982633345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.982633345
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4015461611
Short name T950
Test name
Test status
Simulation time 12010632 ps
CPU time 0.72 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 204084 kb
Host smart-9a5047a0-8798-48f7-af3e-2c3ef02eab7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015461611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4015461611
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2519442761
Short name T53
Test name
Test status
Simulation time 732867700 ps
CPU time 4.24 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:09 PM PDT 24
Peak memory 219252 kb
Host smart-68c2a36a-b7b8-424a-959b-174ccd54e6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519442761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2519442761
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1118568113
Short name T426
Test name
Test status
Simulation time 59031613 ps
CPU time 0.76 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:16:54 PM PDT 24
Peak memory 204824 kb
Host smart-1b7fe8e0-fd29-404e-8368-23396d6e6893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118568113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1118568113
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3131127368
Short name T541
Test name
Test status
Simulation time 1611460833 ps
CPU time 11.72 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:18 PM PDT 24
Peak memory 235220 kb
Host smart-eaa8d8cf-1f10-4598-9bf2-dbe2a9e941b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131127368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3131127368
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2221209250
Short name T895
Test name
Test status
Simulation time 6716125169 ps
CPU time 76.82 seconds
Started May 30 01:17:02 PM PDT 24
Finished May 30 01:18:21 PM PDT 24
Peak memory 248988 kb
Host smart-2012e95b-e012-4a43-87a7-0403bd618d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221209250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2221209250
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.6661338
Short name T517
Test name
Test status
Simulation time 15665668237 ps
CPU time 61.38 seconds
Started May 30 01:17:02 PM PDT 24
Finished May 30 01:18:05 PM PDT 24
Peak memory 224320 kb
Host smart-51968a0c-e2d7-40a7-b601-3d01cfc8971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6661338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.6661338
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2280530536
Short name T392
Test name
Test status
Simulation time 4480116824 ps
CPU time 37.63 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:42 PM PDT 24
Peak memory 248844 kb
Host smart-8f00cadf-1be5-4ae4-a986-b09fc51d54e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280530536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2280530536
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.707096925
Short name T503
Test name
Test status
Simulation time 2621018483 ps
CPU time 7.79 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:16:59 PM PDT 24
Peak memory 218628 kb
Host smart-c7a48932-662e-4e40-b98b-d248a6c66177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707096925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.707096925
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.473961779
Short name T54
Test name
Test status
Simulation time 13297369395 ps
CPU time 35.65 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 255616 kb
Host smart-7a0d68b8-eb57-4d8e-aa29-e4e48529ab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473961779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.473961779
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1331602210
Short name T728
Test name
Test status
Simulation time 121368200 ps
CPU time 1.01 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:16:53 PM PDT 24
Peak memory 217440 kb
Host smart-108ce9cc-8352-40fd-90f7-59e8e443e730
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331602210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1331602210
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2104241910
Short name T532
Test name
Test status
Simulation time 32012434 ps
CPU time 2.65 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:16:55 PM PDT 24
Peak memory 220936 kb
Host smart-e704cc58-1a01-4524-a4b4-d293629294a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104241910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2104241910
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.595296277
Short name T252
Test name
Test status
Simulation time 8244079533 ps
CPU time 5.38 seconds
Started May 30 01:16:53 PM PDT 24
Finished May 30 01:16:59 PM PDT 24
Peak memory 217560 kb
Host smart-f9ed5738-3160-4bd3-bbdd-8b1975dcf186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595296277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.595296277
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.488919365
Short name T706
Test name
Test status
Simulation time 2829758606 ps
CPU time 10.68 seconds
Started May 30 01:17:04 PM PDT 24
Finished May 30 01:17:16 PM PDT 24
Peak memory 218836 kb
Host smart-2eec0297-a192-485f-8044-31134155aa63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=488919365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.488919365
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2773055002
Short name T908
Test name
Test status
Simulation time 89227853815 ps
CPU time 295.33 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:22:02 PM PDT 24
Peak memory 257004 kb
Host smart-97d0c2f7-9eb8-4784-8066-473e6f19cc2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773055002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2773055002
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1142419151
Short name T838
Test name
Test status
Simulation time 6402476627 ps
CPU time 17.53 seconds
Started May 30 01:16:55 PM PDT 24
Finished May 30 01:17:14 PM PDT 24
Peak memory 215992 kb
Host smart-af72ef85-5beb-44fb-91ed-8dd02239ba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142419151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1142419151
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3175204382
Short name T699
Test name
Test status
Simulation time 4392840128 ps
CPU time 3.86 seconds
Started May 30 01:16:55 PM PDT 24
Finished May 30 01:17:00 PM PDT 24
Peak memory 215888 kb
Host smart-6e72ded0-686d-4bfc-85a0-17c5b3561d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175204382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3175204382
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4257369095
Short name T57
Test name
Test status
Simulation time 84198996 ps
CPU time 1.85 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:16:55 PM PDT 24
Peak memory 215792 kb
Host smart-a8419fcd-fb28-4ec7-9847-78bd154f976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257369095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4257369095
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.85655826
Short name T350
Test name
Test status
Simulation time 61680736 ps
CPU time 0.96 seconds
Started May 30 01:16:55 PM PDT 24
Finished May 30 01:16:57 PM PDT 24
Peak memory 205288 kb
Host smart-133d32d0-c587-4b07-a618-4147f02ca37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85655826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.85655826
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1180972907
Short name T829
Test name
Test status
Simulation time 1731151294 ps
CPU time 5.11 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:09 PM PDT 24
Peak memory 224220 kb
Host smart-1e752afd-6510-4c7a-a1a4-aa0e613fe00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180972907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1180972907
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1792954722
Short name T612
Test name
Test status
Simulation time 39465556 ps
CPU time 0.73 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 204916 kb
Host smart-ffbbd328-04a3-4aad-9c0b-93488b3f8668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792954722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1792954722
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1899615106
Short name T475
Test name
Test status
Simulation time 73562304 ps
CPU time 2.22 seconds
Started May 30 01:17:07 PM PDT 24
Finished May 30 01:17:10 PM PDT 24
Peak memory 218304 kb
Host smart-ea3305a4-10e0-44bb-a1d5-c7bd05317ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899615106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1899615106
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.71739482
Short name T406
Test name
Test status
Simulation time 68622607 ps
CPU time 0.79 seconds
Started May 30 01:17:04 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 205944 kb
Host smart-d66b2678-9271-402d-ac7d-251572a17ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71739482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.71739482
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2014018191
Short name T366
Test name
Test status
Simulation time 23540544 ps
CPU time 0.74 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 215432 kb
Host smart-dd99256d-d682-45ad-b3b2-594f540ae333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014018191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2014018191
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.77825596
Short name T298
Test name
Test status
Simulation time 19385935327 ps
CPU time 56.14 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:18:02 PM PDT 24
Peak memory 232532 kb
Host smart-1565c92b-ebf1-4b2d-a524-393745cdf88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77825596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.77825596
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.533099351
Short name T198
Test name
Test status
Simulation time 44225690263 ps
CPU time 281.21 seconds
Started May 30 01:17:04 PM PDT 24
Finished May 30 01:21:47 PM PDT 24
Peak memory 255364 kb
Host smart-8f750c31-9e5f-4bef-994c-66de0c013741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533099351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.533099351
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3512374809
Short name T310
Test name
Test status
Simulation time 699971769 ps
CPU time 9.37 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:13 PM PDT 24
Peak memory 232348 kb
Host smart-43233fa3-cc0a-442e-a964-1e3cd535045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512374809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3512374809
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.382130201
Short name T799
Test name
Test status
Simulation time 844123977 ps
CPU time 9.56 seconds
Started May 30 01:17:06 PM PDT 24
Finished May 30 01:17:17 PM PDT 24
Peak memory 233308 kb
Host smart-5fc04ca6-b4a2-4f42-a8d8-ae7d45f3eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382130201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.382130201
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1003900284
Short name T264
Test name
Test status
Simulation time 6472656484 ps
CPU time 62.27 seconds
Started May 30 01:17:02 PM PDT 24
Finished May 30 01:18:06 PM PDT 24
Peak memory 227180 kb
Host smart-d809290b-8f2a-4da0-9b4f-ec12d9cc4259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003900284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1003900284
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.337801949
Short name T644
Test name
Test status
Simulation time 121850731 ps
CPU time 1.09 seconds
Started May 30 01:17:08 PM PDT 24
Finished May 30 01:17:10 PM PDT 24
Peak memory 216224 kb
Host smart-5a36e258-77a9-4818-97ba-af10224ec990
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337801949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.337801949
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.382774004
Short name T937
Test name
Test status
Simulation time 744230724 ps
CPU time 4.38 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:10 PM PDT 24
Peak memory 233380 kb
Host smart-3e693205-669c-4e5f-8991-a8f3fbc147de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382774004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.382774004
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2002871120
Short name T242
Test name
Test status
Simulation time 684473456 ps
CPU time 4.23 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:09 PM PDT 24
Peak memory 218212 kb
Host smart-72d5d7d1-1224-403c-a890-097a431d1368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002871120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2002871120
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1680942733
Short name T500
Test name
Test status
Simulation time 3917114543 ps
CPU time 8.35 seconds
Started May 30 01:17:01 PM PDT 24
Finished May 30 01:17:11 PM PDT 24
Peak memory 220616 kb
Host smart-8b0bd454-fdc4-4e76-acb2-079654016888
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1680942733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1680942733
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2780742691
Short name T978
Test name
Test status
Simulation time 34421636 ps
CPU time 0.93 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 205972 kb
Host smart-77a9a689-6879-40d7-b84d-ed49046be521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780742691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2780742691
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2446783668
Short name T846
Test name
Test status
Simulation time 6684547704 ps
CPU time 9.61 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:14 PM PDT 24
Peak memory 215996 kb
Host smart-90c4d832-9dda-42f2-8135-15c60590d8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446783668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2446783668
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3134500564
Short name T624
Test name
Test status
Simulation time 15652010212 ps
CPU time 20.7 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 215916 kb
Host smart-e2999c37-4127-43bc-9508-ecc5ceca51bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134500564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3134500564
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2907595259
Short name T650
Test name
Test status
Simulation time 22207158 ps
CPU time 0.92 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 206572 kb
Host smart-c12d483e-6b31-4450-b817-d8ac10473155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907595259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2907595259
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1317332811
Short name T622
Test name
Test status
Simulation time 62997716 ps
CPU time 0.93 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 205768 kb
Host smart-7ba11a57-3cfd-41fe-aaec-c2e4009e350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317332811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1317332811
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4204269685
Short name T967
Test name
Test status
Simulation time 3900354354 ps
CPU time 15.54 seconds
Started May 30 01:17:06 PM PDT 24
Finished May 30 01:17:23 PM PDT 24
Peak memory 218840 kb
Host smart-7fa1bc38-bcad-4304-8a5b-046d8a447920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204269685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4204269685
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.443544598
Short name T659
Test name
Test status
Simulation time 10700048 ps
CPU time 0.67 seconds
Started May 30 01:17:06 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 205244 kb
Host smart-b4aaf1a9-4ef4-492f-bdaa-e703feefc84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443544598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.443544598
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2320734389
Short name T765
Test name
Test status
Simulation time 144295531 ps
CPU time 2.86 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:10 PM PDT 24
Peak memory 218468 kb
Host smart-ad90e99a-bc75-4e5c-ae1a-942faf539689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320734389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2320734389
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1814402322
Short name T502
Test name
Test status
Simulation time 17621360 ps
CPU time 0.84 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 205884 kb
Host smart-e019e1d1-0a31-47a7-b2e7-d85697dfd1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814402322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1814402322
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.675594013
Short name T623
Test name
Test status
Simulation time 6412029194 ps
CPU time 28.28 seconds
Started May 30 01:17:06 PM PDT 24
Finished May 30 01:17:36 PM PDT 24
Peak memory 240632 kb
Host smart-68382bc4-6910-44c6-a142-879c1d41c617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675594013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.675594013
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1245058855
Short name T916
Test name
Test status
Simulation time 6246422033 ps
CPU time 39.77 seconds
Started May 30 01:17:06 PM PDT 24
Finished May 30 01:17:47 PM PDT 24
Peak memory 249340 kb
Host smart-c5bd0eb7-3fc2-4b1d-833f-ff4555bdf1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245058855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1245058855
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2598623644
Short name T303
Test name
Test status
Simulation time 20701642740 ps
CPU time 54.48 seconds
Started May 30 01:17:02 PM PDT 24
Finished May 30 01:17:58 PM PDT 24
Peak memory 252236 kb
Host smart-5bba1000-9e8b-4ae7-9ecf-a304afaef822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598623644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2598623644
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2436408477
Short name T276
Test name
Test status
Simulation time 1776507491 ps
CPU time 8.36 seconds
Started May 30 01:17:04 PM PDT 24
Finished May 30 01:17:13 PM PDT 24
Peak memory 219436 kb
Host smart-38badab5-2699-43db-8efb-bb5981d974c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436408477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2436408477
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2088128122
Short name T481
Test name
Test status
Simulation time 110843277 ps
CPU time 1.93 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:06 PM PDT 24
Peak memory 215724 kb
Host smart-ff6ff47c-753b-47d5-9ff2-d3bab263e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088128122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2088128122
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.97053733
Short name T657
Test name
Test status
Simulation time 48398602 ps
CPU time 1.09 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:08 PM PDT 24
Peak memory 216116 kb
Host smart-3a09cba1-2373-4bc2-92be-6590dbc9a427
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97053733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.97053733
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4003379993
Short name T492
Test name
Test status
Simulation time 5968392422 ps
CPU time 8.78 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:12 PM PDT 24
Peak memory 232416 kb
Host smart-076d8932-e97b-4457-9ca6-e8042b8488f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003379993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4003379993
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2716349249
Short name T723
Test name
Test status
Simulation time 563692876 ps
CPU time 2.77 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 218284 kb
Host smart-c15d0bde-3dbd-4087-ab62-e917f48eb8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716349249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2716349249
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3084114240
Short name T39
Test name
Test status
Simulation time 1570455542 ps
CPU time 18.34 seconds
Started May 30 01:17:06 PM PDT 24
Finished May 30 01:17:26 PM PDT 24
Peak memory 222656 kb
Host smart-a03bbba9-6a9c-481c-b2f6-cb3084c8167e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3084114240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3084114240
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.566020216
Short name T487
Test name
Test status
Simulation time 16799451581 ps
CPU time 21.69 seconds
Started May 30 01:17:02 PM PDT 24
Finished May 30 01:17:25 PM PDT 24
Peak memory 216028 kb
Host smart-714feb76-791c-4164-81d2-5e71e621d460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566020216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.566020216
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4103359835
Short name T740
Test name
Test status
Simulation time 5827892676 ps
CPU time 16.54 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:21 PM PDT 24
Peak memory 215884 kb
Host smart-fd08c036-0e22-4988-aef5-06bb75b01136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103359835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4103359835
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.479364181
Short name T712
Test name
Test status
Simulation time 205659493 ps
CPU time 1.15 seconds
Started May 30 01:17:03 PM PDT 24
Finished May 30 01:17:06 PM PDT 24
Peak memory 207664 kb
Host smart-ce312484-8c3c-4caf-932b-bd7f9971ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479364181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.479364181
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2693325144
Short name T616
Test name
Test status
Simulation time 17196005 ps
CPU time 0.73 seconds
Started May 30 01:17:01 PM PDT 24
Finished May 30 01:17:03 PM PDT 24
Peak memory 205256 kb
Host smart-feffab83-8f4a-433b-bdce-15a1e3ec803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693325144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2693325144
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.969167377
Short name T661
Test name
Test status
Simulation time 123097222 ps
CPU time 3.01 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:09 PM PDT 24
Peak memory 218676 kb
Host smart-73d64eec-f54c-4fda-8a50-e2f38ff1274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969167377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.969167377
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2937592646
Short name T837
Test name
Test status
Simulation time 14172617 ps
CPU time 0.72 seconds
Started May 30 01:17:26 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 204864 kb
Host smart-23659c9a-e107-46de-969c-52078885a0c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937592646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2937592646
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2511328158
Short name T796
Test name
Test status
Simulation time 46975550 ps
CPU time 0.74 seconds
Started May 30 01:17:09 PM PDT 24
Finished May 30 01:17:11 PM PDT 24
Peak memory 205212 kb
Host smart-59974579-60a5-4bf1-b84e-8683eeb9b81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511328158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2511328158
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.259078298
Short name T668
Test name
Test status
Simulation time 35234705688 ps
CPU time 143.98 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:19:46 PM PDT 24
Peak memory 249008 kb
Host smart-df623605-23f0-46e9-8b4e-600b6aaf8bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259078298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.259078298
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2758433223
Short name T195
Test name
Test status
Simulation time 42172769619 ps
CPU time 164.64 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:20:06 PM PDT 24
Peak memory 257092 kb
Host smart-a0e3d2f9-317b-4510-bf94-80d30a3b2dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758433223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2758433223
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3671657204
Short name T437
Test name
Test status
Simulation time 33392236256 ps
CPU time 201.39 seconds
Started May 30 01:17:22 PM PDT 24
Finished May 30 01:20:45 PM PDT 24
Peak memory 255652 kb
Host smart-3cbf6610-d86a-4fed-b2ac-26d4424eb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671657204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3671657204
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1963327442
Short name T558
Test name
Test status
Simulation time 468455213 ps
CPU time 7.41 seconds
Started May 30 01:17:19 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 232400 kb
Host smart-ac6f1915-2246-4e32-9fe6-50d1301770ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963327442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1963327442
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1078286601
Short name T369
Test name
Test status
Simulation time 113443396 ps
CPU time 1.96 seconds
Started May 30 01:17:06 PM PDT 24
Finished May 30 01:17:09 PM PDT 24
Peak memory 215716 kb
Host smart-2a3ee866-ace2-470d-8378-bdad0d9490ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078286601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1078286601
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3077008806
Short name T960
Test name
Test status
Simulation time 454299926 ps
CPU time 4.54 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:26 PM PDT 24
Peak memory 224204 kb
Host smart-1b9521d5-a020-417f-83e0-bafb5f2ceb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077008806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3077008806
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3466727974
Short name T22
Test name
Test status
Simulation time 42088325 ps
CPU time 1.02 seconds
Started May 30 01:17:09 PM PDT 24
Finished May 30 01:17:12 PM PDT 24
Peak memory 216188 kb
Host smart-ba7febcd-8174-4a20-894a-097698c46b3d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466727974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3466727974
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1839995915
Short name T218
Test name
Test status
Simulation time 1135475520 ps
CPU time 8.33 seconds
Started May 30 01:17:04 PM PDT 24
Finished May 30 01:17:14 PM PDT 24
Peak memory 232140 kb
Host smart-cea86de9-0437-4c7b-85b3-0ed55b3cb296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839995915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1839995915
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1752740517
Short name T516
Test name
Test status
Simulation time 1110545000 ps
CPU time 6.82 seconds
Started May 30 01:17:09 PM PDT 24
Finished May 30 01:17:17 PM PDT 24
Peak memory 238164 kb
Host smart-3e070f2d-ea10-4a86-9d56-53a6baff80be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752740517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1752740517
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2189529305
Short name T506
Test name
Test status
Simulation time 2047562005 ps
CPU time 12.12 seconds
Started May 30 01:17:22 PM PDT 24
Finished May 30 01:17:36 PM PDT 24
Peak memory 219988 kb
Host smart-2b902d0e-3255-43b5-ad3e-ccbe287839b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2189529305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2189529305
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.697453516
Short name T860
Test name
Test status
Simulation time 14876936373 ps
CPU time 20.4 seconds
Started May 30 01:17:04 PM PDT 24
Finished May 30 01:17:26 PM PDT 24
Peak memory 215980 kb
Host smart-66cc541d-f6b3-4224-b7c1-1d6fd6c272d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697453516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.697453516
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.659919284
Short name T371
Test name
Test status
Simulation time 15981521948 ps
CPU time 6.28 seconds
Started May 30 01:17:09 PM PDT 24
Finished May 30 01:17:17 PM PDT 24
Peak memory 215884 kb
Host smart-aed11067-bd05-4efa-83c9-d5903bc47ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659919284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.659919284
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.552734792
Short name T605
Test name
Test status
Simulation time 137059831 ps
CPU time 2.71 seconds
Started May 30 01:17:04 PM PDT 24
Finished May 30 01:17:09 PM PDT 24
Peak memory 215880 kb
Host smart-93d33950-a31d-4c40-b655-ee9b839e9110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552734792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.552734792
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.551468776
Short name T556
Test name
Test status
Simulation time 39817142 ps
CPU time 0.82 seconds
Started May 30 01:17:05 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 205272 kb
Host smart-59f09538-20ed-4f71-8eb2-1968fc9844d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551468776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.551468776
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3549289403
Short name T577
Test name
Test status
Simulation time 2234543330 ps
CPU time 6.27 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:31 PM PDT 24
Peak memory 216764 kb
Host smart-c1fe2499-eb99-4621-868f-63db01a6042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549289403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3549289403
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3554903568
Short name T677
Test name
Test status
Simulation time 21229570 ps
CPU time 0.72 seconds
Started May 30 01:17:30 PM PDT 24
Finished May 30 01:17:31 PM PDT 24
Peak memory 204916 kb
Host smart-34092a04-9c22-4a8d-a61c-b86054cbfaf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554903568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3554903568
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2328586798
Short name T260
Test name
Test status
Simulation time 664483408 ps
CPU time 7.04 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:17:35 PM PDT 24
Peak memory 233188 kb
Host smart-112b8dbf-4831-4e8b-9476-c14991fe5f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328586798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2328586798
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.145977891
Short name T368
Test name
Test status
Simulation time 50107029 ps
CPU time 0.77 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:17:29 PM PDT 24
Peak memory 205868 kb
Host smart-10ae036a-acf3-488a-b4f7-8a84de1308be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145977891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.145977891
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.698391748
Short name T600
Test name
Test status
Simulation time 17843619872 ps
CPU time 139.18 seconds
Started May 30 01:17:24 PM PDT 24
Finished May 30 01:19:45 PM PDT 24
Peak memory 254348 kb
Host smart-033c5aae-3ba0-462c-9b5d-893edd6d7c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698391748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.698391748
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2584993525
Short name T625
Test name
Test status
Simulation time 316146289 ps
CPU time 9.2 seconds
Started May 30 01:17:28 PM PDT 24
Finished May 30 01:17:39 PM PDT 24
Peak memory 232332 kb
Host smart-8e6ab58c-6122-4c2c-ac33-19d4ef3102b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584993525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2584993525
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4224190926
Short name T756
Test name
Test status
Simulation time 14951235720 ps
CPU time 7.05 seconds
Started May 30 01:17:26 PM PDT 24
Finished May 30 01:17:35 PM PDT 24
Peak memory 218064 kb
Host smart-e42c15d1-56ed-4f51-9d0f-c678fdc26ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224190926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4224190926
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2510758149
Short name T52
Test name
Test status
Simulation time 2904261087 ps
CPU time 18.99 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:41 PM PDT 24
Peak memory 250256 kb
Host smart-ad38273a-c5a8-480c-8897-1963e6303b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510758149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2510758149
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2199371649
Short name T790
Test name
Test status
Simulation time 29110614 ps
CPU time 0.97 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:23 PM PDT 24
Peak memory 217416 kb
Host smart-709f3fa7-632b-46ad-b250-0aa65fcf94c9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199371649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2199371649
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1788894211
Short name T33
Test name
Test status
Simulation time 1033318312 ps
CPU time 6.97 seconds
Started May 30 01:17:24 PM PDT 24
Finished May 30 01:17:33 PM PDT 24
Peak memory 233464 kb
Host smart-ae255607-cf31-4c39-be1e-9b6631c68a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788894211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1788894211
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2349282070
Short name T521
Test name
Test status
Simulation time 2249503099 ps
CPU time 5.58 seconds
Started May 30 01:17:30 PM PDT 24
Finished May 30 01:17:37 PM PDT 24
Peak memory 233420 kb
Host smart-30340867-34a0-4e07-abe4-7b1bb12c4308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349282070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2349282070
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3055973058
Short name T5
Test name
Test status
Simulation time 1097044814 ps
CPU time 11.07 seconds
Started May 30 01:17:31 PM PDT 24
Finished May 30 01:17:43 PM PDT 24
Peak memory 221324 kb
Host smart-ae43a823-fac4-4843-b910-1a2c684408e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3055973058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3055973058
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.554352571
Short name T751
Test name
Test status
Simulation time 612224814 ps
CPU time 7.34 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:17:36 PM PDT 24
Peak memory 215840 kb
Host smart-19059c69-ec09-420d-b427-dc2192710140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554352571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.554352571
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.517427973
Short name T824
Test name
Test status
Simulation time 8571636348 ps
CPU time 6.38 seconds
Started May 30 01:17:25 PM PDT 24
Finished May 30 01:17:33 PM PDT 24
Peak memory 215908 kb
Host smart-58503288-0d84-4248-b777-8005a2bb7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517427973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.517427973
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.260403750
Short name T407
Test name
Test status
Simulation time 199149907 ps
CPU time 4.97 seconds
Started May 30 01:17:28 PM PDT 24
Finished May 30 01:17:35 PM PDT 24
Peak memory 215884 kb
Host smart-dfbd3141-a7e5-419d-a493-ff05ef737627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260403750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.260403750
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3467484802
Short name T430
Test name
Test status
Simulation time 71594859 ps
CPU time 0.72 seconds
Started May 30 01:17:25 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 205288 kb
Host smart-866a044d-792a-4e7e-bd1d-e6043c05b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467484802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3467484802
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4014640513
Short name T946
Test name
Test status
Simulation time 9933388524 ps
CPU time 6.32 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:31 PM PDT 24
Peak memory 218764 kb
Host smart-71c75965-dd78-4a97-94c9-b63310a061c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014640513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4014640513
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.149019537
Short name T631
Test name
Test status
Simulation time 32603440 ps
CPU time 2.21 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:24 PM PDT 24
Peak memory 220684 kb
Host smart-ef108409-0e71-4278-bb7b-7fb93e5861ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149019537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.149019537
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.299033270
Short name T387
Test name
Test status
Simulation time 61701477 ps
CPU time 0.79 seconds
Started May 30 01:17:25 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 205944 kb
Host smart-dba323ae-99c4-4bbf-be64-e1408e424a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299033270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.299033270
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1769102836
Short name T770
Test name
Test status
Simulation time 21098259157 ps
CPU time 40.01 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:18:08 PM PDT 24
Peak memory 240568 kb
Host smart-4b55e943-8e68-4ddf-8bdf-f6d4f60841f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769102836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1769102836
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2624446158
Short name T215
Test name
Test status
Simulation time 26825411307 ps
CPU time 168.04 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:20:17 PM PDT 24
Peak memory 237168 kb
Host smart-7efeba5d-50d7-4925-a7fd-333dccfd6981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624446158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2624446158
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2034818968
Short name T550
Test name
Test status
Simulation time 1547775878 ps
CPU time 15.2 seconds
Started May 30 01:17:28 PM PDT 24
Finished May 30 01:17:45 PM PDT 24
Peak memory 232280 kb
Host smart-0e5862d2-fb73-4b92-bf63-f5ffe8a6e2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034818968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2034818968
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.188755010
Short name T818
Test name
Test status
Simulation time 326183005 ps
CPU time 4.85 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:29 PM PDT 24
Peak memory 224132 kb
Host smart-4a127ec7-7355-4c43-b276-1fcd9de1dff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188755010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.188755010
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.807297325
Short name T461
Test name
Test status
Simulation time 34879815963 ps
CPU time 20.95 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:17:50 PM PDT 24
Peak memory 218116 kb
Host smart-f3e0141f-e100-49a8-bdb6-1f35b50c4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807297325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.807297325
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2186974875
Short name T738
Test name
Test status
Simulation time 346127776 ps
CPU time 1.02 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:17:29 PM PDT 24
Peak memory 217376 kb
Host smart-87a5ac90-7383-465f-9687-57c492a520cf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186974875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2186974875
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1627992780
Short name T969
Test name
Test status
Simulation time 3762978410 ps
CPU time 13.4 seconds
Started May 30 01:17:19 PM PDT 24
Finished May 30 01:17:34 PM PDT 24
Peak memory 239932 kb
Host smart-75d9e567-36c5-4b0c-a461-84d8a3117fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627992780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1627992780
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.364822740
Short name T527
Test name
Test status
Simulation time 172503912 ps
CPU time 3.19 seconds
Started May 30 01:17:28 PM PDT 24
Finished May 30 01:17:33 PM PDT 24
Peak memory 218392 kb
Host smart-c5068ddf-beff-4c96-ad7a-379d80a6349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364822740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.364822740
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3158447145
Short name T635
Test name
Test status
Simulation time 4993444582 ps
CPU time 10.82 seconds
Started May 30 01:17:28 PM PDT 24
Finished May 30 01:17:41 PM PDT 24
Peak memory 220208 kb
Host smart-5d27b189-02ed-47bf-841c-f1c62ab3fdfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3158447145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3158447145
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1023162235
Short name T156
Test name
Test status
Simulation time 11146004384 ps
CPU time 70.24 seconds
Started May 30 01:17:29 PM PDT 24
Finished May 30 01:18:40 PM PDT 24
Peak memory 240692 kb
Host smart-f06bf31f-f35a-4d44-bf1a-0b7f8ee83578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023162235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1023162235
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1668761603
Short name T320
Test name
Test status
Simulation time 1925553211 ps
CPU time 22.68 seconds
Started May 30 01:17:26 PM PDT 24
Finished May 30 01:17:50 PM PDT 24
Peak memory 219600 kb
Host smart-598cb627-93c7-4d8b-b797-a316f35da113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668761603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1668761603
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2627150272
Short name T389
Test name
Test status
Simulation time 3850589386 ps
CPU time 4.88 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:29 PM PDT 24
Peak memory 215848 kb
Host smart-2a7dc433-6b04-4831-ab7a-8967c63b2991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627150272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2627150272
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.711778928
Short name T384
Test name
Test status
Simulation time 88078108 ps
CPU time 4.59 seconds
Started May 30 01:17:26 PM PDT 24
Finished May 30 01:17:32 PM PDT 24
Peak memory 216060 kb
Host smart-a9f25a65-d2d4-40c4-a7ce-f2a259c13acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711778928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.711778928
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.623161725
Short name T802
Test name
Test status
Simulation time 13897880 ps
CPU time 0.71 seconds
Started May 30 01:17:26 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 204940 kb
Host smart-6b6e6fe7-ca1c-4f5e-9ccb-a5319f1f6f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623161725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.623161725
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3545315332
Short name T263
Test name
Test status
Simulation time 3230462650 ps
CPU time 5.62 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:30 PM PDT 24
Peak memory 221672 kb
Host smart-5f984b8c-88e0-4b24-bc42-ef43faff5df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545315332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3545315332
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2580798041
Short name T955
Test name
Test status
Simulation time 30461519 ps
CPU time 0.7 seconds
Started May 30 01:17:22 PM PDT 24
Finished May 30 01:17:24 PM PDT 24
Peak memory 205180 kb
Host smart-6f25c862-edfe-4d22-a13f-5702817dab1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580798041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2580798041
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.970350094
Short name T397
Test name
Test status
Simulation time 137218761 ps
CPU time 2.59 seconds
Started May 30 01:17:21 PM PDT 24
Finished May 30 01:17:25 PM PDT 24
Peak memory 233856 kb
Host smart-6eb91079-261c-4198-97c3-32e619a8f0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970350094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.970350094
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3936368594
Short name T347
Test name
Test status
Simulation time 37364416 ps
CPU time 0.78 seconds
Started May 30 01:17:29 PM PDT 24
Finished May 30 01:17:31 PM PDT 24
Peak memory 205924 kb
Host smart-895911ca-d594-4670-90c3-d92f0e80113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936368594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3936368594
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2054756750
Short name T171
Test name
Test status
Simulation time 19181293641 ps
CPU time 66.02 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:18:31 PM PDT 24
Peak memory 238312 kb
Host smart-21090edc-c818-4f6a-8775-d4a0f21e2d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054756750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2054756750
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.19762255
Short name T905
Test name
Test status
Simulation time 65437659743 ps
CPU time 112.36 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:19:14 PM PDT 24
Peak memory 256984 kb
Host smart-b6200a2d-2e66-4a17-b0ad-ddba41b94eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19762255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.19762255
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3566444252
Short name T509
Test name
Test status
Simulation time 123738994134 ps
CPU time 127.49 seconds
Started May 30 01:17:22 PM PDT 24
Finished May 30 01:19:31 PM PDT 24
Peak memory 248988 kb
Host smart-8ddbcd3b-27b3-42cc-8eea-e349a8fd8ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566444252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3566444252
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1966270372
Short name T309
Test name
Test status
Simulation time 217214879 ps
CPU time 7.14 seconds
Started May 30 01:17:26 PM PDT 24
Finished May 30 01:17:35 PM PDT 24
Peak memory 232400 kb
Host smart-f4667acd-91db-4c85-a0ed-d841fdbbf2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966270372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1966270372
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2306928616
Short name T591
Test name
Test status
Simulation time 7719321029 ps
CPU time 18.1 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:40 PM PDT 24
Peak memory 233624 kb
Host smart-dc859451-f1a8-4b29-924f-f383a165f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306928616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2306928616
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.805456185
Short name T344
Test name
Test status
Simulation time 566625256 ps
CPU time 3.72 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 234000 kb
Host smart-4deb412c-ead2-4395-984d-38b3574679a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805456185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.805456185
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4263727266
Short name T704
Test name
Test status
Simulation time 73321175 ps
CPU time 1.09 seconds
Started May 30 01:17:24 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 216188 kb
Host smart-c9d07c86-3f6c-4b4e-a25e-ce8220369ef2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263727266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4263727266
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3502030642
Short name T393
Test name
Test status
Simulation time 30265908 ps
CPU time 2.27 seconds
Started May 30 01:17:19 PM PDT 24
Finished May 30 01:17:22 PM PDT 24
Peak memory 232416 kb
Host smart-da5fa6fd-0792-47c3-b949-12318249fe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502030642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3502030642
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1502345062
Short name T188
Test name
Test status
Simulation time 9013899174 ps
CPU time 10.44 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:35 PM PDT 24
Peak memory 233524 kb
Host smart-f47e72f5-283a-4cc3-bde4-4dd3309abff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502345062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1502345062
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1109928008
Short name T520
Test name
Test status
Simulation time 278174463 ps
CPU time 5.51 seconds
Started May 30 01:17:21 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 222616 kb
Host smart-1327379e-db42-4452-890f-afd3d2cb1cbb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109928008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1109928008
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.136414125
Short name T65
Test name
Test status
Simulation time 439503943 ps
CPU time 1.04 seconds
Started May 30 01:17:19 PM PDT 24
Finished May 30 01:17:21 PM PDT 24
Peak memory 206108 kb
Host smart-e8e1ca2c-a2e6-4724-9638-2fce55b27553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136414125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.136414125
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.666852947
Short name T945
Test name
Test status
Simulation time 21124815684 ps
CPU time 29.57 seconds
Started May 30 01:17:25 PM PDT 24
Finished May 30 01:17:56 PM PDT 24
Peak memory 215988 kb
Host smart-589106f8-5d50-4221-8215-02a9be46c479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666852947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.666852947
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2825580490
Short name T766
Test name
Test status
Simulation time 360067365 ps
CPU time 2.18 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 215824 kb
Host smart-c715e182-4eb6-49c3-8b23-c0e236f5c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825580490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2825580490
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3782494600
Short name T326
Test name
Test status
Simulation time 308742498 ps
CPU time 3.1 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 215936 kb
Host smart-91727aca-32cc-4cf1-967d-0d93b88eaa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782494600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3782494600
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2302926299
Short name T358
Test name
Test status
Simulation time 54758294 ps
CPU time 0.76 seconds
Started May 30 01:17:19 PM PDT 24
Finished May 30 01:17:21 PM PDT 24
Peak memory 205216 kb
Host smart-42e5a897-3d39-4163-9616-539f0255f4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302926299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2302926299
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2587487996
Short name T655
Test name
Test status
Simulation time 589276287 ps
CPU time 9.95 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:31 PM PDT 24
Peak memory 250092 kb
Host smart-ed475f63-4889-4e95-82f8-9cb00901e2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587487996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2587487996
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.117874608
Short name T761
Test name
Test status
Simulation time 12009254 ps
CPU time 0.73 seconds
Started May 30 01:17:26 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 204892 kb
Host smart-c8257776-5641-40c9-8ff4-ff281d4bac6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117874608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.117874608
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.205898702
Short name T74
Test name
Test status
Simulation time 915630752 ps
CPU time 3.99 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:26 PM PDT 24
Peak memory 219232 kb
Host smart-97338c09-24c2-47cb-93b8-ed8970b2c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205898702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.205898702
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2327826136
Short name T534
Test name
Test status
Simulation time 49728333 ps
CPU time 0.76 seconds
Started May 30 01:17:21 PM PDT 24
Finished May 30 01:17:23 PM PDT 24
Peak memory 205928 kb
Host smart-dc613f5a-7475-4cf3-b0fb-480a62a772b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327826136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2327826136
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1313749327
Short name T77
Test name
Test status
Simulation time 2678846664 ps
CPU time 55.48 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:18:17 PM PDT 24
Peak memory 252300 kb
Host smart-4421d6b3-17ad-418f-8758-a957b959b9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313749327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1313749327
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1006882125
Short name T233
Test name
Test status
Simulation time 118971744132 ps
CPU time 271.12 seconds
Started May 30 01:17:21 PM PDT 24
Finished May 30 01:21:54 PM PDT 24
Peak memory 250556 kb
Host smart-0aa497fb-43e6-479a-b7a1-b154d84edddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006882125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1006882125
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4210935243
Short name T800
Test name
Test status
Simulation time 493668101 ps
CPU time 7.54 seconds
Started May 30 01:17:27 PM PDT 24
Finished May 30 01:17:36 PM PDT 24
Peak memory 238964 kb
Host smart-4c19a805-783b-4c4e-bb04-1f21a069803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210935243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4210935243
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3541278541
Short name T662
Test name
Test status
Simulation time 1363773883 ps
CPU time 10 seconds
Started May 30 01:17:23 PM PDT 24
Finished May 30 01:17:34 PM PDT 24
Peak memory 236656 kb
Host smart-fae357e7-f22a-440b-b5a2-dd759bcc04ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541278541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3541278541
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3706195462
Short name T811
Test name
Test status
Simulation time 9792386353 ps
CPU time 38.67 seconds
Started May 30 01:17:24 PM PDT 24
Finished May 30 01:18:04 PM PDT 24
Peak memory 233904 kb
Host smart-bc4e35aa-c444-427a-b12e-6008b59f9601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706195462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3706195462
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2595970524
Short name T764
Test name
Test status
Simulation time 211823663 ps
CPU time 1.05 seconds
Started May 30 01:17:19 PM PDT 24
Finished May 30 01:17:21 PM PDT 24
Peak memory 216188 kb
Host smart-669d52f5-ca78-484e-99cc-3d31df0ac4bc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595970524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2595970524
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2761360844
Short name T608
Test name
Test status
Simulation time 1445600047 ps
CPU time 5.03 seconds
Started May 30 01:17:21 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 217568 kb
Host smart-b7f45f6f-ecb4-4c54-b58d-bae1bfda4b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761360844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2761360844
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2015049539
Short name T942
Test name
Test status
Simulation time 754163709 ps
CPU time 9.27 seconds
Started May 30 01:17:28 PM PDT 24
Finished May 30 01:17:38 PM PDT 24
Peak memory 219616 kb
Host smart-e5a09552-c7a0-4812-897a-40d6dd12c176
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2015049539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2015049539
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4190949662
Short name T404
Test name
Test status
Simulation time 211522809 ps
CPU time 1.78 seconds
Started May 30 01:17:25 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 216112 kb
Host smart-d926feb7-567b-4011-b27f-46017522f8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190949662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4190949662
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.721975057
Short name T923
Test name
Test status
Simulation time 20402462 ps
CPU time 0.71 seconds
Started May 30 01:17:21 PM PDT 24
Finished May 30 01:17:23 PM PDT 24
Peak memory 204928 kb
Host smart-7e34c68e-029a-4121-84d1-6d9e9e611d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721975057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.721975057
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3582284345
Short name T739
Test name
Test status
Simulation time 32752505 ps
CPU time 1.16 seconds
Started May 30 01:17:28 PM PDT 24
Finished May 30 01:17:31 PM PDT 24
Peak memory 206540 kb
Host smart-9043792c-e0d6-44f3-981a-563f1afb0642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582284345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3582284345
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1710766871
Short name T966
Test name
Test status
Simulation time 37525913 ps
CPU time 0.74 seconds
Started May 30 01:17:22 PM PDT 24
Finished May 30 01:17:24 PM PDT 24
Peak memory 205272 kb
Host smart-859ca052-eb4d-4173-9536-7c7c67703bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710766871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1710766871
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2919254323
Short name T373
Test name
Test status
Simulation time 26305037370 ps
CPU time 12.19 seconds
Started May 30 01:17:22 PM PDT 24
Finished May 30 01:17:36 PM PDT 24
Peak memory 225536 kb
Host smart-f6b9b777-6e15-42c9-8dd1-1eca4ed0c504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919254323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2919254323
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.718767073
Short name T786
Test name
Test status
Simulation time 13510330 ps
CPU time 0.76 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:17:43 PM PDT 24
Peak memory 204244 kb
Host smart-a147491b-2e14-4e1a-8e8e-119545fcea08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718767073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.718767073
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2477694673
Short name T87
Test name
Test status
Simulation time 379110178 ps
CPU time 5.28 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:51 PM PDT 24
Peak memory 234116 kb
Host smart-3504c774-6eb7-439c-86be-a6fefed03a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477694673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2477694673
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3497000779
Short name T762
Test name
Test status
Simulation time 34533940 ps
CPU time 0.79 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:22 PM PDT 24
Peak memory 205948 kb
Host smart-2f9413cb-371c-4516-8854-fe02a01f4299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497000779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3497000779
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.730538722
Short name T763
Test name
Test status
Simulation time 9051073509 ps
CPU time 97.46 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:19:23 PM PDT 24
Peak memory 250872 kb
Host smart-1e68b4d4-6076-47ad-94e6-eb9062a633cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730538722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.730538722
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3811030313
Short name T823
Test name
Test status
Simulation time 3480131386 ps
CPU time 11.39 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:56 PM PDT 24
Peak memory 236596 kb
Host smart-57186b66-312c-4c15-9815-9eac5c847ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811030313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3811030313
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.4145764836
Short name T229
Test name
Test status
Simulation time 31310070937 ps
CPU time 295.03 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:22:38 PM PDT 24
Peak memory 257264 kb
Host smart-bdf0857a-38b9-4f0e-a6ee-9960a39d9820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145764836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.4145764836
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.34977647
Short name T342
Test name
Test status
Simulation time 9172852534 ps
CPU time 22.13 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:18:06 PM PDT 24
Peak memory 232436 kb
Host smart-3403df33-09e4-4a30-aab1-ec71df341af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34977647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.34977647
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3354256838
Short name T581
Test name
Test status
Simulation time 333899281 ps
CPU time 4.96 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 224044 kb
Host smart-ff89dc9f-07ff-4aeb-927d-6098b1be5823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354256838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3354256838
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.307112233
Short name T717
Test name
Test status
Simulation time 20545290833 ps
CPU time 93.21 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:19:19 PM PDT 24
Peak memory 233200 kb
Host smart-f2356a15-dea7-42d2-b70a-3d5d891d9c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307112233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.307112233
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4011071665
Short name T672
Test name
Test status
Simulation time 105279334 ps
CPU time 1.09 seconds
Started May 30 01:17:26 PM PDT 24
Finished May 30 01:17:29 PM PDT 24
Peak memory 217464 kb
Host smart-7d77d5d8-ebdf-4b83-bb97-40d9ec80eabb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011071665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4011071665
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3585741367
Short name T888
Test name
Test status
Simulation time 61916675914 ps
CPU time 20.35 seconds
Started May 30 01:17:41 PM PDT 24
Finished May 30 01:18:02 PM PDT 24
Peak memory 219360 kb
Host smart-a2a11b5c-99b1-4e07-9d9f-780970ad2809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585741367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3585741367
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2721240072
Short name T464
Test name
Test status
Simulation time 1626852066 ps
CPU time 5.13 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:50 PM PDT 24
Peak memory 219252 kb
Host smart-b1cf9a2a-083f-4a7c-96ff-011a4e8e8a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721240072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2721240072
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.784321512
Short name T615
Test name
Test status
Simulation time 969659470 ps
CPU time 5.73 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:51 PM PDT 24
Peak memory 222408 kb
Host smart-f62d3f59-8daa-4cd8-9422-272775db5e4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=784321512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.784321512
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.256830521
Short name T385
Test name
Test status
Simulation time 5767055036 ps
CPU time 9.07 seconds
Started May 30 01:17:22 PM PDT 24
Finished May 30 01:17:32 PM PDT 24
Peak memory 215956 kb
Host smart-5b9d2b88-9a62-4c4c-83be-b31d2ae2e073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256830521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.256830521
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1660364059
Short name T16
Test name
Test status
Simulation time 528441918 ps
CPU time 3.1 seconds
Started May 30 01:17:20 PM PDT 24
Finished May 30 01:17:25 PM PDT 24
Peak memory 215812 kb
Host smart-d6d46363-7501-4c49-a734-61964386a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660364059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1660364059
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1746413704
Short name T857
Test name
Test status
Simulation time 232777708 ps
CPU time 1.42 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:17:45 PM PDT 24
Peak memory 215872 kb
Host smart-45a9f452-63a4-4959-91ee-bf6735d94bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746413704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1746413704
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.793843042
Short name T778
Test name
Test status
Simulation time 189930354 ps
CPU time 0.92 seconds
Started May 30 01:17:19 PM PDT 24
Finished May 30 01:17:20 PM PDT 24
Peak memory 205224 kb
Host smart-74111240-b190-4867-80ee-90ce610a0d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793843042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.793843042
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2040157078
Short name T957
Test name
Test status
Simulation time 2916383045 ps
CPU time 4.24 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 222544 kb
Host smart-cd14e1a2-bb78-4cd3-9cb3-46cc2cd3672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040157078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2040157078
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4052620780
Short name T468
Test name
Test status
Simulation time 11113728 ps
CPU time 0.71 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:25 PM PDT 24
Peak memory 204292 kb
Host smart-04a0111f-6d53-4f5a-8cc2-9bd9a30ff4a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052620780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
052620780
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3053647077
Short name T278
Test name
Test status
Simulation time 278054220 ps
CPU time 3.58 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:16:25 PM PDT 24
Peak memory 219528 kb
Host smart-056c2667-c144-421d-b026-5b691c4c82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053647077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3053647077
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3330320978
Short name T354
Test name
Test status
Simulation time 62263639 ps
CPU time 0.77 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:16:23 PM PDT 24
Peak memory 206248 kb
Host smart-dd64c783-f97b-4f13-bf32-e94c01a8b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330320978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3330320978
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3458322372
Short name T973
Test name
Test status
Simulation time 12205522457 ps
CPU time 30.68 seconds
Started May 30 01:16:25 PM PDT 24
Finished May 30 01:16:57 PM PDT 24
Peak memory 237528 kb
Host smart-900ce36e-0512-4ff9-8259-ac07a932ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458322372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3458322372
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1796883105
Short name T322
Test name
Test status
Simulation time 13605720997 ps
CPU time 109.03 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 249240 kb
Host smart-dcf9db43-4797-4c97-b46b-da1c70ec1c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796883105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1796883105
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3083476950
Short name T949
Test name
Test status
Simulation time 17665427833 ps
CPU time 33.27 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:59 PM PDT 24
Peak memory 232352 kb
Host smart-be2d071d-ac23-4be6-970d-2285f617815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083476950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3083476950
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2303924794
Short name T720
Test name
Test status
Simulation time 690266972 ps
CPU time 6.13 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:31 PM PDT 24
Peak memory 218228 kb
Host smart-d9207df5-c78c-483d-a035-ed946fe95f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303924794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2303924794
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2267040111
Short name T749
Test name
Test status
Simulation time 27579196051 ps
CPU time 47.83 seconds
Started May 30 01:16:25 PM PDT 24
Finished May 30 01:17:14 PM PDT 24
Peak memory 250536 kb
Host smart-b8949ba7-5948-4cf8-887f-b233a6f9c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267040111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2267040111
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.4059785490
Short name T863
Test name
Test status
Simulation time 46727658 ps
CPU time 1.04 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:26 PM PDT 24
Peak memory 216212 kb
Host smart-fbe8c6b7-8b7d-4201-86b6-8ffc2883a9de
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059785490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.4059785490
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3830197398
Short name T736
Test name
Test status
Simulation time 4723445877 ps
CPU time 8.09 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:29 PM PDT 24
Peak memory 222820 kb
Host smart-3168dbc2-081c-4220-b30c-7f87e9e3a2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830197398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3830197398
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4121656579
Short name T483
Test name
Test status
Simulation time 8425126156 ps
CPU time 12.87 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:33 PM PDT 24
Peak memory 233308 kb
Host smart-7e21b1f0-06d3-456b-9e0b-a02d76ca4d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121656579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4121656579
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1610477846
Short name T400
Test name
Test status
Simulation time 2815434802 ps
CPU time 17.91 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:43 PM PDT 24
Peak memory 220248 kb
Host smart-dc84d823-594d-4ab9-bb80-a63e23777aa5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1610477846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1610477846
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.483175637
Short name T67
Test name
Test status
Simulation time 200447364 ps
CPU time 1.13 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 236372 kb
Host smart-0c6c12f0-c96a-4c1a-847c-91f977832117
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483175637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.483175637
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1559408223
Short name T166
Test name
Test status
Simulation time 84147011398 ps
CPU time 268.64 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:20:54 PM PDT 24
Peak memory 253980 kb
Host smart-e9f8d86a-32c9-4234-97c5-87e9ca997287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559408223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1559408223
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.984317450
Short name T603
Test name
Test status
Simulation time 12515344 ps
CPU time 0.69 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:16:23 PM PDT 24
Peak memory 205036 kb
Host smart-6338d0cb-6c71-4052-93a4-487f5daf6813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984317450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.984317450
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3422669048
Short name T488
Test name
Test status
Simulation time 9854024981 ps
CPU time 8.47 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:16:30 PM PDT 24
Peak memory 215848 kb
Host smart-40e8f630-5308-4e9f-a616-db9d6d7b3c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422669048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3422669048
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.868550905
Short name T675
Test name
Test status
Simulation time 117459709 ps
CPU time 3.25 seconds
Started May 30 01:16:19 PM PDT 24
Finished May 30 01:16:23 PM PDT 24
Peak memory 207908 kb
Host smart-7e0c233d-810f-4175-894d-3ee7b37ef270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868550905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.868550905
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3690590117
Short name T618
Test name
Test status
Simulation time 27307987 ps
CPU time 0.72 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:21 PM PDT 24
Peak memory 205240 kb
Host smart-15d5ee1f-e254-4042-92ea-f9cd1486a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690590117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3690590117
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.971786466
Short name T280
Test name
Test status
Simulation time 12274926763 ps
CPU time 15.53 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:39 PM PDT 24
Peak memory 248760 kb
Host smart-80d997a1-99ec-4f88-b354-b0c32fecfa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971786466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.971786466
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1353707172
Short name T887
Test name
Test status
Simulation time 51491121 ps
CPU time 0.78 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:47 PM PDT 24
Peak memory 205224 kb
Host smart-5127f9ea-3ba1-4b81-90c7-4845fd627598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353707172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1353707172
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1488938271
Short name T822
Test name
Test status
Simulation time 93510518 ps
CPU time 2.89 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:48 PM PDT 24
Peak memory 234080 kb
Host smart-e99f64fb-52c5-4944-8600-85f44dda9f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488938271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1488938271
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1202930441
Short name T414
Test name
Test status
Simulation time 25468748 ps
CPU time 0.76 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:45 PM PDT 24
Peak memory 205216 kb
Host smart-6ce11c44-129b-45ef-a9aa-7d5235a3a211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202930441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1202930441
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3206239324
Short name T927
Test name
Test status
Simulation time 140153291056 ps
CPU time 233.9 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:21:38 PM PDT 24
Peak memory 248816 kb
Host smart-7879526d-5a78-4751-abbc-e55349386e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206239324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3206239324
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4153980974
Short name T983
Test name
Test status
Simulation time 1682815915 ps
CPU time 12.71 seconds
Started May 30 01:17:46 PM PDT 24
Finished May 30 01:18:01 PM PDT 24
Peak memory 240524 kb
Host smart-f24a8d3d-b88c-44b4-8156-0ccb319b5bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153980974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4153980974
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2960233714
Short name T50
Test name
Test status
Simulation time 45283563172 ps
CPU time 252.07 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:21:56 PM PDT 24
Peak memory 252208 kb
Host smart-2e757ee4-5070-4f7d-8ea5-a3a803bacdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960233714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2960233714
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1682603846
Short name T539
Test name
Test status
Simulation time 639570179 ps
CPU time 3.66 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:47 PM PDT 24
Peak memory 223940 kb
Host smart-aaec1c80-d8f7-4810-8096-c60a7cc68112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682603846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1682603846
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3130720793
Short name T968
Test name
Test status
Simulation time 8336889470 ps
CPU time 20.15 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:18:05 PM PDT 24
Peak memory 219428 kb
Host smart-8623fe23-a7e3-453c-a32f-4c3a44ea0eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130720793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3130720793
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1776019195
Short name T250
Test name
Test status
Simulation time 1013907911 ps
CPU time 5.23 seconds
Started May 30 01:17:40 PM PDT 24
Finished May 30 01:17:46 PM PDT 24
Peak memory 216428 kb
Host smart-9414b881-54ae-4e10-9009-d54ea65115ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776019195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1776019195
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1584494713
Short name T673
Test name
Test status
Simulation time 5537050891 ps
CPU time 10.12 seconds
Started May 30 01:17:48 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 233416 kb
Host smart-e4a705f5-dacc-4d26-85f4-652ff557bfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584494713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1584494713
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3449501499
Short name T595
Test name
Test status
Simulation time 2896173551 ps
CPU time 10.58 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:17:54 PM PDT 24
Peak memory 235256 kb
Host smart-31e3b1d0-492a-4982-9423-923a2b4ea0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449501499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3449501499
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.600222381
Short name T353
Test name
Test status
Simulation time 114320945 ps
CPU time 4.12 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 222132 kb
Host smart-7a0ddf08-22c8-498b-a76e-20a736e034ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=600222381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.600222381
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2970846925
Short name T755
Test name
Test status
Simulation time 67572062217 ps
CPU time 298.39 seconds
Started May 30 01:17:46 PM PDT 24
Finished May 30 01:22:47 PM PDT 24
Peak memory 246420 kb
Host smart-7a8c4a06-3dd5-4042-9541-8a44db5c4119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970846925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2970846925
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2063576365
Short name T873
Test name
Test status
Simulation time 2180944306 ps
CPU time 11.19 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:17:54 PM PDT 24
Peak memory 215984 kb
Host smart-67f06040-435e-4351-bb54-9d228e9229cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063576365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2063576365
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2690246467
Short name T844
Test name
Test status
Simulation time 1204971896 ps
CPU time 7.15 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:52 PM PDT 24
Peak memory 215780 kb
Host smart-8157271d-06e5-4763-b834-ff95ddf33061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690246467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2690246467
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.277295241
Short name T453
Test name
Test status
Simulation time 156141108 ps
CPU time 1.29 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:46 PM PDT 24
Peak memory 215844 kb
Host smart-23dc5bc9-63bd-4c6f-ba15-25c19c6ad7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277295241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.277295241
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1481114653
Short name T674
Test name
Test status
Simulation time 30119762 ps
CPU time 0.83 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:17:45 PM PDT 24
Peak memory 205260 kb
Host smart-29674561-5d99-4318-a63c-a2ebb97438d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481114653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1481114653
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.794648041
Short name T244
Test name
Test status
Simulation time 1350918735 ps
CPU time 5.88 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:51 PM PDT 24
Peak memory 218432 kb
Host smart-96d22fe0-f26f-4d75-8dae-9214b6289082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794648041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.794648041
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3740579688
Short name T565
Test name
Test status
Simulation time 12421251 ps
CPU time 0.72 seconds
Started May 30 01:17:46 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 204300 kb
Host smart-bdd6dcca-b002-4e91-b6e8-6b57f667ee58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740579688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3740579688
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.843295162
Short name T792
Test name
Test status
Simulation time 10645536204 ps
CPU time 7.36 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:52 PM PDT 24
Peak memory 234132 kb
Host smart-d834d631-7ef7-4dff-b807-60563b21a9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843295162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.843295162
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3674593239
Short name T825
Test name
Test status
Simulation time 49198584 ps
CPU time 0.75 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:47 PM PDT 24
Peak memory 204816 kb
Host smart-22725c63-f12e-473e-8d8c-65feaf07d5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674593239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3674593239
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.147308418
Short name T791
Test name
Test status
Simulation time 7940172449 ps
CPU time 63.25 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:18:50 PM PDT 24
Peak memory 249316 kb
Host smart-539c819b-b866-4963-9c9e-af7737be01d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147308418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.147308418
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3551409744
Short name T47
Test name
Test status
Simulation time 16950633937 ps
CPU time 83.12 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:19:08 PM PDT 24
Peak memory 232932 kb
Host smart-41eab617-b364-469f-8dfe-4009be5d3060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551409744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3551409744
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4018048020
Short name T312
Test name
Test status
Simulation time 1612996771 ps
CPU time 27.46 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 224156 kb
Host smart-38a71c45-5111-4c6f-bd3d-00c412b0d5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018048020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4018048020
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1842384151
Short name T610
Test name
Test status
Simulation time 428575601 ps
CPU time 2.5 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 218092 kb
Host smart-d4c60b77-4405-4057-881a-d3d6eb246180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842384151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1842384151
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3089795891
Short name T137
Test name
Test status
Simulation time 30339818227 ps
CPU time 37.4 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:18:22 PM PDT 24
Peak memory 240444 kb
Host smart-e72f3168-2a75-4671-839d-2fe590971c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089795891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3089795891
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.418381786
Short name T852
Test name
Test status
Simulation time 2993503804 ps
CPU time 7.35 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:17:54 PM PDT 24
Peak memory 232276 kb
Host smart-ceda68e4-4a27-4033-9bf7-fa578ef6ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418381786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.418381786
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.667712189
Short name T858
Test name
Test status
Simulation time 1730092084 ps
CPU time 4.65 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:17:47 PM PDT 24
Peak memory 224148 kb
Host smart-b30ff983-d66c-40c1-8685-ce94f524a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667712189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.667712189
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.619424116
Short name T596
Test name
Test status
Simulation time 1769815891 ps
CPU time 15.23 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 219864 kb
Host smart-ceb1c9a9-07ae-42c6-9792-41334fef4f9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=619424116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.619424116
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1956443951
Short name T272
Test name
Test status
Simulation time 4027022923 ps
CPU time 54.2 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:18:41 PM PDT 24
Peak memory 248708 kb
Host smart-5d5b8641-e828-476f-be79-b1bf74804a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956443951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1956443951
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3568631521
Short name T436
Test name
Test status
Simulation time 1355310052 ps
CPU time 18.46 seconds
Started May 30 01:17:41 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 216052 kb
Host smart-15d6dd88-a3c0-4fea-b981-8b366d290279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568631521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3568631521
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2603709618
Short name T882
Test name
Test status
Simulation time 9097073848 ps
CPU time 4.39 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 215860 kb
Host smart-760df520-8b53-43b9-b0ae-dbb02cecb3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603709618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2603709618
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.429298519
Short name T420
Test name
Test status
Simulation time 457244602 ps
CPU time 2.98 seconds
Started May 30 01:17:42 PM PDT 24
Finished May 30 01:17:46 PM PDT 24
Peak memory 215876 kb
Host smart-aa9708a8-9d8f-4127-9c1b-80ea605c73e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429298519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.429298519
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2028031483
Short name T433
Test name
Test status
Simulation time 207366614 ps
CPU time 1.06 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:47 PM PDT 24
Peak memory 205288 kb
Host smart-757b15bb-b746-4b58-8bc1-ec2fb200a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028031483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2028031483
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1787921658
Short name T258
Test name
Test status
Simulation time 31933756549 ps
CPU time 19.16 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:18:04 PM PDT 24
Peak memory 236256 kb
Host smart-951b70a5-61aa-41c3-b9a7-06f7116dd161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787921658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1787921658
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2262800976
Short name T338
Test name
Test status
Simulation time 94715514 ps
CPU time 0.73 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:17:48 PM PDT 24
Peak memory 204252 kb
Host smart-496d49ff-21d5-4697-8ce8-4a0ea867ad50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262800976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2262800976
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.359572333
Short name T284
Test name
Test status
Simulation time 64194090 ps
CPU time 3 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:17:52 PM PDT 24
Peak memory 233328 kb
Host smart-01096c2e-f2d4-4c90-8595-2ba9e8c4023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359572333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.359572333
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2980192193
Short name T862
Test name
Test status
Simulation time 38755970 ps
CPU time 0.76 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:17:47 PM PDT 24
Peak memory 205936 kb
Host smart-8d28f2c6-818b-4849-b5f9-b2b886ebf09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980192193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2980192193
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4172558499
Short name T684
Test name
Test status
Simulation time 25416184797 ps
CPU time 105.89 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:19:35 PM PDT 24
Peak memory 251472 kb
Host smart-1bab2325-1c13-4bec-b21e-b5fa59311e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172558499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4172558499
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.445949507
Short name T443
Test name
Test status
Simulation time 16883436024 ps
CPU time 54.89 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 250412 kb
Host smart-c3e6917f-ffcb-43d4-aa58-2a6c591e4ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445949507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.445949507
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3116281695
Short name T868
Test name
Test status
Simulation time 2154605972 ps
CPU time 7.71 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:17:55 PM PDT 24
Peak memory 232472 kb
Host smart-91828aa9-568e-41b1-ba35-50251c46e030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116281695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3116281695
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3626887060
Short name T564
Test name
Test status
Simulation time 200860558 ps
CPU time 3.65 seconds
Started May 30 01:17:46 PM PDT 24
Finished May 30 01:17:52 PM PDT 24
Peak memory 217392 kb
Host smart-a78c6814-3d6f-4feb-9580-78db09617b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626887060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3626887060
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1088724596
Short name T758
Test name
Test status
Simulation time 47667853442 ps
CPU time 102.78 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:19:30 PM PDT 24
Peak memory 232388 kb
Host smart-2588e17a-6905-49fe-8ca5-37e1d4463fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088724596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1088724596
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2747937944
Short name T982
Test name
Test status
Simulation time 407593295 ps
CPU time 5.15 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:51 PM PDT 24
Peak memory 233232 kb
Host smart-a93a59a5-cf4b-4833-bbd5-9677bc3e4a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747937944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2747937944
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1919199726
Short name T964
Test name
Test status
Simulation time 4873986596 ps
CPU time 7.8 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:54 PM PDT 24
Peak memory 220640 kb
Host smart-f4bc3e11-2194-4952-9d22-2185e69270f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919199726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1919199726
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.612963086
Short name T679
Test name
Test status
Simulation time 475526667 ps
CPU time 4.68 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:17:54 PM PDT 24
Peak memory 222008 kb
Host smart-ef74a78c-5f29-4149-a74d-1a8a819be478
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=612963086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.612963086
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1022169503
Short name T604
Test name
Test status
Simulation time 633177022 ps
CPU time 3.22 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:50 PM PDT 24
Peak memory 215892 kb
Host smart-be67f832-4167-47d7-bc29-ee6ec9fdd66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022169503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1022169503
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3997296762
Short name T345
Test name
Test status
Simulation time 2154561961 ps
CPU time 7.14 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:53 PM PDT 24
Peak memory 215832 kb
Host smart-93d5a917-a8f6-45d5-b4a2-9d01d99786f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997296762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3997296762
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1250921001
Short name T415
Test name
Test status
Simulation time 182868319 ps
CPU time 1.95 seconds
Started May 30 01:17:45 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 215940 kb
Host smart-b43739b8-e92b-467b-b0cf-0e219d62872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250921001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1250921001
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2042754037
Short name T688
Test name
Test status
Simulation time 138982365 ps
CPU time 0.81 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:48 PM PDT 24
Peak memory 205288 kb
Host smart-789ef11b-4feb-4efe-a6af-15bebb0d4468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042754037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2042754037
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.728979757
Short name T193
Test name
Test status
Simulation time 2131338660 ps
CPU time 6.72 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:17:55 PM PDT 24
Peak memory 235288 kb
Host smart-3dda3357-24bd-4576-9cbb-f50dcfe9e073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728979757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.728979757
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.20565024
Short name T836
Test name
Test status
Simulation time 27749327 ps
CPU time 0.75 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 204924 kb
Host smart-5dca4235-39f5-47dc-a95d-1becbc7119ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.20565024
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2521917114
Short name T678
Test name
Test status
Simulation time 19908850212 ps
CPU time 14.76 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 235344 kb
Host smart-065d8778-68f7-4a29-93a0-0e1a86cd912f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521917114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2521917114
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1193454712
Short name T139
Test name
Test status
Simulation time 67241310 ps
CPU time 0.72 seconds
Started May 30 01:17:46 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 204904 kb
Host smart-260b555e-d47b-42b1-a1b0-6589c3e69381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193454712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1193454712
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3100880284
Short name T746
Test name
Test status
Simulation time 1309293038 ps
CPU time 26.9 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:18:12 PM PDT 24
Peak memory 240568 kb
Host smart-6b39d59a-6011-4dc1-8f3d-013934c6c7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100880284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3100880284
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4152361083
Short name T238
Test name
Test status
Simulation time 26850385279 ps
CPU time 259.6 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:22:06 PM PDT 24
Peak memory 253352 kb
Host smart-18d57909-f4a7-4aed-a716-3cbd3d0974db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152361083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4152361083
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2708749890
Short name T609
Test name
Test status
Simulation time 733836922 ps
CPU time 4.76 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:50 PM PDT 24
Peak memory 232316 kb
Host smart-8c3a8552-6ec8-46d9-a00c-bbd3e519792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708749890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2708749890
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1145462676
Short name T201
Test name
Test status
Simulation time 2660917979 ps
CPU time 10.28 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 233548 kb
Host smart-c125f5b0-5b70-4b38-ad14-d34a4bdfafff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145462676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1145462676
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.144941097
Short name T656
Test name
Test status
Simulation time 18317011437 ps
CPU time 32.55 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:18:21 PM PDT 24
Peak memory 235788 kb
Host smart-91dabe8d-072d-4528-8528-ed4a6bd27b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144941097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.144941097
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3876319545
Short name T268
Test name
Test status
Simulation time 448663426 ps
CPU time 4.47 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:51 PM PDT 24
Peak memory 218072 kb
Host smart-3ac12e14-39f3-4c27-b4de-ff8e7b675d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876319545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3876319545
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.686103627
Short name T611
Test name
Test status
Simulation time 1852275613 ps
CPU time 3.53 seconds
Started May 30 01:17:47 PM PDT 24
Finished May 30 01:17:52 PM PDT 24
Peak memory 217828 kb
Host smart-d1d2cbbc-a8f7-4272-ac58-f17e1afca0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686103627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.686103627
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.74238530
Short name T473
Test name
Test status
Simulation time 3281541644 ps
CPU time 4.16 seconds
Started May 30 01:17:44 PM PDT 24
Finished May 30 01:17:51 PM PDT 24
Peak memory 220076 kb
Host smart-17493ce7-0ea9-4129-b58e-2cc647eb64de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=74238530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.74238530
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2562508977
Short name T826
Test name
Test status
Simulation time 3532968279 ps
CPU time 73.85 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:19:15 PM PDT 24
Peak memory 257044 kb
Host smart-428e3cc1-aae4-4863-bc9b-d697cbec094c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562508977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2562508977
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1998991054
Short name T491
Test name
Test status
Simulation time 43649868 ps
CPU time 0.69 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:46 PM PDT 24
Peak memory 205000 kb
Host smart-ae6d792c-33e8-4adb-a220-b1fa08c8e9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998991054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1998991054
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3800643533
Short name T424
Test name
Test status
Simulation time 16389990 ps
CPU time 0.72 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:46 PM PDT 24
Peak memory 205012 kb
Host smart-8dc09f91-7515-4bcf-a0f1-54e7ad2db05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800643533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3800643533
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.317553751
Short name T497
Test name
Test status
Simulation time 70290727 ps
CPU time 1.04 seconds
Started May 30 01:17:46 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 206944 kb
Host smart-cc46799a-a1f8-4c83-87b7-f01bd3b23a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317553751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.317553751
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1555002675
Short name T348
Test name
Test status
Simulation time 360945575 ps
CPU time 0.96 seconds
Started May 30 01:17:43 PM PDT 24
Finished May 30 01:17:45 PM PDT 24
Peak memory 205216 kb
Host smart-1b6bb547-6bf8-45bc-9019-2fa0f0f11d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555002675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1555002675
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3727287971
Short name T479
Test name
Test status
Simulation time 7144033039 ps
CPU time 15.6 seconds
Started May 30 01:17:46 PM PDT 24
Finished May 30 01:18:03 PM PDT 24
Peak memory 240508 kb
Host smart-c2da4739-51cb-4645-a379-20c2b14a0310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727287971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3727287971
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2331072907
Short name T594
Test name
Test status
Simulation time 57914467 ps
CPU time 0.75 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 204256 kb
Host smart-98292059-9a96-404c-8b8a-48d38e5dc3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331072907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2331072907
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.631712136
Short name T898
Test name
Test status
Simulation time 243074942 ps
CPU time 5.05 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:07 PM PDT 24
Peak memory 224156 kb
Host smart-f6b8f2dd-48df-4909-884c-5223119997af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631712136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.631712136
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2987538391
Short name T341
Test name
Test status
Simulation time 14694936 ps
CPU time 0.73 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:18:07 PM PDT 24
Peak memory 204864 kb
Host smart-425d6f24-3975-4efd-ac29-95b77c271c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987538391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2987538391
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3662383473
Short name T590
Test name
Test status
Simulation time 29923769 ps
CPU time 0.85 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 215680 kb
Host smart-2089c22f-c5c0-4359-ae15-73a94d1f5ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662383473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3662383473
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.890530181
Short name T19
Test name
Test status
Simulation time 214762390174 ps
CPU time 375.87 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:24:17 PM PDT 24
Peak memory 260140 kb
Host smart-d0312031-8748-4ffd-8c8e-4aef6c6373d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890530181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.890530181
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2334646939
Short name T567
Test name
Test status
Simulation time 2586268198 ps
CPU time 26.68 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:18:33 PM PDT 24
Peak memory 239624 kb
Host smart-2fe720f3-b25e-42db-9d8c-269854951f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334646939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2334646939
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3216964661
Short name T781
Test name
Test status
Simulation time 599889637 ps
CPU time 3.85 seconds
Started May 30 01:17:56 PM PDT 24
Finished May 30 01:18:01 PM PDT 24
Peak memory 224168 kb
Host smart-3bb5c2d7-980e-45b6-837e-e021aa229981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216964661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3216964661
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1981722711
Short name T956
Test name
Test status
Simulation time 320412927 ps
CPU time 2.4 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:18:03 PM PDT 24
Peak memory 218188 kb
Host smart-f2b9174f-b31f-4265-82ad-5c887851a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981722711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1981722711
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1110710007
Short name T683
Test name
Test status
Simulation time 96727520108 ps
CPU time 57.72 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:18:55 PM PDT 24
Peak memory 240380 kb
Host smart-74d296a0-8355-4d5a-8e28-fa64189e8710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110710007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1110710007
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.564942370
Short name T504
Test name
Test status
Simulation time 10840382078 ps
CPU time 13.96 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:14 PM PDT 24
Peak memory 220956 kb
Host smart-649c2d30-0632-48e1-8067-94301d0fc104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564942370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.564942370
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3637014656
Short name T538
Test name
Test status
Simulation time 1799219347 ps
CPU time 11.09 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:12 PM PDT 24
Peak memory 233308 kb
Host smart-b7d96074-0f34-41f5-a987-02a2af74d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637014656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3637014656
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2493261363
Short name T798
Test name
Test status
Simulation time 415710352 ps
CPU time 3.16 seconds
Started May 30 01:18:01 PM PDT 24
Finished May 30 01:18:06 PM PDT 24
Peak memory 218524 kb
Host smart-55118a23-cbfb-44c3-8cd5-ce1044aedf1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2493261363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2493261363
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2680338428
Short name T157
Test name
Test status
Simulation time 65345956524 ps
CPU time 117.91 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:19:57 PM PDT 24
Peak memory 236204 kb
Host smart-7ef4b129-4ed6-486a-9ce6-8934c6e46c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680338428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2680338428
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.119215213
Short name T412
Test name
Test status
Simulation time 70502220 ps
CPU time 0.71 seconds
Started May 30 01:17:56 PM PDT 24
Finished May 30 01:17:57 PM PDT 24
Peak memory 205140 kb
Host smart-2dbab854-90b9-4509-be55-a590636582c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119215213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.119215213
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2294275440
Short name T701
Test name
Test status
Simulation time 840621675 ps
CPU time 5.03 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:04 PM PDT 24
Peak memory 215672 kb
Host smart-c7cea0ae-2565-407d-98f3-636a089d5a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294275440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2294275440
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2472117522
Short name T355
Test name
Test status
Simulation time 64659410 ps
CPU time 0.95 seconds
Started May 30 01:17:56 PM PDT 24
Finished May 30 01:17:58 PM PDT 24
Peak memory 206792 kb
Host smart-31e28d55-4b04-47bd-83be-aaab96d759d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472117522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2472117522
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2598193385
Short name T779
Test name
Test status
Simulation time 198580379 ps
CPU time 0.84 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 205256 kb
Host smart-bbff1d79-2ede-4d6f-8a49-f192de5b7534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598193385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2598193385
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3053910661
Short name T769
Test name
Test status
Simulation time 319270870 ps
CPU time 2.52 seconds
Started May 30 01:18:06 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 218140 kb
Host smart-584f0bcf-1357-44fd-8d71-724a0c953413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053910661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3053910661
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3830332197
Short name T606
Test name
Test status
Simulation time 52586611 ps
CPU time 0.67 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 204908 kb
Host smart-83706418-6c96-4dc0-bca8-da283783aa93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830332197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3830332197
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3652469580
Short name T819
Test name
Test status
Simulation time 1117323215 ps
CPU time 7.65 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:18 PM PDT 24
Peak memory 234508 kb
Host smart-97f95b7c-5c32-4b3f-8743-caf0d3a426df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652469580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3652469580
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1033774599
Short name T330
Test name
Test status
Simulation time 15352300 ps
CPU time 0.78 seconds
Started May 30 01:18:02 PM PDT 24
Finished May 30 01:18:04 PM PDT 24
Peak memory 205836 kb
Host smart-53aae68c-a5d3-427d-99a4-47c560feaf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033774599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1033774599
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.794599023
Short name T933
Test name
Test status
Simulation time 26571367709 ps
CPU time 248.27 seconds
Started May 30 01:17:55 PM PDT 24
Finished May 30 01:22:05 PM PDT 24
Peak memory 253476 kb
Host smart-7b1f154c-74da-41f0-9908-bc7de8e30937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794599023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.794599023
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1567726535
Short name T209
Test name
Test status
Simulation time 32460354353 ps
CPU time 235.25 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:21:55 PM PDT 24
Peak memory 249180 kb
Host smart-353e9ce4-120f-4437-b69c-d4b7510760cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567726535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1567726535
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4105851206
Short name T702
Test name
Test status
Simulation time 554182881 ps
CPU time 13.11 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 240536 kb
Host smart-c7ce90a0-d987-474a-b6ea-d554bef0a76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105851206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4105851206
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1159269909
Short name T666
Test name
Test status
Simulation time 361406841 ps
CPU time 5.59 seconds
Started May 30 01:18:04 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 233480 kb
Host smart-b4116022-9125-499c-adbe-c82c350d66aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159269909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1159269909
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3050413551
Short name T853
Test name
Test status
Simulation time 1489883771 ps
CPU time 18.43 seconds
Started May 30 01:17:56 PM PDT 24
Finished May 30 01:18:15 PM PDT 24
Peak memory 235620 kb
Host smart-b2525643-15d8-4dc2-aa52-89cae2580e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050413551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3050413551
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2343503679
Short name T335
Test name
Test status
Simulation time 250520053 ps
CPU time 2.04 seconds
Started May 30 01:17:56 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 215704 kb
Host smart-751eabb6-818f-4e82-9774-5b361f8eb5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343503679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2343503679
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3890306370
Short name T508
Test name
Test status
Simulation time 327989364 ps
CPU time 2.06 seconds
Started May 30 01:17:56 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 215640 kb
Host smart-fe00ca96-34a7-4d5d-a3cb-f43e440c9cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890306370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3890306370
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.458250606
Short name T951
Test name
Test status
Simulation time 586025912 ps
CPU time 4.04 seconds
Started May 30 01:18:02 PM PDT 24
Finished May 30 01:18:07 PM PDT 24
Peak memory 219608 kb
Host smart-c7cf2f8b-1a5a-4c2e-bd28-e115c36cb680
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=458250606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.458250606
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2258755135
Short name T153
Test name
Test status
Simulation time 13449038969 ps
CPU time 69.34 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:19:10 PM PDT 24
Peak memory 256936 kb
Host smart-7eb1aa52-a178-4841-bfa2-c4230129b479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258755135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2258755135
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4105212578
Short name T507
Test name
Test status
Simulation time 5231519776 ps
CPU time 26.62 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:28 PM PDT 24
Peak memory 215980 kb
Host smart-97946d46-3fd1-4a00-b7ae-02ad16fa4fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105212578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4105212578
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1374551520
Short name T785
Test name
Test status
Simulation time 13309386276 ps
CPU time 17.98 seconds
Started May 30 01:17:56 PM PDT 24
Finished May 30 01:18:15 PM PDT 24
Peak memory 215792 kb
Host smart-b550a58e-7207-47f9-bb26-16891623ff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374551520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1374551520
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2989545736
Short name T593
Test name
Test status
Simulation time 113914428 ps
CPU time 2.26 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:18:03 PM PDT 24
Peak memory 215876 kb
Host smart-adee0f40-f641-46d1-8e01-48e1b188046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989545736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2989545736
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.860695271
Short name T980
Test name
Test status
Simulation time 241376273 ps
CPU time 0.96 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 206140 kb
Host smart-eee13052-e9aa-42f5-98ac-a6569c25afe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860695271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.860695271
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.727684964
Short name T78
Test name
Test status
Simulation time 2580256523 ps
CPU time 3.06 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:03 PM PDT 24
Peak memory 216292 kb
Host smart-d5f56cd2-547a-49bf-ab94-ccdfafe49441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727684964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.727684964
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2222154139
Short name T346
Test name
Test status
Simulation time 115240286 ps
CPU time 0.7 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:18:01 PM PDT 24
Peak memory 205280 kb
Host smart-c12ba612-2cff-436e-8e5b-9c16eb9c8668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222154139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2222154139
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1961084105
Short name T958
Test name
Test status
Simulation time 60602234 ps
CPU time 2.1 seconds
Started May 30 01:17:55 PM PDT 24
Finished May 30 01:17:58 PM PDT 24
Peak memory 220564 kb
Host smart-4f87fab8-5444-457b-bf57-4098fa229454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961084105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1961084105
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2499013590
Short name T548
Test name
Test status
Simulation time 51158977 ps
CPU time 0.82 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 205928 kb
Host smart-84368285-a667-4276-9bfe-8907e459aa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499013590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2499013590
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1682949969
Short name T902
Test name
Test status
Simulation time 22357672540 ps
CPU time 51.38 seconds
Started May 30 01:18:04 PM PDT 24
Finished May 30 01:18:57 PM PDT 24
Peak memory 236656 kb
Host smart-91ac1eb3-2a0a-479f-bcb2-1c324f81842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682949969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1682949969
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3216098042
Short name T788
Test name
Test status
Simulation time 10319142838 ps
CPU time 123.27 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:20:05 PM PDT 24
Peak memory 255996 kb
Host smart-85705016-8461-452b-ba44-837b2babb6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216098042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3216098042
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1510642456
Short name T900
Test name
Test status
Simulation time 373428022 ps
CPU time 4.98 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:05 PM PDT 24
Peak memory 224204 kb
Host smart-3cf6df77-b5d8-40c0-92cc-2edb6997e7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510642456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1510642456
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3576709418
Short name T841
Test name
Test status
Simulation time 209028329 ps
CPU time 4.73 seconds
Started May 30 01:18:01 PM PDT 24
Finished May 30 01:18:07 PM PDT 24
Peak memory 234092 kb
Host smart-85826f22-46d3-4a1a-b354-d309d355687c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576709418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3576709418
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.56424680
Short name T89
Test name
Test status
Simulation time 247376306 ps
CPU time 9.42 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 235068 kb
Host smart-5417a19d-57af-4210-8614-d09bb6fc094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56424680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.56424680
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2280540710
Short name T725
Test name
Test status
Simulation time 6365832756 ps
CPU time 11.15 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:18:18 PM PDT 24
Peak memory 224216 kb
Host smart-7d983913-34ab-4e34-9889-e3336859dacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280540710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2280540710
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3903094938
Short name T741
Test name
Test status
Simulation time 8569527110 ps
CPU time 11.49 seconds
Started May 30 01:18:01 PM PDT 24
Finished May 30 01:18:13 PM PDT 24
Peak memory 236760 kb
Host smart-c3264ced-c4aa-48f3-b92d-d6f7d5679e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903094938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3903094938
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1417064793
Short name T734
Test name
Test status
Simulation time 586350102 ps
CPU time 8.37 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 220240 kb
Host smart-d4b115ab-8b7e-4622-b28c-8d35b787f774
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1417064793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1417064793
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.356025497
Short name T731
Test name
Test status
Simulation time 3615763554 ps
CPU time 17.24 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:19 PM PDT 24
Peak memory 216132 kb
Host smart-7bec6179-ff93-4471-a317-ebfd8f3606a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356025497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.356025497
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1456061295
Short name T568
Test name
Test status
Simulation time 5004738352 ps
CPU time 13.38 seconds
Started May 30 01:18:01 PM PDT 24
Finished May 30 01:18:16 PM PDT 24
Peak memory 215888 kb
Host smart-a36402a1-c1c6-4a86-8123-7cef75403e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456061295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1456061295
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.307602687
Short name T643
Test name
Test status
Simulation time 330555589 ps
CPU time 1.56 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:18:02 PM PDT 24
Peak memory 215916 kb
Host smart-50bfe892-825e-4036-b1a8-a1ee9e3a13ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307602687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.307602687
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4225057439
Short name T76
Test name
Test status
Simulation time 203958160 ps
CPU time 0.82 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 205284 kb
Host smart-0d2e3a5a-0935-45b1-bc12-4256f3396efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225057439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4225057439
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1968936698
Short name T626
Test name
Test status
Simulation time 160046797 ps
CPU time 3.38 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:03 PM PDT 24
Peak memory 217092 kb
Host smart-175ab1ca-df07-45c1-81ac-776031f73ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968936698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1968936698
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.92171928
Short name T403
Test name
Test status
Simulation time 14153261 ps
CPU time 0.7 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 205272 kb
Host smart-d40d4b5c-e0c6-4ac7-8993-5144bf5d1ab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92171928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.92171928
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.275364007
Short name T782
Test name
Test status
Simulation time 263110669 ps
CPU time 3.3 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:12 PM PDT 24
Peak memory 224204 kb
Host smart-a78ba202-3a29-49be-9c6a-20480d76e9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275364007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.275364007
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3336661990
Short name T421
Test name
Test status
Simulation time 18522183 ps
CPU time 0.79 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 205900 kb
Host smart-d6940837-afe1-46a5-bf2f-287ee8c3c9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336661990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3336661990
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2410857195
Short name T584
Test name
Test status
Simulation time 2501436409 ps
CPU time 53.3 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:18:51 PM PDT 24
Peak memory 251788 kb
Host smart-824a5aad-14c8-43b8-946e-1eb19d8bf0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410857195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2410857195
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.113522387
Short name T217
Test name
Test status
Simulation time 16378319767 ps
CPU time 77.93 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:19:24 PM PDT 24
Peak memory 255864 kb
Host smart-cfbbf839-062e-48ba-bd3d-5e525dc2f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113522387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.113522387
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.590155163
Short name T944
Test name
Test status
Simulation time 18957670411 ps
CPU time 16.88 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:18:23 PM PDT 24
Peak memory 232436 kb
Host smart-eef37cc5-3221-4226-b710-d1b674324330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590155163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.590155163
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1663923880
Short name T279
Test name
Test status
Simulation time 270186278 ps
CPU time 5.35 seconds
Started May 30 01:18:01 PM PDT 24
Finished May 30 01:18:08 PM PDT 24
Peak memory 218124 kb
Host smart-d6722ea3-49d7-43d1-9dad-eedcdb9d9fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663923880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1663923880
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1389177179
Short name T633
Test name
Test status
Simulation time 3461387974 ps
CPU time 13.1 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:14 PM PDT 24
Peak memory 233488 kb
Host smart-801e17f8-b4ad-4757-b35b-2711df35028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389177179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1389177179
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2763936942
Short name T265
Test name
Test status
Simulation time 903542096 ps
CPU time 2.64 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:12 PM PDT 24
Peak memory 218488 kb
Host smart-ce4bcfd6-0b77-4735-add7-84b9dc20ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763936942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2763936942
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.370259805
Short name T903
Test name
Test status
Simulation time 261170838 ps
CPU time 2.91 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:05 PM PDT 24
Peak memory 233192 kb
Host smart-9f85c04c-a9cc-4918-b0cf-bd3b02b89cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370259805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.370259805
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2777284143
Short name T793
Test name
Test status
Simulation time 4949440718 ps
CPU time 12.61 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:21 PM PDT 24
Peak memory 218708 kb
Host smart-94a7e662-15a4-4284-a689-0fcdc7159544
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2777284143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2777284143
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2378713260
Short name T965
Test name
Test status
Simulation time 47852029 ps
CPU time 1.18 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:18:01 PM PDT 24
Peak memory 206456 kb
Host smart-1f8a6a35-e85e-4adc-8cb5-fc78e66e968c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378713260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2378713260
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1565812131
Short name T813
Test name
Test status
Simulation time 3788326052 ps
CPU time 29.5 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:38 PM PDT 24
Peak memory 215944 kb
Host smart-2e4fd538-86ac-44f2-ba2e-93ad6e50aed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565812131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1565812131
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.606590413
Short name T349
Test name
Test status
Simulation time 1118321776 ps
CPU time 6.67 seconds
Started May 30 01:18:04 PM PDT 24
Finished May 30 01:18:13 PM PDT 24
Peak memory 215756 kb
Host smart-50002189-adf7-4fa4-94fe-a21ab342d43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606590413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.606590413
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3571740978
Short name T850
Test name
Test status
Simulation time 2047612885 ps
CPU time 4.05 seconds
Started May 30 01:18:06 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 216032 kb
Host smart-7f817f38-1a73-4690-8fa8-f02822da1384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571740978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3571740978
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3907901352
Short name T447
Test name
Test status
Simulation time 29106308 ps
CPU time 0.8 seconds
Started May 30 01:18:01 PM PDT 24
Finished May 30 01:18:03 PM PDT 24
Peak memory 205136 kb
Host smart-2d44605c-9d88-4a14-9efb-a170628bbe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907901352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3907901352
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1112176372
Short name T948
Test name
Test status
Simulation time 11454201097 ps
CPU time 12.25 seconds
Started May 30 01:18:06 PM PDT 24
Finished May 30 01:18:19 PM PDT 24
Peak memory 227148 kb
Host smart-98a2ef22-15a1-45ae-b2aa-0feaafe873cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112176372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1112176372
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3939735119
Short name T434
Test name
Test status
Simulation time 14461564 ps
CPU time 0.74 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:00 PM PDT 24
Peak memory 205172 kb
Host smart-bc3fa210-94d0-4d06-b588-5fd262001166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939735119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3939735119
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.442924271
Short name T505
Test name
Test status
Simulation time 33774903 ps
CPU time 2.45 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:18:03 PM PDT 24
Peak memory 220644 kb
Host smart-03309490-3117-47e4-8965-db44e5cf70bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442924271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.442924271
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1636142708
Short name T828
Test name
Test status
Simulation time 40888644 ps
CPU time 0.74 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 204908 kb
Host smart-17acc491-200d-401b-86f7-efc540ffa4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636142708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1636142708
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.837703515
Short name T899
Test name
Test status
Simulation time 56713534329 ps
CPU time 109.19 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:19:59 PM PDT 24
Peak memory 256776 kb
Host smart-a72d76b6-2e90-425f-9d9c-6645ea1e21ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837703515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.837703515
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1532193111
Short name T136
Test name
Test status
Simulation time 5030890644 ps
CPU time 28.33 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:38 PM PDT 24
Peak memory 217384 kb
Host smart-57920c3a-5062-4cc8-a9bc-ad861fbd5af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532193111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1532193111
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.495577493
Short name T140
Test name
Test status
Simulation time 20499316657 ps
CPU time 207.86 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:21:36 PM PDT 24
Peak memory 255336 kb
Host smart-a7d71739-1a07-41c9-a733-78a097397d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495577493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.495577493
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.825994688
Short name T881
Test name
Test status
Simulation time 517282779 ps
CPU time 2.37 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:18:09 PM PDT 24
Peak memory 224140 kb
Host smart-d49efbf6-74fc-49eb-8271-1f22396af6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825994688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.825994688
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.967830011
Short name T9
Test name
Test status
Simulation time 458614118 ps
CPU time 4.7 seconds
Started May 30 01:18:04 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 233292 kb
Host smart-9982b358-10bf-4775-b533-8ecc023dd574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967830011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.967830011
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1997103460
Short name T938
Test name
Test status
Simulation time 2600908715 ps
CPU time 19.11 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:18:25 PM PDT 24
Peak memory 233776 kb
Host smart-729baab1-3fda-4b7d-a951-abd53fcdc1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997103460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1997103460
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3725112523
Short name T575
Test name
Test status
Simulation time 5799015989 ps
CPU time 17.07 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:16 PM PDT 24
Peak memory 218260 kb
Host smart-6ecd5216-fb09-48b7-ab53-cf618655efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725112523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3725112523
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2605807279
Short name T249
Test name
Test status
Simulation time 12375466549 ps
CPU time 25.37 seconds
Started May 30 01:17:57 PM PDT 24
Finished May 30 01:18:24 PM PDT 24
Peak memory 238712 kb
Host smart-00d018ca-ffd4-4462-a09a-81c35cbef501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605807279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2605807279
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1162547668
Short name T484
Test name
Test status
Simulation time 216761578 ps
CPU time 4.72 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:05 PM PDT 24
Peak memory 222524 kb
Host smart-6cb7221c-db0f-4915-bf74-67b78f4a6992
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1162547668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1162547668
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3409115870
Short name T165
Test name
Test status
Simulation time 34350561583 ps
CPU time 144.92 seconds
Started May 30 01:17:59 PM PDT 24
Finished May 30 01:20:25 PM PDT 24
Peak memory 248900 kb
Host smart-25dbf247-450f-4c38-950c-a1f735518445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409115870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3409115870
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4064645460
Short name T729
Test name
Test status
Simulation time 969579531 ps
CPU time 5.46 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:07 PM PDT 24
Peak memory 215888 kb
Host smart-f5f3ed8c-eedc-4748-bedf-b301c1f21c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064645460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4064645460
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1028972532
Short name T801
Test name
Test status
Simulation time 2731324280 ps
CPU time 6.08 seconds
Started May 30 01:18:04 PM PDT 24
Finished May 30 01:18:12 PM PDT 24
Peak memory 215876 kb
Host smart-1b464bb4-0206-4b0e-bed5-53b7a63b5a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028972532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1028972532
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1666366949
Short name T336
Test name
Test status
Simulation time 502125614 ps
CPU time 3.92 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 215976 kb
Host smart-eb87ce79-0679-4ebf-bb5e-2934f02c2c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666366949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1666366949
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3729538748
Short name T861
Test name
Test status
Simulation time 570089439 ps
CPU time 0.9 seconds
Started May 30 01:18:04 PM PDT 24
Finished May 30 01:18:07 PM PDT 24
Peak memory 205304 kb
Host smart-e088208b-445b-4837-9a9f-66a9bd9739fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729538748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3729538748
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1145301231
Short name T774
Test name
Test status
Simulation time 5921587976 ps
CPU time 7.67 seconds
Started May 30 01:18:05 PM PDT 24
Finished May 30 01:18:14 PM PDT 24
Peak memory 228288 kb
Host smart-dc123690-b728-40df-8935-5b6d62cd5d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145301231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1145301231
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2045863189
Short name T571
Test name
Test status
Simulation time 23976440 ps
CPU time 0.7 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 205228 kb
Host smart-0f04f947-e99a-412d-b92b-b61675edd5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045863189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2045863189
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.413604602
Short name T551
Test name
Test status
Simulation time 655326058 ps
CPU time 7.38 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:18:19 PM PDT 24
Peak memory 218040 kb
Host smart-0d93d556-6cea-4a5b-af41-a5ca06964a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413604602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.413604602
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3388397149
Short name T501
Test name
Test status
Simulation time 29601566 ps
CPU time 0.82 seconds
Started May 30 01:18:03 PM PDT 24
Finished May 30 01:18:05 PM PDT 24
Peak memory 205872 kb
Host smart-4a533188-d68f-46d8-a97b-2ed4be556652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388397149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3388397149
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4115951620
Short name T55
Test name
Test status
Simulation time 3240171929 ps
CPU time 32.17 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 249176 kb
Host smart-85d26fdd-9fa2-4f42-a5c3-71d937ee42c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115951620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4115951620
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4146106085
Short name T474
Test name
Test status
Simulation time 461535479873 ps
CPU time 248.69 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:22:21 PM PDT 24
Peak memory 250372 kb
Host smart-6771b0b9-e01a-4f8a-996b-06cf2555fc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146106085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4146106085
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3118122815
Short name T169
Test name
Test status
Simulation time 9235981778 ps
CPU time 37.09 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:18:48 PM PDT 24
Peak memory 248896 kb
Host smart-37373133-24aa-4c5e-af88-dab37ffefbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118122815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3118122815
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1937496026
Short name T496
Test name
Test status
Simulation time 934008624 ps
CPU time 11.33 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:18:24 PM PDT 24
Peak memory 224172 kb
Host smart-3fc1ad1e-ec15-4a38-8152-1a2dd95caa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937496026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1937496026
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.322364218
Short name T877
Test name
Test status
Simulation time 518108226 ps
CPU time 5.32 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:15 PM PDT 24
Peak memory 218356 kb
Host smart-e68ef46f-cc8d-495e-ae12-924e7b1a8349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322364218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.322364218
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3348277667
Short name T540
Test name
Test status
Simulation time 51373438 ps
CPU time 2.04 seconds
Started May 30 01:18:12 PM PDT 24
Finished May 30 01:18:15 PM PDT 24
Peak memory 215984 kb
Host smart-6b47fd34-7116-4916-85a5-f8a699ac80af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348277667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3348277667
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4033662961
Short name T118
Test name
Test status
Simulation time 12651307958 ps
CPU time 16.35 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:18:27 PM PDT 24
Peak memory 246856 kb
Host smart-e6180e89-f921-4163-bfae-59002f3df8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033662961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4033662961
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2399263813
Short name T536
Test name
Test status
Simulation time 1449387505 ps
CPU time 5.55 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:18:16 PM PDT 24
Peak memory 222176 kb
Host smart-b3692e64-df72-4374-b120-2eede8891428
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2399263813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2399263813
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.350774235
Short name T291
Test name
Test status
Simulation time 4530066870 ps
CPU time 37.31 seconds
Started May 30 01:18:06 PM PDT 24
Finished May 30 01:18:45 PM PDT 24
Peak memory 232456 kb
Host smart-5596259f-a7c5-47c1-848b-e55380697d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350774235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.350774235
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2181208297
Short name T11
Test name
Test status
Simulation time 13652209543 ps
CPU time 48.06 seconds
Started May 30 01:18:02 PM PDT 24
Finished May 30 01:18:51 PM PDT 24
Peak memory 215916 kb
Host smart-5593f0fc-7a0e-448c-aa31-3327aa08a746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181208297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2181208297
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2174773513
Short name T645
Test name
Test status
Simulation time 19716189885 ps
CPU time 7.34 seconds
Started May 30 01:17:58 PM PDT 24
Finished May 30 01:18:07 PM PDT 24
Peak memory 215912 kb
Host smart-0806badf-51ea-48a4-b2d1-eddef54aea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174773513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2174773513
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3760855729
Short name T586
Test name
Test status
Simulation time 1135482195 ps
CPU time 10.9 seconds
Started May 30 01:18:00 PM PDT 24
Finished May 30 01:18:12 PM PDT 24
Peak memory 215832 kb
Host smart-e219f4c4-c485-4ea9-8c82-b3b544afc78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760855729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3760855729
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1243812886
Short name T959
Test name
Test status
Simulation time 13325433 ps
CPU time 0.7 seconds
Started May 30 01:18:01 PM PDT 24
Finished May 30 01:18:03 PM PDT 24
Peak memory 205240 kb
Host smart-704a729a-177e-40d2-b1f3-99399da8b494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243812886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1243812886
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2359919479
Short name T876
Test name
Test status
Simulation time 804520414 ps
CPU time 2.2 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 207524 kb
Host smart-dcfc1fdf-e6e8-4f32-9e0f-507efd5e3919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359919479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2359919479
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3001304063
Short name T737
Test name
Test status
Simulation time 16626318 ps
CPU time 0.76 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 204892 kb
Host smart-456d50a6-faff-470c-9443-b522bb945229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001304063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
001304063
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2201897307
Short name T261
Test name
Test status
Simulation time 877586009 ps
CPU time 8.26 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:34 PM PDT 24
Peak memory 233828 kb
Host smart-14592dc0-2ed1-40c8-b9a4-44bd804ec6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201897307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2201897307
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.14168350
Short name T511
Test name
Test status
Simulation time 282349459 ps
CPU time 0.8 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 205940 kb
Host smart-2903edc5-08fd-4b84-82c7-2087d4a99949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14168350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.14168350
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1099584073
Short name T640
Test name
Test status
Simulation time 27379170767 ps
CPU time 59.41 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:17:21 PM PDT 24
Peak memory 250032 kb
Host smart-f8640223-1cec-4551-b4ba-22b8e118c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099584073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1099584073
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2310887647
Short name T542
Test name
Test status
Simulation time 76105759318 ps
CPU time 208.74 seconds
Started May 30 01:16:26 PM PDT 24
Finished May 30 01:19:56 PM PDT 24
Peak memory 248864 kb
Host smart-48ba24eb-4eda-42e8-888e-fd7614d87888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310887647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2310887647
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2152230623
Short name T649
Test name
Test status
Simulation time 11146660023 ps
CPU time 128.03 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:18:32 PM PDT 24
Peak memory 248912 kb
Host smart-5cf0e7d8-cc03-4cca-9216-4f8b84824f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152230623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2152230623
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.819467556
Short name T146
Test name
Test status
Simulation time 127457984 ps
CPU time 5.85 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:31 PM PDT 24
Peak memory 242076 kb
Host smart-23d8dc7c-1b69-499a-be7f-6232b2ea500b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819467556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.819467556
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3095760826
Short name T815
Test name
Test status
Simulation time 1576587157 ps
CPU time 8.49 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:33 PM PDT 24
Peak memory 219616 kb
Host smart-3c4cd428-9dd7-4af9-920e-d02f52ec3017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095760826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3095760826
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2406116680
Short name T281
Test name
Test status
Simulation time 9186404187 ps
CPU time 19.67 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:45 PM PDT 24
Peak memory 238188 kb
Host smart-5180bbbf-4889-4a33-b539-30ffe27c4508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406116680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2406116680
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3895445961
Short name T676
Test name
Test status
Simulation time 114991451 ps
CPU time 1.04 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 216212 kb
Host smart-00db38e6-3fb4-4a61-b2a4-1110ede56b73
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895445961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3895445961
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3483972413
Short name T906
Test name
Test status
Simulation time 538592474 ps
CPU time 3.82 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:29 PM PDT 24
Peak memory 217940 kb
Host smart-42d9258b-411d-4a3a-88aa-84166cb7382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483972413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3483972413
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2738833016
Short name T499
Test name
Test status
Simulation time 656205285 ps
CPU time 4.29 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:29 PM PDT 24
Peak memory 218592 kb
Host smart-d3ff77d5-3611-4731-a894-9dea42257da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738833016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2738833016
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1487050748
Short name T840
Test name
Test status
Simulation time 1279742173 ps
CPU time 7.67 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:31 PM PDT 24
Peak memory 222076 kb
Host smart-52ff5ee8-b668-4772-8807-9694e69908e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1487050748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1487050748
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3483447528
Short name T70
Test name
Test status
Simulation time 127476468 ps
CPU time 1.22 seconds
Started May 30 01:16:21 PM PDT 24
Finished May 30 01:16:24 PM PDT 24
Peak memory 236368 kb
Host smart-d975784a-bb5c-405e-a2a0-be889df51a31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483447528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3483447528
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.855522745
Short name T572
Test name
Test status
Simulation time 2711154242 ps
CPU time 6.17 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:32 PM PDT 24
Peak memory 224292 kb
Host smart-cd9aaf51-8862-44ea-87c1-ef728fbc064f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855522745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.855522745
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3229989321
Short name T324
Test name
Test status
Simulation time 7749134393 ps
CPU time 22.62 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:48 PM PDT 24
Peak memory 215972 kb
Host smart-a989d594-bf25-43f8-8047-de1f96e2f6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229989321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3229989321
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3323516244
Short name T864
Test name
Test status
Simulation time 1880042437 ps
CPU time 6.9 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:32 PM PDT 24
Peak memory 215836 kb
Host smart-eab16b51-e506-4000-bcc3-371f2e7b6614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323516244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3323516244
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1790913142
Short name T85
Test name
Test status
Simulation time 372050645 ps
CPU time 1.82 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:26 PM PDT 24
Peak memory 216004 kb
Host smart-68d2dbd0-c217-4c09-a75d-45da3ba9da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790913142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1790913142
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.135219931
Short name T632
Test name
Test status
Simulation time 79489853 ps
CPU time 0.96 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:26 PM PDT 24
Peak memory 205324 kb
Host smart-55bd5d4e-2ccc-4db2-9e4c-22bab98bd015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135219931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.135219931
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3339225675
Short name T553
Test name
Test status
Simulation time 190053928 ps
CPU time 3.11 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:28 PM PDT 24
Peak memory 233380 kb
Host smart-d94addd9-d0e9-4d24-a1d5-a43619439f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339225675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3339225675
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1245453533
Short name T329
Test name
Test status
Simulation time 12411499 ps
CPU time 0.73 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:09 PM PDT 24
Peak memory 204268 kb
Host smart-27a6af36-3b85-405f-8bdf-8368b74239a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245453533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1245453533
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2102931419
Short name T86
Test name
Test status
Simulation time 41518382 ps
CPU time 2.34 seconds
Started May 30 01:18:06 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 233968 kb
Host smart-41001245-beb9-4780-8863-0e425b9d4f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102931419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2102931419
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3136964965
Short name T839
Test name
Test status
Simulation time 152121318 ps
CPU time 0.72 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 204868 kb
Host smart-9fe0b7b1-ee01-461f-9023-52b36b70cb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136964965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3136964965
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1833388449
Short name T35
Test name
Test status
Simulation time 14253186510 ps
CPU time 99.33 seconds
Started May 30 01:18:12 PM PDT 24
Finished May 30 01:19:53 PM PDT 24
Peak memory 250664 kb
Host smart-bfd6ac2d-a1c8-4c80-9a06-713ad078e3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833388449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1833388449
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1996479036
Short name T286
Test name
Test status
Simulation time 5581202251 ps
CPU time 106.56 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:19:56 PM PDT 24
Peak memory 264600 kb
Host smart-b9308d74-0943-4f6f-81aa-bdad1ad5403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996479036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1996479036
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1098721897
Short name T653
Test name
Test status
Simulation time 182143622 ps
CPU time 5.45 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:18:17 PM PDT 24
Peak memory 232416 kb
Host smart-d9211344-c6cc-4bca-adfe-597076bb8a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098721897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1098721897
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1596499169
Short name T912
Test name
Test status
Simulation time 143539300 ps
CPU time 3.79 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:18:14 PM PDT 24
Peak memory 233080 kb
Host smart-bd8186ae-1d65-43a1-a041-f631cb57905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596499169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1596499169
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.793455741
Short name T922
Test name
Test status
Simulation time 7304056063 ps
CPU time 31.69 seconds
Started May 30 01:18:11 PM PDT 24
Finished May 30 01:18:45 PM PDT 24
Peak memory 220160 kb
Host smart-a46ca635-8815-44cf-a5af-f16112c6dbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793455741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.793455741
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2042788238
Short name T379
Test name
Test status
Simulation time 110304596 ps
CPU time 2.51 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 221068 kb
Host smart-a599ca29-25f2-4ff0-b8bc-f4ed5eb69762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042788238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2042788238
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3908543734
Short name T773
Test name
Test status
Simulation time 25634552502 ps
CPU time 26.41 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:35 PM PDT 24
Peak memory 252604 kb
Host smart-391f8e50-933e-4705-be23-f963cedb2407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908543734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3908543734
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2570326793
Short name T759
Test name
Test status
Simulation time 1496770419 ps
CPU time 4.97 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:18:17 PM PDT 24
Peak memory 219792 kb
Host smart-7cc03985-cfa6-4ac7-83a4-0563d8cd6db3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570326793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2570326793
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2017253520
Short name T356
Test name
Test status
Simulation time 824188035 ps
CPU time 7.51 seconds
Started May 30 01:18:11 PM PDT 24
Finished May 30 01:18:20 PM PDT 24
Peak memory 215884 kb
Host smart-11d61483-d71b-4864-ba07-43238d4c8017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017253520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2017253520
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3284472188
Short name T378
Test name
Test status
Simulation time 18428870 ps
CPU time 0.71 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 204996 kb
Host smart-88218447-05dc-48b7-9abe-ed39b18bf10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284472188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3284472188
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2864521601
Short name T719
Test name
Test status
Simulation time 581032204 ps
CPU time 1.89 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:12 PM PDT 24
Peak memory 215940 kb
Host smart-c8a789cc-44c6-43f7-adb6-12a28bad7e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864521601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2864521601
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1521560032
Short name T411
Test name
Test status
Simulation time 70326350 ps
CPU time 0.95 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 205304 kb
Host smart-9cf09cf3-3f85-4842-aa5d-d60e1bfd2ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521560032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1521560032
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1384500605
Short name T470
Test name
Test status
Simulation time 80603314965 ps
CPU time 21.67 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:18:33 PM PDT 24
Peak memory 225992 kb
Host smart-62dafd47-da12-40b0-b7af-2e0476d02166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384500605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1384500605
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4234022608
Short name T138
Test name
Test status
Simulation time 43313205 ps
CPU time 0.76 seconds
Started May 30 01:18:12 PM PDT 24
Finished May 30 01:18:14 PM PDT 24
Peak memory 204244 kb
Host smart-13557a88-ff81-42fc-9367-5920ad5f65b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234022608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4234022608
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.439715270
Short name T601
Test name
Test status
Simulation time 878144753 ps
CPU time 3.59 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:18:16 PM PDT 24
Peak memory 218388 kb
Host smart-522f5413-1444-47fe-9d0e-8a97c23158d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439715270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.439715270
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3554715952
Short name T59
Test name
Test status
Simulation time 76254390 ps
CPU time 0.84 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:10 PM PDT 24
Peak memory 205908 kb
Host smart-2c68caa4-7826-4dfa-a240-9a19617bbd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554715952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3554715952
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1900470538
Short name T80
Test name
Test status
Simulation time 315733244568 ps
CPU time 572.05 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:27:43 PM PDT 24
Peak memory 265224 kb
Host smart-fc905897-48a9-451a-adb4-74c09edefc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900470538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1900470538
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2757811275
Short name T562
Test name
Test status
Simulation time 30945493256 ps
CPU time 278.99 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:22:50 PM PDT 24
Peak memory 253164 kb
Host smart-7c2b7881-4b38-4b11-b6d6-ce46d65696c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757811275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2757811275
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.490600708
Short name T817
Test name
Test status
Simulation time 51911555317 ps
CPU time 111.63 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:20:04 PM PDT 24
Peak memory 239544 kb
Host smart-870c655a-b999-4288-a447-c663f8ce831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490600708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.490600708
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2612761847
Short name T691
Test name
Test status
Simulation time 31976758 ps
CPU time 2.85 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:18:15 PM PDT 24
Peak memory 223276 kb
Host smart-3a115c91-7d5c-427f-8ecf-e62f84ef7cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612761847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2612761847
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3724948733
Short name T237
Test name
Test status
Simulation time 4893781652 ps
CPU time 13.23 seconds
Started May 30 01:18:17 PM PDT 24
Finished May 30 01:18:31 PM PDT 24
Peak memory 232352 kb
Host smart-adf93ed8-eab5-41b6-ad63-da9c78e57973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724948733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3724948733
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3306688359
Short name T727
Test name
Test status
Simulation time 27589293575 ps
CPU time 56.9 seconds
Started May 30 01:18:11 PM PDT 24
Finished May 30 01:19:10 PM PDT 24
Peak memory 233444 kb
Host smart-effb5d38-0dc8-4314-ad88-5227c840868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306688359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3306688359
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2122158187
Short name T210
Test name
Test status
Simulation time 598032187 ps
CPU time 10.63 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:18:22 PM PDT 24
Peak memory 237440 kb
Host smart-cb505d84-5452-4419-adf0-549199783eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122158187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2122158187
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3774652147
Short name T518
Test name
Test status
Simulation time 3757776455 ps
CPU time 8.47 seconds
Started May 30 01:18:10 PM PDT 24
Finished May 30 01:18:20 PM PDT 24
Peak memory 240012 kb
Host smart-34a1c67f-19c7-4a51-bb1d-9b3a065be5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774652147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3774652147
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3215199100
Short name T724
Test name
Test status
Simulation time 676919667 ps
CPU time 5.55 seconds
Started May 30 01:18:07 PM PDT 24
Finished May 30 01:18:15 PM PDT 24
Peak memory 220144 kb
Host smart-7d657069-8694-491c-a901-cdf6b995810f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3215199100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3215199100
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3542658388
Short name T186
Test name
Test status
Simulation time 16442317890 ps
CPU time 98.27 seconds
Started May 30 01:18:16 PM PDT 24
Finished May 30 01:19:55 PM PDT 24
Peak memory 235528 kb
Host smart-99156c1c-ddcf-4448-aac2-ea98649c55f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542658388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3542658388
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2311591327
Short name T321
Test name
Test status
Simulation time 5050768526 ps
CPU time 35.79 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:46 PM PDT 24
Peak memory 215912 kb
Host smart-fe07b58f-97f3-4949-bdde-b3107ac08024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311591327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2311591327
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2323937021
Short name T976
Test name
Test status
Simulation time 628666871 ps
CPU time 4.67 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:15 PM PDT 24
Peak memory 215816 kb
Host smart-e4e1e0fe-d4a3-4bfb-9b2f-3883319c517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323937021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2323937021
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1671309972
Short name T747
Test name
Test status
Simulation time 97771176 ps
CPU time 1.35 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 215964 kb
Host smart-4d220961-cb08-4a82-8978-df4db8faabcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671309972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1671309972
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3147418286
Short name T446
Test name
Test status
Simulation time 100809001 ps
CPU time 0.87 seconds
Started May 30 01:18:08 PM PDT 24
Finished May 30 01:18:11 PM PDT 24
Peak memory 205292 kb
Host smart-8f8af0e4-39dc-4a61-b16f-0fb41b7a9049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147418286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3147418286
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3996085428
Short name T196
Test name
Test status
Simulation time 3447790221 ps
CPU time 14.82 seconds
Started May 30 01:18:11 PM PDT 24
Finished May 30 01:18:28 PM PDT 24
Peak memory 234884 kb
Host smart-4cbc6c7f-09ee-4905-b104-e68b8ac774af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996085428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3996085428
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3086238573
Short name T767
Test name
Test status
Simulation time 15330099 ps
CPU time 0.73 seconds
Started May 30 01:18:27 PM PDT 24
Finished May 30 01:18:29 PM PDT 24
Peak memory 205240 kb
Host smart-7b9c6e3f-a201-40cc-9cac-b87cc1430927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086238573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3086238573
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2104713847
Short name T248
Test name
Test status
Simulation time 326912124 ps
CPU time 3.27 seconds
Started May 30 01:18:21 PM PDT 24
Finished May 30 01:18:25 PM PDT 24
Peak memory 233532 kb
Host smart-6070dbd9-7d49-4f26-8fef-9f8db2404cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104713847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2104713847
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.398580791
Short name T707
Test name
Test status
Simulation time 58737629 ps
CPU time 0.86 seconds
Started May 30 01:18:11 PM PDT 24
Finished May 30 01:18:14 PM PDT 24
Peak memory 206216 kb
Host smart-6a220884-e73f-4466-82c3-9963d75f35b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398580791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.398580791
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2610200502
Short name T920
Test name
Test status
Simulation time 30025163 ps
CPU time 0.74 seconds
Started May 30 01:18:20 PM PDT 24
Finished May 30 01:18:22 PM PDT 24
Peak memory 215320 kb
Host smart-71b9786a-e9e5-445d-8499-7546b59c882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610200502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2610200502
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4289462158
Short name T48
Test name
Test status
Simulation time 66172479672 ps
CPU time 225.12 seconds
Started May 30 01:18:22 PM PDT 24
Finished May 30 01:22:08 PM PDT 24
Peak memory 251680 kb
Host smart-c7bf2d26-6e58-4333-99b9-06718409a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289462158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4289462158
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1350233239
Short name T467
Test name
Test status
Simulation time 13702402642 ps
CPU time 44.3 seconds
Started May 30 01:18:30 PM PDT 24
Finished May 30 01:19:16 PM PDT 24
Peak memory 248832 kb
Host smart-27d0d1a6-6113-4f5a-a325-a596baea06c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350233239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1350233239
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1712578818
Short name T352
Test name
Test status
Simulation time 724915800 ps
CPU time 4.28 seconds
Started May 30 01:18:22 PM PDT 24
Finished May 30 01:18:27 PM PDT 24
Peak memory 224128 kb
Host smart-44ecfbc0-a1c2-43e0-b846-256ffaa5df1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712578818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1712578818
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.671338635
Short name T689
Test name
Test status
Simulation time 550293929 ps
CPU time 4.46 seconds
Started May 30 01:18:27 PM PDT 24
Finished May 30 01:18:33 PM PDT 24
Peak memory 218192 kb
Host smart-b44710d7-8a1d-40cd-abf4-374305b0b6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671338635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.671338635
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3536816991
Short name T463
Test name
Test status
Simulation time 54231921281 ps
CPU time 118.09 seconds
Started May 30 01:18:24 PM PDT 24
Finished May 30 01:20:24 PM PDT 24
Peak memory 248216 kb
Host smart-faf9958e-06d1-4dd8-b81a-7f289113e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536816991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3536816991
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1651795210
Short name T963
Test name
Test status
Simulation time 257556739 ps
CPU time 3.09 seconds
Started May 30 01:18:09 PM PDT 24
Finished May 30 01:18:15 PM PDT 24
Peak memory 232872 kb
Host smart-34f62f00-d739-43a0-a5b7-65244fff5402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651795210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1651795210
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.657625893
Short name T757
Test name
Test status
Simulation time 166455123 ps
CPU time 3.07 seconds
Started May 30 01:18:16 PM PDT 24
Finished May 30 01:18:20 PM PDT 24
Peak memory 232620 kb
Host smart-a1d27858-51d7-44b5-9fda-65c5ae9ab0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657625893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.657625893
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3645193016
Short name T394
Test name
Test status
Simulation time 1639780835 ps
CPU time 13.93 seconds
Started May 30 01:18:21 PM PDT 24
Finished May 30 01:18:36 PM PDT 24
Peak memory 222080 kb
Host smart-0604ff71-bd8b-4e52-9e6e-7d5cba700706
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3645193016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3645193016
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2485629106
Short name T197
Test name
Test status
Simulation time 49965441315 ps
CPU time 82 seconds
Started May 30 01:18:28 PM PDT 24
Finished May 30 01:19:51 PM PDT 24
Peak memory 248884 kb
Host smart-31142cf0-c5e4-4c41-bab3-e662e2129a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485629106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2485629106
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1469487502
Short name T890
Test name
Test status
Simulation time 848262023 ps
CPU time 12.36 seconds
Started May 30 01:18:17 PM PDT 24
Finished May 30 01:18:30 PM PDT 24
Peak memory 215844 kb
Host smart-c25c04a0-2643-4096-aff2-257623db5b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469487502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1469487502
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1399184091
Short name T471
Test name
Test status
Simulation time 9406854110 ps
CPU time 21.15 seconds
Started May 30 01:18:16 PM PDT 24
Finished May 30 01:18:38 PM PDT 24
Peak memory 215868 kb
Host smart-f4281b94-c739-46da-a1ef-b24aaca96e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399184091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1399184091
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2432553684
Short name T634
Test name
Test status
Simulation time 114478682 ps
CPU time 1.42 seconds
Started May 30 01:18:11 PM PDT 24
Finished May 30 01:18:14 PM PDT 24
Peak memory 215892 kb
Host smart-d673ac79-de3a-4f99-bd18-ff2008ffdbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432553684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2432553684
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.456048151
Short name T432
Test name
Test status
Simulation time 67296484 ps
CPU time 0.84 seconds
Started May 30 01:18:16 PM PDT 24
Finished May 30 01:18:17 PM PDT 24
Peak memory 205228 kb
Host smart-96d61d8f-048c-4556-8647-de2fb519a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456048151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.456048151
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.462236948
Short name T690
Test name
Test status
Simulation time 68379163 ps
CPU time 2.18 seconds
Started May 30 01:18:23 PM PDT 24
Finished May 30 01:18:26 PM PDT 24
Peak memory 212148 kb
Host smart-3a0e286d-ae82-4641-8a00-8315cf5fe8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462236948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.462236948
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1944785272
Short name T714
Test name
Test status
Simulation time 11340125 ps
CPU time 0.78 seconds
Started May 30 01:18:27 PM PDT 24
Finished May 30 01:18:28 PM PDT 24
Peak memory 204272 kb
Host smart-e73dee6a-c346-4a57-890b-c9f4c5e30a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944785272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1944785272
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2982861700
Short name T921
Test name
Test status
Simulation time 213458615 ps
CPU time 2.9 seconds
Started May 30 01:18:26 PM PDT 24
Finished May 30 01:18:30 PM PDT 24
Peak memory 234148 kb
Host smart-10114297-9585-46d3-84df-ec1fc5537b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982861700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2982861700
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3814819240
Short name T56
Test name
Test status
Simulation time 41140253 ps
CPU time 0.74 seconds
Started May 30 01:18:22 PM PDT 24
Finished May 30 01:18:23 PM PDT 24
Peak memory 204888 kb
Host smart-a5db8844-0bbe-48ee-a1c3-d2a887cb24ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814819240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3814819240
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3120981349
Short name T444
Test name
Test status
Simulation time 13147657970 ps
CPU time 28.25 seconds
Started May 30 01:18:26 PM PDT 24
Finished May 30 01:18:56 PM PDT 24
Peak memory 240612 kb
Host smart-aaf36282-cd11-4ba2-9a69-d49a7af79580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120981349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3120981349
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3248673610
Short name T262
Test name
Test status
Simulation time 12246347326 ps
CPU time 94.01 seconds
Started May 30 01:18:31 PM PDT 24
Finished May 30 01:20:06 PM PDT 24
Peak memory 249520 kb
Host smart-e437536f-c168-4d17-8a38-4883af6f127d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248673610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3248673610
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3912536598
Short name T771
Test name
Test status
Simulation time 3144761054 ps
CPU time 71.18 seconds
Started May 30 01:18:22 PM PDT 24
Finished May 30 01:19:34 PM PDT 24
Peak memory 257060 kb
Host smart-8b4d72b4-d332-4cd4-94fa-9572c8a7200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912536598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3912536598
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.831874079
Short name T316
Test name
Test status
Simulation time 22482622410 ps
CPU time 13.83 seconds
Started May 30 01:18:27 PM PDT 24
Finished May 30 01:18:42 PM PDT 24
Peak memory 248832 kb
Host smart-0f22e1c3-46a2-47d6-a533-e86795c7b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831874079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.831874079
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.953061245
Short name T743
Test name
Test status
Simulation time 1416848670 ps
CPU time 2.25 seconds
Started May 30 01:18:32 PM PDT 24
Finished May 30 01:18:35 PM PDT 24
Peak memory 215772 kb
Host smart-c35ac40d-5bcf-4bc0-8ba4-9652f78fbf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953061245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.953061245
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3015391281
Short name T274
Test name
Test status
Simulation time 141306961 ps
CPU time 5.11 seconds
Started May 30 01:18:24 PM PDT 24
Finished May 30 01:18:31 PM PDT 24
Peak memory 233560 kb
Host smart-104300a0-c407-4276-a45b-0c0bc1e239fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015391281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3015391281
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1303595909
Short name T524
Test name
Test status
Simulation time 399730762 ps
CPU time 3.04 seconds
Started May 30 01:18:29 PM PDT 24
Finished May 30 01:18:33 PM PDT 24
Peak memory 232364 kb
Host smart-e73c45b4-f0ce-4eb2-9b73-75ce6e21a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303595909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1303595909
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3855157457
Short name T851
Test name
Test status
Simulation time 46584392277 ps
CPU time 30.36 seconds
Started May 30 01:18:29 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 217660 kb
Host smart-433451b0-cf34-4e5c-8f2a-35c5757589fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855157457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3855157457
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2360041594
Short name T784
Test name
Test status
Simulation time 16620486324 ps
CPU time 12.38 seconds
Started May 30 01:18:26 PM PDT 24
Finished May 30 01:18:39 PM PDT 24
Peak memory 222204 kb
Host smart-d3f82a97-3ac0-4f39-8a55-1deee7976b46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2360041594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2360041594
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1956721810
Short name T530
Test name
Test status
Simulation time 1394312133 ps
CPU time 8.52 seconds
Started May 30 01:18:31 PM PDT 24
Finished May 30 01:18:41 PM PDT 24
Peak memory 215876 kb
Host smart-473c4001-922f-4f4f-b405-e2cba6dc305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956721810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1956721810
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2929427991
Short name T531
Test name
Test status
Simulation time 735082930 ps
CPU time 5.07 seconds
Started May 30 01:18:25 PM PDT 24
Finished May 30 01:18:31 PM PDT 24
Peak memory 215684 kb
Host smart-a3d9bd48-c10f-4442-8e89-082bad263186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929427991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2929427991
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3881596054
Short name T17
Test name
Test status
Simulation time 521765359 ps
CPU time 10.62 seconds
Started May 30 01:18:27 PM PDT 24
Finished May 30 01:18:39 PM PDT 24
Peak memory 215880 kb
Host smart-024f4c56-8255-4692-883e-f5695f87d4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881596054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3881596054
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.724246945
Short name T573
Test name
Test status
Simulation time 25959409 ps
CPU time 0.83 seconds
Started May 30 01:18:29 PM PDT 24
Finished May 30 01:18:30 PM PDT 24
Peak memory 205280 kb
Host smart-f1cd2921-e212-4b46-a8de-4592638c0011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724246945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.724246945
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2813529531
Short name T754
Test name
Test status
Simulation time 1318948896 ps
CPU time 5.19 seconds
Started May 30 01:18:29 PM PDT 24
Finished May 30 01:18:35 PM PDT 24
Peak memory 225796 kb
Host smart-7a5a4fe1-4c0f-4b62-b84a-bc769ceb3b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813529531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2813529531
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1431729976
Short name T744
Test name
Test status
Simulation time 14041517 ps
CPU time 0.71 seconds
Started May 30 01:18:26 PM PDT 24
Finished May 30 01:18:28 PM PDT 24
Peak memory 204280 kb
Host smart-6b77e217-04b4-4f0b-b5de-a4e6ee2a7da6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431729976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1431729976
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1145059731
Short name T30
Test name
Test status
Simulation time 203109263 ps
CPU time 4.62 seconds
Started May 30 01:18:28 PM PDT 24
Finished May 30 01:18:34 PM PDT 24
Peak memory 219480 kb
Host smart-6d47eae6-be1a-430d-99b3-a7f9bec25759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145059731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1145059731
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2759564498
Short name T364
Test name
Test status
Simulation time 18585717 ps
CPU time 0.75 seconds
Started May 30 01:18:23 PM PDT 24
Finished May 30 01:18:25 PM PDT 24
Peak memory 204868 kb
Host smart-ff390dc2-3efc-4bca-a57c-f676a2ee001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759564498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2759564498
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1985974005
Short name T775
Test name
Test status
Simulation time 26549569771 ps
CPU time 148.86 seconds
Started May 30 01:18:24 PM PDT 24
Finished May 30 01:20:53 PM PDT 24
Peak memory 248788 kb
Host smart-a05dd598-1a24-49c7-9207-5352fd89ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985974005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1985974005
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1039728537
Short name T8
Test name
Test status
Simulation time 39474243706 ps
CPU time 46.73 seconds
Started May 30 01:18:22 PM PDT 24
Finished May 30 01:19:10 PM PDT 24
Peak memory 236712 kb
Host smart-6008d043-84cd-4527-982c-43e5fe6ffca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039728537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1039728537
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1367704370
Short name T29
Test name
Test status
Simulation time 8744017402 ps
CPU time 146.2 seconds
Started May 30 01:18:25 PM PDT 24
Finished May 30 01:20:52 PM PDT 24
Peak memory 255988 kb
Host smart-81c61abb-99b2-4e22-9981-1ee202b3e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367704370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1367704370
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_intercept.255050952
Short name T192
Test name
Test status
Simulation time 1065259891 ps
CPU time 14.43 seconds
Started May 30 01:18:25 PM PDT 24
Finished May 30 01:18:40 PM PDT 24
Peak memory 218092 kb
Host smart-fa56a786-9bf2-4bc8-a6c4-87e0bf062797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255050952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.255050952
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3574115069
Short name T894
Test name
Test status
Simulation time 6116541558 ps
CPU time 46.73 seconds
Started May 30 01:18:30 PM PDT 24
Finished May 30 01:19:18 PM PDT 24
Peak memory 218288 kb
Host smart-d456f4df-0b90-459c-b405-721a54e60f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574115069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3574115069
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1350091385
Short name T709
Test name
Test status
Simulation time 236600239 ps
CPU time 3.45 seconds
Started May 30 01:18:31 PM PDT 24
Finished May 30 01:18:36 PM PDT 24
Peak memory 232832 kb
Host smart-83381aef-579a-4832-b381-d4723a1718f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350091385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1350091385
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3642129868
Short name T627
Test name
Test status
Simulation time 5587960945 ps
CPU time 17.55 seconds
Started May 30 01:18:25 PM PDT 24
Finished May 30 01:18:43 PM PDT 24
Peak memory 222116 kb
Host smart-fe4622dc-601e-48ed-a813-eb51473a9a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642129868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3642129868
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2164558031
Short name T386
Test name
Test status
Simulation time 185579315 ps
CPU time 5.31 seconds
Started May 30 01:18:27 PM PDT 24
Finished May 30 01:18:34 PM PDT 24
Peak memory 222044 kb
Host smart-81ab455e-7da0-43a2-a7e7-c7f36415ec16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2164558031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2164558031
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3672929245
Short name T776
Test name
Test status
Simulation time 34731861 ps
CPU time 0.97 seconds
Started May 30 01:18:24 PM PDT 24
Finished May 30 01:18:26 PM PDT 24
Peak memory 206232 kb
Host smart-ddf246e1-b629-44e0-aa99-4bbc3f5bbeff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672929245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3672929245
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2190228523
Short name T934
Test name
Test status
Simulation time 12520483149 ps
CPU time 13.34 seconds
Started May 30 01:18:30 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 215976 kb
Host smart-f928cb5a-53cd-4efe-ac1e-bf6654d15ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190228523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2190228523
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.591913086
Short name T889
Test name
Test status
Simulation time 2401896489 ps
CPU time 7.1 seconds
Started May 30 01:18:23 PM PDT 24
Finished May 30 01:18:31 PM PDT 24
Peak memory 215828 kb
Host smart-57f0b33c-49ec-47c0-988b-03dd2f582ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591913086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.591913086
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2447486879
Short name T641
Test name
Test status
Simulation time 132455681 ps
CPU time 1.67 seconds
Started May 30 01:18:23 PM PDT 24
Finished May 30 01:18:26 PM PDT 24
Peak memory 215864 kb
Host smart-cb4da6e7-061c-4599-bbad-511dd91bad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447486879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2447486879
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3234739563
Short name T884
Test name
Test status
Simulation time 52710687 ps
CPU time 0.73 seconds
Started May 30 01:18:23 PM PDT 24
Finished May 30 01:18:25 PM PDT 24
Peak memory 205292 kb
Host smart-47ff18bc-1a66-4e08-b59c-c6a0e277bdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234739563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3234739563
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2836355651
Short name T331
Test name
Test status
Simulation time 77110850 ps
CPU time 2.3 seconds
Started May 30 01:18:25 PM PDT 24
Finished May 30 01:18:28 PM PDT 24
Peak memory 207524 kb
Host smart-603260e0-a098-4879-9a11-6df048fa7a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836355651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2836355651
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3640898111
Short name T458
Test name
Test status
Simulation time 12875425 ps
CPU time 0.75 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:41 PM PDT 24
Peak memory 204916 kb
Host smart-8904d86e-bd99-40f6-b5a7-b14b044236d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640898111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3640898111
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2251865961
Short name T943
Test name
Test status
Simulation time 2813177785 ps
CPU time 5.91 seconds
Started May 30 01:18:36 PM PDT 24
Finished May 30 01:18:43 PM PDT 24
Peak memory 233192 kb
Host smart-9c1b5e02-b4a5-4163-8dfb-568e9bce967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251865961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2251865961
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1338941232
Short name T367
Test name
Test status
Simulation time 18560524 ps
CPU time 0.73 seconds
Started May 30 01:18:23 PM PDT 24
Finished May 30 01:18:24 PM PDT 24
Peak memory 204884 kb
Host smart-9156152e-374a-4f88-b0fb-e2d26242dbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338941232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1338941232
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2108357588
Short name T170
Test name
Test status
Simulation time 5501473261 ps
CPU time 19.43 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:57 PM PDT 24
Peak memory 232444 kb
Host smart-59c2ca04-220a-4a30-9e7a-7f6ff2d2e77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108357588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2108357588
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2276045598
Short name T588
Test name
Test status
Simulation time 1640653582 ps
CPU time 21.95 seconds
Started May 30 01:18:24 PM PDT 24
Finished May 30 01:18:47 PM PDT 24
Peak memory 218192 kb
Host smart-54f5ad67-ad00-450b-999b-96cb9c3c48e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276045598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2276045598
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.19810188
Short name T794
Test name
Test status
Simulation time 2131240538 ps
CPU time 18.08 seconds
Started May 30 01:18:30 PM PDT 24
Finished May 30 01:18:49 PM PDT 24
Peak memory 235080 kb
Host smart-8ae64c42-6722-4b14-bb28-2d7bbef413c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19810188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.19810188
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3059582015
Short name T952
Test name
Test status
Simulation time 279196374 ps
CPU time 3.16 seconds
Started May 30 01:18:27 PM PDT 24
Finished May 30 01:18:31 PM PDT 24
Peak memory 233780 kb
Host smart-28105e5d-c908-49f7-b5f8-a5e6f5bac531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059582015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3059582015
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2239910637
Short name T931
Test name
Test status
Simulation time 1058914465 ps
CPU time 4.66 seconds
Started May 30 01:18:28 PM PDT 24
Finished May 30 01:18:33 PM PDT 24
Peak memory 235956 kb
Host smart-278d7a69-6b79-4c63-8ef7-d047f82de637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239910637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2239910637
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.791915916
Short name T351
Test name
Test status
Simulation time 546055492 ps
CPU time 4.89 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 222552 kb
Host smart-a4278221-a202-4b29-ad37-5f8085e9d253
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=791915916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.791915916
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1247203629
Short name T190
Test name
Test status
Simulation time 26028987060 ps
CPU time 160.23 seconds
Started May 30 01:18:35 PM PDT 24
Finished May 30 01:21:16 PM PDT 24
Peak memory 249532 kb
Host smart-da8f2c08-b66d-4a23-98d4-917cef84b231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247203629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1247203629
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2817854356
Short name T787
Test name
Test status
Simulation time 4892618491 ps
CPU time 27.94 seconds
Started May 30 01:18:28 PM PDT 24
Finished May 30 01:18:57 PM PDT 24
Peak memory 215948 kb
Host smart-d9778c3a-76bc-4f7e-8e47-d9d5bd903dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817854356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2817854356
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.233951823
Short name T866
Test name
Test status
Simulation time 3823573853 ps
CPU time 3.89 seconds
Started May 30 01:18:24 PM PDT 24
Finished May 30 01:18:30 PM PDT 24
Peak memory 215652 kb
Host smart-28f7ace9-cb6f-4d0a-9ddd-728b0138f7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233951823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.233951823
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4195999336
Short name T4
Test name
Test status
Simulation time 119142375 ps
CPU time 1.94 seconds
Started May 30 01:18:24 PM PDT 24
Finished May 30 01:18:26 PM PDT 24
Peak memory 215908 kb
Host smart-6926f1ff-87e5-4c00-87bb-290770dc6d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195999336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4195999336
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.834611561
Short name T399
Test name
Test status
Simulation time 47704898 ps
CPU time 0.86 seconds
Started May 30 01:18:31 PM PDT 24
Finished May 30 01:18:33 PM PDT 24
Peak memory 206260 kb
Host smart-893e6023-eac5-4df1-a589-aac0b19a8199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834611561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.834611561
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.184661900
Short name T239
Test name
Test status
Simulation time 25014284028 ps
CPU time 37.49 seconds
Started May 30 01:18:25 PM PDT 24
Finished May 30 01:19:03 PM PDT 24
Peak memory 233552 kb
Host smart-73c4f696-091a-4b12-b35b-563ed1408da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184661900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.184661900
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1789084494
Short name T410
Test name
Test status
Simulation time 38083885 ps
CPU time 0.68 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:18:41 PM PDT 24
Peak memory 204928 kb
Host smart-827d9c8f-d3ed-4efc-9119-0bb289f5c65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789084494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1789084494
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3690737305
Short name T413
Test name
Test status
Simulation time 2592672288 ps
CPU time 20.89 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 224152 kb
Host smart-ebb91792-44ee-4bac-bd4f-608f8003bc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690737305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3690737305
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2704156050
Short name T854
Test name
Test status
Simulation time 27139677 ps
CPU time 0.75 seconds
Started May 30 01:18:35 PM PDT 24
Finished May 30 01:18:36 PM PDT 24
Peak memory 205144 kb
Host smart-97ddb722-14ce-42ae-8b1d-af2cbc0348a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704156050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2704156050
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.664763764
Short name T869
Test name
Test status
Simulation time 23004680790 ps
CPU time 27.44 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:19:07 PM PDT 24
Peak memory 233480 kb
Host smart-f8a9559a-3738-46be-b3bb-7aeac8eb8f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664763764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.664763764
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.165286235
Short name T219
Test name
Test status
Simulation time 61439599129 ps
CPU time 610.85 seconds
Started May 30 01:18:36 PM PDT 24
Finished May 30 01:28:48 PM PDT 24
Peak memory 256668 kb
Host smart-c458ab08-2b61-49ed-a623-0ac488a5578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165286235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.165286235
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.745948644
Short name T574
Test name
Test status
Simulation time 239557803 ps
CPU time 3.9 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:42 PM PDT 24
Peak memory 224100 kb
Host smart-21c59fea-d0ee-4f86-a562-aced36b1e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745948644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.745948644
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1986851876
Short name T259
Test name
Test status
Simulation time 1448486522 ps
CPU time 13.38 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:18:54 PM PDT 24
Peak memory 234012 kb
Host smart-6a0db39d-9ba1-454c-adc8-6f428d03b33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986851876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1986851876
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2922853744
Short name T275
Test name
Test status
Simulation time 2332163143 ps
CPU time 6.29 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 224212 kb
Host smart-6b2e9aca-8b64-4146-bc46-bcd0d139075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922853744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2922853744
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.41234957
Short name T227
Test name
Test status
Simulation time 659407414 ps
CPU time 4.25 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:18:47 PM PDT 24
Peak memory 233308 kb
Host smart-72c686e3-3f8d-4b59-b8e1-afcb1cf3d3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41234957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.41234957
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.669334580
Short name T547
Test name
Test status
Simulation time 1419702708 ps
CPU time 5.76 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:18:46 PM PDT 24
Peak memory 218124 kb
Host smart-75d58c48-030c-447d-a528-ef2a0eab45f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669334580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.669334580
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2326697579
Short name T145
Test name
Test status
Simulation time 300268268 ps
CPU time 3.86 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 221996 kb
Host smart-1c2910df-8b1f-4679-bb8f-b9a00d9ecf6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2326697579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2326697579
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3833920563
Short name T893
Test name
Test status
Simulation time 39479450375 ps
CPU time 351.4 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:24:34 PM PDT 24
Peak memory 268028 kb
Host smart-d366712c-4a70-4a00-8ee4-42216c0ce424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833920563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3833920563
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3170886907
Short name T523
Test name
Test status
Simulation time 38978912603 ps
CPU time 41.54 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:19:22 PM PDT 24
Peak memory 214920 kb
Host smart-79024944-4bf1-41a4-a4e4-3f687ee5adb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170886907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3170886907
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4100097732
Short name T589
Test name
Test status
Simulation time 1121753965 ps
CPU time 6.77 seconds
Started May 30 01:18:35 PM PDT 24
Finished May 30 01:18:43 PM PDT 24
Peak memory 215832 kb
Host smart-de27dad1-b317-4269-89db-666225e98c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100097732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4100097732
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3392790410
Short name T359
Test name
Test status
Simulation time 124167110 ps
CPU time 1.69 seconds
Started May 30 01:18:36 PM PDT 24
Finished May 30 01:18:38 PM PDT 24
Peak memory 215928 kb
Host smart-52e1f1c6-0839-4a8c-8390-86b2fec042e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392790410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3392790410
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2639116663
Short name T375
Test name
Test status
Simulation time 69613716 ps
CPU time 0.8 seconds
Started May 30 01:18:35 PM PDT 24
Finished May 30 01:18:37 PM PDT 24
Peak memory 205296 kb
Host smart-b72989b4-2fa3-4257-8a31-3661c46affeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639116663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2639116663
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2388048205
Short name T425
Test name
Test status
Simulation time 3308255193 ps
CPU time 12.61 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:18:56 PM PDT 24
Peak memory 218584 kb
Host smart-350c3085-3920-42ce-8bc0-07bcb37f9c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388048205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2388048205
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3504418813
Short name T1
Test name
Test status
Simulation time 11187903 ps
CPU time 0.72 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:39 PM PDT 24
Peak memory 204268 kb
Host smart-d07d5a26-c357-49a1-a366-7bb8cd1c21e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504418813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3504418813
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4135979768
Short name T277
Test name
Test status
Simulation time 1248953337 ps
CPU time 18.48 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:19:01 PM PDT 24
Peak memory 221136 kb
Host smart-ee9b8230-8721-4dcd-b214-6da470f753ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135979768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4135979768
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2772962957
Short name T883
Test name
Test status
Simulation time 35896277 ps
CPU time 0.73 seconds
Started May 30 01:18:36 PM PDT 24
Finished May 30 01:18:37 PM PDT 24
Peak memory 205244 kb
Host smart-b8c67a24-fdd5-4a1b-bebd-24a612979eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772962957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2772962957
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3324377021
Short name T670
Test name
Test status
Simulation time 24291453262 ps
CPU time 178.99 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:21:42 PM PDT 24
Peak memory 249012 kb
Host smart-b6fce254-135a-4aa6-897d-8595a59da568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324377021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3324377021
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.329521533
Short name T896
Test name
Test status
Simulation time 24375076350 ps
CPU time 136.86 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:20:56 PM PDT 24
Peak memory 249696 kb
Host smart-206ca78d-441a-40e3-9642-a688af51bfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329521533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.329521533
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1683700834
Short name T962
Test name
Test status
Simulation time 6349208926 ps
CPU time 52.65 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:19:30 PM PDT 24
Peak memory 240588 kb
Host smart-fa86f564-5201-4f42-a853-fd99ad30d175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683700834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1683700834
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.130641351
Short name T318
Test name
Test status
Simulation time 8018161373 ps
CPU time 49.66 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:19:32 PM PDT 24
Peak memory 252912 kb
Host smart-6a524a6b-59db-439d-af23-66173d501554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130641351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.130641351
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3566258646
Short name T211
Test name
Test status
Simulation time 470535471 ps
CPU time 7.35 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:47 PM PDT 24
Peak memory 233080 kb
Host smart-b36696ae-d33a-4111-bad9-7ae407089b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566258646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3566258646
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.774858430
Short name T223
Test name
Test status
Simulation time 1843351144 ps
CPU time 11.16 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:50 PM PDT 24
Peak memory 239136 kb
Host smart-b2dd644f-279c-4d72-a79e-2b4b586defcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774858430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.774858430
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3663327233
Short name T295
Test name
Test status
Simulation time 31023658865 ps
CPU time 15.52 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:54 PM PDT 24
Peak memory 221284 kb
Host smart-a302f473-0952-4d97-9aed-a243002f72b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663327233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3663327233
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.947864836
Short name T285
Test name
Test status
Simulation time 1860511180 ps
CPU time 7.99 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:46 PM PDT 24
Peak memory 233184 kb
Host smart-e7cab6a1-8f87-41fb-a418-6c3650faee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947864836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.947864836
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2905505220
Short name T941
Test name
Test status
Simulation time 2014201304 ps
CPU time 11.39 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:51 PM PDT 24
Peak memory 218868 kb
Host smart-14abe2d2-572c-4b95-89ed-123c02e81bdb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2905505220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2905505220
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3931694749
Short name T529
Test name
Test status
Simulation time 10749546807 ps
CPU time 25.51 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:19:08 PM PDT 24
Peak memory 215944 kb
Host smart-e41066b5-bc4d-47b3-be72-8afdaa1de84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931694749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3931694749
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3322098483
Short name T669
Test name
Test status
Simulation time 5085768171 ps
CPU time 8.13 seconds
Started May 30 01:18:40 PM PDT 24
Finished May 30 01:18:50 PM PDT 24
Peak memory 215852 kb
Host smart-ca501ff2-7a18-4a96-ae6f-511b6e12da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322098483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3322098483
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3888454068
Short name T745
Test name
Test status
Simulation time 90110078 ps
CPU time 0.98 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 206784 kb
Host smart-109e3274-0cd2-490e-81cd-042f63e96824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888454068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3888454068
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2148698710
Short name T848
Test name
Test status
Simulation time 40979426 ps
CPU time 0.74 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:39 PM PDT 24
Peak memory 205288 kb
Host smart-e82b4075-9619-4962-92dc-7769cd58848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148698710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2148698710
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.491557506
Short name T874
Test name
Test status
Simulation time 2205819234 ps
CPU time 7.35 seconds
Started May 30 01:18:36 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 233200 kb
Host smart-51c2d7cd-ef2b-44eb-b9af-905105240dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491557506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.491557506
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2645955900
Short name T449
Test name
Test status
Simulation time 42559233 ps
CPU time 0.7 seconds
Started May 30 01:18:40 PM PDT 24
Finished May 30 01:18:42 PM PDT 24
Peak memory 204888 kb
Host smart-b3088723-a453-4ec0-920e-9129c2080b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645955900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2645955900
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1591658646
Short name T875
Test name
Test status
Simulation time 682281158 ps
CPU time 3.1 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:18:43 PM PDT 24
Peak memory 219088 kb
Host smart-36358dd7-03c3-4afd-81bd-4191ac4569aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591658646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1591658646
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.57382985
Short name T830
Test name
Test status
Simulation time 27545990 ps
CPU time 0.69 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:39 PM PDT 24
Peak memory 205224 kb
Host smart-e5a57dc6-b40d-4fee-9d97-c11ee93be0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57382985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.57382985
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.946397345
Short name T222
Test name
Test status
Simulation time 63088350817 ps
CPU time 119 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:20:42 PM PDT 24
Peak memory 248780 kb
Host smart-cc6be28d-b926-4c31-a776-c9ba29a2c359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946397345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.946397345
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1383705525
Short name T926
Test name
Test status
Simulation time 39306408967 ps
CPU time 143.25 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:21:03 PM PDT 24
Peak memory 247824 kb
Host smart-217941af-b2bf-4488-a82f-89720929ecee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383705525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1383705525
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.4259538781
Short name T418
Test name
Test status
Simulation time 16046045477 ps
CPU time 74.5 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:19:55 PM PDT 24
Peak memory 249804 kb
Host smart-14f402e4-fc9d-4d6b-a87c-d45d04fd62b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259538781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.4259538781
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.993497382
Short name T695
Test name
Test status
Simulation time 5114828440 ps
CPU time 9.74 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:18:53 PM PDT 24
Peak memory 232736 kb
Host smart-3e32a53f-e17e-4d89-8064-761743cccd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993497382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.993497382
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3231892695
Short name T753
Test name
Test status
Simulation time 100840558 ps
CPU time 4.46 seconds
Started May 30 01:18:36 PM PDT 24
Finished May 30 01:18:42 PM PDT 24
Peak memory 234056 kb
Host smart-09c74cdd-9dd2-4c2d-82e7-aa32f98e4b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231892695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3231892695
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1021235307
Short name T172
Test name
Test status
Simulation time 16144281553 ps
CPU time 208.98 seconds
Started May 30 01:18:42 PM PDT 24
Finished May 30 01:22:12 PM PDT 24
Peak memory 232072 kb
Host smart-32aa6b4f-8503-4873-9a8d-817778c3f029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021235307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1021235307
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2731113822
Short name T975
Test name
Test status
Simulation time 1432502381 ps
CPU time 6.92 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:46 PM PDT 24
Peak memory 217464 kb
Host smart-c160622b-7867-4791-bd7c-66b2407a61ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731113822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2731113822
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2281170362
Short name T607
Test name
Test status
Simulation time 1693163296 ps
CPU time 5.45 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:43 PM PDT 24
Peak memory 232384 kb
Host smart-f81b541a-0e98-4947-94bf-8e4d47533061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281170362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2281170362
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1364177695
Short name T361
Test name
Test status
Simulation time 1652004398 ps
CPU time 5.55 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:46 PM PDT 24
Peak memory 222768 kb
Host smart-a46ae7e1-f8c5-42e8-bbb2-9b4579b01254
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364177695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1364177695
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.277515494
Short name T64
Test name
Test status
Simulation time 3999637437 ps
CPU time 30.88 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:19:11 PM PDT 24
Peak memory 224320 kb
Host smart-ad85a749-da33-4c69-b349-16059c777c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277515494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.277515494
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2127398651
Short name T478
Test name
Test status
Simulation time 17082320385 ps
CPU time 48.26 seconds
Started May 30 01:18:36 PM PDT 24
Finished May 30 01:19:25 PM PDT 24
Peak memory 215956 kb
Host smart-12c575df-84d5-49e5-b0fb-297d79ddcf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127398651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2127398651
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.344854972
Short name T953
Test name
Test status
Simulation time 921507367 ps
CPU time 6.26 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:18:49 PM PDT 24
Peak memory 215776 kb
Host smart-f88533fc-42ff-407d-83e5-25e2bd0ffe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344854972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.344854972
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3523488801
Short name T382
Test name
Test status
Simulation time 63465014 ps
CPU time 3.45 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:43 PM PDT 24
Peak memory 215912 kb
Host smart-27ac6ca2-7255-4150-9d60-7f49ef0a9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523488801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3523488801
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3176958950
Short name T805
Test name
Test status
Simulation time 37894837 ps
CPU time 0.81 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:18:41 PM PDT 24
Peak memory 205248 kb
Host smart-b6fd2484-67c3-4819-86c8-3cb190739f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176958950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3176958950
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.472195867
Short name T685
Test name
Test status
Simulation time 4307333197 ps
CPU time 5.91 seconds
Started May 30 01:18:40 PM PDT 24
Finished May 30 01:18:47 PM PDT 24
Peak memory 217064 kb
Host smart-69e16297-a84b-42ab-bb99-705886a8ce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472195867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.472195867
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2748889974
Short name T629
Test name
Test status
Simulation time 52036356 ps
CPU time 0.74 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:18:55 PM PDT 24
Peak memory 205260 kb
Host smart-2dc8065e-f594-43f6-a803-e3d5445ae090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748889974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2748889974
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1166500995
Short name T88
Test name
Test status
Simulation time 662652493 ps
CPU time 7.01 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 234048 kb
Host smart-582d1265-17a3-41ad-ad6a-0c695da79113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166500995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1166500995
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.315048009
Short name T370
Test name
Test status
Simulation time 65853015 ps
CPU time 0.8 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:18:44 PM PDT 24
Peak memory 205908 kb
Host smart-454eb42f-d7f6-4bf2-b11d-4dbac5ff4f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315048009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.315048009
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1491467026
Short name T301
Test name
Test status
Simulation time 2617319541 ps
CPU time 35.27 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:19:30 PM PDT 24
Peak memory 224192 kb
Host smart-60682cfa-6f56-419c-a97f-44f79f0b2e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491467026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1491467026
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.662165208
Short name T327
Test name
Test status
Simulation time 24330653286 ps
CPU time 29.85 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:25 PM PDT 24
Peak memory 217108 kb
Host smart-cbeb8ec2-aee0-4819-8f85-9d155efcc5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662165208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.662165208
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1707903327
Short name T827
Test name
Test status
Simulation time 113253661500 ps
CPU time 344.44 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:24:38 PM PDT 24
Peak memory 252520 kb
Host smart-614b8086-61ab-492c-91be-c49f6974859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707903327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1707903327
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2452653670
Short name T144
Test name
Test status
Simulation time 9103849500 ps
CPU time 33.19 seconds
Started May 30 01:18:51 PM PDT 24
Finished May 30 01:19:26 PM PDT 24
Peak memory 232464 kb
Host smart-1b4224ae-238a-4010-a607-cf847ab7bab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452653670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2452653670
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3486255800
Short name T638
Test name
Test status
Simulation time 232697270 ps
CPU time 4.9 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:45 PM PDT 24
Peak memory 233368 kb
Host smart-4d3d760f-cd9b-4605-a25c-f6fffed4a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486255800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3486255800
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.553799287
Short name T910
Test name
Test status
Simulation time 4420133057 ps
CPU time 25.99 seconds
Started May 30 01:18:35 PM PDT 24
Finished May 30 01:19:02 PM PDT 24
Peak memory 218368 kb
Host smart-7cc68843-fdf2-43de-b210-cfbe28ee49b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553799287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.553799287
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1813282324
Short name T161
Test name
Test status
Simulation time 327010950 ps
CPU time 6.09 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:45 PM PDT 24
Peak memory 216324 kb
Host smart-c9d211a5-d6c3-43ec-80d2-b5851cf167b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813282324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1813282324
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2284374091
Short name T752
Test name
Test status
Simulation time 77242707 ps
CPU time 2.45 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:18:43 PM PDT 24
Peak memory 233316 kb
Host smart-498e99d0-aea7-4f64-a2f3-3238b0ae57df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284374091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2284374091
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.548611037
Short name T486
Test name
Test status
Simulation time 4715361956 ps
CPU time 11.95 seconds
Started May 30 01:18:51 PM PDT 24
Finished May 30 01:19:04 PM PDT 24
Peak memory 222352 kb
Host smart-fa46c5e9-8571-47e5-bd36-a7f6c082ed47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=548611037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.548611037
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1920052011
Short name T750
Test name
Test status
Simulation time 3523665871 ps
CPU time 34.17 seconds
Started May 30 01:18:41 PM PDT 24
Finished May 30 01:19:17 PM PDT 24
Peak memory 216036 kb
Host smart-5a6476af-2454-40f4-b852-fbd1e4e9ba44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920052011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1920052011
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1604730263
Short name T383
Test name
Test status
Simulation time 2817404620 ps
CPU time 5.66 seconds
Started May 30 01:18:38 PM PDT 24
Finished May 30 01:18:46 PM PDT 24
Peak memory 215940 kb
Host smart-bfa4161b-a48b-46e3-82ba-ee6aa682169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604730263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1604730263
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.729095094
Short name T667
Test name
Test status
Simulation time 22001605 ps
CPU time 1.24 seconds
Started May 30 01:18:39 PM PDT 24
Finished May 30 01:18:42 PM PDT 24
Peak memory 207340 kb
Host smart-ef46441c-5993-4e66-8446-d1ab63cf279a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729095094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.729095094
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.628378920
Short name T885
Test name
Test status
Simulation time 173954305 ps
CPU time 0.74 seconds
Started May 30 01:18:37 PM PDT 24
Finished May 30 01:18:40 PM PDT 24
Peak memory 205224 kb
Host smart-dbdaceb3-8ff4-400e-b7e8-9947bc676e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628378920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.628378920
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1543096771
Short name T485
Test name
Test status
Simulation time 11793495749 ps
CPU time 21.26 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:17 PM PDT 24
Peak memory 219160 kb
Host smart-f991fa55-4386-49a1-bfc7-00eeb88360b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543096771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1543096771
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1761224789
Short name T560
Test name
Test status
Simulation time 29947802 ps
CPU time 0.73 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:16:43 PM PDT 24
Peak memory 204276 kb
Host smart-bc850440-2709-4f3b-8fec-e0874207a0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761224789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
761224789
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2650594916
Short name T401
Test name
Test status
Simulation time 1817669304 ps
CPU time 3.06 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:29 PM PDT 24
Peak memory 232408 kb
Host smart-ab265ba9-3805-4e50-9dd0-a3619c85d5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650594916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2650594916
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3025062024
Short name T849
Test name
Test status
Simulation time 28552216 ps
CPU time 0.77 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:27 PM PDT 24
Peak memory 204868 kb
Host smart-85f015b3-1f0a-475a-8e6c-b890f8b339ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025062024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3025062024
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.808487644
Short name T79
Test name
Test status
Simulation time 13402232393 ps
CPU time 80.18 seconds
Started May 30 01:16:38 PM PDT 24
Finished May 30 01:17:59 PM PDT 24
Peak memory 248868 kb
Host smart-520f08ee-450f-4e0f-85e4-22f748f14c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808487644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.808487644
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3012867071
Short name T429
Test name
Test status
Simulation time 1419965225 ps
CPU time 6.94 seconds
Started May 30 01:16:42 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 217084 kb
Host smart-deaccbca-ae9e-43f6-9a50-ee5bcc3f8748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012867071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3012867071
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.506728
Short name T628
Test name
Test status
Simulation time 272504051 ps
CPU time 11.97 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:35 PM PDT 24
Peak memory 240592 kb
Host smart-4e3eaad9-eb85-4286-9f53-703f843bf376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.506728
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4103446260
Short name T224
Test name
Test status
Simulation time 512555070 ps
CPU time 5.9 seconds
Started May 30 01:16:25 PM PDT 24
Finished May 30 01:16:32 PM PDT 24
Peak memory 233264 kb
Host smart-6728e46b-b2a0-4ae9-b67b-5124714cd8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103446260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4103446260
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1530022788
Short name T465
Test name
Test status
Simulation time 108757295 ps
CPU time 2.59 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:27 PM PDT 24
Peak memory 221080 kb
Host smart-19067cdc-8221-46ea-8447-a5bb75061611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530022788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1530022788
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2842327734
Short name T21
Test name
Test status
Simulation time 61724181 ps
CPU time 1.06 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:25 PM PDT 24
Peak memory 216208 kb
Host smart-e0282f64-70b1-473f-b42b-093a3d38dc0c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842327734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2842327734
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.654230106
Short name T698
Test name
Test status
Simulation time 1917937323 ps
CPU time 12.69 seconds
Started May 30 01:16:22 PM PDT 24
Finished May 30 01:16:36 PM PDT 24
Peak memory 227864 kb
Host smart-4138ea1e-cfe4-4e54-9d94-58a690f2e7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654230106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
654230106
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.569651270
Short name T700
Test name
Test status
Simulation time 257541118 ps
CPU time 3.03 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:28 PM PDT 24
Peak memory 218540 kb
Host smart-4fda9ebf-43d4-4bd9-8690-3f347616f4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569651270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.569651270
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1536351838
Short name T658
Test name
Test status
Simulation time 1746059637 ps
CPU time 21.51 seconds
Started May 30 01:16:26 PM PDT 24
Finished May 30 01:16:49 PM PDT 24
Peak memory 218456 kb
Host smart-6a29925c-a5f4-4e42-8b1b-c0b52e68fb43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1536351838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1536351838
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3391688279
Short name T68
Test name
Test status
Simulation time 123311269 ps
CPU time 0.98 seconds
Started May 30 01:16:35 PM PDT 24
Finished May 30 01:16:36 PM PDT 24
Peak memory 234792 kb
Host smart-29dd76f7-c044-4497-97d4-c841ebbf8cb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391688279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3391688279
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2398340802
Short name T803
Test name
Test status
Simulation time 2264663829 ps
CPU time 18.25 seconds
Started May 30 01:16:25 PM PDT 24
Finished May 30 01:16:45 PM PDT 24
Peak memory 218560 kb
Host smart-6503d29a-3ca0-4879-882d-82c4d343e8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398340802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2398340802
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1751935921
Short name T636
Test name
Test status
Simulation time 1938075503 ps
CPU time 7.91 seconds
Started May 30 01:16:20 PM PDT 24
Finished May 30 01:16:29 PM PDT 24
Peak memory 215768 kb
Host smart-f95fb619-b113-4088-b341-34702cc7d90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751935921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1751935921
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2952399513
Short name T372
Test name
Test status
Simulation time 57673641 ps
CPU time 1.45 seconds
Started May 30 01:16:26 PM PDT 24
Finished May 30 01:16:29 PM PDT 24
Peak memory 207788 kb
Host smart-a9c0293c-7d78-4250-87f5-7b19576080ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952399513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2952399513
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1966091122
Short name T435
Test name
Test status
Simulation time 392133336 ps
CPU time 0.83 seconds
Started May 30 01:16:23 PM PDT 24
Finished May 30 01:16:25 PM PDT 24
Peak memory 205304 kb
Host smart-bc6a30ad-1263-41fc-b863-46552236649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966091122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1966091122
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3535543895
Short name T977
Test name
Test status
Simulation time 189921855 ps
CPU time 2.48 seconds
Started May 30 01:16:24 PM PDT 24
Finished May 30 01:16:28 PM PDT 24
Peak memory 220788 kb
Host smart-ff5008f6-8478-4970-a11d-747f73811c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535543895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3535543895
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.18038089
Short name T380
Test name
Test status
Simulation time 11941632 ps
CPU time 0.73 seconds
Started May 30 01:18:50 PM PDT 24
Finished May 30 01:18:52 PM PDT 24
Peak memory 204908 kb
Host smart-b3d178a0-75da-4fa8-bc77-273eae14c95c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18038089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.18038089
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4015222714
Short name T6
Test name
Test status
Simulation time 187439144 ps
CPU time 3.96 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 219496 kb
Host smart-d6240c8a-df6b-453c-95b0-bbd6f4ced3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015222714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4015222714
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3387198522
Short name T390
Test name
Test status
Simulation time 37901046 ps
CPU time 0.78 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:18:54 PM PDT 24
Peak memory 206228 kb
Host smart-fe1ece93-9513-4c29-9487-2d419b2efbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387198522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3387198522
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1862669866
Short name T494
Test name
Test status
Simulation time 5153945033 ps
CPU time 50.29 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:19:45 PM PDT 24
Peak memory 251412 kb
Host smart-dd0cbdf5-4b44-4703-ba36-889406f25548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862669866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1862669866
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1028390046
Short name T652
Test name
Test status
Simulation time 18058488357 ps
CPU time 38.91 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:34 PM PDT 24
Peak memory 240700 kb
Host smart-680efbe6-b307-4328-874e-9a69d1388c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028390046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1028390046
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2028073507
Short name T614
Test name
Test status
Simulation time 576855597 ps
CPU time 4.63 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 224176 kb
Host smart-980e456c-d8c0-4402-bc0f-07aae39a72b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028073507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2028073507
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4129921396
Short name T181
Test name
Test status
Simulation time 1426662535 ps
CPU time 5.73 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:19:03 PM PDT 24
Peak memory 217492 kb
Host smart-d2972832-05ad-4184-90ca-1e02a6858e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129921396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4129921396
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1239960981
Short name T812
Test name
Test status
Simulation time 551721845 ps
CPU time 10.47 seconds
Started May 30 01:18:51 PM PDT 24
Finished May 30 01:19:03 PM PDT 24
Peak memory 233880 kb
Host smart-74e26bf4-858c-4de0-b96e-36fc5ae22601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239960981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1239960981
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3154395579
Short name T929
Test name
Test status
Simulation time 1908116483 ps
CPU time 8.49 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:19:05 PM PDT 24
Peak memory 226372 kb
Host smart-d421a669-be76-46aa-a6ae-8bf421beec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154395579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3154395579
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.342130340
Short name T228
Test name
Test status
Simulation time 559969170 ps
CPU time 6.4 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:19:05 PM PDT 24
Peak memory 231432 kb
Host smart-a097e1d0-ecb4-45a6-99cc-65630b02f69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342130340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.342130340
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3767514363
Short name T546
Test name
Test status
Simulation time 983567425 ps
CPU time 5.55 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 218360 kb
Host smart-892d8706-f0f5-4b84-8582-63e791739412
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3767514363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3767514363
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1578233650
Short name T454
Test name
Test status
Simulation time 29773655 ps
CPU time 0.69 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:18:58 PM PDT 24
Peak memory 205056 kb
Host smart-60f2f86a-8303-45b0-a91c-72dcee41ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578233650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1578233650
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3625147071
Short name T732
Test name
Test status
Simulation time 1663258976 ps
CPU time 7.87 seconds
Started May 30 01:18:51 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 215844 kb
Host smart-418e163c-f3cc-4e08-9ebe-2be7610c7e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625147071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3625147071
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.728557424
Short name T566
Test name
Test status
Simulation time 22167416 ps
CPU time 1 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:18:54 PM PDT 24
Peak memory 206584 kb
Host smart-43b73b10-1726-4a6b-b157-93198a23023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728557424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.728557424
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2272823247
Short name T843
Test name
Test status
Simulation time 61969760 ps
CPU time 0.76 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:18:54 PM PDT 24
Peak memory 205288 kb
Host smart-8acdb64e-3205-4184-802e-660a6139faff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272823247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2272823247
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1026154744
Short name T428
Test name
Test status
Simulation time 1750688459 ps
CPU time 4.68 seconds
Started May 30 01:18:52 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 233996 kb
Host smart-18d80218-e0ee-48be-8f70-9a4dd3101451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026154744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1026154744
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.160725591
Short name T438
Test name
Test status
Simulation time 39780778 ps
CPU time 0.73 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:18:58 PM PDT 24
Peak memory 204924 kb
Host smart-11e84f68-2cb7-40b3-8d5d-27bb85319a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160725591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.160725591
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3550437248
Short name T585
Test name
Test status
Simulation time 4553853891 ps
CPU time 12.22 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:19:09 PM PDT 24
Peak memory 233804 kb
Host smart-6d96ee6b-9826-439d-bb35-9ce51befa27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550437248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3550437248
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.152445471
Short name T333
Test name
Test status
Simulation time 44853110 ps
CPU time 0.74 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:18:58 PM PDT 24
Peak memory 204868 kb
Host smart-3155edbb-06e3-40b3-a9d0-eca9e091eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152445471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.152445471
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4213099790
Short name T961
Test name
Test status
Simulation time 14778048782 ps
CPU time 113.7 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:20:50 PM PDT 24
Peak memory 248804 kb
Host smart-395a5731-45a5-4a76-8e17-2e53ba30087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213099790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4213099790
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2917561907
Short name T184
Test name
Test status
Simulation time 31054382933 ps
CPU time 313.94 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:24:13 PM PDT 24
Peak memory 252024 kb
Host smart-27105adb-f430-4c29-a65c-ed96e008c786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917561907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2917561907
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1765290774
Short name T456
Test name
Test status
Simulation time 131599551392 ps
CPU time 93.17 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:20:30 PM PDT 24
Peak memory 232408 kb
Host smart-d4b3baa2-4772-48ba-a8c4-b53e06c923e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765290774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1765290774
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1940734231
Short name T947
Test name
Test status
Simulation time 739088730 ps
CPU time 3.43 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 232364 kb
Host smart-406a27d9-e17b-4f0b-8f0a-254cfb402303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940734231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1940734231
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.355075836
Short name T835
Test name
Test status
Simulation time 301217201 ps
CPU time 5.85 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:02 PM PDT 24
Peak memory 233500 kb
Host smart-13b0c7d3-21cb-4044-9648-c006c00eadab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355075836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.355075836
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.991972112
Short name T339
Test name
Test status
Simulation time 95750321 ps
CPU time 2.41 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:19:01 PM PDT 24
Peak memory 217348 kb
Host smart-e8f8b592-5fa7-4657-a8cc-bfc7441babc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991972112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.991972112
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1888322237
Short name T780
Test name
Test status
Simulation time 3554625258 ps
CPU time 7.33 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:04 PM PDT 24
Peak memory 233320 kb
Host smart-e6aaffff-abaf-4125-bf66-48e6309cda6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888322237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1888322237
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1426990417
Short name T251
Test name
Test status
Simulation time 5467715637 ps
CPU time 5.73 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:02 PM PDT 24
Peak memory 217060 kb
Host smart-e18d9c99-2ce4-4c29-a455-262ef5834611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426990417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1426990417
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1986135405
Short name T599
Test name
Test status
Simulation time 2114597009 ps
CPU time 17.9 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:13 PM PDT 24
Peak memory 222500 kb
Host smart-1b813efe-cbca-4a98-a565-0b08ef819adf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986135405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1986135405
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.277171710
Short name T337
Test name
Test status
Simulation time 137306695 ps
CPU time 0.97 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:18:56 PM PDT 24
Peak memory 205996 kb
Host smart-f8880813-5d9b-43cd-a4f6-a239fd28d06a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277171710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.277171710
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1544073227
Short name T579
Test name
Test status
Simulation time 5027806336 ps
CPU time 7.67 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:03 PM PDT 24
Peak memory 215948 kb
Host smart-42181109-cc9a-4309-9424-23fabea4ac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544073227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1544073227
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2988204706
Short name T2
Test name
Test status
Simulation time 16714128396 ps
CPU time 12.35 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:08 PM PDT 24
Peak memory 215912 kb
Host smart-670e6df8-0680-4cb5-a72c-a268a6cdced8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988204706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2988204706
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3252968351
Short name T832
Test name
Test status
Simulation time 827317503 ps
CPU time 1.11 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 207424 kb
Host smart-a12cfac6-ec7f-4b55-839e-d4f73e0c3d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252968351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3252968351
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.300089185
Short name T693
Test name
Test status
Simulation time 299915443 ps
CPU time 0.77 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:18:57 PM PDT 24
Peak memory 205304 kb
Host smart-f951aa6d-0809-4c89-9d58-f569ae480e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300089185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.300089185
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.807755130
Short name T647
Test name
Test status
Simulation time 131758954 ps
CPU time 3.54 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 224076 kb
Host smart-8bf7213f-77de-4c0e-b363-0e11026fe156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807755130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.807755130
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1309627105
Short name T721
Test name
Test status
Simulation time 93473076 ps
CPU time 0.7 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 204260 kb
Host smart-27b6c7c4-83ef-4d6e-9771-d1c6872edc0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309627105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1309627105
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4005040864
Short name T462
Test name
Test status
Simulation time 1625958663 ps
CPU time 13.62 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:19:12 PM PDT 24
Peak memory 234240 kb
Host smart-d66ea513-37a4-49d0-99f6-d118378fb0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005040864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4005040864
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3999232955
Short name T402
Test name
Test status
Simulation time 13585571 ps
CPU time 0.82 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:18:58 PM PDT 24
Peak memory 206228 kb
Host smart-08ed71b4-4fb1-4c7d-b06e-08df2833473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999232955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3999232955
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2789179869
Short name T214
Test name
Test status
Simulation time 10354990725 ps
CPU time 84.27 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:20:22 PM PDT 24
Peak memory 248784 kb
Host smart-88fb662d-681f-4001-87e9-267562a5c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789179869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2789179869
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.608538385
Short name T974
Test name
Test status
Simulation time 6894107103 ps
CPU time 67.79 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:20:06 PM PDT 24
Peak memory 248920 kb
Host smart-e68ae92a-da95-4eea-8942-18e033487a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608538385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.608538385
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1094749020
Short name T240
Test name
Test status
Simulation time 53312852107 ps
CPU time 80.92 seconds
Started May 30 01:18:57 PM PDT 24
Finished May 30 01:20:21 PM PDT 24
Peak memory 256220 kb
Host smart-b694dba2-15fa-4a90-a041-538d619e1184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094749020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1094749020
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1027771554
Short name T314
Test name
Test status
Simulation time 11718641338 ps
CPU time 36.09 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:19:33 PM PDT 24
Peak memory 240580 kb
Host smart-c5bb972f-1ee5-42da-a405-c177aef28ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027771554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1027771554
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1490941262
Short name T38
Test name
Test status
Simulation time 7721296318 ps
CPU time 16.12 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:19:13 PM PDT 24
Peak memory 219432 kb
Host smart-4e8cc6c5-66e0-4845-96e7-83209a2364f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490941262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1490941262
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1134804060
Short name T886
Test name
Test status
Simulation time 8839362106 ps
CPU time 17.12 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:19:16 PM PDT 24
Peak memory 234244 kb
Host smart-066f55a3-7509-406e-8b17-291679543762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134804060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1134804060
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.741128824
Short name T528
Test name
Test status
Simulation time 15015228866 ps
CPU time 10.3 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:19:08 PM PDT 24
Peak memory 232436 kb
Host smart-8c405d17-fd55-48c9-b3b1-462b97331699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741128824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.741128824
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2598794301
Short name T879
Test name
Test status
Simulation time 404299208 ps
CPU time 3.21 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 218428 kb
Host smart-2f1c7bd9-3c8c-41d2-8184-bbfaef88dd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598794301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2598794301
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.337199273
Short name T3
Test name
Test status
Simulation time 5030323245 ps
CPU time 9.01 seconds
Started May 30 01:18:54 PM PDT 24
Finished May 30 01:19:06 PM PDT 24
Peak memory 222804 kb
Host smart-6ce2d86a-b38b-4fa8-88ce-deac4275e777
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=337199273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.337199273
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.754149980
Short name T810
Test name
Test status
Simulation time 3953631322 ps
CPU time 85.91 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:20:21 PM PDT 24
Peak memory 256840 kb
Host smart-30a7e460-667a-41e3-9071-735dc0630074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754149980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.754149980
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3216688138
Short name T334
Test name
Test status
Simulation time 117428944 ps
CPU time 0.71 seconds
Started May 30 01:18:51 PM PDT 24
Finished May 30 01:18:53 PM PDT 24
Peak memory 205076 kb
Host smart-91b2854a-4247-4f0d-a624-987752c9bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216688138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3216688138
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1033230507
Short name T897
Test name
Test status
Simulation time 352703495 ps
CPU time 2.76 seconds
Started May 30 01:18:53 PM PDT 24
Finished May 30 01:18:58 PM PDT 24
Peak memory 215788 kb
Host smart-7052a767-51f5-4953-8aa4-5fda154c781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033230507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1033230507
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2032285579
Short name T24
Test name
Test status
Simulation time 242392331 ps
CPU time 3.28 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:19:01 PM PDT 24
Peak memory 215936 kb
Host smart-71740343-8434-4e28-af10-366c3a43f13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032285579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2032285579
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3721384186
Short name T343
Test name
Test status
Simulation time 26331101 ps
CPU time 0.73 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 204920 kb
Host smart-6d4de126-125f-4914-901a-fed351b4c789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721384186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3721384186
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2767883149
Short name T25
Test name
Test status
Simulation time 975748116 ps
CPU time 7.22 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:19:05 PM PDT 24
Peak memory 240568 kb
Host smart-83df6862-3679-4463-b5c6-fba42e123872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767883149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2767883149
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1409420355
Short name T357
Test name
Test status
Simulation time 12725270 ps
CPU time 0.72 seconds
Started May 30 01:19:05 PM PDT 24
Finished May 30 01:19:06 PM PDT 24
Peak memory 205236 kb
Host smart-4982ab77-5a6b-44bd-8ed9-403d0c0f60ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409420355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1409420355
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4087687185
Short name T639
Test name
Test status
Simulation time 32062974 ps
CPU time 2.1 seconds
Started May 30 01:19:09 PM PDT 24
Finished May 30 01:19:13 PM PDT 24
Peak memory 216396 kb
Host smart-01ec8e87-0dc3-41d8-a6f1-8d1d94039876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087687185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4087687185
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.101261233
Short name T549
Test name
Test status
Simulation time 55096762 ps
CPU time 0.77 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 205920 kb
Host smart-ffcbbc8e-ff49-481d-829f-d4c0e1a03b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101261233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.101261233
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1331907705
Short name T901
Test name
Test status
Simulation time 5560365011 ps
CPU time 39.62 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:51 PM PDT 24
Peak memory 233540 kb
Host smart-bfad0b52-f823-4dce-a500-ac2586a58fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331907705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1331907705
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3436268275
Short name T71
Test name
Test status
Simulation time 1912350149 ps
CPU time 14.78 seconds
Started May 30 01:19:05 PM PDT 24
Finished May 30 01:19:21 PM PDT 24
Peak memory 240212 kb
Host smart-ee0bab7d-1eb8-4252-a918-462489263a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436268275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3436268275
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.835692634
Short name T514
Test name
Test status
Simulation time 134643843 ps
CPU time 2.47 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 220776 kb
Host smart-a6a6aaf3-7f71-476e-ada1-fbc175a87e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835692634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.835692634
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1946507666
Short name T235
Test name
Test status
Simulation time 6650437931 ps
CPU time 19.18 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:27 PM PDT 24
Peak memory 234748 kb
Host smart-bd0f3c67-7e24-4a79-b4af-06831bc248a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946507666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1946507666
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3271479315
Short name T304
Test name
Test status
Simulation time 10401934745 ps
CPU time 27.65 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:19:26 PM PDT 24
Peak memory 246032 kb
Host smart-b694ee58-7a08-407c-9e08-0374f9885cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271479315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3271479315
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1209483904
Short name T816
Test name
Test status
Simulation time 282772337 ps
CPU time 2.22 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:19:01 PM PDT 24
Peak memory 215752 kb
Host smart-e72ba478-76d6-4c88-8073-21d74edaf810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209483904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1209483904
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1398940714
Short name T363
Test name
Test status
Simulation time 431908641 ps
CPU time 4.04 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:19:11 PM PDT 24
Peak memory 218464 kb
Host smart-8ae38e9e-715a-46d4-b815-9bd7e3716200
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1398940714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1398940714
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2750980080
Short name T409
Test name
Test status
Simulation time 33672134 ps
CPU time 0.91 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:19:08 PM PDT 24
Peak memory 205944 kb
Host smart-f04d41f3-33c8-427a-956e-a4f6f4952750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750980080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2750980080
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4228576368
Short name T535
Test name
Test status
Simulation time 1066091786 ps
CPU time 18.73 seconds
Started May 30 01:18:57 PM PDT 24
Finished May 30 01:19:19 PM PDT 24
Peak memory 218996 kb
Host smart-0e7352c7-7ff8-452a-b744-38e0bb866524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228576368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4228576368
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.589308638
Short name T913
Test name
Test status
Simulation time 133210211 ps
CPU time 1.29 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 207368 kb
Host smart-4a9c86ab-c78d-4fc3-a793-e87e725a77ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589308638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.589308638
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2682306125
Short name T665
Test name
Test status
Simulation time 73226186 ps
CPU time 0.84 seconds
Started May 30 01:18:56 PM PDT 24
Finished May 30 01:19:00 PM PDT 24
Peak memory 206340 kb
Host smart-7c495743-911e-4f69-8804-99589c54a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682306125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2682306125
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1804083104
Short name T664
Test name
Test status
Simulation time 31618289 ps
CPU time 0.76 seconds
Started May 30 01:18:55 PM PDT 24
Finished May 30 01:18:59 PM PDT 24
Peak memory 205276 kb
Host smart-f14c516f-7847-4e03-a18a-343d445871ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804083104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1804083104
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1090506252
Short name T748
Test name
Test status
Simulation time 201588584 ps
CPU time 2.37 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:19:09 PM PDT 24
Peak memory 220880 kb
Host smart-26cf5907-1893-4493-af98-0db904e61318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090506252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1090506252
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3521338684
Short name T576
Test name
Test status
Simulation time 17587435 ps
CPU time 0.73 seconds
Started May 30 01:19:03 PM PDT 24
Finished May 30 01:19:04 PM PDT 24
Peak memory 204908 kb
Host smart-f13cd996-8a45-4135-ab85-53aa292bfc7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521338684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3521338684
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3650091472
Short name T519
Test name
Test status
Simulation time 104138359 ps
CPU time 2.52 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:14 PM PDT 24
Peak memory 220936 kb
Host smart-2b41c5e7-7b3a-492e-925b-624422c2a857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650091472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3650091472
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2920168166
Short name T545
Test name
Test status
Simulation time 139013720 ps
CPU time 0.8 seconds
Started May 30 01:19:04 PM PDT 24
Finished May 30 01:19:06 PM PDT 24
Peak memory 205868 kb
Host smart-68268823-06cd-4091-a18f-026b3f31dc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920168166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2920168166
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1301366535
Short name T482
Test name
Test status
Simulation time 7376397511 ps
CPU time 93.41 seconds
Started May 30 01:19:04 PM PDT 24
Finished May 30 01:20:38 PM PDT 24
Peak memory 250408 kb
Host smart-ccec1abb-300f-4d9e-a96a-d1d0e7c8d103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301366535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1301366535
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.839584215
Short name T654
Test name
Test status
Simulation time 4929460935 ps
CPU time 30.47 seconds
Started May 30 01:19:08 PM PDT 24
Finished May 30 01:19:39 PM PDT 24
Peak memory 239076 kb
Host smart-2328f444-6a92-43f9-b048-ec0de331ab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839584215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.839584215
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1467066125
Short name T307
Test name
Test status
Simulation time 67779808356 ps
CPU time 409.41 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:25:57 PM PDT 24
Peak memory 248904 kb
Host smart-7cc5c52c-4511-421a-b748-47775b9be35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467066125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1467066125
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.222977561
Short name T317
Test name
Test status
Simulation time 657335975 ps
CPU time 3.19 seconds
Started May 30 01:19:09 PM PDT 24
Finished May 30 01:19:14 PM PDT 24
Peak memory 232340 kb
Host smart-f460d82a-f201-4267-be63-98bd016262e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222977561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.222977561
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3696907972
Short name T510
Test name
Test status
Simulation time 604395934 ps
CPU time 8.65 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:20 PM PDT 24
Peak memory 233820 kb
Host smart-8499e244-53d1-483f-85a8-493c49378309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696907972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3696907972
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3676386720
Short name T255
Test name
Test status
Simulation time 7510262344 ps
CPU time 26.79 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:19:34 PM PDT 24
Peak memory 238632 kb
Host smart-8e8b3daf-6d3f-418a-9d19-e25850d81bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676386720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3676386720
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2243799269
Short name T282
Test name
Test status
Simulation time 7847900766 ps
CPU time 12.51 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:21 PM PDT 24
Peak memory 232884 kb
Host smart-cbe48253-b3e6-48d0-8f3b-da703b2797d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243799269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2243799269
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3042142085
Short name T563
Test name
Test status
Simulation time 601182177 ps
CPU time 3.51 seconds
Started May 30 01:19:05 PM PDT 24
Finished May 30 01:19:10 PM PDT 24
Peak memory 218176 kb
Host smart-bd671204-4c7b-4380-9012-d122ff397d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042142085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3042142085
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3754648646
Short name T14
Test name
Test status
Simulation time 2007099022 ps
CPU time 24.27 seconds
Started May 30 01:19:05 PM PDT 24
Finished May 30 01:19:30 PM PDT 24
Peak memory 219880 kb
Host smart-0dffb8f8-706b-41b9-a60a-3837864eb9de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3754648646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3754648646
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.906362538
Short name T206
Test name
Test status
Simulation time 19981476845 ps
CPU time 154.17 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:21:42 PM PDT 24
Peak memory 260908 kb
Host smart-f6c5d58b-348a-48a6-926f-ba1997c2d82d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906362538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.906362538
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.20020784
Short name T716
Test name
Test status
Simulation time 4599744489 ps
CPU time 24.41 seconds
Started May 30 01:19:05 PM PDT 24
Finished May 30 01:19:30 PM PDT 24
Peak memory 215980 kb
Host smart-582d1f0e-b010-4f19-9b2d-c1fea2d89a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20020784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.20020784
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2800111598
Short name T360
Test name
Test status
Simulation time 22753544646 ps
CPU time 14.63 seconds
Started May 30 01:19:09 PM PDT 24
Finished May 30 01:19:25 PM PDT 24
Peak memory 215892 kb
Host smart-16fb5cd2-696b-4625-a369-8bee8074f2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800111598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2800111598
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.568388489
Short name T445
Test name
Test status
Simulation time 37406631 ps
CPU time 1.17 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:13 PM PDT 24
Peak memory 207552 kb
Host smart-920577ab-8203-4337-80fc-cc4021621e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568388489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.568388489
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2845916866
Short name T660
Test name
Test status
Simulation time 100085942 ps
CPU time 0.88 seconds
Started May 30 01:19:09 PM PDT 24
Finished May 30 01:19:12 PM PDT 24
Peak memory 206300 kb
Host smart-0ac239d6-bd8a-44de-9eca-9092177fe8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845916866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2845916866
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4012523610
Short name T208
Test name
Test status
Simulation time 39380522 ps
CPU time 2.08 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:13 PM PDT 24
Peak memory 222080 kb
Host smart-77a5f7e3-c606-4252-a82d-57845dd2d6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012523610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4012523610
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3560666407
Short name T62
Test name
Test status
Simulation time 43139518 ps
CPU time 0.71 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:09 PM PDT 24
Peak memory 204272 kb
Host smart-1373c675-5950-48cf-9cec-87c7e329cb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560666407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3560666407
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2256425799
Short name T870
Test name
Test status
Simulation time 439565177 ps
CPU time 2.48 seconds
Started May 30 01:19:11 PM PDT 24
Finished May 30 01:19:15 PM PDT 24
Peak memory 216924 kb
Host smart-ead28981-b95f-496c-ab0c-3c60815a3a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256425799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2256425799
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.857373439
Short name T730
Test name
Test status
Simulation time 46150911 ps
CPU time 0.78 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:09 PM PDT 24
Peak memory 205916 kb
Host smart-145f8bd0-a568-42ff-97ab-732dd163612f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857373439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.857373439
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1927549746
Short name T269
Test name
Test status
Simulation time 3516040496 ps
CPU time 80.49 seconds
Started May 30 01:19:05 PM PDT 24
Finished May 30 01:20:26 PM PDT 24
Peak memory 262308 kb
Host smart-4da2af53-2bf6-4f04-830a-7f3499fc4e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927549746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1927549746
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.316763378
Short name T266
Test name
Test status
Simulation time 17282956408 ps
CPU time 189.05 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:22:16 PM PDT 24
Peak memory 265064 kb
Host smart-3005fa62-b13a-4704-a586-283e99891fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316763378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.316763378
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1019105232
Short name T742
Test name
Test status
Simulation time 194049655197 ps
CPU time 402.89 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:25:50 PM PDT 24
Peak memory 261236 kb
Host smart-806336f2-b8fe-4991-a1d4-1c64f0cd2124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019105232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1019105232
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.916317635
Short name T135
Test name
Test status
Simulation time 141743424 ps
CPU time 3.79 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:19:11 PM PDT 24
Peak memory 224156 kb
Host smart-640c5d0a-b69b-4680-baaf-572f84d25132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916317635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.916317635
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.814467571
Short name T231
Test name
Test status
Simulation time 347907412 ps
CPU time 3.26 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:15 PM PDT 24
Peak memory 233360 kb
Host smart-cdf5de80-5ccd-4dbd-9c03-617f4cb68963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814467571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.814467571
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3880652948
Short name T814
Test name
Test status
Simulation time 74693364272 ps
CPU time 48.64 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:57 PM PDT 24
Peak memory 240612 kb
Host smart-a689e6bc-b4ab-4932-a8a9-e37bc6bbe4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880652948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3880652948
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.640866573
Short name T718
Test name
Test status
Simulation time 57149616357 ps
CPU time 22.85 seconds
Started May 30 01:19:11 PM PDT 24
Finished May 30 01:19:36 PM PDT 24
Peak memory 234928 kb
Host smart-f3ece7c4-5eff-45f4-8033-171a8953a304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640866573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.640866573
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2842719474
Short name T75
Test name
Test status
Simulation time 255017525 ps
CPU time 3.93 seconds
Started May 30 01:19:05 PM PDT 24
Finished May 30 01:19:10 PM PDT 24
Peak memory 218524 kb
Host smart-857a2a93-8ee6-4fe9-8e53-13afe2cf4877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842719474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2842719474
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.358598953
Short name T522
Test name
Test status
Simulation time 1318134301 ps
CPU time 10.01 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:22 PM PDT 24
Peak memory 222060 kb
Host smart-096d6d5a-c5a0-466c-a031-a29081f161c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=358598953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.358598953
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1723564182
Short name T20
Test name
Test status
Simulation time 63169716111 ps
CPU time 566.42 seconds
Started May 30 01:19:09 PM PDT 24
Finished May 30 01:28:38 PM PDT 24
Peak memory 265228 kb
Host smart-0d04b84f-e60d-43b8-9f4f-bd8e207ee09e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723564182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1723564182
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4054544013
Short name T513
Test name
Test status
Simulation time 1056475977 ps
CPU time 17.6 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:19:25 PM PDT 24
Peak memory 216064 kb
Host smart-43e8c2b0-8b9f-431a-a4dd-64063a78a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054544013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4054544013
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2899046390
Short name T51
Test name
Test status
Simulation time 3937399976 ps
CPU time 12.47 seconds
Started May 30 01:19:03 PM PDT 24
Finished May 30 01:19:17 PM PDT 24
Peak memory 215880 kb
Host smart-9801fbac-6f00-4a86-9e3b-1c8cf6e1176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899046390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2899046390
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2254516146
Short name T396
Test name
Test status
Simulation time 125873946 ps
CPU time 1.28 seconds
Started May 30 01:19:09 PM PDT 24
Finished May 30 01:19:12 PM PDT 24
Peak memory 215932 kb
Host smart-3e3cfff3-1520-4b4e-9deb-bc2a00a21382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254516146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2254516146
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2978561637
Short name T365
Test name
Test status
Simulation time 100199087 ps
CPU time 0.86 seconds
Started May 30 01:19:08 PM PDT 24
Finished May 30 01:19:10 PM PDT 24
Peak memory 205224 kb
Host smart-ea865e1d-ea8e-486c-8ee8-04da22aad816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978561637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2978561637
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1531193911
Short name T859
Test name
Test status
Simulation time 363024683 ps
CPU time 2.44 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:11 PM PDT 24
Peak memory 218148 kb
Host smart-ae91eada-9ee1-4541-9097-6d294bf11996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531193911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1531193911
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3135284565
Short name T630
Test name
Test status
Simulation time 14350805 ps
CPU time 0.74 seconds
Started May 30 01:19:12 PM PDT 24
Finished May 30 01:19:14 PM PDT 24
Peak memory 205024 kb
Host smart-be7f335a-c35e-4d9e-9a2c-fbd90839eeda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135284565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3135284565
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.492177701
Short name T257
Test name
Test status
Simulation time 8739236740 ps
CPU time 6.87 seconds
Started May 30 01:19:12 PM PDT 24
Finished May 30 01:19:20 PM PDT 24
Peak memory 218620 kb
Host smart-ab11ab1c-d875-473a-a9b3-abcfd0f1f933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492177701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.492177701
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3560162548
Short name T919
Test name
Test status
Simulation time 43154623 ps
CPU time 0.79 seconds
Started May 30 01:19:06 PM PDT 24
Finished May 30 01:19:08 PM PDT 24
Peak memory 205892 kb
Host smart-d520e19f-7a0b-4e60-8818-795a33333bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560162548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3560162548
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3714471300
Short name T302
Test name
Test status
Simulation time 5374256692 ps
CPU time 65.95 seconds
Started May 30 01:19:12 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 248904 kb
Host smart-128dd159-e617-4586-8b53-994e5a53911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714471300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3714471300
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.835726413
Short name T544
Test name
Test status
Simulation time 13215644854 ps
CPU time 29.51 seconds
Started May 30 01:19:09 PM PDT 24
Finished May 30 01:19:40 PM PDT 24
Peak memory 224300 kb
Host smart-dc2cf65b-4320-4c47-83b0-37ee6e62d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835726413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.835726413
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2360978077
Short name T311
Test name
Test status
Simulation time 1782755177 ps
CPU time 24.39 seconds
Started May 30 01:19:08 PM PDT 24
Finished May 30 01:19:34 PM PDT 24
Peak memory 224172 kb
Host smart-9613b112-e08f-46eb-87b1-8ee484dac0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360978077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2360978077
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1169318651
Short name T705
Test name
Test status
Simulation time 2009339159 ps
CPU time 9.57 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:18 PM PDT 24
Peak memory 224092 kb
Host smart-f01a1309-033d-4d85-8517-373d14c9505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169318651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1169318651
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3553331376
Short name T681
Test name
Test status
Simulation time 814120190 ps
CPU time 9.88 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:18 PM PDT 24
Peak memory 231260 kb
Host smart-09f8aceb-0b45-4f55-b39d-7f88a2be607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553331376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3553331376
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3351102162
Short name T696
Test name
Test status
Simulation time 2025721650 ps
CPU time 7.83 seconds
Started May 30 01:19:12 PM PDT 24
Finished May 30 01:19:21 PM PDT 24
Peak memory 233496 kb
Host smart-11d988fa-de31-4880-b61d-f4c424fa69cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351102162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3351102162
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.758017699
Short name T904
Test name
Test status
Simulation time 390180173 ps
CPU time 5.07 seconds
Started May 30 01:19:08 PM PDT 24
Finished May 30 01:19:14 PM PDT 24
Peak memory 218500 kb
Host smart-5290129f-95a2-41b3-a73e-67371088f598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758017699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.758017699
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.297728475
Short name T466
Test name
Test status
Simulation time 538572215 ps
CPU time 5.54 seconds
Started May 30 01:19:08 PM PDT 24
Finished May 30 01:19:15 PM PDT 24
Peak memory 222120 kb
Host smart-651326ee-54be-4d9c-85f1-7ce22ca489e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=297728475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.297728475
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.303497505
Short name T159
Test name
Test status
Simulation time 22259887998 ps
CPU time 92.38 seconds
Started May 30 01:19:09 PM PDT 24
Finished May 30 01:20:44 PM PDT 24
Peak memory 248880 kb
Host smart-7a8a0555-4560-464b-925a-aca10028c6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303497505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.303497505
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2187432085
Short name T323
Test name
Test status
Simulation time 15246682951 ps
CPU time 45.94 seconds
Started May 30 01:19:08 PM PDT 24
Finished May 30 01:19:56 PM PDT 24
Peak memory 215956 kb
Host smart-461f59e4-a84a-4f38-ac66-9706594f58c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187432085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2187432085
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2352272217
Short name T417
Test name
Test status
Simulation time 3821013950 ps
CPU time 10.12 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:22 PM PDT 24
Peak memory 215832 kb
Host smart-dc0e4e56-2bf2-475d-97c0-992e67756be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352272217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2352272217
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1675745881
Short name T954
Test name
Test status
Simulation time 34064626 ps
CPU time 0.79 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:13 PM PDT 24
Peak memory 205244 kb
Host smart-56e506ed-6cb6-4e04-8c19-6b2cd2997d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675745881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1675745881
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3337600834
Short name T555
Test name
Test status
Simulation time 54534594 ps
CPU time 0.88 seconds
Started May 30 01:19:04 PM PDT 24
Finished May 30 01:19:06 PM PDT 24
Peak memory 205196 kb
Host smart-7360fc7b-e22a-4ccd-8642-a4814271b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337600834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3337600834
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3552501582
Short name T189
Test name
Test status
Simulation time 1194728651 ps
CPU time 7.45 seconds
Started May 30 01:19:12 PM PDT 24
Finished May 30 01:19:21 PM PDT 24
Peak memory 217448 kb
Host smart-9ec32702-0593-405b-9eb3-433ed1b4e7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552501582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3552501582
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2150526053
Short name T939
Test name
Test status
Simulation time 14622746 ps
CPU time 0.71 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:20 PM PDT 24
Peak memory 204888 kb
Host smart-175b6e68-426d-4aea-8755-c119ee524c81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150526053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2150526053
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3665643357
Short name T254
Test name
Test status
Simulation time 461547857 ps
CPU time 2.77 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:15 PM PDT 24
Peak memory 233940 kb
Host smart-0a537ec3-9e43-4555-8617-7444ca9d03ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665643357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3665643357
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.235666515
Short name T537
Test name
Test status
Simulation time 16074083 ps
CPU time 0.76 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:12 PM PDT 24
Peak memory 204880 kb
Host smart-a32f61fe-2b15-42f7-8ff2-33e3bb761086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235666515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.235666515
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3015971585
Short name T216
Test name
Test status
Simulation time 34935766219 ps
CPU time 293.78 seconds
Started May 30 01:19:15 PM PDT 24
Finished May 30 01:24:10 PM PDT 24
Peak memory 249944 kb
Host smart-9a93647e-b64a-45ac-a8f8-b26ca7c5e99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015971585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3015971585
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2403676848
Short name T294
Test name
Test status
Simulation time 308932178021 ps
CPU time 621.31 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:29:41 PM PDT 24
Peak memory 263868 kb
Host smart-789dc2ef-79e3-4c07-a086-b12c1c94ba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403676848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2403676848
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1045914414
Short name T935
Test name
Test status
Simulation time 573117844 ps
CPU time 4.66 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:13 PM PDT 24
Peak memory 240544 kb
Host smart-f1df8030-53b4-48a5-b1ae-96501c5f3564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045914414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1045914414
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.877903023
Short name T981
Test name
Test status
Simulation time 201152331 ps
CPU time 3.41 seconds
Started May 30 01:19:15 PM PDT 24
Finished May 30 01:19:19 PM PDT 24
Peak memory 217164 kb
Host smart-4eb2dfd9-3ffa-4b88-994b-67f86dee0d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877903023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.877903023
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2214858849
Short name T91
Test name
Test status
Simulation time 7889518229 ps
CPU time 30.79 seconds
Started May 30 01:19:07 PM PDT 24
Finished May 30 01:19:39 PM PDT 24
Peak memory 229188 kb
Host smart-5ca4298a-9540-41be-93b7-342de02f1581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214858849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2214858849
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2417986064
Short name T270
Test name
Test status
Simulation time 4120770370 ps
CPU time 11.1 seconds
Started May 30 01:19:11 PM PDT 24
Finished May 30 01:19:24 PM PDT 24
Peak memory 233376 kb
Host smart-0def87d7-d94f-4c1d-b3d2-b19401f4e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417986064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2417986064
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2940274120
Short name T710
Test name
Test status
Simulation time 272902003 ps
CPU time 2.03 seconds
Started May 30 01:19:15 PM PDT 24
Finished May 30 01:19:18 PM PDT 24
Peak memory 215752 kb
Host smart-7e1e057c-2f2f-4000-bae9-bba54a2bffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940274120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2940274120
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2502050132
Short name T377
Test name
Test status
Simulation time 406863974 ps
CPU time 4.52 seconds
Started May 30 01:19:14 PM PDT 24
Finished May 30 01:19:20 PM PDT 24
Peak memory 219604 kb
Host smart-8af5f568-7f9b-474c-bcc6-4e6ece6cdc73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2502050132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2502050132
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1034060428
Short name T388
Test name
Test status
Simulation time 6253249466 ps
CPU time 7.17 seconds
Started May 30 01:19:14 PM PDT 24
Finished May 30 01:19:23 PM PDT 24
Peak memory 215980 kb
Host smart-1fd9ed43-c3cf-4dc8-8807-22d1aa623ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034060428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1034060428
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.673568821
Short name T395
Test name
Test status
Simulation time 2856715265 ps
CPU time 12.42 seconds
Started May 30 01:19:15 PM PDT 24
Finished May 30 01:19:28 PM PDT 24
Peak memory 215920 kb
Host smart-59ddfd7b-d54f-4ff4-a7fd-6c05126ef64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673568821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.673568821
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1872678682
Short name T559
Test name
Test status
Simulation time 14947548 ps
CPU time 0.8 seconds
Started May 30 01:19:08 PM PDT 24
Finished May 30 01:19:10 PM PDT 24
Peak memory 205348 kb
Host smart-5bb16298-de7e-4b13-a68e-0d7434ed65f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872678682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1872678682
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4157188400
Short name T972
Test name
Test status
Simulation time 323038730 ps
CPU time 0.95 seconds
Started May 30 01:19:10 PM PDT 24
Finished May 30 01:19:13 PM PDT 24
Peak memory 206328 kb
Host smart-78eb06df-2f53-4211-9e64-4babe5f9ab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157188400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4157188400
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3810803558
Short name T932
Test name
Test status
Simulation time 7834686711 ps
CPU time 18.42 seconds
Started May 30 01:19:08 PM PDT 24
Finished May 30 01:19:28 PM PDT 24
Peak memory 232400 kb
Host smart-157d2d59-869f-48f5-90a3-e67fa2a5923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810803558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3810803558
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2313338710
Short name T376
Test name
Test status
Simulation time 12222509 ps
CPU time 0.73 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:19:33 PM PDT 24
Peak memory 204288 kb
Host smart-c1f8d685-77e4-42e4-bb0d-3b8edda3c726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313338710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2313338710
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.707315832
Short name T619
Test name
Test status
Simulation time 4430483322 ps
CPU time 9.66 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:29 PM PDT 24
Peak memory 233192 kb
Host smart-55757bbe-4a2b-4b00-96a9-59ca6ab990aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707315832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.707315832
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1526522225
Short name T569
Test name
Test status
Simulation time 18381217 ps
CPU time 0.81 seconds
Started May 30 01:19:11 PM PDT 24
Finished May 30 01:19:14 PM PDT 24
Peak memory 205928 kb
Host smart-f03241ca-f888-410e-8c18-46d5d3c04bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526522225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1526522225
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1355256633
Short name T246
Test name
Test status
Simulation time 2389921997 ps
CPU time 54.43 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:20:15 PM PDT 24
Peak memory 256712 kb
Host smart-7d38b8eb-e47b-432f-81a9-0c3787ea7f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355256633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1355256633
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2923417140
Short name T308
Test name
Test status
Simulation time 76722171962 ps
CPU time 807.31 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:32:47 PM PDT 24
Peak memory 255032 kb
Host smart-28c40633-3ca1-4cf8-8238-f995300c59ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923417140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2923417140
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1484607801
Short name T168
Test name
Test status
Simulation time 11458133708 ps
CPU time 82.16 seconds
Started May 30 01:19:20 PM PDT 24
Finished May 30 01:20:43 PM PDT 24
Peak memory 254164 kb
Host smart-0cd89428-733f-4492-96aa-956f32e0fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484607801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1484607801
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2010571448
Short name T687
Test name
Test status
Simulation time 172713329 ps
CPU time 3.54 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:23 PM PDT 24
Peak memory 233064 kb
Host smart-46d68064-024f-4df2-9f5a-fcb18d1aea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010571448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2010571448
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4293762181
Short name T554
Test name
Test status
Simulation time 294526100 ps
CPU time 5.33 seconds
Started May 30 01:19:17 PM PDT 24
Finished May 30 01:19:23 PM PDT 24
Peak memory 218072 kb
Host smart-eb3a2a25-5805-441a-a61f-6dc519cd6cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293762181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4293762181
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3787919263
Short name T92
Test name
Test status
Simulation time 11617402357 ps
CPU time 6.35 seconds
Started May 30 01:19:17 PM PDT 24
Finished May 30 01:19:25 PM PDT 24
Peak memory 218364 kb
Host smart-ce9ced33-0dee-4786-a02a-13e1eb84e525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787919263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3787919263
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1474610557
Short name T472
Test name
Test status
Simulation time 2199819897 ps
CPU time 8.51 seconds
Started May 30 01:19:17 PM PDT 24
Finished May 30 01:19:27 PM PDT 24
Peak memory 226440 kb
Host smart-554753c6-ad40-40c1-b4dc-16b13beefb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474610557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1474610557
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1734960481
Short name T598
Test name
Test status
Simulation time 2089513288 ps
CPU time 13.45 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:33 PM PDT 24
Peak memory 222576 kb
Host smart-df199bf6-f02d-4b32-835e-c28cf7fa7b12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1734960481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1734960481
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3847057372
Short name T154
Test name
Test status
Simulation time 83138960806 ps
CPU time 170.49 seconds
Started May 30 01:19:20 PM PDT 24
Finished May 30 01:22:12 PM PDT 24
Peak memory 240736 kb
Host smart-d3513c73-098b-48b1-a73b-f18fab4a8df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847057372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3847057372
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3283480734
Short name T398
Test name
Test status
Simulation time 7085689233 ps
CPU time 3.81 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:23 PM PDT 24
Peak memory 215948 kb
Host smart-ddc20782-bb1c-4054-b770-d771ec0bdbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283480734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3283480734
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3625219811
Short name T557
Test name
Test status
Simulation time 869754955 ps
CPU time 2.96 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:22 PM PDT 24
Peak memory 207336 kb
Host smart-a57b9924-3965-40fc-8b86-7ba0d950fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625219811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3625219811
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.168116613
Short name T459
Test name
Test status
Simulation time 817206663 ps
CPU time 3.1 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:22 PM PDT 24
Peak memory 215912 kb
Host smart-046907e1-1fff-4b11-bb06-20e74913149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168116613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.168116613
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1634275583
Short name T431
Test name
Test status
Simulation time 76393396 ps
CPU time 0.94 seconds
Started May 30 01:19:17 PM PDT 24
Finished May 30 01:19:19 PM PDT 24
Peak memory 206348 kb
Host smart-2768d411-e221-467b-91bc-d89c7dcdeba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634275583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1634275583
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.474180226
Short name T621
Test name
Test status
Simulation time 1344860692 ps
CPU time 3.61 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:23 PM PDT 24
Peak memory 232408 kb
Host smart-e52132ad-7518-4869-a3a5-626a15032486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474180226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.474180226
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2346867654
Short name T925
Test name
Test status
Simulation time 43629759 ps
CPU time 0.68 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:22 PM PDT 24
Peak memory 204296 kb
Host smart-f3f1978d-71eb-4b77-b9bd-fc57218798cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346867654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2346867654
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1097805812
Short name T907
Test name
Test status
Simulation time 129535993 ps
CPU time 3.14 seconds
Started May 30 01:19:21 PM PDT 24
Finished May 30 01:19:26 PM PDT 24
Peak memory 218548 kb
Host smart-d44a6a9e-b30b-4a74-8967-be454f0b0b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097805812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1097805812
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2404865417
Short name T515
Test name
Test status
Simulation time 16285273 ps
CPU time 0.83 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:21 PM PDT 24
Peak memory 205848 kb
Host smart-97bf97dc-d441-4945-b52e-6aad6fe558b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404865417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2404865417
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4172290848
Short name T187
Test name
Test status
Simulation time 26426309147 ps
CPU time 186.34 seconds
Started May 30 01:19:21 PM PDT 24
Finished May 30 01:22:29 PM PDT 24
Peak memory 263860 kb
Host smart-6a388748-3be9-4b66-a2a3-58960a53ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172290848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4172290848
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3065203357
Short name T480
Test name
Test status
Simulation time 14158159591 ps
CPU time 49.8 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:20:09 PM PDT 24
Peak memory 253444 kb
Host smart-d03b8c55-694a-4a66-a70b-2a79e5c932d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065203357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3065203357
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1435841412
Short name T422
Test name
Test status
Simulation time 56540626 ps
CPU time 0.77 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:20 PM PDT 24
Peak memory 216484 kb
Host smart-824a20f9-155d-4dff-a01b-312ad2679241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435841412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1435841412
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1146889741
Short name T451
Test name
Test status
Simulation time 2319115957 ps
CPU time 5.94 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:25 PM PDT 24
Peak memory 232452 kb
Host smart-e25fb920-54b8-4279-a328-de39bbb9a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146889741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1146889741
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3910393945
Short name T583
Test name
Test status
Simulation time 97741266 ps
CPU time 2.05 seconds
Started May 30 01:19:20 PM PDT 24
Finished May 30 01:19:24 PM PDT 24
Peak memory 215652 kb
Host smart-ecfe7339-7d0f-46ac-8954-4c8532e04ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910393945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3910393945
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3026665430
Short name T651
Test name
Test status
Simulation time 1685587165 ps
CPU time 10.27 seconds
Started May 30 01:19:20 PM PDT 24
Finished May 30 01:19:32 PM PDT 24
Peak memory 229280 kb
Host smart-8c3859bd-7878-4ae5-a4df-eec2840f937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026665430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3026665430
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1467359675
Short name T457
Test name
Test status
Simulation time 5072937137 ps
CPU time 11.03 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:31 PM PDT 24
Peak memory 221564 kb
Host smart-b8bfc0b6-00e7-4c80-92ca-2a984f102a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467359675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1467359675
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3394257807
Short name T867
Test name
Test status
Simulation time 1715105072 ps
CPU time 3.67 seconds
Started May 30 01:19:17 PM PDT 24
Finished May 30 01:19:22 PM PDT 24
Peak memory 233928 kb
Host smart-af940bba-1457-49cc-8333-384cc46572f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394257807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3394257807
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.328685403
Short name T423
Test name
Test status
Simulation time 1050488349 ps
CPU time 11.97 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:33 PM PDT 24
Peak memory 222636 kb
Host smart-e47719e0-50e4-48dc-a093-5e046db34960
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=328685403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.328685403
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1714872977
Short name T306
Test name
Test status
Simulation time 14438881409 ps
CPU time 103.06 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:21:03 PM PDT 24
Peak memory 236060 kb
Host smart-19996ec0-e088-4bb2-ad3b-d52ab8a7d113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714872977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1714872977
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1315027777
Short name T671
Test name
Test status
Simulation time 6349119756 ps
CPU time 33.34 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:54 PM PDT 24
Peak memory 215952 kb
Host smart-634cd842-8344-48d3-b649-35fac4f4adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315027777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1315027777
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2285130026
Short name T405
Test name
Test status
Simulation time 64527507830 ps
CPU time 12.39 seconds
Started May 30 01:19:20 PM PDT 24
Finished May 30 01:19:34 PM PDT 24
Peak memory 215460 kb
Host smart-114bb1a9-ce86-4ef0-98dd-c792a53eeb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285130026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2285130026
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2631159288
Short name T970
Test name
Test status
Simulation time 192618436 ps
CPU time 0.84 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:21 PM PDT 24
Peak memory 205348 kb
Host smart-2bccdb45-e4f7-4124-be1d-eeb3ba908252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631159288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2631159288
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2179239808
Short name T73
Test name
Test status
Simulation time 427387163 ps
CPU time 0.87 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:20 PM PDT 24
Peak memory 205300 kb
Host smart-e9fb7803-f3a0-4e6d-816b-6f2b4a4ff0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179239808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2179239808
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1365459686
Short name T72
Test name
Test status
Simulation time 6503175184 ps
CPU time 22.08 seconds
Started May 30 01:19:21 PM PDT 24
Finished May 30 01:19:44 PM PDT 24
Peak memory 219376 kb
Host smart-00407ca6-8af7-4fc8-9e1f-2f2c2d598b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365459686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1365459686
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.254852328
Short name T495
Test name
Test status
Simulation time 20346633 ps
CPU time 0.7 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:16:44 PM PDT 24
Peak memory 204244 kb
Host smart-28333d3e-e09d-4e8e-8023-c09d79417207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254852328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.254852328
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3127870143
Short name T726
Test name
Test status
Simulation time 41410676 ps
CPU time 2.74 seconds
Started May 30 01:16:42 PM PDT 24
Finished May 30 01:16:47 PM PDT 24
Peak memory 233260 kb
Host smart-43377df0-0660-4b61-9812-c952260403b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127870143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3127870143
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3726673331
Short name T60
Test name
Test status
Simulation time 15675633 ps
CPU time 0.78 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:16:40 PM PDT 24
Peak memory 205920 kb
Host smart-119b1ea7-8bed-400c-b7e2-287447a029db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726673331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3726673331
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.861918112
Short name T230
Test name
Test status
Simulation time 51161959036 ps
CPU time 74.17 seconds
Started May 30 01:16:43 PM PDT 24
Finished May 30 01:17:58 PM PDT 24
Peak memory 249332 kb
Host smart-2729cda1-240c-4774-af73-2aeb8b85e090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861918112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.861918112
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3761481962
Short name T28
Test name
Test status
Simulation time 24768377483 ps
CPU time 90.68 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:18:09 PM PDT 24
Peak memory 249072 kb
Host smart-cec1e747-dcc2-4ce3-925d-ec6b7a3d3d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761481962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3761481962
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2567972330
Short name T299
Test name
Test status
Simulation time 18230649762 ps
CPU time 84.46 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:18:07 PM PDT 24
Peak memory 252060 kb
Host smart-7b0d5b00-94b0-4c03-b562-d993145aa976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567972330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2567972330
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2377711519
Short name T381
Test name
Test status
Simulation time 220074561 ps
CPU time 6.25 seconds
Started May 30 01:16:36 PM PDT 24
Finished May 30 01:16:43 PM PDT 24
Peak memory 232324 kb
Host smart-3b847d44-200a-4e2a-8ca4-0deb0641fb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377711519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2377711519
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3123000112
Short name T820
Test name
Test status
Simulation time 16804611108 ps
CPU time 18.2 seconds
Started May 30 01:16:36 PM PDT 24
Finished May 30 01:16:55 PM PDT 24
Peak memory 219400 kb
Host smart-d73d6197-9204-4d25-beea-9439d292dc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123000112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3123000112
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1844016390
Short name T682
Test name
Test status
Simulation time 99746915 ps
CPU time 2.92 seconds
Started May 30 01:16:42 PM PDT 24
Finished May 30 01:16:46 PM PDT 24
Peak memory 233924 kb
Host smart-9167de65-1199-4eec-bfc1-dd8b6ad12a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844016390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1844016390
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.288503589
Short name T578
Test name
Test status
Simulation time 24156469 ps
CPU time 1.11 seconds
Started May 30 01:16:38 PM PDT 24
Finished May 30 01:16:40 PM PDT 24
Peak memory 216220 kb
Host smart-186cbb3f-cb24-4376-8a44-5c9f179c8434
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288503589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.288503589
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1189923018
Short name T300
Test name
Test status
Simulation time 14341055575 ps
CPU time 13.8 seconds
Started May 30 01:16:36 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 232412 kb
Host smart-c209f9b6-3753-4f3f-9780-877e8bba3b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189923018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1189923018
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.518052052
Short name T477
Test name
Test status
Simulation time 12844655957 ps
CPU time 36.52 seconds
Started May 30 01:16:36 PM PDT 24
Finished May 30 01:17:14 PM PDT 24
Peak memory 228204 kb
Host smart-90ed016f-83ef-4084-833e-3a0fc5e4606b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518052052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.518052052
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1997418581
Short name T40
Test name
Test status
Simulation time 58844691 ps
CPU time 3.41 seconds
Started May 30 01:16:43 PM PDT 24
Finished May 30 01:16:48 PM PDT 24
Peak memory 219556 kb
Host smart-73eb654e-8096-456d-bae7-7a2396e28375
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1997418581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1997418581
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2406899025
Short name T160
Test name
Test status
Simulation time 49826388451 ps
CPU time 402.08 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:23:20 PM PDT 24
Peak memory 270928 kb
Host smart-a37c2bff-9092-4f78-be22-060bfa67c32b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406899025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2406899025
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1248530564
Short name T878
Test name
Test status
Simulation time 38857663 ps
CPU time 0.79 seconds
Started May 30 01:16:35 PM PDT 24
Finished May 30 01:16:37 PM PDT 24
Peak memory 205060 kb
Host smart-feb20347-ff79-40c8-9ad1-e4d7431729ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248530564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1248530564
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3644026890
Short name T362
Test name
Test status
Simulation time 1548913053 ps
CPU time 8.34 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 215852 kb
Host smart-cb3ec46a-1c61-489a-999b-08f127cacd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644026890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3644026890
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1237191791
Short name T476
Test name
Test status
Simulation time 42141963 ps
CPU time 0.87 seconds
Started May 30 01:16:36 PM PDT 24
Finished May 30 01:16:38 PM PDT 24
Peak memory 205980 kb
Host smart-5c1845d1-c65c-4cbb-b796-e53a6fc757f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237191791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1237191791
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.478184111
Short name T450
Test name
Test status
Simulation time 283042186 ps
CPU time 0.96 seconds
Started May 30 01:16:38 PM PDT 24
Finished May 30 01:16:40 PM PDT 24
Peak memory 205316 kb
Host smart-69810171-a423-4418-92fa-46c6251d2b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478184111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.478184111
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3999439907
Short name T162
Test name
Test status
Simulation time 1793374870 ps
CPU time 4.58 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:16:46 PM PDT 24
Peak memory 234048 kb
Host smart-1abfe892-6770-472f-b1cd-6c4ef99b3123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999439907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3999439907
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.335753920
Short name T620
Test name
Test status
Simulation time 18955771 ps
CPU time 0.77 seconds
Started May 30 01:16:43 PM PDT 24
Finished May 30 01:16:45 PM PDT 24
Peak memory 204864 kb
Host smart-2fac7040-bd0e-4e0e-ae78-dee4da062294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335753920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.335753920
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2601124878
Short name T256
Test name
Test status
Simulation time 4141272717 ps
CPU time 10.35 seconds
Started May 30 01:16:39 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 233008 kb
Host smart-5f7586ff-93c8-44a6-9c44-d64374d941a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601124878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2601124878
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1690968137
Short name T617
Test name
Test status
Simulation time 18935915 ps
CPU time 0.82 seconds
Started May 30 01:16:38 PM PDT 24
Finished May 30 01:16:40 PM PDT 24
Peak memory 205960 kb
Host smart-a093ab5f-588c-49e9-8bf6-bfb6f87c80c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690968137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1690968137
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1006611782
Short name T821
Test name
Test status
Simulation time 73568495192 ps
CPU time 74.78 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:17:53 PM PDT 24
Peak memory 240580 kb
Host smart-52624926-490a-4b74-beba-0b09d55578b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006611782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1006611782
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2537302402
Short name T221
Test name
Test status
Simulation time 119157280437 ps
CPU time 350.32 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:22:31 PM PDT 24
Peak memory 249920 kb
Host smart-e076f9a1-eca4-4286-9567-c8a576290758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537302402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2537302402
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3310516293
Short name T273
Test name
Test status
Simulation time 131960784045 ps
CPU time 276.53 seconds
Started May 30 01:16:38 PM PDT 24
Finished May 30 01:21:16 PM PDT 24
Peak memory 254296 kb
Host smart-65863c22-6873-4adf-80ee-282440f858e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310516293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3310516293
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3657080223
Short name T940
Test name
Test status
Simulation time 5463682288 ps
CPU time 69.6 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:17:51 PM PDT 24
Peak memory 248812 kb
Host smart-e113ead2-3fe7-4e9c-96a4-4088b900028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657080223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3657080223
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1958358806
Short name T979
Test name
Test status
Simulation time 2663155272 ps
CPU time 26.61 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 233996 kb
Host smart-8940fd22-2a6b-4a29-8ebb-88bbeee6275c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958358806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1958358806
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2486703105
Short name T808
Test name
Test status
Simulation time 10070623987 ps
CPU time 65.95 seconds
Started May 30 01:16:34 PM PDT 24
Finished May 30 01:17:41 PM PDT 24
Peak memory 248792 kb
Host smart-81c1bbb7-c1ab-462d-9afe-24537ff225ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486703105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2486703105
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.620328537
Short name T715
Test name
Test status
Simulation time 14310263 ps
CPU time 1.04 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:16:39 PM PDT 24
Peak memory 216228 kb
Host smart-ee18338f-7aa0-465d-a91e-88e1ecefc06b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620328537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.620328537
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.725208544
Short name T297
Test name
Test status
Simulation time 322077407 ps
CPU time 5.57 seconds
Started May 30 01:16:42 PM PDT 24
Finished May 30 01:16:49 PM PDT 24
Peak memory 225344 kb
Host smart-4e71e2c1-9e91-4517-b81b-684c7d34c18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725208544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
725208544
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1166032935
Short name T722
Test name
Test status
Simulation time 1507423316 ps
CPU time 7.88 seconds
Started May 30 01:16:35 PM PDT 24
Finished May 30 01:16:44 PM PDT 24
Peak memory 218356 kb
Host smart-863116ad-465d-4363-ab7b-c04332b8a243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166032935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1166032935
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2512998252
Short name T490
Test name
Test status
Simulation time 953425319 ps
CPU time 8.84 seconds
Started May 30 01:16:36 PM PDT 24
Finished May 30 01:16:46 PM PDT 24
Peak memory 218324 kb
Host smart-b472fafb-38b8-4f12-803d-d731e9edeeb3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2512998252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2512998252
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1659932863
Short name T292
Test name
Test status
Simulation time 101963244948 ps
CPU time 216.96 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 256460 kb
Host smart-e360722e-533f-4430-8be3-3f9a1a40f526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659932863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1659932863
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.808581001
Short name T768
Test name
Test status
Simulation time 6255869444 ps
CPU time 15.7 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:16:58 PM PDT 24
Peak memory 215960 kb
Host smart-94d3974b-a441-426e-bddb-89ac247af581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808581001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.808581001
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.245766040
Short name T374
Test name
Test status
Simulation time 62148753367 ps
CPU time 25.32 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:17:07 PM PDT 24
Peak memory 215900 kb
Host smart-b1acff21-ddde-4087-b580-08298c23222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245766040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.245766040
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1043670616
Short name T526
Test name
Test status
Simulation time 186885360 ps
CPU time 1.52 seconds
Started May 30 01:16:38 PM PDT 24
Finished May 30 01:16:41 PM PDT 24
Peak memory 215808 kb
Host smart-452cb47c-353a-452a-b83d-0b3d335cbd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043670616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1043670616
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.246807369
Short name T842
Test name
Test status
Simulation time 67554915 ps
CPU time 0.72 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:16:38 PM PDT 24
Peak memory 205284 kb
Host smart-6f193c3a-270b-4f75-97c7-323b9f4f682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246807369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.246807369
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.461116860
Short name T245
Test name
Test status
Simulation time 4644137323 ps
CPU time 8.8 seconds
Started May 30 01:16:39 PM PDT 24
Finished May 30 01:16:49 PM PDT 24
Peak memory 229352 kb
Host smart-b698a766-62e7-45cc-9aae-b00779d5fe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461116860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.461116860
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.99421605
Short name T915
Test name
Test status
Simulation time 22145866 ps
CPU time 0.74 seconds
Started May 30 01:16:42 PM PDT 24
Finished May 30 01:16:45 PM PDT 24
Peak memory 204664 kb
Host smart-c2c0e2ce-cb62-45a7-87ae-94051ceffbee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99421605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.99421605
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4218320970
Short name T971
Test name
Test status
Simulation time 1351868640 ps
CPU time 3.99 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:16:46 PM PDT 24
Peak memory 219428 kb
Host smart-e4c19b58-2c57-4159-967d-7ec6a6f29b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218320970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4218320970
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.853905855
Short name T580
Test name
Test status
Simulation time 57277344 ps
CPU time 0.78 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:16:42 PM PDT 24
Peak memory 205952 kb
Host smart-f5ac1974-bb80-416f-8045-37c27633d2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853905855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.853905855
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3275907107
Short name T13
Test name
Test status
Simulation time 70788839763 ps
CPU time 64.86 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:17:43 PM PDT 24
Peak memory 249524 kb
Host smart-86a56036-b930-472b-9581-f6cd1976ec52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275907107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3275907107
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2268420087
Short name T134
Test name
Test status
Simulation time 16240271419 ps
CPU time 87.03 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:18:05 PM PDT 24
Peak memory 232476 kb
Host smart-489c8217-0689-450b-9228-512052c9d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268420087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2268420087
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3484508361
Short name T32
Test name
Test status
Simulation time 52569587691 ps
CPU time 306.68 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:21:48 PM PDT 24
Peak memory 263416 kb
Host smart-36773e97-9c62-4f9a-9b16-ac5e1ce6b686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484508361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3484508361
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.284370699
Short name T582
Test name
Test status
Simulation time 1261424828 ps
CPU time 6.76 seconds
Started May 30 01:16:39 PM PDT 24
Finished May 30 01:16:47 PM PDT 24
Peak memory 224188 kb
Host smart-62768a1c-e057-46ee-aa6b-d17f14557e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284370699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.284370699
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1148011608
Short name T183
Test name
Test status
Simulation time 14431307225 ps
CPU time 20.8 seconds
Started May 30 01:16:43 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 219244 kb
Host smart-f429227b-cf4f-4b9f-99f4-e7c84dca71f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148011608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1148011608
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1600078224
Short name T930
Test name
Test status
Simulation time 7370884918 ps
CPU time 18.64 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:17:01 PM PDT 24
Peak memory 239228 kb
Host smart-e22d7134-1b93-414c-ab2f-df98c34dc42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600078224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1600078224
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.749604809
Short name T880
Test name
Test status
Simulation time 353883218 ps
CPU time 1.02 seconds
Started May 30 01:16:39 PM PDT 24
Finished May 30 01:16:42 PM PDT 24
Peak memory 216212 kb
Host smart-dfd63201-9f06-43c7-9ed0-edf1ee484550
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749604809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.749604809
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3676391158
Short name T642
Test name
Test status
Simulation time 6858348857 ps
CPU time 10.65 seconds
Started May 30 01:16:34 PM PDT 24
Finished May 30 01:16:45 PM PDT 24
Peak memory 233428 kb
Host smart-776e71a7-c173-4703-a283-030268b279ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676391158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3676391158
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.292072026
Short name T241
Test name
Test status
Simulation time 495521187 ps
CPU time 3.38 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:16:42 PM PDT 24
Peak memory 219448 kb
Host smart-c7241f22-4ce8-4158-9897-06c2f8944992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292072026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.292072026
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3243310412
Short name T914
Test name
Test status
Simulation time 2805696390 ps
CPU time 9.24 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 222284 kb
Host smart-eeba10b6-b076-4866-ad31-7aeb8845fa20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3243310412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3243310412
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2105248763
Short name T46
Test name
Test status
Simulation time 14884771783 ps
CPU time 232.98 seconds
Started May 30 01:16:34 PM PDT 24
Finished May 30 01:20:28 PM PDT 24
Peak memory 263796 kb
Host smart-07e28952-cb1f-4a69-baf0-58110852eb1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105248763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2105248763
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3738850186
Short name T936
Test name
Test status
Simulation time 3852665609 ps
CPU time 6.8 seconds
Started May 30 01:16:42 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 215976 kb
Host smart-692e2d00-fd48-44ff-a33d-4da48862cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738850186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3738850186
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.804829780
Short name T442
Test name
Test status
Simulation time 8516091756 ps
CPU time 23.14 seconds
Started May 30 01:16:38 PM PDT 24
Finished May 30 01:17:03 PM PDT 24
Peak memory 215980 kb
Host smart-44684a7b-edc9-4647-8fa6-47d402dc3511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804829780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.804829780
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3712613085
Short name T543
Test name
Test status
Simulation time 32858879 ps
CPU time 1.61 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:16:41 PM PDT 24
Peak memory 215872 kb
Host smart-41f0cb1b-b571-41a9-a3e7-d5c499bf3311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712613085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3712613085
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1244518681
Short name T831
Test name
Test status
Simulation time 40046872 ps
CPU time 0.74 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:16:43 PM PDT 24
Peak memory 204956 kb
Host smart-64971f9e-be12-485e-998b-81b45e0a7f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244518681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1244518681
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4273032042
Short name T493
Test name
Test status
Simulation time 12003683134 ps
CPU time 40.3 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:17:18 PM PDT 24
Peak memory 237912 kb
Host smart-1dd8e717-2ea3-4483-ae3c-53ceb8cbb12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273032042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4273032042
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3377722061
Short name T427
Test name
Test status
Simulation time 45716097 ps
CPU time 0.71 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:16:54 PM PDT 24
Peak memory 204848 kb
Host smart-5bf8d291-40fd-4e9b-a7c0-c8a1d1e5f2d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377722061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
377722061
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.450552956
Short name T247
Test name
Test status
Simulation time 487811305 ps
CPU time 3.87 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:16:46 PM PDT 24
Peak memory 234092 kb
Host smart-c377035b-deba-4bbe-a9f0-563456c4eeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450552956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.450552956
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1871749834
Short name T797
Test name
Test status
Simulation time 26776561 ps
CPU time 0.78 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:16:43 PM PDT 24
Peak memory 205896 kb
Host smart-c8b2860f-7f13-4987-87d1-8b10269371a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871749834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1871749834
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4200955734
Short name T37
Test name
Test status
Simulation time 28704613244 ps
CPU time 226.17 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:20:39 PM PDT 24
Peak memory 250596 kb
Host smart-c9a41668-e227-401b-9bdd-276b59d109ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200955734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4200955734
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2450466783
Short name T772
Test name
Test status
Simulation time 3355634386 ps
CPU time 19.45 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:17:12 PM PDT 24
Peak memory 217096 kb
Host smart-be8c5219-b596-4f09-b167-dd012ae23ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450466783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2450466783
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3920007000
Short name T212
Test name
Test status
Simulation time 98578512302 ps
CPU time 265.85 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:21:20 PM PDT 24
Peak memory 252940 kb
Host smart-c4c47401-b80b-40f8-a1f1-377e1b9e8bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920007000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3920007000
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3338209367
Short name T806
Test name
Test status
Simulation time 1494647039 ps
CPU time 25.14 seconds
Started May 30 01:16:48 PM PDT 24
Finished May 30 01:17:14 PM PDT 24
Peak memory 232288 kb
Host smart-b922572f-1a41-4393-8c4d-25805448a898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338209367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3338209367
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2225816934
Short name T452
Test name
Test status
Simulation time 663871708 ps
CPU time 4.39 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:16:46 PM PDT 24
Peak memory 233152 kb
Host smart-3107a598-cd29-4057-abd5-9a616c0ad6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225816934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2225816934
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.482045214
Short name T552
Test name
Test status
Simulation time 111345273 ps
CPU time 3.31 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:16:45 PM PDT 24
Peak memory 218060 kb
Host smart-a9c3ee35-f5e5-4cca-a030-ffbf80ff31ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482045214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.482045214
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3104519351
Short name T408
Test name
Test status
Simulation time 25780382 ps
CPU time 1.16 seconds
Started May 30 01:16:42 PM PDT 24
Finished May 30 01:16:45 PM PDT 24
Peak memory 216304 kb
Host smart-5f38c902-64a3-4e92-b83c-bd55a23db05a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104519351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3104519351
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3789181106
Short name T733
Test name
Test status
Simulation time 181682235 ps
CPU time 2.68 seconds
Started May 30 01:16:37 PM PDT 24
Finished May 30 01:16:41 PM PDT 24
Peak memory 220892 kb
Host smart-c8f182fa-f1b7-4cdc-8784-e2dd1e4d38b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789181106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3789181106
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2214074879
Short name T570
Test name
Test status
Simulation time 296382654 ps
CPU time 3.75 seconds
Started May 30 01:16:42 PM PDT 24
Finished May 30 01:16:48 PM PDT 24
Peak memory 233252 kb
Host smart-c0c08dce-6623-48a3-8db2-78ab8eac751f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214074879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2214074879
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3015757388
Short name T637
Test name
Test status
Simulation time 538957847 ps
CPU time 3.84 seconds
Started May 30 01:16:48 PM PDT 24
Finished May 30 01:16:52 PM PDT 24
Peak memory 218488 kb
Host smart-438fa3b1-a137-4838-a5ab-3ca95c3a60ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3015757388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3015757388
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1244189384
Short name T911
Test name
Test status
Simulation time 20165041538 ps
CPU time 262.32 seconds
Started May 30 01:16:49 PM PDT 24
Finished May 30 01:21:13 PM PDT 24
Peak memory 257108 kb
Host smart-07df67c6-d41a-4cbb-9ec6-d0474122995f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244189384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1244189384
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2745096528
Short name T735
Test name
Test status
Simulation time 3118866482 ps
CPU time 22.84 seconds
Started May 30 01:16:41 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 215908 kb
Host smart-39da30ef-386b-41ea-bc3b-73005ee2cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745096528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2745096528
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.528688217
Short name T648
Test name
Test status
Simulation time 1729433543 ps
CPU time 1.85 seconds
Started May 30 01:16:40 PM PDT 24
Finished May 30 01:16:44 PM PDT 24
Peak memory 207276 kb
Host smart-47d60dd8-5917-4aac-8a08-0c9ed370c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528688217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.528688217
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.235695058
Short name T592
Test name
Test status
Simulation time 66036357 ps
CPU time 1.1 seconds
Started May 30 01:16:38 PM PDT 24
Finished May 30 01:16:41 PM PDT 24
Peak memory 207368 kb
Host smart-ea1508ee-cf25-47d9-aaf1-64e22e583ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235695058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.235695058
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3784511245
Short name T856
Test name
Test status
Simulation time 455549528 ps
CPU time 0.8 seconds
Started May 30 01:16:39 PM PDT 24
Finished May 30 01:16:41 PM PDT 24
Peak memory 205256 kb
Host smart-2aa4d842-85c7-43fd-b2ba-63c4f6c1ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784511245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3784511245
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1858537389
Short name T226
Test name
Test status
Simulation time 280316271 ps
CPU time 2.72 seconds
Started May 30 01:16:39 PM PDT 24
Finished May 30 01:16:43 PM PDT 24
Peak memory 232372 kb
Host smart-36848d71-453c-4955-8ecf-9acb55e6a9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858537389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1858537389
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3680425714
Short name T865
Test name
Test status
Simulation time 16292465 ps
CPU time 0.7 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:16:54 PM PDT 24
Peak memory 204924 kb
Host smart-1902fa46-5f5d-4989-ac1d-b83bfc43ab90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680425714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
680425714
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.32509783
Short name T871
Test name
Test status
Simulation time 121870420 ps
CPU time 2.46 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:16:56 PM PDT 24
Peak memory 221164 kb
Host smart-745680b6-ccae-4fd1-b333-73777a60f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32509783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.32509783
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3251464485
Short name T340
Test name
Test status
Simulation time 36544898 ps
CPU time 0.74 seconds
Started May 30 01:16:49 PM PDT 24
Finished May 30 01:16:51 PM PDT 24
Peak memory 204872 kb
Host smart-34a5b368-116f-4aed-b7cf-cac4ffeb2ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251464485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3251464485
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2439532402
Short name T236
Test name
Test status
Simulation time 3281279861 ps
CPU time 33.32 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:17:26 PM PDT 24
Peak memory 235668 kb
Host smart-4d07fba7-b10c-4d35-85a8-f17304182b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439532402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2439532402
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2988147011
Short name T194
Test name
Test status
Simulation time 2700274259 ps
CPU time 34.71 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:17:27 PM PDT 24
Peak memory 224272 kb
Host smart-6fc87074-2253-45bb-bc63-10c0d2a6d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988147011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2988147011
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.392904714
Short name T872
Test name
Test status
Simulation time 178471169 ps
CPU time 3.19 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:16:55 PM PDT 24
Peak memory 216948 kb
Host smart-def20055-11e6-48cc-8c44-c521bbfd6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392904714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
392904714
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.521965418
Short name T313
Test name
Test status
Simulation time 664848130 ps
CPU time 10.1 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:17:04 PM PDT 24
Peak memory 234412 kb
Host smart-cfbda804-b234-41f4-96ae-4bfa838073dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521965418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.521965418
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.507628484
Short name T663
Test name
Test status
Simulation time 1956462647 ps
CPU time 7.3 seconds
Started May 30 01:16:48 PM PDT 24
Finished May 30 01:16:56 PM PDT 24
Peak memory 219520 kb
Host smart-74989fe8-d898-4c85-9155-d43ce3880baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507628484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.507628484
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.133754266
Short name T918
Test name
Test status
Simulation time 2944236214 ps
CPU time 13.12 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:17:06 PM PDT 24
Peak memory 223716 kb
Host smart-48ead993-69da-4de7-bab5-fdcf8b856ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133754266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.133754266
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2686626995
Short name T460
Test name
Test status
Simulation time 14426857 ps
CPU time 1.02 seconds
Started May 30 01:16:48 PM PDT 24
Finished May 30 01:16:50 PM PDT 24
Peak memory 216224 kb
Host smart-4f8e7986-a9f6-486f-8456-273f6eaee6eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686626995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2686626995
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2442583665
Short name T289
Test name
Test status
Simulation time 2436776002 ps
CPU time 10.87 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:17:02 PM PDT 24
Peak memory 248496 kb
Host smart-f2c5d9d8-d63f-4aa7-9290-ddca2153bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442583665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2442583665
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4088221100
Short name T185
Test name
Test status
Simulation time 3563376452 ps
CPU time 5.46 seconds
Started May 30 01:16:52 PM PDT 24
Finished May 30 01:16:59 PM PDT 24
Peak memory 217132 kb
Host smart-700173a6-eda2-47a9-9a6f-606b119c6649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088221100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4088221100
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2770384627
Short name T924
Test name
Test status
Simulation time 3918119091 ps
CPU time 12.4 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:17:05 PM PDT 24
Peak memory 219672 kb
Host smart-93578868-8cc3-49fd-8429-ab4cb65a491a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2770384627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2770384627
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2658216755
Short name T155
Test name
Test status
Simulation time 37206710987 ps
CPU time 56.45 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:17:49 PM PDT 24
Peak memory 224244 kb
Host smart-0ba05221-962b-4e40-bfda-30b636ff4bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658216755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2658216755
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3922977965
Short name T602
Test name
Test status
Simulation time 34413224735 ps
CPU time 23.08 seconds
Started May 30 01:16:49 PM PDT 24
Finished May 30 01:17:14 PM PDT 24
Peak memory 216024 kb
Host smart-6cba1646-3789-4997-a2b2-937ea81f6db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922977965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3922977965
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.948319688
Short name T132
Test name
Test status
Simulation time 684011210 ps
CPU time 2.2 seconds
Started May 30 01:16:55 PM PDT 24
Finished May 30 01:16:59 PM PDT 24
Peak memory 215640 kb
Host smart-061097cc-eadc-4b9c-bcc0-cc6474f201b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948319688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.948319688
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2551732445
Short name T325
Test name
Test status
Simulation time 242216964 ps
CPU time 2.07 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:16:53 PM PDT 24
Peak memory 215892 kb
Host smart-f57744a2-34aa-4389-b272-d8ec71963ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551732445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2551732445
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3202207932
Short name T809
Test name
Test status
Simulation time 270185999 ps
CPU time 0.91 seconds
Started May 30 01:16:51 PM PDT 24
Finished May 30 01:16:53 PM PDT 24
Peak memory 206316 kb
Host smart-fe393e93-4d95-408f-b534-4dc9ff2669ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202207932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3202207932
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.224472233
Short name T439
Test name
Test status
Simulation time 6471372333 ps
CPU time 20.86 seconds
Started May 30 01:16:50 PM PDT 24
Finished May 30 01:17:12 PM PDT 24
Peak memory 227352 kb
Host smart-fbbed5f7-4043-4055-b775-7c7137cd557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224472233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.224472233
Directory /workspace/9.spi_device_upload/latest
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