Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3409726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4010422

1

T1

49770

T2

1237

T3

899

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4163817	1			T1	78041		T2	725		T3	7
values[0x0]	1627046	1			T1	26084		T2	456		T3	457
values[0x1]	1629285	1			T1	26020		T2	439		T3	437

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2430447	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4989701

1

T1

75107

T2

1306

T3

900

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26339	1			T1	472		T2	8		T3	3
valid_sources[0x01]	31336	1			T1	1576		T2	4		T3	6
valid_sources[0x02]	26589	1			T1	839		T2	7		T3	5
valid_sources[0x03]	26246	1			T1	329		T2	5		T3	5
valid_sources[0x04]	29177	1			T1	363		T2	5		T3	3
valid_sources[0x05]	31853	1			T1	332		T2	7		T3	1
valid_sources[0x06]	31594	1			T1	275		T2	13		T3	4
valid_sources[0x07]	28044	1			T1	690		T2	2		T3	5
valid_sources[0x08]	32743	1			T1	751		T2	7		T3	2
valid_sources[0x09]	27305	1			T1	412		T2	7		T3	5
valid_sources[0x0a]	26438	1			T1	802		T2	9		T3	5
valid_sources[0x0b]	26715	1			T1	730		T2	6		T3	4
valid_sources[0x0c]	27186	1			T1	522		T2	5		T3	5
valid_sources[0x0d]	28370	1			T1	688		T2	4		T3	2
valid_sources[0x0e]	27519	1			T1	424		T2	7		T3	6
valid_sources[0x0f]	29543	1			T1	935		T2	7		T3	2
valid_sources[0x10]	29589	1			T1	466		T2	2		T3	2
valid_sources[0x11]	27603	1			T1	561		T2	9		T3	1
valid_sources[0x12]	32096	1			T1	665		T2	5		T3	5
valid_sources[0x13]	28070	1			T1	633		T2	3		T3	5
valid_sources[0x14]	27800	1			T1	493		T2	7		T3	8
valid_sources[0x15]	28537	1			T1	335		T2	5		T3	4
valid_sources[0x16]	27447	1			T1	464		T2	10		T3	1
valid_sources[0x17]	27947	1			T1	318		T2	5		T3	4
valid_sources[0x18]	28102	1			T1	443		T2	7		T3	1
valid_sources[0x19]	29462	1			T1	615		T2	5		T3	6
valid_sources[0x1a]	27629	1			T1	645		T2	10		T3	6
valid_sources[0x1b]	29807	1			T1	348		T2	4		T3	1
valid_sources[0x1c]	30689	1			T1	436		T2	4		T3	1
valid_sources[0x1d]	26011	1			T1	489		T2	3		T3	8
valid_sources[0x1e]	28332	1			T1	118		T2	3		T3	2
valid_sources[0x1f]	26694	1			T1	405		T2	4		T3	2
valid_sources[0x20]	32639	1			T1	176		T2	6		T3	4
valid_sources[0x21]	27864	1			T1	445		T2	2		T3	3
valid_sources[0x22]	28248	1			T1	559		T2	7		T3	3
valid_sources[0x23]	26962	1			T1	504		T2	11		T3	2
valid_sources[0x24]	35722	1			T1	421		T2	7		T3	9
valid_sources[0x25]	26843	1			T1	475		T2	3		T3	2
valid_sources[0x26]	30908	1			T1	492		T2	9		T3	2
valid_sources[0x27]	27202	1			T1	818		T2	8		T3	6
valid_sources[0x28]	26590	1			T1	248		T2	5		T3	3
valid_sources[0x29]	27163	1			T1	348		T2	8		T3	3
valid_sources[0x2a]	27473	1			T1	413		T2	7		T3	7
valid_sources[0x2b]	29191	1			T1	464		T2	5		T3	5
valid_sources[0x2c]	27490	1			T1	232		T2	8		T3	3
valid_sources[0x2d]	25995	1			T1	492		T2	5		T3	1
valid_sources[0x2e]	27404	1			T1	331		T2	8		T3	4
valid_sources[0x2f]	60863	1			T1	977		T2	4		T3	3
valid_sources[0x30]	29203	1			T1	1219		T2	4		T3	7
valid_sources[0x31]	29898	1			T1	660		T2	9		T3	3
valid_sources[0x32]	28660	1			T1	460		T2	3		T3	5
valid_sources[0x33]	27100	1			T1	142		T2	6		T3	4
valid_sources[0x34]	28935	1			T1	1216		T2	4		T3	2
valid_sources[0x35]	25678	1			T1	290		T2	9		T3	5
valid_sources[0x36]	26466	1			T1	531		T2	8		T3	2
valid_sources[0x37]	26769	1			T1	754		T2	7		T3	4
valid_sources[0x38]	29401	1			T1	298		T2	5		T3	4
valid_sources[0x39]	27561	1			T1	344		T2	2		T3	3
valid_sources[0x3a]	65839	1			T1	790		T2	6		T3	3
valid_sources[0x3b]	26339	1			T1	380		T2	8		T3	2
valid_sources[0x3c]	28090	1			T1	478		T2	2		T3	6
valid_sources[0x3d]	28356	1			T1	343		T2	3		T3	2
valid_sources[0x3e]	27538	1			T1	851		T2	8		T3	3
valid_sources[0x3f]	26605	1			T1	424		T2	4		T3	2
valid_sources[0x40]	26656	1			T1	511		T2	5		T3	4
valid_sources[0x41]	28506	1			T1	884		T2	4		T3	6
valid_sources[0x42]	27027	1			T1	558		T2	3		T3	4
valid_sources[0x43]	32598	1			T1	367		T2	6		T3	4
valid_sources[0x44]	28014	1			T1	421		T2	5		T3	2
valid_sources[0x45]	33431	1			T1	351		T2	10		T3	8
valid_sources[0x46]	32392	1			T1	789		T2	2		T3	2
valid_sources[0x47]	27089	1			T1	746		T2	8		T3	8
valid_sources[0x48]	26725	1			T1	481		T2	5		T3	3
valid_sources[0x49]	26843	1			T1	752		T2	5		T3	2
valid_sources[0x4a]	26817	1			T1	651		T2	8		T3	2
valid_sources[0x4b]	31988	1			T1	540		T2	6		T4	27
valid_sources[0x4c]	27897	1			T1	663		T2	5		T3	4
valid_sources[0x4d]	28149	1			T1	672		T2	8		T3	4
valid_sources[0x4e]	30146	1			T1	462		T2	2		T3	4
valid_sources[0x4f]	34845	1			T1	632		T2	7		T3	2
valid_sources[0x50]	27640	1			T1	629		T2	8		T3	1
valid_sources[0x51]	27276	1			T1	141		T2	4		T3	8
valid_sources[0x52]	27953	1			T1	604		T2	9		T3	4
valid_sources[0x53]	28812	1			T1	446		T2	6		T3	3
valid_sources[0x54]	27167	1			T1	510		T2	9		T3	2
valid_sources[0x55]	27623	1			T1	708		T2	6		T3	1
valid_sources[0x56]	27967	1			T1	62		T2	5		T3	3
valid_sources[0x57]	28895	1			T1	364		T2	3		T3	3
valid_sources[0x58]	27172	1			T1	441		T2	4		T3	4
valid_sources[0x59]	29967	1			T1	438		T2	9		T3	5
valid_sources[0x5a]	25443	1			T1	230		T2	13		T3	3
valid_sources[0x5b]	29172	1			T1	778		T2	9		T3	9
valid_sources[0x5c]	29508	1			T1	237		T2	9		T3	6
valid_sources[0x5d]	27519	1			T1	688		T2	6		T3	1
valid_sources[0x5e]	26502	1			T1	266		T2	6		T3	1
valid_sources[0x5f]	26371	1			T1	341		T2	7		T3	3
valid_sources[0x60]	26194	1			T1	610		T2	6		T3	4
valid_sources[0x61]	28484	1			T1	246		T2	7		T3	4
valid_sources[0x62]	39837	1			T1	590		T2	6		T3	3
valid_sources[0x63]	30082	1			T1	542		T2	7		T3	2
valid_sources[0x64]	27784	1			T1	275		T2	6		T3	2
valid_sources[0x65]	30632	1			T1	366		T2	7		T3	2
valid_sources[0x66]	27368	1			T1	438		T2	10		T3	1
valid_sources[0x67]	27360	1			T1	702		T2	4		T3	4
valid_sources[0x68]	27801	1			T1	342		T2	8		T3	4
valid_sources[0x69]	28147	1			T1	748		T2	4		T3	1
valid_sources[0x6a]	27095	1			T1	527		T2	2		T3	1
valid_sources[0x6b]	25603	1			T1	493		T2	7		T3	8
valid_sources[0x6c]	26848	1			T1	554		T2	5		T3	1
valid_sources[0x6d]	28059	1			T1	922		T2	5		T3	2
valid_sources[0x6e]	25824	1			T1	440		T2	5		T3	2
valid_sources[0x6f]	28624	1			T1	429		T2	5		T3	4
valid_sources[0x70]	38931	1			T1	206		T2	9		T3	7
valid_sources[0x71]	34674	1			T1	275		T2	9		T3	3
valid_sources[0x72]	29722	1			T1	655		T2	2		T3	7
valid_sources[0x73]	25985	1			T1	490		T2	6		T3	3
valid_sources[0x74]	28094	1			T1	401		T2	8		T3	6
valid_sources[0x75]	29808	1			T1	405		T2	7		T3	3
valid_sources[0x76]	28569	1			T1	926		T2	6		T3	3
valid_sources[0x77]	27821	1			T1	318		T2	2		T3	4
valid_sources[0x78]	28824	1			T1	911		T2	11		T3	7
valid_sources[0x79]	27618	1			T1	1291		T2	5		T3	4
valid_sources[0x7a]	27176	1			T1	625		T2	8		T3	4
valid_sources[0x7b]	27416	1			T1	456		T2	3		T3	1
valid_sources[0x7c]	26512	1			T1	363		T2	3		T3	3
valid_sources[0x7d]	26992	1			T1	347		T2	6		T3	4
valid_sources[0x7e]	28196	1			T1	489		T2	8		T3	1
valid_sources[0x7f]	27588	1			T1	181		T2	3		T3	4
valid_sources[0x80]	27458	1			T1	642		T2	5		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1065781

1

T1

5547

T2

347

T3

6

values[0x0]

all_enables

biggest_size

1483309

1

T1

22335

T2

456

T3

456

values[0x1]

all_enables

biggest_size

1461332

1

T1

21888

T2

434

T3

437