Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3428583

1

T1

80375

T2

383

T3

2

full_word

4009512

1

T1

49770

T2

1237

T3

899

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7437675	1			T1	130145		T2	1620		T3	901
auto[TlIntgErrCmd]	150	1			T96	7		T98	6		T101	3
auto[TlIntgErrData]	138	1			T96	6		T98	8		T101	4
auto[TlIntgErrBoth]	132	1			T96	7		T98	6		T101	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4165110

1

T1

78041

T2

725

T3

7

auto[1]

3272985

1

T1

52104

T2

895

T3

894

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3099098	1			T1	72494		T2	378		T3	1
auto[TlIntgErrNone]	partial	auto[1]	329096	1			T1	7881		T2	5		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	1065833	1			T1	5547		T2	347		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	2943648	1			T1	44223		T2	890		T3	893
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T96	3		T98	2		T103	2
auto[TlIntgErrCmd]	partial	auto[1]	88	1			T96	3		T98	4		T101	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T118	1		T149	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T96	1		T103	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T96	1		T98	3		T101	3
auto[TlIntgErrData]	partial	auto[1]	74	1			T96	4		T98	5		T101	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T96	1		T103	1		T149	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T103	1		T179	1		T180	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T96	2		T98	2		T101	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T96	5		T98	3		T101	2
auto[TlIntgErrBoth]	full_word	auto[0]	10	1			T98	1		T103	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T103	1		T118	1		T175	2