Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T6,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Unreachable
1	1	Covered	T1,T6,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T20

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T20
1	0	Covered	T1,T7,T20

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T7,T20

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T20

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	639017924	504524495	0	0
CheckNGreaterZero_A	2775	2775	0	0
GntImpliesReady_A	639017924	3139063	0	0
GntImpliesValid_A	639017924	3139063	0	0
GrantKnown_A	639017924	504524495	0	0
IdxKnown_A	639017924	504524495	0	0
IndexIsCorrect_A	639017924	3139063	0	0
LockArbDecision_A	639017924	0	0	0
NoReadyValidNoGrant_A	639017924	0	0	0
ReadyAndValidImplyGrant_A	639017924	3139063	0	0
ReqAndReadyImplyGrant_A	639017924	3139063	0	0
ReqImpliesValid_A	639017924	3139063	0	0
ReqStaysHighUntilGranted0_M	639017924	0	0	0
RoundRobin_A	639017924	4	0	925
ValidKnown_A	639017924	504524495	0	0
gen_data_port_assertion.DataFlow_A	639017924	3139063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	504524495	0	0
T1	876752	1735559	0	0
T2	21233	17277	0	0
T3	517058	452632	0	0
T4	474451	356763	0	0
T5	1212	1145	0	0
T6	10924	6421	0	0
T7	601109	413987	0	0
T8	6183	5036	0	0
T9	57948	36195	0	0
T10	108861	87690	0	0
T11	156558	78178	0	0
T12	0	8272	0	0
T13	0	97488	0	0
T14	0	105720	0	0
T15	0	5848	0	0
T16	0	1024	0	0
T17	0	1008	0	0
T18	0	325312	0	0
T19	0	10384	0	0
T45	0	92208	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2775	2775	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	3139063	0	0
T1	876752	20784	0	0
T2	21233	832	0	0
T3	517058	832	0	0
T4	474451	832	0	0
T5	1212	0	0	0
T6	10924	104	0	0
T7	601109	3676	0	0
T8	6183	0	0	0
T9	57948	832	0	0
T10	108861	832	0	0
T11	156558	832	0	0
T12	0	832	0	0
T14	0	5105	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T20	0	1388	0	0
T21	0	5097	0	0
T27	0	258	0	0
T28	0	2411	0	0
T29	0	1616	0	0
T30	0	9359	0	0
T46	0	4312	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	3139063	0	0
T1	876752	20784	0	0
T2	21233	832	0	0
T3	517058	832	0	0
T4	474451	832	0	0
T5	1212	0	0	0
T6	10924	104	0	0
T7	601109	3676	0	0
T8	6183	0	0	0
T9	57948	832	0	0
T10	108861	832	0	0
T11	156558	832	0	0
T12	0	832	0	0
T14	0	5105	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T20	0	1388	0	0
T21	0	5097	0	0
T27	0	258	0	0
T28	0	2411	0	0
T29	0	1616	0	0
T30	0	9359	0	0
T46	0	4312	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	504524495	0	0
T1	876752	1735559	0	0
T2	21233	17277	0	0
T3	517058	452632	0	0
T4	474451	356763	0	0
T5	1212	1145	0	0
T6	10924	6421	0	0
T7	601109	413987	0	0
T8	6183	5036	0	0
T9	57948	36195	0	0
T10	108861	87690	0	0
T11	156558	78178	0	0
T12	0	8272	0	0
T13	0	97488	0	0
T14	0	105720	0	0
T15	0	5848	0	0
T16	0	1024	0	0
T17	0	1008	0	0
T18	0	325312	0	0
T19	0	10384	0	0
T45	0	92208	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	504524495	0	0
T1	876752	1735559	0	0
T2	21233	17277	0	0
T3	517058	452632	0	0
T4	474451	356763	0	0
T5	1212	1145	0	0
T6	10924	6421	0	0
T7	601109	413987	0	0
T8	6183	5036	0	0
T9	57948	36195	0	0
T10	108861	87690	0	0
T11	156558	78178	0	0
T12	0	8272	0	0
T13	0	97488	0	0
T14	0	105720	0	0
T15	0	5848	0	0
T16	0	1024	0	0
T17	0	1008	0	0
T18	0	325312	0	0
T19	0	10384	0	0
T45	0	92208	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	3139063	0	0
T1	876752	20784	0	0
T2	21233	832	0	0
T3	517058	832	0	0
T4	474451	832	0	0
T5	1212	0	0	0
T6	10924	104	0	0
T7	601109	3676	0	0
T8	6183	0	0	0
T9	57948	832	0	0
T10	108861	832	0	0
T11	156558	832	0	0
T12	0	832	0	0
T14	0	5105	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T20	0	1388	0	0
T21	0	5097	0	0
T27	0	258	0	0
T28	0	2411	0	0
T29	0	1616	0	0
T30	0	9359	0	0
T46	0	4312	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	3139063	0	0
T1	876752	20784	0	0
T2	21233	832	0	0
T3	517058	832	0	0
T4	474451	832	0	0
T5	1212	0	0	0
T6	10924	104	0	0
T7	601109	3676	0	0
T8	6183	0	0	0
T9	57948	832	0	0
T10	108861	832	0	0
T11	156558	832	0	0
T12	0	832	0	0
T14	0	5105	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T20	0	1388	0	0
T21	0	5097	0	0
T27	0	258	0	0
T28	0	2411	0	0
T29	0	1616	0	0
T30	0	9359	0	0
T46	0	4312	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	3139063	0	0
T1	876752	20784	0	0
T2	21233	832	0	0
T3	517058	832	0	0
T4	474451	832	0	0
T5	1212	0	0	0
T6	10924	104	0	0
T7	601109	3676	0	0
T8	6183	0	0	0
T9	57948	832	0	0
T10	108861	832	0	0
T11	156558	832	0	0
T12	0	832	0	0
T14	0	5105	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T20	0	1388	0	0
T21	0	5097	0	0
T27	0	258	0	0
T28	0	2411	0	0
T29	0	1616	0	0
T30	0	9359	0	0
T46	0	4312	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	3139063	0	0
T1	876752	20784	0	0
T2	21233	832	0	0
T3	517058	832	0	0
T4	474451	832	0	0
T5	1212	0	0	0
T6	10924	104	0	0
T7	601109	3676	0	0
T8	6183	0	0	0
T9	57948	832	0	0
T10	108861	832	0	0
T11	156558	832	0	0
T12	0	832	0	0
T14	0	5105	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T20	0	1388	0	0
T21	0	5097	0	0
T27	0	258	0	0
T28	0	2411	0	0
T29	0	1616	0	0
T30	0	9359	0	0
T46	0	4312	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	4	0	925
T26	3007	0	0	1
T47	927220	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	1574	0	0	1
T52	248477	0	0	1
T53	264207	0	0	1
T54	120757	0	0	1
T55	46718	0	0	1
T56	191864	0	0	1
T57	1083	0	0	1
T58	126528	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	504524495	0	0
T1	876752	1735559	0	0
T2	21233	17277	0	0
T3	517058	452632	0	0
T4	474451	356763	0	0
T5	1212	1145	0	0
T6	10924	6421	0	0
T7	601109	413987	0	0
T8	6183	5036	0	0
T9	57948	36195	0	0
T10	108861	87690	0	0
T11	156558	78178	0	0
T12	0	8272	0	0
T13	0	97488	0	0
T14	0	105720	0	0
T15	0	5848	0	0
T16	0	1024	0	0
T17	0	1008	0	0
T18	0	325312	0	0
T19	0	10384	0	0
T45	0	92208	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639017924	3139063	0	0
T1	876752	20784	0	0
T2	21233	832	0	0
T3	517058	832	0	0
T4	474451	832	0	0
T5	1212	0	0	0
T6	10924	104	0	0
T7	601109	3676	0	0
T8	6183	0	0	0
T9	57948	832	0	0
T10	108861	832	0	0
T11	156558	832	0	0
T12	0	832	0	0
T14	0	5105	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T20	0	1388	0	0
T21	0	5097	0	0
T27	0	258	0	0
T28	0	2411	0	0
T29	0	1616	0	0
T30	0	9359	0	0
T46	0	4312	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T6,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Unreachable
1	1	Covered	T1,T6,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T14
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	133137849	28510553	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	133137849	618215	0	0
GntImpliesValid_A	133137849	618215	0	0
GrantKnown_A	133137849	28510553	0	0
IdxKnown_A	133137849	28510553	0	0
IndexIsCorrect_A	133137849	618215	0	0
LockArbDecision_A	133137849	0	0	0
NoReadyValidNoGrant_A	133137849	0	0	0
ReadyAndValidImplyGrant_A	133137849	618215	0	0
ReqAndReadyImplyGrant_A	133137849	618215	0	0
ReqImpliesValid_A	133137849	618215	0	0
ReqStaysHighUntilGranted0_M	133137849	0	0	0
RoundRobin_A	133137849	0	0	0
ValidKnown_A	133137849	28510553	0	0
gen_data_port_assertion.DataFlow_A	133137849	618215	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	28510553	0	0
T1	108855	132960	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	4424	0	0
T7	185763	0	0	0
T8	754	432	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T13	0	97488	0	0
T14	0	105720	0	0
T15	0	5848	0	0
T16	0	1024	0	0
T17	0	1008	0	0
T18	0	325312	0	0
T45	0	92208	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	618215	0	0
T1	108855	6043	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	53	0	0
T7	185763	0	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	4889	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T21	0	4958	0	0
T28	0	2401	0	0
T29	0	1616	0	0
T46	0	4312	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	618215	0	0
T1	108855	6043	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	53	0	0
T7	185763	0	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	4889	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T21	0	4958	0	0
T28	0	2401	0	0
T29	0	1616	0	0
T46	0	4312	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	28510553	0	0
T1	108855	132960	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	4424	0	0
T7	185763	0	0	0
T8	754	432	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T13	0	97488	0	0
T14	0	105720	0	0
T15	0	5848	0	0
T16	0	1024	0	0
T17	0	1008	0	0
T18	0	325312	0	0
T45	0	92208	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	28510553	0	0
T1	108855	132960	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	4424	0	0
T7	185763	0	0	0
T8	754	432	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T13	0	97488	0	0
T14	0	105720	0	0
T15	0	5848	0	0
T16	0	1024	0	0
T17	0	1008	0	0
T18	0	325312	0	0
T45	0	92208	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	618215	0	0
T1	108855	6043	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	53	0	0
T7	185763	0	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	4889	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T21	0	4958	0	0
T28	0	2401	0	0
T29	0	1616	0	0
T46	0	4312	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	618215	0	0
T1	108855	6043	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	53	0	0
T7	185763	0	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	4889	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T21	0	4958	0	0
T28	0	2401	0	0
T29	0	1616	0	0
T46	0	4312	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	618215	0	0
T1	108855	6043	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	53	0	0
T7	185763	0	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	4889	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T21	0	4958	0	0
T28	0	2401	0	0
T29	0	1616	0	0
T46	0	4312	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	618215	0	0
T1	108855	6043	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	53	0	0
T7	185763	0	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	4889	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T21	0	4958	0	0
T28	0	2401	0	0
T29	0	1616	0	0
T46	0	4312	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	28510553	0	0
T1	108855	132960	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	4424	0	0
T7	185763	0	0	0
T8	754	432	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T13	0	97488	0	0
T14	0	105720	0	0
T15	0	5848	0	0
T16	0	1024	0	0
T17	0	1008	0	0
T18	0	325312	0	0
T45	0	92208	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	618215	0	0
T1	108855	6043	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	53	0	0
T7	185763	0	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	4889	0	0
T15	0	228	0	0
T16	0	111	0	0
T18	0	3360	0	0
T21	0	4958	0	0
T28	0	2401	0	0
T29	0	1616	0	0
T46	0	4312	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T20

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T20
1	0	Covered	T1,T7,T20

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T7,T20

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T20
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	133137849	103356093	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	133137849	463512	0	0
GntImpliesValid_A	133137849	463512	0	0
GrantKnown_A	133137849	103356093	0	0
IdxKnown_A	133137849	103356093	0	0
IndexIsCorrect_A	133137849	463512	0	0
LockArbDecision_A	133137849	0	0	0
NoReadyValidNoGrant_A	133137849	0	0	0
ReadyAndValidImplyGrant_A	133137849	463512	0	0
ReqAndReadyImplyGrant_A	133137849	463512	0	0
ReqImpliesValid_A	133137849	463512	0	0
ReqStaysHighUntilGranted0_M	133137849	0	0	0
RoundRobin_A	133137849	0	0	0
ValidKnown_A	133137849	103356093	0	0
gen_data_port_assertion.DataFlow_A	133137849	463512	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	103356093	0	0
T1	108855	943566	0	0
T2	3559	3216	0	0
T3	64268	64208	0	0
T4	117632	117632	0	0
T6	4424	0	0	0
T7	185763	184504	0	0
T8	754	0	0	0
T9	21696	21696	0	0
T10	21098	21098	0	0
T11	78279	78178	0	0
T12	0	8272	0	0
T19	0	10384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	463512	0	0
T1	108855	149	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	0	0	0
T7	185763	270	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	216	0	0
T20	0	1388	0	0
T21	0	139	0	0
T27	0	258	0	0
T28	0	10	0	0
T30	0	9359	0	0
T31	0	17	0	0
T59	0	4415	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	463512	0	0
T1	108855	149	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	0	0	0
T7	185763	270	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	216	0	0
T20	0	1388	0	0
T21	0	139	0	0
T27	0	258	0	0
T28	0	10	0	0
T30	0	9359	0	0
T31	0	17	0	0
T59	0	4415	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	103356093	0	0
T1	108855	943566	0	0
T2	3559	3216	0	0
T3	64268	64208	0	0
T4	117632	117632	0	0
T6	4424	0	0	0
T7	185763	184504	0	0
T8	754	0	0	0
T9	21696	21696	0	0
T10	21098	21098	0	0
T11	78279	78178	0	0
T12	0	8272	0	0
T19	0	10384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	103356093	0	0
T1	108855	943566	0	0
T2	3559	3216	0	0
T3	64268	64208	0	0
T4	117632	117632	0	0
T6	4424	0	0	0
T7	185763	184504	0	0
T8	754	0	0	0
T9	21696	21696	0	0
T10	21098	21098	0	0
T11	78279	78178	0	0
T12	0	8272	0	0
T19	0	10384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	463512	0	0
T1	108855	149	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	0	0	0
T7	185763	270	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	216	0	0
T20	0	1388	0	0
T21	0	139	0	0
T27	0	258	0	0
T28	0	10	0	0
T30	0	9359	0	0
T31	0	17	0	0
T59	0	4415	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	463512	0	0
T1	108855	149	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	0	0	0
T7	185763	270	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	216	0	0
T20	0	1388	0	0
T21	0	139	0	0
T27	0	258	0	0
T28	0	10	0	0
T30	0	9359	0	0
T31	0	17	0	0
T59	0	4415	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	463512	0	0
T1	108855	149	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	0	0	0
T7	185763	270	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	216	0	0
T20	0	1388	0	0
T21	0	139	0	0
T27	0	258	0	0
T28	0	10	0	0
T30	0	9359	0	0
T31	0	17	0	0
T59	0	4415	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	463512	0	0
T1	108855	149	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	0	0	0
T7	185763	270	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	216	0	0
T20	0	1388	0	0
T21	0	139	0	0
T27	0	258	0	0
T28	0	10	0	0
T30	0	9359	0	0
T31	0	17	0	0
T59	0	4415	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	103356093	0	0
T1	108855	943566	0	0
T2	3559	3216	0	0
T3	64268	64208	0	0
T4	117632	117632	0	0
T6	4424	0	0	0
T7	185763	184504	0	0
T8	754	0	0	0
T9	21696	21696	0	0
T10	21098	21098	0	0
T11	78279	78178	0	0
T12	0	8272	0	0
T19	0	10384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133137849	463512	0	0
T1	108855	149	0	0
T2	3559	0	0	0
T3	64268	0	0	0
T4	117632	0	0	0
T6	4424	0	0	0
T7	185763	270	0	0
T8	754	0	0	0
T9	21696	0	0	0
T10	21098	0	0	0
T11	78279	0	0	0
T14	0	216	0	0
T20	0	1388	0	0
T21	0	139	0	0
T27	0	258	0	0
T28	0	10	0	0
T30	0	9359	0	0
T31	0	17	0	0
T59	0	4415	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T20

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	372742226	372657849	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	372742226	2057336	0	0
GntImpliesValid_A	372742226	2057336	0	0
GrantKnown_A	372742226	372657849	0	0
IdxKnown_A	372742226	372657849	0	0
IndexIsCorrect_A	372742226	2057336	0	0
LockArbDecision_A	372742226	0	0	0
NoReadyValidNoGrant_A	372742226	0	0	0
ReadyAndValidImplyGrant_A	372742226	2057336	0	0
ReqAndReadyImplyGrant_A	372742226	2057336	0	0
ReqImpliesValid_A	372742226	2057336	0	0
ReqStaysHighUntilGranted0_M	372742226	0	0	0
RoundRobin_A	372742226	4	0	925
ValidKnown_A	372742226	372657849	0	0
gen_data_port_assertion.DataFlow_A	372742226	2057336	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	372657849	0	0
T1	659042	659033	0	0
T2	14115	14061	0	0
T3	388522	388424	0	0
T4	239187	239131	0	0
T5	1212	1145	0	0
T6	2076	1997	0	0
T7	229583	229483	0	0
T8	4675	4604	0	0
T9	14556	14499	0	0
T10	66665	66592	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	2057336	0	0
T1	659042	14592	0	0
T2	14115	832	0	0
T3	388522	832	0	0
T4	239187	832	0	0
T5	1212	0	0	0
T6	2076	51	0	0
T7	229583	3406	0	0
T8	4675	0	0	0
T9	14556	832	0	0
T10	66665	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	2057336	0	0
T1	659042	14592	0	0
T2	14115	832	0	0
T3	388522	832	0	0
T4	239187	832	0	0
T5	1212	0	0	0
T6	2076	51	0	0
T7	229583	3406	0	0
T8	4675	0	0	0
T9	14556	832	0	0
T10	66665	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	372657849	0	0
T1	659042	659033	0	0
T2	14115	14061	0	0
T3	388522	388424	0	0
T4	239187	239131	0	0
T5	1212	1145	0	0
T6	2076	1997	0	0
T7	229583	229483	0	0
T8	4675	4604	0	0
T9	14556	14499	0	0
T10	66665	66592	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	372657849	0	0
T1	659042	659033	0	0
T2	14115	14061	0	0
T3	388522	388424	0	0
T4	239187	239131	0	0
T5	1212	1145	0	0
T6	2076	1997	0	0
T7	229583	229483	0	0
T8	4675	4604	0	0
T9	14556	14499	0	0
T10	66665	66592	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	2057336	0	0
T1	659042	14592	0	0
T2	14115	832	0	0
T3	388522	832	0	0
T4	239187	832	0	0
T5	1212	0	0	0
T6	2076	51	0	0
T7	229583	3406	0	0
T8	4675	0	0	0
T9	14556	832	0	0
T10	66665	832	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	2057336	0	0
T1	659042	14592	0	0
T2	14115	832	0	0
T3	388522	832	0	0
T4	239187	832	0	0
T5	1212	0	0	0
T6	2076	51	0	0
T7	229583	3406	0	0
T8	4675	0	0	0
T9	14556	832	0	0
T10	66665	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	2057336	0	0
T1	659042	14592	0	0
T2	14115	832	0	0
T3	388522	832	0	0
T4	239187	832	0	0
T5	1212	0	0	0
T6	2076	51	0	0
T7	229583	3406	0	0
T8	4675	0	0	0
T9	14556	832	0	0
T10	66665	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	2057336	0	0
T1	659042	14592	0	0
T2	14115	832	0	0
T3	388522	832	0	0
T4	239187	832	0	0
T5	1212	0	0	0
T6	2076	51	0	0
T7	229583	3406	0	0
T8	4675	0	0	0
T9	14556	832	0	0
T10	66665	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	4	0	925
T26	3007	0	0	1
T47	927220	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	1574	0	0	1
T52	248477	0	0	1
T53	264207	0	0	1
T54	120757	0	0	1
T55	46718	0	0	1
T56	191864	0	0	1
T57	1083	0	0	1
T58	126528	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	372657849	0	0
T1	659042	659033	0	0
T2	14115	14061	0	0
T3	388522	388424	0	0
T4	239187	239131	0	0
T5	1212	1145	0	0
T6	2076	1997	0	0
T7	229583	229483	0	0
T8	4675	4604	0	0
T9	14556	14499	0	0
T10	66665	66592	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372742226	2057336	0	0
T1	659042	14592	0	0
T2	14115	832	0	0
T3	388522	832	0	0
T4	239187	832	0	0
T5	1212	0	0	0
T6	2076	51	0	0
T7	229583	3406	0	0
T8	4675	0	0	0
T9	14556	832	0	0
T10	66665	832	0	0
T11	0	832	0	0
T12	0	832	0	0