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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.12 98.36 94.20 98.61 89.36 97.24 95.82 99.25


Total test records in report: 1100
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T130 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2284048531 Jun 02 01:52:21 PM PDT 24 Jun 02 01:52:46 PM PDT 24 2192552240 ps
T1014 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.505818194 Jun 02 01:52:39 PM PDT 24 Jun 02 01:52:41 PM PDT 24 88733650 ps
T108 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2708802191 Jun 02 01:52:34 PM PDT 24 Jun 02 01:52:37 PM PDT 24 434652601 ps
T1015 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3968521980 Jun 02 01:52:48 PM PDT 24 Jun 02 01:52:52 PM PDT 24 58000501 ps
T1016 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2799399309 Jun 02 01:52:47 PM PDT 24 Jun 02 01:52:49 PM PDT 24 15157217 ps
T176 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2352993203 Jun 02 01:52:17 PM PDT 24 Jun 02 01:52:40 PM PDT 24 3380388461 ps
T1017 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.701535953 Jun 02 01:52:46 PM PDT 24 Jun 02 01:52:47 PM PDT 24 10614749 ps
T1018 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1834676263 Jun 02 01:52:50 PM PDT 24 Jun 02 01:52:52 PM PDT 24 28691541 ps
T1019 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4048126017 Jun 02 01:52:14 PM PDT 24 Jun 02 01:52:15 PM PDT 24 12380965 ps
T87 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.669113690 Jun 02 01:52:17 PM PDT 24 Jun 02 01:52:19 PM PDT 24 68327530 ps
T1020 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2351931467 Jun 02 01:52:20 PM PDT 24 Jun 02 01:52:23 PM PDT 24 91237881 ps
T131 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2022643462 Jun 02 01:52:38 PM PDT 24 Jun 02 01:52:40 PM PDT 24 40393319 ps
T1021 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3819125711 Jun 02 01:52:38 PM PDT 24 Jun 02 01:52:40 PM PDT 24 70302454 ps
T1022 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.417812280 Jun 02 01:52:48 PM PDT 24 Jun 02 01:52:50 PM PDT 24 18365189 ps
T1023 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2591767985 Jun 02 01:52:23 PM PDT 24 Jun 02 01:52:40 PM PDT 24 609062800 ps
T1024 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.828792480 Jun 02 01:52:28 PM PDT 24 Jun 02 01:52:33 PM PDT 24 314055905 ps
T1025 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2720781287 Jun 02 01:52:14 PM PDT 24 Jun 02 01:52:15 PM PDT 24 31572333 ps
T179 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3999838670 Jun 02 01:52:43 PM PDT 24 Jun 02 01:53:07 PM PDT 24 5531733509 ps
T1026 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3692101397 Jun 02 01:52:16 PM PDT 24 Jun 02 01:52:42 PM PDT 24 5743489321 ps
T1027 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2585308156 Jun 02 01:52:23 PM PDT 24 Jun 02 01:52:46 PM PDT 24 939630631 ps
T1028 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1438355532 Jun 02 01:52:28 PM PDT 24 Jun 02 01:52:29 PM PDT 24 12305232 ps
T1029 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3288976664 Jun 02 01:52:34 PM PDT 24 Jun 02 01:52:37 PM PDT 24 132162340 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.202764133 Jun 02 01:52:18 PM PDT 24 Jun 02 01:52:21 PM PDT 24 84880470 ps
T1031 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2798807268 Jun 02 01:52:24 PM PDT 24 Jun 02 01:52:25 PM PDT 24 139690010 ps
T1032 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1028065222 Jun 02 01:52:35 PM PDT 24 Jun 02 01:52:36 PM PDT 24 53393587 ps
T1033 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1488359890 Jun 02 01:52:34 PM PDT 24 Jun 02 01:52:39 PM PDT 24 795922956 ps
T1034 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.850802514 Jun 02 01:52:28 PM PDT 24 Jun 02 01:52:33 PM PDT 24 183662763 ps
T1035 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3464478101 Jun 02 01:52:35 PM PDT 24 Jun 02 01:52:36 PM PDT 24 10907896 ps
T1036 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.421804218 Jun 02 01:52:23 PM PDT 24 Jun 02 01:52:26 PM PDT 24 51096403 ps
T1037 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2427343482 Jun 02 01:52:34 PM PDT 24 Jun 02 01:52:38 PM PDT 24 546412262 ps
T1038 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1011498123 Jun 02 01:52:26 PM PDT 24 Jun 02 01:52:30 PM PDT 24 105472333 ps
T106 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2735215650 Jun 02 01:52:36 PM PDT 24 Jun 02 01:52:40 PM PDT 24 294929286 ps
T1039 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3772030232 Jun 02 01:52:46 PM PDT 24 Jun 02 01:52:49 PM PDT 24 40749725 ps
T1040 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3418761492 Jun 02 01:52:18 PM PDT 24 Jun 02 01:52:19 PM PDT 24 95291705 ps
T1041 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2922375827 Jun 02 01:52:28 PM PDT 24 Jun 02 01:52:33 PM PDT 24 795687367 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2888480269 Jun 02 01:52:19 PM PDT 24 Jun 02 01:52:22 PM PDT 24 235680555 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3626703316 Jun 02 01:52:19 PM PDT 24 Jun 02 01:52:20 PM PDT 24 44538511 ps
T1044 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3940685138 Jun 02 01:52:33 PM PDT 24 Jun 02 01:52:49 PM PDT 24 1440327701 ps
T1045 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1169793607 Jun 02 01:52:43 PM PDT 24 Jun 02 01:52:45 PM PDT 24 308659399 ps
T1046 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3305239369 Jun 02 01:52:38 PM PDT 24 Jun 02 01:52:42 PM PDT 24 43812691 ps
T1047 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3359757847 Jun 02 01:52:27 PM PDT 24 Jun 02 01:52:30 PM PDT 24 41537355 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2695771820 Jun 02 01:52:36 PM PDT 24 Jun 02 01:52:38 PM PDT 24 348990121 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1036029336 Jun 02 01:52:24 PM PDT 24 Jun 02 01:52:36 PM PDT 24 2999848277 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4138513012 Jun 02 01:52:32 PM PDT 24 Jun 02 01:52:36 PM PDT 24 60129174 ps
T1051 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.22281871 Jun 02 01:52:32 PM PDT 24 Jun 02 01:52:34 PM PDT 24 45449307 ps
T1052 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.476778821 Jun 02 01:52:28 PM PDT 24 Jun 02 01:52:31 PM PDT 24 316638071 ps
T1053 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2634487720 Jun 02 01:52:44 PM PDT 24 Jun 02 01:52:46 PM PDT 24 24351919 ps
T1054 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4011999269 Jun 02 01:52:48 PM PDT 24 Jun 02 01:52:51 PM PDT 24 313586892 ps
T1055 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2366363462 Jun 02 01:52:26 PM PDT 24 Jun 02 01:52:29 PM PDT 24 103022750 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4043792563 Jun 02 01:52:55 PM PDT 24 Jun 02 01:52:56 PM PDT 24 41214958 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2770117435 Jun 02 01:52:29 PM PDT 24 Jun 02 01:52:46 PM PDT 24 696823547 ps
T173 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4104940066 Jun 02 01:52:18 PM PDT 24 Jun 02 01:52:20 PM PDT 24 269128264 ps
T1058 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1709455457 Jun 02 01:52:38 PM PDT 24 Jun 02 01:52:47 PM PDT 24 1361272739 ps
T1059 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.653269129 Jun 02 01:52:31 PM PDT 24 Jun 02 01:52:34 PM PDT 24 66424762 ps
T1060 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1847765615 Jun 02 01:52:28 PM PDT 24 Jun 02 01:52:29 PM PDT 24 66548700 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4215714311 Jun 02 01:52:19 PM PDT 24 Jun 02 01:52:21 PM PDT 24 54933458 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3035839320 Jun 02 01:52:32 PM PDT 24 Jun 02 01:52:33 PM PDT 24 12079854 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.366478389 Jun 02 01:52:26 PM PDT 24 Jun 02 01:52:27 PM PDT 24 50138176 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1185365372 Jun 02 01:52:15 PM PDT 24 Jun 02 01:52:16 PM PDT 24 36016325 ps
T1065 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.294024167 Jun 02 01:52:39 PM PDT 24 Jun 02 01:52:40 PM PDT 24 38358582 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2683407468 Jun 02 01:52:14 PM PDT 24 Jun 02 01:52:38 PM PDT 24 706609447 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2735725546 Jun 02 01:52:11 PM PDT 24 Jun 02 01:52:14 PM PDT 24 441501856 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3892981937 Jun 02 01:52:17 PM PDT 24 Jun 02 01:52:21 PM PDT 24 127468364 ps
T1069 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2283475516 Jun 02 01:52:43 PM PDT 24 Jun 02 01:52:44 PM PDT 24 249508448 ps
T113 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.820011278 Jun 02 01:52:31 PM PDT 24 Jun 02 01:52:34 PM PDT 24 696741661 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1001204918 Jun 02 01:52:09 PM PDT 24 Jun 02 01:52:12 PM PDT 24 169178090 ps
T1070 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3064085433 Jun 02 01:52:35 PM PDT 24 Jun 02 01:52:39 PM PDT 24 66285461 ps
T1071 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1087357084 Jun 02 01:52:47 PM PDT 24 Jun 02 01:52:48 PM PDT 24 16679967 ps
T1072 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4255858725 Jun 02 01:52:50 PM PDT 24 Jun 02 01:52:51 PM PDT 24 14509099 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3346960483 Jun 02 01:52:12 PM PDT 24 Jun 02 01:52:13 PM PDT 24 120196999 ps
T1074 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2536395257 Jun 02 01:52:33 PM PDT 24 Jun 02 01:52:36 PM PDT 24 204082735 ps
T1075 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.865593036 Jun 02 01:52:35 PM PDT 24 Jun 02 01:52:39 PM PDT 24 2303885227 ps
T1076 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4286488284 Jun 02 01:52:36 PM PDT 24 Jun 02 01:52:39 PM PDT 24 464108088 ps
T1077 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.939575128 Jun 02 01:52:22 PM PDT 24 Jun 02 01:52:25 PM PDT 24 40946319 ps
T1078 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2401646343 Jun 02 01:52:18 PM PDT 24 Jun 02 01:52:34 PM PDT 24 843697090 ps
T1079 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2422825467 Jun 02 01:52:46 PM PDT 24 Jun 02 01:52:48 PM PDT 24 25343940 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2686600523 Jun 02 01:52:28 PM PDT 24 Jun 02 01:52:32 PM PDT 24 57082282 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4118548732 Jun 02 01:52:18 PM PDT 24 Jun 02 01:52:20 PM PDT 24 35467942 ps
T1082 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.56521403 Jun 02 01:52:25 PM PDT 24 Jun 02 01:52:39 PM PDT 24 202790269 ps
T1083 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.560933995 Jun 02 01:52:32 PM PDT 24 Jun 02 01:52:55 PM PDT 24 1065580830 ps
T1084 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2300250441 Jun 02 01:52:16 PM PDT 24 Jun 02 01:52:40 PM PDT 24 1111174907 ps
T174 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.419335997 Jun 02 01:52:24 PM PDT 24 Jun 02 01:52:28 PM PDT 24 143951551 ps
T1085 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1034529434 Jun 02 01:52:50 PM PDT 24 Jun 02 01:52:51 PM PDT 24 13136032 ps
T1086 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3413078006 Jun 02 01:52:46 PM PDT 24 Jun 02 01:52:50 PM PDT 24 209195316 ps
T180 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3284352061 Jun 02 01:52:20 PM PDT 24 Jun 02 01:52:29 PM PDT 24 1435456750 ps
T1087 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.406451018 Jun 02 01:52:46 PM PDT 24 Jun 02 01:52:48 PM PDT 24 15729020 ps
T1088 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1697432143 Jun 02 01:52:50 PM PDT 24 Jun 02 01:52:51 PM PDT 24 39060740 ps
T178 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4193133366 Jun 02 01:52:17 PM PDT 24 Jun 02 01:52:38 PM PDT 24 296898404 ps
T1089 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.183578013 Jun 02 01:52:52 PM PDT 24 Jun 02 01:52:53 PM PDT 24 84542401 ps
T1090 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1014051247 Jun 02 01:52:12 PM PDT 24 Jun 02 01:52:15 PM PDT 24 73183593 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2375190786 Jun 02 01:52:18 PM PDT 24 Jun 02 01:52:20 PM PDT 24 276920316 ps
T1092 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2637524550 Jun 02 01:52:43 PM PDT 24 Jun 02 01:52:44 PM PDT 24 63052563 ps
T1093 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3681790451 Jun 02 01:52:18 PM PDT 24 Jun 02 01:52:57 PM PDT 24 5431862395 ps
T1094 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2186994305 Jun 02 01:52:39 PM PDT 24 Jun 02 01:52:44 PM PDT 24 241481146 ps
T1095 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.649526853 Jun 02 01:52:43 PM PDT 24 Jun 02 01:52:44 PM PDT 24 13504902 ps
T1096 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2054089390 Jun 02 01:52:49 PM PDT 24 Jun 02 01:52:50 PM PDT 24 43139002 ps
T1097 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.369371116 Jun 02 01:52:44 PM PDT 24 Jun 02 01:52:45 PM PDT 24 43691294 ps
T1098 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1071675987 Jun 02 01:52:49 PM PDT 24 Jun 02 01:52:50 PM PDT 24 44625659 ps
T1099 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2362401454 Jun 02 01:52:34 PM PDT 24 Jun 02 01:52:57 PM PDT 24 2152210235 ps
T1100 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4240013693 Jun 02 01:52:40 PM PDT 24 Jun 02 01:52:53 PM PDT 24 2769953141 ps

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.252790873
Short name T1
Test name
Test status
Simulation time 66569876833 ps
CPU time 687.04 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 02:01:38 PM PDT 24
Peak memory 254484 kb
Host smart-24ca3141-e63f-46f5-9d1d-37710082fe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252790873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.252790873
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1840433646
Short name T28
Test name
Test status
Simulation time 4705686284 ps
CPU time 25.41 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:49:16 PM PDT 24
Peak memory 233484 kb
Host smart-384c2fe0-132b-4911-9ec5-0623c2b2c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840433646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1840433646
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1894775975
Short name T59
Test name
Test status
Simulation time 6700189672 ps
CPU time 92.68 seconds
Started Jun 02 01:49:21 PM PDT 24
Finished Jun 02 01:50:54 PM PDT 24
Peak memory 267120 kb
Host smart-3de9b80c-ad6d-46ff-a9e3-fccc36bc9766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894775975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1894775975
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2139607943
Short name T103
Test name
Test status
Simulation time 1289063162 ps
CPU time 14.89 seconds
Started Jun 02 01:52:31 PM PDT 24
Finished Jun 02 01:52:47 PM PDT 24
Peak memory 215828 kb
Host smart-1f206ed1-3199-4a85-8249-6cdacf2b7a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139607943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2139607943
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.897446155
Short name T33
Test name
Test status
Simulation time 7070427529 ps
CPU time 75.88 seconds
Started Jun 02 01:49:52 PM PDT 24
Finished Jun 02 01:51:08 PM PDT 24
Peak memory 250520 kb
Host smart-578eec2e-8f7a-4884-b911-0f37a910ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897446155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.897446155
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.707429467
Short name T84
Test name
Test status
Simulation time 56712702934 ps
CPU time 593.45 seconds
Started Jun 02 01:49:48 PM PDT 24
Finished Jun 02 01:59:42 PM PDT 24
Peak memory 265160 kb
Host smart-aeda82be-33a2-4e47-88d1-e849eb29e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707429467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.707429467
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.746620322
Short name T140
Test name
Test status
Simulation time 377008273714 ps
CPU time 1039.8 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 02:06:14 PM PDT 24
Peak memory 285412 kb
Host smart-b4b7df78-a182-4e51-857b-8ac8773b91e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746620322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.746620322
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1369897678
Short name T69
Test name
Test status
Simulation time 152174096 ps
CPU time 0.73 seconds
Started Jun 02 01:48:37 PM PDT 24
Finished Jun 02 01:48:38 PM PDT 24
Peak memory 215644 kb
Host smart-3e0bbf33-2694-4df9-a78e-b68633af7302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369897678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1369897678
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3003122828
Short name T35
Test name
Test status
Simulation time 209392250380 ps
CPU time 549.63 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 02:00:26 PM PDT 24
Peak memory 263840 kb
Host smart-ad429d6c-382a-4ef7-a3e4-19a742eaffdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003122828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3003122828
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.534338682
Short name T49
Test name
Test status
Simulation time 253047299118 ps
CPU time 663.38 seconds
Started Jun 02 01:50:06 PM PDT 24
Finished Jun 02 02:01:10 PM PDT 24
Peak memory 281544 kb
Host smart-1500121b-0bfd-4993-83db-ad5ee7d232d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534338682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.534338682
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3010261352
Short name T102
Test name
Test status
Simulation time 140182588 ps
CPU time 3.67 seconds
Started Jun 02 01:52:36 PM PDT 24
Finished Jun 02 01:52:40 PM PDT 24
Peak memory 215896 kb
Host smart-bdaeaf56-1098-4edf-95e5-7f14014ab189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010261352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3010261352
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3183925890
Short name T38
Test name
Test status
Simulation time 3798828190 ps
CPU time 57.57 seconds
Started Jun 02 01:50:09 PM PDT 24
Finished Jun 02 01:51:07 PM PDT 24
Peak memory 232372 kb
Host smart-328d9a90-2758-4663-8849-25430d0d64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183925890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3183925890
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3441451700
Short name T66
Test name
Test status
Simulation time 118619969 ps
CPU time 0.95 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:48 PM PDT 24
Peak memory 234660 kb
Host smart-0a0f60a4-ae21-466a-aecb-eb138b60bf2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441451700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3441451700
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4150874598
Short name T221
Test name
Test status
Simulation time 46550279121 ps
CPU time 267.94 seconds
Started Jun 02 01:48:38 PM PDT 24
Finished Jun 02 01:53:07 PM PDT 24
Peak memory 266224 kb
Host smart-8862dfe0-8050-4ad6-b72b-aa9847824a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150874598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4150874598
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2708542888
Short name T47
Test name
Test status
Simulation time 9658878565 ps
CPU time 139.35 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:51:39 PM PDT 24
Peak memory 257000 kb
Host smart-ba7ac3e9-e1d7-4aff-89e3-51b56e7868b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708542888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2708542888
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1951490996
Short name T85
Test name
Test status
Simulation time 73971858 ps
CPU time 1.44 seconds
Started Jun 02 01:52:21 PM PDT 24
Finished Jun 02 01:52:23 PM PDT 24
Peak memory 207208 kb
Host smart-6c6fe1fa-f15d-42ba-8c5a-32e4c3ea1acb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951490996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1951490996
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.135481726
Short name T188
Test name
Test status
Simulation time 43208046360 ps
CPU time 358.4 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:55:42 PM PDT 24
Peak memory 262960 kb
Host smart-f47316d7-d9f0-48c2-a280-d2349f565b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135481726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.135481726
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2760920338
Short name T194
Test name
Test status
Simulation time 140022797234 ps
CPU time 645.69 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 02:00:17 PM PDT 24
Peak memory 250432 kb
Host smart-88d96d0e-6df5-4fde-aff1-008aebc8be9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760920338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2760920338
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2426806410
Short name T68
Test name
Test status
Simulation time 7002696939 ps
CPU time 84.38 seconds
Started Jun 02 01:49:33 PM PDT 24
Finished Jun 02 01:50:58 PM PDT 24
Peak memory 250928 kb
Host smart-62ebc06e-3b2e-4e58-bc0d-2ef95072e33f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426806410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2426806410
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.543574369
Short name T534
Test name
Test status
Simulation time 26761237 ps
CPU time 1 seconds
Started Jun 02 01:48:43 PM PDT 24
Finished Jun 02 01:48:45 PM PDT 24
Peak memory 217356 kb
Host smart-343f5973-5a8e-4728-9266-6588f16569af
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543574369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.543574369
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2736841258
Short name T14
Test name
Test status
Simulation time 30597369931 ps
CPU time 341.84 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:56:24 PM PDT 24
Peak memory 252260 kb
Host smart-b6e875db-cf76-45d7-8736-b7ec11697c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736841258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2736841258
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1034430114
Short name T164
Test name
Test status
Simulation time 65809410185 ps
CPU time 484.59 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:56:56 PM PDT 24
Peak memory 255728 kb
Host smart-3d43d370-cfac-4128-a6c7-6cbe35c7e36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034430114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1034430114
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3934458630
Short name T105
Test name
Test status
Simulation time 161556644 ps
CPU time 4.25 seconds
Started Jun 02 01:52:33 PM PDT 24
Finished Jun 02 01:52:38 PM PDT 24
Peak memory 215688 kb
Host smart-c873faf3-b66d-40a0-a657-89adbbbf7a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934458630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3934458630
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2743610709
Short name T30
Test name
Test status
Simulation time 33920433528 ps
CPU time 176.03 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:52:16 PM PDT 24
Peak memory 260332 kb
Host smart-be7ec1ee-8570-4e45-92ec-ec2c074f5cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743610709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2743610709
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1862921651
Short name T367
Test name
Test status
Simulation time 32144565 ps
CPU time 0.69 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:49:28 PM PDT 24
Peak memory 204176 kb
Host smart-b2e56872-f0a4-492e-9c60-de76d111c230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862921651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1862921651
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.955080531
Short name T298
Test name
Test status
Simulation time 512032370972 ps
CPU time 371.72 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:55:57 PM PDT 24
Peak memory 252756 kb
Host smart-36ba47ef-50fe-41d0-a30e-f624453047d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955080531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.955080531
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3581357351
Short name T305
Test name
Test status
Simulation time 189819327964 ps
CPU time 297.65 seconds
Started Jun 02 01:50:14 PM PDT 24
Finished Jun 02 01:55:12 PM PDT 24
Peak memory 256248 kb
Host smart-19441097-affe-4cc3-aa90-aac014f696d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581357351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3581357351
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2380538637
Short name T149
Test name
Test status
Simulation time 1795020023 ps
CPU time 22.44 seconds
Started Jun 02 01:52:41 PM PDT 24
Finished Jun 02 01:53:04 PM PDT 24
Peak memory 215476 kb
Host smart-48bd5f5d-5f2e-4547-8e14-dd7c5b927668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380538637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2380538637
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2154368360
Short name T279
Test name
Test status
Simulation time 6129367826 ps
CPU time 149.65 seconds
Started Jun 02 01:49:13 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 272936 kb
Host smart-866d2ba6-0575-4c25-b02a-f9f4bc6404db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154368360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2154368360
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3845755563
Short name T197
Test name
Test status
Simulation time 153927608621 ps
CPU time 415.45 seconds
Started Jun 02 01:49:23 PM PDT 24
Finished Jun 02 01:56:18 PM PDT 24
Peak memory 250248 kb
Host smart-5e45ca96-d54a-448d-811d-492a651093ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845755563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3845755563
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3932291163
Short name T45
Test name
Test status
Simulation time 4280615630 ps
CPU time 7.4 seconds
Started Jun 02 01:50:25 PM PDT 24
Finished Jun 02 01:50:33 PM PDT 24
Peak memory 215788 kb
Host smart-9082e4a7-ee41-41af-ae83-0a14cb5a515b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932291163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3932291163
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.548648135
Short name T48
Test name
Test status
Simulation time 17802423201 ps
CPU time 228.69 seconds
Started Jun 02 01:50:16 PM PDT 24
Finished Jun 02 01:54:05 PM PDT 24
Peak memory 254808 kb
Host smart-628e6d10-6437-4fe6-beaf-a0a7a68bcf64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548648135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.548648135
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2421312900
Short name T276
Test name
Test status
Simulation time 59570728575 ps
CPU time 383.83 seconds
Started Jun 02 01:50:31 PM PDT 24
Finished Jun 02 01:56:55 PM PDT 24
Peak memory 273380 kb
Host smart-699aa6cb-9eaf-410a-9fec-71bc4d16655a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421312900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2421312900
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2854779482
Short name T10
Test name
Test status
Simulation time 687264922 ps
CPU time 4.69 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:50:00 PM PDT 24
Peak memory 233180 kb
Host smart-879a597e-ce96-4287-ba38-f7db7478a1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854779482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2854779482
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3040178369
Short name T92
Test name
Test status
Simulation time 638545210 ps
CPU time 6.25 seconds
Started Jun 02 01:49:33 PM PDT 24
Finished Jun 02 01:49:39 PM PDT 24
Peak memory 219772 kb
Host smart-3d88eeef-6ddc-4a88-94a6-19030db44284
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3040178369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3040178369
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.130575660
Short name T32
Test name
Test status
Simulation time 184632930974 ps
CPU time 251.06 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:53:31 PM PDT 24
Peak memory 248824 kb
Host smart-ed5f89f4-76df-4dfd-a284-833b8a14f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130575660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.130575660
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.494313170
Short name T182
Test name
Test status
Simulation time 221657763030 ps
CPU time 386.79 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:55:53 PM PDT 24
Peak memory 254180 kb
Host smart-41bc1886-f908-424e-be27-c817931bd532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494313170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.494313170
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1359367352
Short name T219
Test name
Test status
Simulation time 9344435250 ps
CPU time 176.9 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 269276 kb
Host smart-7cc3d231-666f-428b-810c-4d865048a238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359367352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1359367352
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4095901486
Short name T952
Test name
Test status
Simulation time 808596612 ps
CPU time 7.46 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:49:52 PM PDT 24
Peak memory 224036 kb
Host smart-c12b3d70-5fe2-4c74-b50e-4b9213d1094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095901486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4095901486
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1389602586
Short name T296
Test name
Test status
Simulation time 734973056036 ps
CPU time 306.92 seconds
Started Jun 02 01:49:54 PM PDT 24
Finished Jun 02 01:55:02 PM PDT 24
Peak memory 261688 kb
Host smart-a920aff6-5a6c-412f-922a-1afbf744d813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389602586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1389602586
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3962965579
Short name T157
Test name
Test status
Simulation time 81082761994 ps
CPU time 398.28 seconds
Started Jun 02 01:50:24 PM PDT 24
Finished Jun 02 01:57:03 PM PDT 24
Peak memory 268240 kb
Host smart-dbf1cd99-8eff-4fa0-88f5-3d207175e84f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962965579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3962965579
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3337391678
Short name T208
Test name
Test status
Simulation time 8357094224 ps
CPU time 132.2 seconds
Started Jun 02 01:51:16 PM PDT 24
Finished Jun 02 01:53:29 PM PDT 24
Peak memory 255924 kb
Host smart-be2c09fd-b826-4cb4-86d3-a9e975e0d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337391678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3337391678
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.419335997
Short name T174
Test name
Test status
Simulation time 143951551 ps
CPU time 4.05 seconds
Started Jun 02 01:52:24 PM PDT 24
Finished Jun 02 01:52:28 PM PDT 24
Peak memory 216564 kb
Host smart-11a5fe2c-8031-4c13-ad48-9fbdf338481c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419335997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.419335997
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.384275149
Short name T22
Test name
Test status
Simulation time 19583560518 ps
CPU time 215.53 seconds
Started Jun 02 01:50:27 PM PDT 24
Finished Jun 02 01:54:03 PM PDT 24
Peak memory 249092 kb
Host smart-4fd8fffa-0e35-4e13-a25e-6435ad195194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384275149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.384275149
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2226056731
Short name T307
Test name
Test status
Simulation time 75270290855 ps
CPU time 365.97 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:54:58 PM PDT 24
Peak memory 248852 kb
Host smart-ca9388f7-5c0a-416f-9d4b-010d6af0033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226056731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2226056731
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1133077253
Short name T168
Test name
Test status
Simulation time 11720924776 ps
CPU time 11.67 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:49:27 PM PDT 24
Peak memory 233188 kb
Host smart-f361f2f2-d63c-41b0-8c06-161b3d1ce6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133077253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1133077253
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4118575971
Short name T324
Test name
Test status
Simulation time 1831143610 ps
CPU time 5.02 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:49:32 PM PDT 24
Peak memory 218328 kb
Host smart-3109fb8a-ad9e-4569-a610-032092d91a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118575971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4118575971
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2642680414
Short name T146
Test name
Test status
Simulation time 587561024 ps
CPU time 5.69 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:49:51 PM PDT 24
Peak memory 232256 kb
Host smart-e9ccb840-0bd3-459a-8431-3ec7146e52cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642680414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2642680414
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2907541982
Short name T961
Test name
Test status
Simulation time 302545265 ps
CPU time 7.2 seconds
Started Jun 02 01:49:42 PM PDT 24
Finished Jun 02 01:49:50 PM PDT 24
Peak memory 238260 kb
Host smart-cea6ab27-0127-4e24-9a45-77233d42536f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907541982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2907541982
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1817084940
Short name T295
Test name
Test status
Simulation time 13537433157 ps
CPU time 74.57 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:50:04 PM PDT 24
Peak memory 250860 kb
Host smart-77f62a8f-7035-4dc5-a14c-ad745af2ab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817084940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1817084940
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2037206087
Short name T306
Test name
Test status
Simulation time 100575595016 ps
CPU time 259.96 seconds
Started Jun 02 01:51:19 PM PDT 24
Finished Jun 02 01:55:39 PM PDT 24
Peak memory 253804 kb
Host smart-85d5e0eb-28c7-4b12-811d-00a404d3d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037206087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2037206087
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3715480461
Short name T314
Test name
Test status
Simulation time 24717366077 ps
CPU time 68.55 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:49:57 PM PDT 24
Peak memory 240512 kb
Host smart-ed423800-db69-4d40-94d5-470e3578bfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715480461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3715480461
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.375603080
Short name T88
Test name
Test status
Simulation time 72807037354 ps
CPU time 366.29 seconds
Started Jun 02 01:49:39 PM PDT 24
Finished Jun 02 01:55:45 PM PDT 24
Peak memory 265236 kb
Host smart-24e8c98b-4fe0-474d-9ed3-baa70e1da485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375603080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.375603080
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3756245524
Short name T123
Test name
Test status
Simulation time 919529363 ps
CPU time 22.93 seconds
Started Jun 02 01:52:14 PM PDT 24
Finished Jun 02 01:52:37 PM PDT 24
Peak memory 215540 kb
Host smart-a8a4e3e1-588a-4aa5-a791-5f12bfd8869d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756245524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3756245524
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2683407468
Short name T1066
Test name
Test status
Simulation time 706609447 ps
CPU time 24.38 seconds
Started Jun 02 01:52:14 PM PDT 24
Finished Jun 02 01:52:38 PM PDT 24
Peak memory 215764 kb
Host smart-3494ff32-977f-49c6-add2-b2610ab14bc2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683407468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2683407468
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3346960483
Short name T1073
Test name
Test status
Simulation time 120196999 ps
CPU time 1.43 seconds
Started Jun 02 01:52:12 PM PDT 24
Finished Jun 02 01:52:13 PM PDT 24
Peak memory 207540 kb
Host smart-2aa168ad-2901-4af2-a287-55030e99aa18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346960483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3346960483
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2182004335
Short name T116
Test name
Test status
Simulation time 564373889 ps
CPU time 3.69 seconds
Started Jun 02 01:52:14 PM PDT 24
Finished Jun 02 01:52:18 PM PDT 24
Peak memory 217056 kb
Host smart-ae2fa275-4e41-4f80-82bb-e0cf715a7b62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182004335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2182004335
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1788076018
Short name T986
Test name
Test status
Simulation time 37032709 ps
CPU time 2.22 seconds
Started Jun 02 01:52:11 PM PDT 24
Finished Jun 02 01:52:14 PM PDT 24
Peak memory 207348 kb
Host smart-13877a0b-2783-4bab-b7ed-80181e74c03e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788076018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
788076018
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2751211794
Short name T988
Test name
Test status
Simulation time 18474086 ps
CPU time 0.71 seconds
Started Jun 02 01:52:14 PM PDT 24
Finished Jun 02 01:52:15 PM PDT 24
Peak memory 203744 kb
Host smart-4c143225-2272-4b31-b547-c7c0590f7a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751211794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
751211794
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3577376984
Short name T126
Test name
Test status
Simulation time 38886994 ps
CPU time 1.29 seconds
Started Jun 02 01:52:15 PM PDT 24
Finished Jun 02 01:52:16 PM PDT 24
Peak memory 215660 kb
Host smart-b21ee6fc-bfc7-4cf5-a74d-b92d8a6c81cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577376984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3577376984
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3420598988
Short name T992
Test name
Test status
Simulation time 11270466 ps
CPU time 0.69 seconds
Started Jun 02 01:52:15 PM PDT 24
Finished Jun 02 01:52:16 PM PDT 24
Peak memory 203960 kb
Host smart-af7718f2-1fb6-42d3-a6e7-ba134873e48f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420598988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3420598988
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2237110569
Short name T1001
Test name
Test status
Simulation time 62251387 ps
CPU time 3.87 seconds
Started Jun 02 01:52:13 PM PDT 24
Finished Jun 02 01:52:18 PM PDT 24
Peak memory 215448 kb
Host smart-e5516781-2db1-4faa-ada7-a1a57a0f2ccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237110569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2237110569
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1001204918
Short name T115
Test name
Test status
Simulation time 169178090 ps
CPU time 3.13 seconds
Started Jun 02 01:52:09 PM PDT 24
Finished Jun 02 01:52:12 PM PDT 24
Peak memory 216680 kb
Host smart-8c1c61c8-b5bf-455d-811d-77eab00b0802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001204918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
001204918
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.635426019
Short name T101
Test name
Test status
Simulation time 110513573 ps
CPU time 6.51 seconds
Started Jun 02 01:52:07 PM PDT 24
Finished Jun 02 01:52:14 PM PDT 24
Peak memory 215704 kb
Host smart-ac58bb59-3e27-4c7e-884a-7f9b41d3848b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635426019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.635426019
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2401646343
Short name T1078
Test name
Test status
Simulation time 843697090 ps
CPU time 15.95 seconds
Started Jun 02 01:52:18 PM PDT 24
Finished Jun 02 01:52:34 PM PDT 24
Peak memory 207360 kb
Host smart-e8ca8e2b-4fa6-4553-9175-ea569e3016bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401646343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2401646343
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2699691595
Short name T127
Test name
Test status
Simulation time 11222393545 ps
CPU time 39.8 seconds
Started Jun 02 01:52:15 PM PDT 24
Finished Jun 02 01:52:55 PM PDT 24
Peak memory 215492 kb
Host smart-d8e91edf-8a28-42a0-974b-5937e56393c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699691595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2699691595
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1185365372
Short name T1064
Test name
Test status
Simulation time 36016325 ps
CPU time 1.19 seconds
Started Jun 02 01:52:15 PM PDT 24
Finished Jun 02 01:52:16 PM PDT 24
Peak memory 207296 kb
Host smart-a2c95079-c91c-4115-b156-cf008eeeaac8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185365372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1185365372
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2375190786
Short name T1091
Test name
Test status
Simulation time 276920316 ps
CPU time 1.97 seconds
Started Jun 02 01:52:18 PM PDT 24
Finished Jun 02 01:52:20 PM PDT 24
Peak memory 216664 kb
Host smart-b733cdd6-14a1-4912-b45c-c29fd369210a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375190786 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2375190786
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2735725546
Short name T1067
Test name
Test status
Simulation time 441501856 ps
CPU time 2.64 seconds
Started Jun 02 01:52:11 PM PDT 24
Finished Jun 02 01:52:14 PM PDT 24
Peak memory 215484 kb
Host smart-4754b481-2eff-4977-9d3d-e95e47cbad95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735725546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
735725546
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.40787111
Short name T977
Test name
Test status
Simulation time 93825547 ps
CPU time 0.71 seconds
Started Jun 02 01:52:14 PM PDT 24
Finished Jun 02 01:52:15 PM PDT 24
Peak memory 203712 kb
Host smart-3f3fc581-34fc-4b1c-b852-3edd28a432cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40787111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.40787111
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2720781287
Short name T1025
Test name
Test status
Simulation time 31572333 ps
CPU time 1.26 seconds
Started Jun 02 01:52:14 PM PDT 24
Finished Jun 02 01:52:15 PM PDT 24
Peak memory 215528 kb
Host smart-93110c11-d284-4723-891b-394c5e2db947
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720781287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2720781287
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4048126017
Short name T1019
Test name
Test status
Simulation time 12380965 ps
CPU time 0.65 seconds
Started Jun 02 01:52:14 PM PDT 24
Finished Jun 02 01:52:15 PM PDT 24
Peak memory 203676 kb
Host smart-5d3ae867-c8f4-4caf-916c-775572f65e6c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048126017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4048126017
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1994233150
Short name T1011
Test name
Test status
Simulation time 29572963 ps
CPU time 1.75 seconds
Started Jun 02 01:52:16 PM PDT 24
Finished Jun 02 01:52:18 PM PDT 24
Peak memory 207176 kb
Host smart-8555d718-be68-42aa-a92e-68752eb93318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994233150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1994233150
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1014051247
Short name T1090
Test name
Test status
Simulation time 73183593 ps
CPU time 2.74 seconds
Started Jun 02 01:52:12 PM PDT 24
Finished Jun 02 01:52:15 PM PDT 24
Peak memory 215612 kb
Host smart-584e2797-4fef-4cb6-8202-440f1dad8d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014051247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
014051247
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2577297789
Short name T177
Test name
Test status
Simulation time 98349092 ps
CPU time 6.7 seconds
Started Jun 02 01:52:15 PM PDT 24
Finished Jun 02 01:52:22 PM PDT 24
Peak memory 215468 kb
Host smart-c632b822-a856-463a-a8a4-cf2f7d0b1cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577297789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2577297789
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4138513012
Short name T1050
Test name
Test status
Simulation time 60129174 ps
CPU time 4.38 seconds
Started Jun 02 01:52:32 PM PDT 24
Finished Jun 02 01:52:36 PM PDT 24
Peak memory 217836 kb
Host smart-7e43054c-62ad-41ad-afc5-39e6f69b8e68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138513012 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4138513012
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3359757847
Short name T1047
Test name
Test status
Simulation time 41537355 ps
CPU time 1.93 seconds
Started Jun 02 01:52:27 PM PDT 24
Finished Jun 02 01:52:30 PM PDT 24
Peak memory 207324 kb
Host smart-2d713470-224a-458b-ad68-5a6047341b98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359757847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3359757847
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.366478389
Short name T1063
Test name
Test status
Simulation time 50138176 ps
CPU time 0.68 seconds
Started Jun 02 01:52:26 PM PDT 24
Finished Jun 02 01:52:27 PM PDT 24
Peak memory 204048 kb
Host smart-597aa582-2bdb-4ca9-ac69-57da0c17d540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366478389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.366478389
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1011498123
Short name T1038
Test name
Test status
Simulation time 105472333 ps
CPU time 2.98 seconds
Started Jun 02 01:52:26 PM PDT 24
Finished Jun 02 01:52:30 PM PDT 24
Peak memory 215492 kb
Host smart-03f77864-b803-46ea-9a16-eed826bb1984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011498123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1011498123
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4185206912
Short name T97
Test name
Test status
Simulation time 366682787 ps
CPU time 1.65 seconds
Started Jun 02 01:52:32 PM PDT 24
Finished Jun 02 01:52:33 PM PDT 24
Peak memory 215588 kb
Host smart-116bfc5d-8bbb-40d5-b43a-b721b905265b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185206912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4185206912
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.926838685
Short name T175
Test name
Test status
Simulation time 3062807464 ps
CPU time 9.02 seconds
Started Jun 02 01:52:29 PM PDT 24
Finished Jun 02 01:52:39 PM PDT 24
Peak memory 215592 kb
Host smart-2d7c6c5b-5e75-4323-8119-a53a3adcab49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926838685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.926838685
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3408426484
Short name T150
Test name
Test status
Simulation time 226787736 ps
CPU time 1.78 seconds
Started Jun 02 01:52:35 PM PDT 24
Finished Jun 02 01:52:37 PM PDT 24
Peak memory 215560 kb
Host smart-3e036a77-238f-48d9-8b8e-2f722bd13134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408426484 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3408426484
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3237380026
Short name T145
Test name
Test status
Simulation time 22905178 ps
CPU time 1.34 seconds
Started Jun 02 01:52:28 PM PDT 24
Finished Jun 02 01:52:30 PM PDT 24
Peak memory 215540 kb
Host smart-820d636b-3ad5-47c7-be75-fc35f17e27af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237380026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3237380026
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1438355532
Short name T1028
Test name
Test status
Simulation time 12305232 ps
CPU time 0.7 seconds
Started Jun 02 01:52:28 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 203720 kb
Host smart-ea3e7796-68e3-419d-b771-8a6067eec9a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438355532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1438355532
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3181281554
Short name T979
Test name
Test status
Simulation time 151107590 ps
CPU time 4.28 seconds
Started Jun 02 01:52:33 PM PDT 24
Finished Jun 02 01:52:38 PM PDT 24
Peak memory 215512 kb
Host smart-710d7fab-c7fa-4983-91e1-ffb8fb50f782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181281554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3181281554
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2144751358
Short name T104
Test name
Test status
Simulation time 125303876 ps
CPU time 3.16 seconds
Started Jun 02 01:52:25 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 215684 kb
Host smart-9c261278-ff8f-447a-84fb-bdd27ba0b593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144751358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2144751358
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3940685138
Short name T1044
Test name
Test status
Simulation time 1440327701 ps
CPU time 15.75 seconds
Started Jun 02 01:52:33 PM PDT 24
Finished Jun 02 01:52:49 PM PDT 24
Peak memory 215520 kb
Host smart-ff394699-55c6-49b8-9fba-2a9cd6f8a5f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940685138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3940685138
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.140575802
Short name T1013
Test name
Test status
Simulation time 57670886 ps
CPU time 4.1 seconds
Started Jun 02 01:52:34 PM PDT 24
Finished Jun 02 01:52:39 PM PDT 24
Peak memory 218616 kb
Host smart-494aba0b-2b3e-4ab2-b14d-e25e97bae962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140575802 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.140575802
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2695771820
Short name T1048
Test name
Test status
Simulation time 348990121 ps
CPU time 2.22 seconds
Started Jun 02 01:52:36 PM PDT 24
Finished Jun 02 01:52:38 PM PDT 24
Peak memory 207264 kb
Host smart-b6fc14ae-6738-4da7-9999-cbf2d926ca62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695771820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2695771820
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3808355363
Short name T976
Test name
Test status
Simulation time 92347075 ps
CPU time 0.75 seconds
Started Jun 02 01:52:32 PM PDT 24
Finished Jun 02 01:52:33 PM PDT 24
Peak memory 203752 kb
Host smart-cf30c4a9-0b47-4310-b0b2-5e9d3b1b5d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808355363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3808355363
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1556497562
Short name T995
Test name
Test status
Simulation time 439243523 ps
CPU time 3.09 seconds
Started Jun 02 01:52:34 PM PDT 24
Finished Jun 02 01:52:37 PM PDT 24
Peak memory 215496 kb
Host smart-1e515cc7-7ecf-4aba-b0bd-dc059927e1a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556497562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1556497562
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.820011278
Short name T113
Test name
Test status
Simulation time 696741661 ps
CPU time 2.06 seconds
Started Jun 02 01:52:31 PM PDT 24
Finished Jun 02 01:52:34 PM PDT 24
Peak memory 215652 kb
Host smart-3d53527a-086b-4223-8d27-4cfee700420e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820011278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.820011278
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.377688333
Short name T118
Test name
Test status
Simulation time 327941909 ps
CPU time 19.53 seconds
Started Jun 02 01:52:32 PM PDT 24
Finished Jun 02 01:52:52 PM PDT 24
Peak memory 215516 kb
Host smart-3ea413b0-97ba-40ad-a325-52a9d637f588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377688333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.377688333
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.865593036
Short name T1075
Test name
Test status
Simulation time 2303885227 ps
CPU time 3.64 seconds
Started Jun 02 01:52:35 PM PDT 24
Finished Jun 02 01:52:39 PM PDT 24
Peak memory 217964 kb
Host smart-088ce702-b3d6-495f-87fb-0897811a5272
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865593036 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.865593036
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1883446561
Short name T129
Test name
Test status
Simulation time 87885032 ps
CPU time 2.3 seconds
Started Jun 02 01:52:31 PM PDT 24
Finished Jun 02 01:52:34 PM PDT 24
Peak memory 207236 kb
Host smart-cf745e24-e312-43b0-b4d2-3befdd20d4d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883446561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1883446561
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3035839320
Short name T1062
Test name
Test status
Simulation time 12079854 ps
CPU time 0.69 seconds
Started Jun 02 01:52:32 PM PDT 24
Finished Jun 02 01:52:33 PM PDT 24
Peak memory 204032 kb
Host smart-4fbb9592-fb30-46e8-859c-a2ccbd813498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035839320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3035839320
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1488359890
Short name T1033
Test name
Test status
Simulation time 795922956 ps
CPU time 3.93 seconds
Started Jun 02 01:52:34 PM PDT 24
Finished Jun 02 01:52:39 PM PDT 24
Peak memory 215424 kb
Host smart-4d92bf1c-c977-45a8-a9f4-8e86ec9a0684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488359890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1488359890
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2735215650
Short name T106
Test name
Test status
Simulation time 294929286 ps
CPU time 3.22 seconds
Started Jun 02 01:52:36 PM PDT 24
Finished Jun 02 01:52:40 PM PDT 24
Peak memory 215640 kb
Host smart-852063a1-ddac-49c9-8f43-f8e01f100f23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735215650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2735215650
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2362401454
Short name T1099
Test name
Test status
Simulation time 2152210235 ps
CPU time 22.55 seconds
Started Jun 02 01:52:34 PM PDT 24
Finished Jun 02 01:52:57 PM PDT 24
Peak memory 215884 kb
Host smart-52d0f4c3-3c2c-4efc-99e5-5fd664dacae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362401454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2362401454
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.951960535
Short name T117
Test name
Test status
Simulation time 86347811 ps
CPU time 3.13 seconds
Started Jun 02 01:52:33 PM PDT 24
Finished Jun 02 01:52:36 PM PDT 24
Peak memory 216924 kb
Host smart-d2cef74c-2b35-4602-ab35-bf5677a4a247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951960535 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.951960535
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4286488284
Short name T1076
Test name
Test status
Simulation time 464108088 ps
CPU time 2.61 seconds
Started Jun 02 01:52:36 PM PDT 24
Finished Jun 02 01:52:39 PM PDT 24
Peak memory 215468 kb
Host smart-d7738180-591d-4f8c-8d2f-7585ea2dc263
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286488284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4286488284
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3464478101
Short name T1035
Test name
Test status
Simulation time 10907896 ps
CPU time 0.66 seconds
Started Jun 02 01:52:35 PM PDT 24
Finished Jun 02 01:52:36 PM PDT 24
Peak memory 203672 kb
Host smart-1384a16d-c126-47cd-bb88-3612f1a8b540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464478101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3464478101
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3064085433
Short name T1070
Test name
Test status
Simulation time 66285461 ps
CPU time 3.62 seconds
Started Jun 02 01:52:35 PM PDT 24
Finished Jun 02 01:52:39 PM PDT 24
Peak memory 215476 kb
Host smart-e204770d-3d5f-4013-a29e-6054667b2d49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064085433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3064085433
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3924346091
Short name T98
Test name
Test status
Simulation time 402877223 ps
CPU time 12.68 seconds
Started Jun 02 01:52:34 PM PDT 24
Finished Jun 02 01:52:47 PM PDT 24
Peak memory 215572 kb
Host smart-9c19e082-36c9-4f67-be0d-b4156363f904
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924346091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3924346091
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.389415742
Short name T111
Test name
Test status
Simulation time 2161393358 ps
CPU time 3.27 seconds
Started Jun 02 01:52:39 PM PDT 24
Finished Jun 02 01:52:43 PM PDT 24
Peak memory 217020 kb
Host smart-a86647ea-833b-4d77-b9b8-4d1b6e1e5949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389415742 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.389415742
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3288976664
Short name T1029
Test name
Test status
Simulation time 132162340 ps
CPU time 2.67 seconds
Started Jun 02 01:52:34 PM PDT 24
Finished Jun 02 01:52:37 PM PDT 24
Peak memory 215484 kb
Host smart-095828f2-6524-4f96-b3af-d15abe3ce6bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288976664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3288976664
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1028065222
Short name T1032
Test name
Test status
Simulation time 53393587 ps
CPU time 0.77 seconds
Started Jun 02 01:52:35 PM PDT 24
Finished Jun 02 01:52:36 PM PDT 24
Peak memory 203772 kb
Host smart-09d95104-f564-4c39-86d9-df8a6f06c60c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028065222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1028065222
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2433718803
Short name T1004
Test name
Test status
Simulation time 121337104 ps
CPU time 3.87 seconds
Started Jun 02 01:52:38 PM PDT 24
Finished Jun 02 01:52:42 PM PDT 24
Peak memory 215516 kb
Host smart-238145ab-33de-45fb-b8eb-b9b5df596d3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433718803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2433718803
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.945676751
Short name T112
Test name
Test status
Simulation time 64563519 ps
CPU time 3.84 seconds
Started Jun 02 01:52:36 PM PDT 24
Finished Jun 02 01:52:41 PM PDT 24
Peak memory 215616 kb
Host smart-5ead241b-8989-4116-acbf-b30b59b82fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945676751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.945676751
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.560933995
Short name T1083
Test name
Test status
Simulation time 1065580830 ps
CPU time 22.26 seconds
Started Jun 02 01:52:32 PM PDT 24
Finished Jun 02 01:52:55 PM PDT 24
Peak memory 215508 kb
Host smart-4f7a1af6-dea3-4651-acfa-2a68147088f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560933995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.560933995
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3819125711
Short name T1021
Test name
Test status
Simulation time 70302454 ps
CPU time 1.58 seconds
Started Jun 02 01:52:38 PM PDT 24
Finished Jun 02 01:52:40 PM PDT 24
Peak memory 215556 kb
Host smart-85ed0dc2-0f1d-4ecb-9b6e-b63fba088b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819125711 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3819125711
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.51922592
Short name T1000
Test name
Test status
Simulation time 151265100 ps
CPU time 2.57 seconds
Started Jun 02 01:52:38 PM PDT 24
Finished Jun 02 01:52:41 PM PDT 24
Peak memory 207312 kb
Host smart-2b53cdf3-034a-4f82-8bc4-42b18278fdf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51922592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.51922592
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.765793106
Short name T984
Test name
Test status
Simulation time 68951438 ps
CPU time 0.78 seconds
Started Jun 02 01:52:40 PM PDT 24
Finished Jun 02 01:52:41 PM PDT 24
Peak memory 203664 kb
Host smart-06ae68f3-a09e-45e3-9158-090cd2c6ff73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765793106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.765793106
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.505818194
Short name T1014
Test name
Test status
Simulation time 88733650 ps
CPU time 1.72 seconds
Started Jun 02 01:52:39 PM PDT 24
Finished Jun 02 01:52:41 PM PDT 24
Peak memory 207244 kb
Host smart-20e558a0-ec8a-4e2c-8192-e721c292b28e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505818194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.505818194
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2186994305
Short name T1094
Test name
Test status
Simulation time 241481146 ps
CPU time 3.86 seconds
Started Jun 02 01:52:39 PM PDT 24
Finished Jun 02 01:52:44 PM PDT 24
Peak memory 216900 kb
Host smart-3b512d0e-9341-4e4a-a8af-9f3c60c9e57b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186994305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2186994305
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3305239369
Short name T1046
Test name
Test status
Simulation time 43812691 ps
CPU time 2.96 seconds
Started Jun 02 01:52:38 PM PDT 24
Finished Jun 02 01:52:42 PM PDT 24
Peak memory 217156 kb
Host smart-8fcb2c7e-cdea-4d6e-927f-7fcc40251123
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305239369 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3305239369
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2022643462
Short name T131
Test name
Test status
Simulation time 40393319 ps
CPU time 1.29 seconds
Started Jun 02 01:52:38 PM PDT 24
Finished Jun 02 01:52:40 PM PDT 24
Peak memory 207220 kb
Host smart-6028c1a7-ec99-44ba-8b6f-70deee597849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022643462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2022643462
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2869271852
Short name T989
Test name
Test status
Simulation time 24593463 ps
CPU time 0.74 seconds
Started Jun 02 01:52:39 PM PDT 24
Finished Jun 02 01:52:41 PM PDT 24
Peak memory 203724 kb
Host smart-e0562dc1-5e25-460b-87b6-df890a714f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869271852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2869271852
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1444209078
Short name T144
Test name
Test status
Simulation time 60456944 ps
CPU time 1.83 seconds
Started Jun 02 01:52:39 PM PDT 24
Finished Jun 02 01:52:41 PM PDT 24
Peak memory 215560 kb
Host smart-60416125-9c6b-4e77-97bc-1e3a563c7ee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444209078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1444209078
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1709455457
Short name T1058
Test name
Test status
Simulation time 1361272739 ps
CPU time 7.75 seconds
Started Jun 02 01:52:38 PM PDT 24
Finished Jun 02 01:52:47 PM PDT 24
Peak memory 215456 kb
Host smart-bc90c16d-b8b6-4003-811f-3bfff9164209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709455457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1709455457
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2634487720
Short name T1053
Test name
Test status
Simulation time 24351919 ps
CPU time 1.71 seconds
Started Jun 02 01:52:44 PM PDT 24
Finished Jun 02 01:52:46 PM PDT 24
Peak memory 215632 kb
Host smart-b0294213-2fe8-4857-92ad-3e9824987434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634487720 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2634487720
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1169793607
Short name T1045
Test name
Test status
Simulation time 308659399 ps
CPU time 2.02 seconds
Started Jun 02 01:52:43 PM PDT 24
Finished Jun 02 01:52:45 PM PDT 24
Peak memory 215504 kb
Host smart-6fc352ef-d852-45c6-923f-d2f05cf53b20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169793607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1169793607
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.294024167
Short name T1065
Test name
Test status
Simulation time 38358582 ps
CPU time 0.72 seconds
Started Jun 02 01:52:39 PM PDT 24
Finished Jun 02 01:52:40 PM PDT 24
Peak memory 204092 kb
Host smart-9e0e3ada-6c9a-4640-a1d4-e264fd877517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294024167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.294024167
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3772030232
Short name T1039
Test name
Test status
Simulation time 40749725 ps
CPU time 2.53 seconds
Started Jun 02 01:52:46 PM PDT 24
Finished Jun 02 01:52:49 PM PDT 24
Peak memory 215292 kb
Host smart-c86cfdce-117a-40f4-88d6-096d1459fec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772030232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3772030232
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3828221360
Short name T99
Test name
Test status
Simulation time 379513600 ps
CPU time 3.58 seconds
Started Jun 02 01:52:39 PM PDT 24
Finished Jun 02 01:52:43 PM PDT 24
Peak memory 215644 kb
Host smart-2a84f05f-f494-4671-8eb8-927001ac4b35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828221360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3828221360
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4240013693
Short name T1100
Test name
Test status
Simulation time 2769953141 ps
CPU time 13.06 seconds
Started Jun 02 01:52:40 PM PDT 24
Finished Jun 02 01:52:53 PM PDT 24
Peak memory 215488 kb
Host smart-31d704e5-ecdc-4d38-8942-f7c171f6b520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240013693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4240013693
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2250619625
Short name T114
Test name
Test status
Simulation time 54107872 ps
CPU time 3.34 seconds
Started Jun 02 01:52:49 PM PDT 24
Finished Jun 02 01:52:53 PM PDT 24
Peak memory 217432 kb
Host smart-ed5df935-2049-4f09-9709-06087c97897c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250619625 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2250619625
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4011999269
Short name T1054
Test name
Test status
Simulation time 313586892 ps
CPU time 2.67 seconds
Started Jun 02 01:52:48 PM PDT 24
Finished Jun 02 01:52:51 PM PDT 24
Peak memory 215508 kb
Host smart-60f47c6c-a622-4e70-bd34-7ce24a3f5e3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011999269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4011999269
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1834676263
Short name T1018
Test name
Test status
Simulation time 28691541 ps
CPU time 0.79 seconds
Started Jun 02 01:52:50 PM PDT 24
Finished Jun 02 01:52:52 PM PDT 24
Peak memory 203888 kb
Host smart-d4d9ebd9-256d-4e19-8c10-ecafaca2e8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834676263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1834676263
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3968521980
Short name T1015
Test name
Test status
Simulation time 58000501 ps
CPU time 3.9 seconds
Started Jun 02 01:52:48 PM PDT 24
Finished Jun 02 01:52:52 PM PDT 24
Peak memory 215464 kb
Host smart-c8b99065-0141-4e6d-9282-1356d83a39eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968521980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3968521980
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3413078006
Short name T1086
Test name
Test status
Simulation time 209195316 ps
CPU time 3.77 seconds
Started Jun 02 01:52:46 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 215644 kb
Host smart-aaeb41d7-89ce-49a5-8505-d9b0c664bf37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413078006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3413078006
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3999838670
Short name T179
Test name
Test status
Simulation time 5531733509 ps
CPU time 23.97 seconds
Started Jun 02 01:52:43 PM PDT 24
Finished Jun 02 01:53:07 PM PDT 24
Peak memory 215584 kb
Host smart-ca7fa97b-9ad9-45cd-b824-b307955bcab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999838670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3999838670
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2284048531
Short name T130
Test name
Test status
Simulation time 2192552240 ps
CPU time 23.72 seconds
Started Jun 02 01:52:21 PM PDT 24
Finished Jun 02 01:52:46 PM PDT 24
Peak memory 215580 kb
Host smart-4e6a1e3f-1429-4e83-8a66-044377a74a11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284048531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2284048531
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3681790451
Short name T1093
Test name
Test status
Simulation time 5431862395 ps
CPU time 39.13 seconds
Started Jun 02 01:52:18 PM PDT 24
Finished Jun 02 01:52:57 PM PDT 24
Peak memory 215460 kb
Host smart-30aa21ba-ad06-449b-88be-3e1ded6c2283
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681790451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3681790451
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.669113690
Short name T87
Test name
Test status
Simulation time 68327530 ps
CPU time 0.96 seconds
Started Jun 02 01:52:17 PM PDT 24
Finished Jun 02 01:52:19 PM PDT 24
Peak memory 207024 kb
Host smart-3e189b6d-d6f5-4a21-8836-4b54842da0a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669113690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.669113690
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2430933568
Short name T100
Test name
Test status
Simulation time 27271156 ps
CPU time 1.81 seconds
Started Jun 02 01:52:21 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 215540 kb
Host smart-e9421e2a-647b-44e7-a748-447c79616106
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430933568 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2430933568
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2888480269
Short name T1042
Test name
Test status
Simulation time 235680555 ps
CPU time 2.03 seconds
Started Jun 02 01:52:19 PM PDT 24
Finished Jun 02 01:52:22 PM PDT 24
Peak memory 215456 kb
Host smart-2307e426-d2a0-4bd7-950c-df42439b159d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888480269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
888480269
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1334783945
Short name T1003
Test name
Test status
Simulation time 24878423 ps
CPU time 0.75 seconds
Started Jun 02 01:52:21 PM PDT 24
Finished Jun 02 01:52:23 PM PDT 24
Peak memory 204000 kb
Host smart-c07d58af-2b42-404d-8e1e-45526dc23e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334783945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
334783945
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3879072414
Short name T125
Test name
Test status
Simulation time 19063251 ps
CPU time 1.2 seconds
Started Jun 02 01:52:17 PM PDT 24
Finished Jun 02 01:52:18 PM PDT 24
Peak memory 215580 kb
Host smart-3e1287cd-6030-451e-b91f-eb59d8d32fdd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879072414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3879072414
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4043792563
Short name T1056
Test name
Test status
Simulation time 41214958 ps
CPU time 0.65 seconds
Started Jun 02 01:52:55 PM PDT 24
Finished Jun 02 01:52:56 PM PDT 24
Peak memory 203972 kb
Host smart-eea97eba-3ea3-4c4c-9db3-18e7e069906c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043792563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4043792563
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4130741667
Short name T151
Test name
Test status
Simulation time 844886269 ps
CPU time 4.34 seconds
Started Jun 02 01:52:19 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 215492 kb
Host smart-1cc4f488-38df-41c0-9681-f5de0a89fea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130741667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4130741667
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4104940066
Short name T173
Test name
Test status
Simulation time 269128264 ps
CPU time 1.79 seconds
Started Jun 02 01:52:18 PM PDT 24
Finished Jun 02 01:52:20 PM PDT 24
Peak memory 215664 kb
Host smart-ace8a0c0-03bc-4c3a-af08-88c8ea690388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104940066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
104940066
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1669282754
Short name T96
Test name
Test status
Simulation time 575768169 ps
CPU time 15.17 seconds
Started Jun 02 01:52:20 PM PDT 24
Finished Jun 02 01:52:35 PM PDT 24
Peak memory 223572 kb
Host smart-9add1c0f-b66a-489a-8134-98fc795b79aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669282754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1669282754
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3382035667
Short name T980
Test name
Test status
Simulation time 19001389 ps
CPU time 0.8 seconds
Started Jun 02 01:52:49 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 203824 kb
Host smart-c9b6ee68-5aa9-43e6-8572-ee7e5c594b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382035667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3382035667
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1745363286
Short name T982
Test name
Test status
Simulation time 18318723 ps
CPU time 0.76 seconds
Started Jun 02 01:52:43 PM PDT 24
Finished Jun 02 01:52:44 PM PDT 24
Peak memory 203692 kb
Host smart-80a655a2-ad75-4b01-b217-c954c23029fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745363286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1745363286
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2062556300
Short name T1012
Test name
Test status
Simulation time 143026706 ps
CPU time 0.7 seconds
Started Jun 02 01:52:48 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 204040 kb
Host smart-4188d013-f2bd-4353-9004-ec7874311403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062556300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2062556300
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2579396207
Short name T1005
Test name
Test status
Simulation time 22953487 ps
CPU time 0.73 seconds
Started Jun 02 01:52:44 PM PDT 24
Finished Jun 02 01:52:45 PM PDT 24
Peak memory 204024 kb
Host smart-4dffa60f-778b-4152-a5d4-6bf9be709dea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579396207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2579396207
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2102489129
Short name T993
Test name
Test status
Simulation time 13790351 ps
CPU time 0.7 seconds
Started Jun 02 01:52:45 PM PDT 24
Finished Jun 02 01:52:46 PM PDT 24
Peak memory 203768 kb
Host smart-22c44935-9081-4b90-ad6d-83cf05a8e4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102489129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2102489129
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3528231104
Short name T996
Test name
Test status
Simulation time 16992097 ps
CPU time 0.76 seconds
Started Jun 02 01:52:48 PM PDT 24
Finished Jun 02 01:52:49 PM PDT 24
Peak memory 203732 kb
Host smart-31d532b4-1395-4d88-9e7b-25533130a462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528231104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3528231104
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1034529434
Short name T1085
Test name
Test status
Simulation time 13136032 ps
CPU time 0.73 seconds
Started Jun 02 01:52:50 PM PDT 24
Finished Jun 02 01:52:51 PM PDT 24
Peak memory 203840 kb
Host smart-8724af21-1c49-4f3e-8b02-01f9a70687a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034529434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1034529434
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1774222697
Short name T985
Test name
Test status
Simulation time 13719103 ps
CPU time 0.74 seconds
Started Jun 02 01:52:46 PM PDT 24
Finished Jun 02 01:52:47 PM PDT 24
Peak memory 203980 kb
Host smart-3f4168ec-f957-4751-bd27-e0b86fcef6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774222697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1774222697
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.649526853
Short name T1095
Test name
Test status
Simulation time 13504902 ps
CPU time 0.71 seconds
Started Jun 02 01:52:43 PM PDT 24
Finished Jun 02 01:52:44 PM PDT 24
Peak memory 203744 kb
Host smart-faf15415-8993-4c63-a404-2a6346d9c8ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649526853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.649526853
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1308869017
Short name T1008
Test name
Test status
Simulation time 17724801 ps
CPU time 0.79 seconds
Started Jun 02 01:52:47 PM PDT 24
Finished Jun 02 01:52:49 PM PDT 24
Peak memory 203696 kb
Host smart-18c8525b-f01f-4c45-9326-3c7d5269d628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308869017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1308869017
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2300250441
Short name T1084
Test name
Test status
Simulation time 1111174907 ps
CPU time 23.87 seconds
Started Jun 02 01:52:16 PM PDT 24
Finished Jun 02 01:52:40 PM PDT 24
Peak memory 207284 kb
Host smart-0e8dcb5e-0cf9-4bb5-ad6e-e1712f76b37e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300250441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2300250441
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3692101397
Short name T1026
Test name
Test status
Simulation time 5743489321 ps
CPU time 25.42 seconds
Started Jun 02 01:52:16 PM PDT 24
Finished Jun 02 01:52:42 PM PDT 24
Peak memory 207396 kb
Host smart-b23fd921-5b9f-4558-9ab6-e458201e016c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692101397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3692101397
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.202764133
Short name T1030
Test name
Test status
Simulation time 84880470 ps
CPU time 1.78 seconds
Started Jun 02 01:52:18 PM PDT 24
Finished Jun 02 01:52:21 PM PDT 24
Peak memory 216660 kb
Host smart-a5cc771a-1482-4b4f-979a-8f9616739b29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202764133 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.202764133
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.86405041
Short name T1010
Test name
Test status
Simulation time 74370313 ps
CPU time 1.35 seconds
Started Jun 02 01:52:19 PM PDT 24
Finished Jun 02 01:52:21 PM PDT 24
Peak memory 215404 kb
Host smart-9ea7c2d5-0004-4891-8b17-8ee05bc36209
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86405041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.86405041
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3626703316
Short name T1043
Test name
Test status
Simulation time 44538511 ps
CPU time 0.7 seconds
Started Jun 02 01:52:19 PM PDT 24
Finished Jun 02 01:52:20 PM PDT 24
Peak memory 203760 kb
Host smart-2c4a4cbd-655e-4909-b178-3d3687e2c7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626703316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
626703316
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2351931467
Short name T1020
Test name
Test status
Simulation time 91237881 ps
CPU time 1.93 seconds
Started Jun 02 01:52:20 PM PDT 24
Finished Jun 02 01:52:23 PM PDT 24
Peak memory 215532 kb
Host smart-6c19d68c-c911-4040-8af2-c0b6f1060a36
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351931467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2351931467
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4118548732
Short name T1081
Test name
Test status
Simulation time 35467942 ps
CPU time 0.67 seconds
Started Jun 02 01:52:18 PM PDT 24
Finished Jun 02 01:52:20 PM PDT 24
Peak memory 203700 kb
Host smart-221ab5db-e4f3-4d1e-a00b-81c2e744df90
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118548732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4118548732
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3892981937
Short name T1068
Test name
Test status
Simulation time 127468364 ps
CPU time 3.15 seconds
Started Jun 02 01:52:17 PM PDT 24
Finished Jun 02 01:52:21 PM PDT 24
Peak memory 215424 kb
Host smart-8a591c03-7d14-4838-8cb7-8f8d88d42874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892981937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3892981937
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2264469263
Short name T109
Test name
Test status
Simulation time 197622465 ps
CPU time 3.06 seconds
Started Jun 02 01:52:18 PM PDT 24
Finished Jun 02 01:52:22 PM PDT 24
Peak memory 215648 kb
Host smart-a0357742-8a46-4c5b-8fdd-498cce7fc682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264469263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
264469263
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2352993203
Short name T176
Test name
Test status
Simulation time 3380388461 ps
CPU time 22.3 seconds
Started Jun 02 01:52:17 PM PDT 24
Finished Jun 02 01:52:40 PM PDT 24
Peak memory 216352 kb
Host smart-8f51f916-9a7d-4f43-bfea-dc38d25394a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352993203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2352993203
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3212056613
Short name T991
Test name
Test status
Simulation time 23275717 ps
CPU time 0.71 seconds
Started Jun 02 01:52:47 PM PDT 24
Finished Jun 02 01:52:48 PM PDT 24
Peak memory 203708 kb
Host smart-c5777054-9132-4cfe-92ad-eadfec39f051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212056613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3212056613
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1892966867
Short name T987
Test name
Test status
Simulation time 11180428 ps
CPU time 0.69 seconds
Started Jun 02 01:52:49 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 204036 kb
Host smart-77856d2e-b6c7-46f4-a94e-926f16479c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892966867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1892966867
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.406451018
Short name T1087
Test name
Test status
Simulation time 15729020 ps
CPU time 0.74 seconds
Started Jun 02 01:52:46 PM PDT 24
Finished Jun 02 01:52:48 PM PDT 24
Peak memory 203696 kb
Host smart-8140c063-2683-4f89-adfa-a1eabd1f2489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406451018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.406451018
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.255363053
Short name T1007
Test name
Test status
Simulation time 22389292 ps
CPU time 0.76 seconds
Started Jun 02 01:52:48 PM PDT 24
Finished Jun 02 01:52:49 PM PDT 24
Peak memory 204044 kb
Host smart-0b5d8693-a8df-41bf-aa60-c93efcb73ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255363053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.255363053
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.183578013
Short name T1089
Test name
Test status
Simulation time 84542401 ps
CPU time 0.74 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:52:53 PM PDT 24
Peak memory 203684 kb
Host smart-5b2294fd-222f-4893-b1e3-96da8d7de7a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183578013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.183578013
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2799399309
Short name T1016
Test name
Test status
Simulation time 15157217 ps
CPU time 0.74 seconds
Started Jun 02 01:52:47 PM PDT 24
Finished Jun 02 01:52:49 PM PDT 24
Peak memory 203664 kb
Host smart-6c4b9c07-13ec-4492-96ab-889c9d22391a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799399309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2799399309
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.701535953
Short name T1017
Test name
Test status
Simulation time 10614749 ps
CPU time 0.69 seconds
Started Jun 02 01:52:46 PM PDT 24
Finished Jun 02 01:52:47 PM PDT 24
Peak memory 203564 kb
Host smart-3bd5fa2c-9ef2-4955-934f-9c06a4139058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701535953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.701535953
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4270010416
Short name T994
Test name
Test status
Simulation time 54946833 ps
CPU time 0.76 seconds
Started Jun 02 01:52:47 PM PDT 24
Finished Jun 02 01:52:48 PM PDT 24
Peak memory 204024 kb
Host smart-55d04849-0a8d-4d1e-bd0c-216e1c59a018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270010416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4270010416
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2422825467
Short name T1079
Test name
Test status
Simulation time 25343940 ps
CPU time 0.75 seconds
Started Jun 02 01:52:46 PM PDT 24
Finished Jun 02 01:52:48 PM PDT 24
Peak memory 203716 kb
Host smart-2b89a92b-fbf2-4eb7-baae-64a8fcb223ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422825467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2422825467
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2283475516
Short name T1069
Test name
Test status
Simulation time 249508448 ps
CPU time 0.78 seconds
Started Jun 02 01:52:43 PM PDT 24
Finished Jun 02 01:52:44 PM PDT 24
Peak memory 203952 kb
Host smart-cfc7a8fd-bddf-4e2b-b0e4-efe063ebce07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283475516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2283475516
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2585308156
Short name T1027
Test name
Test status
Simulation time 939630631 ps
CPU time 22.62 seconds
Started Jun 02 01:52:23 PM PDT 24
Finished Jun 02 01:52:46 PM PDT 24
Peak memory 215408 kb
Host smart-8df70301-b95e-4ec0-94aa-300cc183793b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585308156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2585308156
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1036029336
Short name T1049
Test name
Test status
Simulation time 2999848277 ps
CPU time 11.5 seconds
Started Jun 02 01:52:24 PM PDT 24
Finished Jun 02 01:52:36 PM PDT 24
Peak memory 207324 kb
Host smart-d85bc697-2645-47e2-8646-31e1d6e679b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036029336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1036029336
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4147009971
Short name T86
Test name
Test status
Simulation time 164534688 ps
CPU time 1.41 seconds
Started Jun 02 01:52:22 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 216516 kb
Host smart-07da720a-4a70-43cc-8491-e3e13fe60d60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147009971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4147009971
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4220844726
Short name T1002
Test name
Test status
Simulation time 116276760 ps
CPU time 3.83 seconds
Started Jun 02 01:52:25 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 217300 kb
Host smart-151b169a-deb4-4b4e-9604-2da23a032385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220844726 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4220844726
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.945056958
Short name T121
Test name
Test status
Simulation time 185313124 ps
CPU time 1.23 seconds
Started Jun 02 01:52:23 PM PDT 24
Finished Jun 02 01:52:25 PM PDT 24
Peak memory 207360 kb
Host smart-0128dc1d-bcde-4ac8-8d4a-c266fdedefab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945056958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.945056958
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4215714311
Short name T1061
Test name
Test status
Simulation time 54933458 ps
CPU time 0.75 seconds
Started Jun 02 01:52:19 PM PDT 24
Finished Jun 02 01:52:21 PM PDT 24
Peak memory 203724 kb
Host smart-879953c9-6dcc-47d4-aa81-6ac7bbddeead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215714311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
215714311
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3287019421
Short name T124
Test name
Test status
Simulation time 528245605 ps
CPU time 2.2 seconds
Started Jun 02 01:52:22 PM PDT 24
Finished Jun 02 01:52:25 PM PDT 24
Peak memory 215544 kb
Host smart-4d0463c3-e62d-4368-8fb2-3dc68e7a03a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287019421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3287019421
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3418761492
Short name T1040
Test name
Test status
Simulation time 95291705 ps
CPU time 0.66 seconds
Started Jun 02 01:52:18 PM PDT 24
Finished Jun 02 01:52:19 PM PDT 24
Peak memory 203640 kb
Host smart-128ce60a-c006-45d0-a35e-435879d83065
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418761492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3418761492
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3700979350
Short name T983
Test name
Test status
Simulation time 155955329 ps
CPU time 4.21 seconds
Started Jun 02 01:52:22 PM PDT 24
Finished Jun 02 01:52:27 PM PDT 24
Peak memory 215472 kb
Host smart-b988880b-bb6c-409e-b252-930a95c5637d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700979350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3700979350
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3178707647
Short name T107
Test name
Test status
Simulation time 93260860 ps
CPU time 1.75 seconds
Started Jun 02 01:52:22 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 215640 kb
Host smart-d9e7cd93-7eaf-45b4-9582-25cd6b011035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178707647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
178707647
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4193133366
Short name T178
Test name
Test status
Simulation time 296898404 ps
CPU time 20.18 seconds
Started Jun 02 01:52:17 PM PDT 24
Finished Jun 02 01:52:38 PM PDT 24
Peak memory 215472 kb
Host smart-2366170c-ed34-498f-aa15-ce7e071e791e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193133366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4193133366
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.417812280
Short name T1022
Test name
Test status
Simulation time 18365189 ps
CPU time 0.7 seconds
Started Jun 02 01:52:48 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 203684 kb
Host smart-e76fbc66-328e-4e1f-93ac-0c1e038f777d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417812280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.417812280
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.369371116
Short name T1097
Test name
Test status
Simulation time 43691294 ps
CPU time 0.72 seconds
Started Jun 02 01:52:44 PM PDT 24
Finished Jun 02 01:52:45 PM PDT 24
Peak memory 203668 kb
Host smart-d1d2e4fa-3cf1-49c1-afbd-107beb750c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369371116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.369371116
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1087357084
Short name T1071
Test name
Test status
Simulation time 16679967 ps
CPU time 0.78 seconds
Started Jun 02 01:52:47 PM PDT 24
Finished Jun 02 01:52:48 PM PDT 24
Peak memory 204004 kb
Host smart-b35b6ccd-95cf-451d-a79a-fd693d8ae6ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087357084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1087357084
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1071675987
Short name T1098
Test name
Test status
Simulation time 44625659 ps
CPU time 0.7 seconds
Started Jun 02 01:52:49 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 204056 kb
Host smart-610dbdae-fbb8-4eda-921e-1c4c06173606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071675987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1071675987
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4255858725
Short name T1072
Test name
Test status
Simulation time 14509099 ps
CPU time 0.74 seconds
Started Jun 02 01:52:50 PM PDT 24
Finished Jun 02 01:52:51 PM PDT 24
Peak memory 203728 kb
Host smart-9db3a72f-9fd1-432d-9792-b540e6632bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255858725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4255858725
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1697432143
Short name T1088
Test name
Test status
Simulation time 39060740 ps
CPU time 0.73 seconds
Started Jun 02 01:52:50 PM PDT 24
Finished Jun 02 01:52:51 PM PDT 24
Peak memory 203760 kb
Host smart-4a2c0532-f30d-43f4-b072-26815b320ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697432143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1697432143
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4080117950
Short name T1006
Test name
Test status
Simulation time 42492446 ps
CPU time 0.69 seconds
Started Jun 02 01:52:44 PM PDT 24
Finished Jun 02 01:52:45 PM PDT 24
Peak memory 204064 kb
Host smart-061aebb5-ff38-4d9a-892e-ae7e22eff7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080117950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4080117950
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2637524550
Short name T1092
Test name
Test status
Simulation time 63052563 ps
CPU time 0.75 seconds
Started Jun 02 01:52:43 PM PDT 24
Finished Jun 02 01:52:44 PM PDT 24
Peak memory 203796 kb
Host smart-981e2473-f471-4d33-83cb-d21d7b59a9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637524550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2637524550
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2054089390
Short name T1096
Test name
Test status
Simulation time 43139002 ps
CPU time 0.74 seconds
Started Jun 02 01:52:49 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 204040 kb
Host smart-9241ecc6-88fb-4698-9652-73bcbc32297b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054089390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2054089390
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3551684887
Short name T990
Test name
Test status
Simulation time 20873473 ps
CPU time 0.7 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:52:53 PM PDT 24
Peak memory 203752 kb
Host smart-2e647fc5-9671-4f8a-83e3-8b2c0d9f4814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551684887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3551684887
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.421804218
Short name T1036
Test name
Test status
Simulation time 51096403 ps
CPU time 1.7 seconds
Started Jun 02 01:52:23 PM PDT 24
Finished Jun 02 01:52:26 PM PDT 24
Peak memory 215608 kb
Host smart-10695000-2131-46f4-af71-60a66b005378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421804218 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.421804218
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2406652991
Short name T128
Test name
Test status
Simulation time 130166162 ps
CPU time 2.36 seconds
Started Jun 02 01:52:25 PM PDT 24
Finished Jun 02 01:52:28 PM PDT 24
Peak memory 207356 kb
Host smart-9ff7e556-1874-48e5-b356-21971cbabc59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406652991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
406652991
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2871436194
Short name T1009
Test name
Test status
Simulation time 38448555 ps
CPU time 0.71 seconds
Started Jun 02 01:52:23 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 204088 kb
Host smart-7e82a7aa-4bd0-4221-8274-fec0d62c305b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871436194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
871436194
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.828792480
Short name T1024
Test name
Test status
Simulation time 314055905 ps
CPU time 4.21 seconds
Started Jun 02 01:52:28 PM PDT 24
Finished Jun 02 01:52:33 PM PDT 24
Peak memory 215488 kb
Host smart-0e7baece-3b12-4229-af70-fce8730d4057
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828792480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.828792480
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.939575128
Short name T1077
Test name
Test status
Simulation time 40946319 ps
CPU time 2.66 seconds
Started Jun 02 01:52:22 PM PDT 24
Finished Jun 02 01:52:25 PM PDT 24
Peak memory 215680 kb
Host smart-cf47274f-f09b-4b89-bb0f-3244e83a0e91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939575128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.939575128
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3284352061
Short name T180
Test name
Test status
Simulation time 1435456750 ps
CPU time 8.44 seconds
Started Jun 02 01:52:20 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 215500 kb
Host smart-9d3c7499-43de-4207-a9df-fa989205e7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284352061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3284352061
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1057248593
Short name T997
Test name
Test status
Simulation time 82778141 ps
CPU time 1.49 seconds
Started Jun 02 01:52:22 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 215584 kb
Host smart-68484678-fab1-44f7-ad5c-14de0e8ed693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057248593 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1057248593
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3411395339
Short name T122
Test name
Test status
Simulation time 401368913 ps
CPU time 1.85 seconds
Started Jun 02 01:52:23 PM PDT 24
Finished Jun 02 01:52:25 PM PDT 24
Peak memory 215504 kb
Host smart-735e1e50-8782-40e2-995a-5d31b581116f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411395339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
411395339
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2798807268
Short name T1031
Test name
Test status
Simulation time 139690010 ps
CPU time 0.7 seconds
Started Jun 02 01:52:24 PM PDT 24
Finished Jun 02 01:52:25 PM PDT 24
Peak memory 203764 kb
Host smart-27648470-86f6-401c-8480-52ed1dee1d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798807268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
798807268
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2563139309
Short name T978
Test name
Test status
Simulation time 87351411 ps
CPU time 2.78 seconds
Started Jun 02 01:52:21 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 215440 kb
Host smart-6775388f-3a04-4a2c-9300-ceb0a639f9e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563139309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2563139309
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2591767985
Short name T1023
Test name
Test status
Simulation time 609062800 ps
CPU time 16.5 seconds
Started Jun 02 01:52:23 PM PDT 24
Finished Jun 02 01:52:40 PM PDT 24
Peak memory 215932 kb
Host smart-c27d4289-4126-4724-9123-2c861122da99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591767985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2591767985
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4022726247
Short name T999
Test name
Test status
Simulation time 25032765 ps
CPU time 1.77 seconds
Started Jun 02 01:52:32 PM PDT 24
Finished Jun 02 01:52:34 PM PDT 24
Peak memory 215628 kb
Host smart-bf98bbbe-8fce-4b9d-804c-2b16caf28494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022726247 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4022726247
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.653269129
Short name T1059
Test name
Test status
Simulation time 66424762 ps
CPU time 2.36 seconds
Started Jun 02 01:52:31 PM PDT 24
Finished Jun 02 01:52:34 PM PDT 24
Peak memory 215432 kb
Host smart-808c78de-c3a7-4fec-8bbf-dbbac7a6864d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653269129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.653269129
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1438064131
Short name T981
Test name
Test status
Simulation time 16401481 ps
CPU time 0.74 seconds
Started Jun 02 01:52:26 PM PDT 24
Finished Jun 02 01:52:28 PM PDT 24
Peak memory 204028 kb
Host smart-4346dc91-9fb1-4724-8db2-c30508307dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438064131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
438064131
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2922375827
Short name T1041
Test name
Test status
Simulation time 795687367 ps
CPU time 4.22 seconds
Started Jun 02 01:52:28 PM PDT 24
Finished Jun 02 01:52:33 PM PDT 24
Peak memory 215396 kb
Host smart-4be1bb1a-1a77-4fd4-b13a-b7f4d9e5af28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922375827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2922375827
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2708802191
Short name T108
Test name
Test status
Simulation time 434652601 ps
CPU time 1.99 seconds
Started Jun 02 01:52:34 PM PDT 24
Finished Jun 02 01:52:37 PM PDT 24
Peak memory 215608 kb
Host smart-118600b8-a5ea-47fd-b3c8-870d5f57c3ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708802191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
708802191
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.56521403
Short name T1082
Test name
Test status
Simulation time 202790269 ps
CPU time 13.02 seconds
Started Jun 02 01:52:25 PM PDT 24
Finished Jun 02 01:52:39 PM PDT 24
Peak memory 215568 kb
Host smart-ff7ba5f2-66d4-4881-b38b-3e178892b3e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56521403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_t
l_intg_err.56521403
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2366363462
Short name T1055
Test name
Test status
Simulation time 103022750 ps
CPU time 2.76 seconds
Started Jun 02 01:52:26 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 217260 kb
Host smart-dd4e65fd-9abc-4884-b842-89aae5de1e14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366363462 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2366363462
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.22281871
Short name T1051
Test name
Test status
Simulation time 45449307 ps
CPU time 1.7 seconds
Started Jun 02 01:52:32 PM PDT 24
Finished Jun 02 01:52:34 PM PDT 24
Peak memory 207208 kb
Host smart-f7a3df9b-b5de-4059-bd68-7050422e9598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22281871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.22281871
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1847765615
Short name T1060
Test name
Test status
Simulation time 66548700 ps
CPU time 0.73 seconds
Started Jun 02 01:52:28 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 203768 kb
Host smart-b1269b84-cbd3-48dc-ac16-24c95f093f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847765615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
847765615
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2427343482
Short name T1037
Test name
Test status
Simulation time 546412262 ps
CPU time 3.33 seconds
Started Jun 02 01:52:34 PM PDT 24
Finished Jun 02 01:52:38 PM PDT 24
Peak memory 215456 kb
Host smart-fc16adf1-d645-4c8e-8e0d-a2adce329fee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427343482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2427343482
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4217780412
Short name T110
Test name
Test status
Simulation time 213383677 ps
CPU time 3.09 seconds
Started Jun 02 01:52:27 PM PDT 24
Finished Jun 02 01:52:32 PM PDT 24
Peak memory 215588 kb
Host smart-1e472a87-b8ac-4b62-89a1-6d2d63c1e71a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217780412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4
217780412
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.850802514
Short name T1034
Test name
Test status
Simulation time 183662763 ps
CPU time 3.91 seconds
Started Jun 02 01:52:28 PM PDT 24
Finished Jun 02 01:52:33 PM PDT 24
Peak memory 217740 kb
Host smart-bfa69943-82f1-4980-b0dc-fbd714dc0d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850802514 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.850802514
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.476778821
Short name T1052
Test name
Test status
Simulation time 316638071 ps
CPU time 2.75 seconds
Started Jun 02 01:52:28 PM PDT 24
Finished Jun 02 01:52:31 PM PDT 24
Peak memory 215448 kb
Host smart-17fc2249-4646-40cb-a944-3108f60a0fe7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476778821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.476778821
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.625358497
Short name T998
Test name
Test status
Simulation time 29305844 ps
CPU time 0.76 seconds
Started Jun 02 01:52:27 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 203716 kb
Host smart-1b3ee9ce-9d06-48fb-a5eb-b8761b9cae4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625358497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.625358497
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2686600523
Short name T1080
Test name
Test status
Simulation time 57082282 ps
CPU time 3.84 seconds
Started Jun 02 01:52:28 PM PDT 24
Finished Jun 02 01:52:32 PM PDT 24
Peak memory 215480 kb
Host smart-ee3f7a70-f266-40c9-a1e0-b72348b57bff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686600523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2686600523
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2536395257
Short name T1074
Test name
Test status
Simulation time 204082735 ps
CPU time 2.93 seconds
Started Jun 02 01:52:33 PM PDT 24
Finished Jun 02 01:52:36 PM PDT 24
Peak memory 216588 kb
Host smart-0c28d0ea-acd8-4739-ad1e-4379e8fcb11c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536395257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
536395257
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2770117435
Short name T1057
Test name
Test status
Simulation time 696823547 ps
CPU time 16.66 seconds
Started Jun 02 01:52:29 PM PDT 24
Finished Jun 02 01:52:46 PM PDT 24
Peak memory 223596 kb
Host smart-21c86043-13d0-4bea-9545-9586815e6ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770117435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2770117435
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.109415116
Short name T659
Test name
Test status
Simulation time 36205778 ps
CPU time 0.72 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:48 PM PDT 24
Peak memory 204820 kb
Host smart-942c0cf8-1b42-475d-9530-2af85df356c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109415116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.109415116
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1013796663
Short name T479
Test name
Test status
Simulation time 6035141478 ps
CPU time 15.06 seconds
Started Jun 02 01:48:35 PM PDT 24
Finished Jun 02 01:48:50 PM PDT 24
Peak memory 234556 kb
Host smart-92de5af0-0611-45d2-a0de-58f440b29ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013796663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1013796663
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.677949522
Short name T557
Test name
Test status
Simulation time 56360913 ps
CPU time 0.73 seconds
Started Jun 02 01:48:42 PM PDT 24
Finished Jun 02 01:48:43 PM PDT 24
Peak memory 205168 kb
Host smart-7240252f-669f-4c15-9c7d-bf6485baf0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677949522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.677949522
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4190384071
Short name T209
Test name
Test status
Simulation time 39917284381 ps
CPU time 135.92 seconds
Started Jun 02 01:48:38 PM PDT 24
Finished Jun 02 01:50:54 PM PDT 24
Peak memory 240564 kb
Host smart-fc314295-98ee-4e55-932a-16421a1f2a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190384071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4190384071
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3712217455
Short name T636
Test name
Test status
Simulation time 78059272233 ps
CPU time 191.05 seconds
Started Jun 02 01:48:38 PM PDT 24
Finished Jun 02 01:51:50 PM PDT 24
Peak memory 253192 kb
Host smart-4cc62ad3-9c74-4315-8f06-ce4001c7367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712217455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3712217455
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.960165010
Short name T824
Test name
Test status
Simulation time 12022260062 ps
CPU time 86.48 seconds
Started Jun 02 01:48:37 PM PDT 24
Finished Jun 02 01:50:04 PM PDT 24
Peak memory 253736 kb
Host smart-a12ad582-4991-4336-b985-6ca02cebf4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960165010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
960165010
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3603540911
Short name T332
Test name
Test status
Simulation time 158810326 ps
CPU time 4.78 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 224108 kb
Host smart-7cf79e98-7000-4772-9c22-00c43e000aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603540911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3603540911
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2517296511
Short name T972
Test name
Test status
Simulation time 208526923 ps
CPU time 4.81 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:56 PM PDT 24
Peak memory 234132 kb
Host smart-8b996ad4-6460-4d1a-a14f-af817a269702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517296511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2517296511
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.767851218
Short name T908
Test name
Test status
Simulation time 2068090426 ps
CPU time 17.03 seconds
Started Jun 02 01:48:37 PM PDT 24
Finished Jun 02 01:48:55 PM PDT 24
Peak memory 232712 kb
Host smart-a4b0b5d5-79e7-4e46-956d-acd99d77a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767851218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.767851218
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1786771282
Short name T634
Test name
Test status
Simulation time 2111945488 ps
CPU time 5.08 seconds
Started Jun 02 01:48:43 PM PDT 24
Finished Jun 02 01:48:49 PM PDT 24
Peak memory 232984 kb
Host smart-cfd9f7b4-5ca4-4083-9b0d-9fa156378ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786771282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1786771282
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1619490154
Short name T560
Test name
Test status
Simulation time 1044109944 ps
CPU time 3.44 seconds
Started Jun 02 01:48:44 PM PDT 24
Finished Jun 02 01:48:48 PM PDT 24
Peak memory 217992 kb
Host smart-71ce06f9-55fc-4794-88b7-952883c4763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619490154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1619490154
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3235229609
Short name T779
Test name
Test status
Simulation time 183135523 ps
CPU time 4.67 seconds
Started Jun 02 01:48:35 PM PDT 24
Finished Jun 02 01:48:40 PM PDT 24
Peak memory 222000 kb
Host smart-345b31db-465c-48d6-8370-7e146747de91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3235229609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3235229609
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.708772344
Short name T73
Test name
Test status
Simulation time 174054856 ps
CPU time 1.21 seconds
Started Jun 02 01:48:38 PM PDT 24
Finished Jun 02 01:48:39 PM PDT 24
Peak memory 234652 kb
Host smart-bc6cf8c5-8f1e-4f13-a39a-e9a39df6a9af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708772344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.708772344
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4096328051
Short name T493
Test name
Test status
Simulation time 3049607525 ps
CPU time 19.73 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:49:07 PM PDT 24
Peak memory 216032 kb
Host smart-17c4d5bf-d103-4b41-ac46-1fc5442b8508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096328051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4096328051
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3992502234
Short name T773
Test name
Test status
Simulation time 8239047622 ps
CPU time 7.78 seconds
Started Jun 02 01:48:41 PM PDT 24
Finished Jun 02 01:48:49 PM PDT 24
Peak memory 215780 kb
Host smart-b856e211-0666-495f-8476-b9d286df93f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992502234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3992502234
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2312453355
Short name T747
Test name
Test status
Simulation time 147519557 ps
CPU time 1.71 seconds
Started Jun 02 01:48:39 PM PDT 24
Finished Jun 02 01:48:41 PM PDT 24
Peak memory 215832 kb
Host smart-610e7490-28d4-449d-90e8-68160092b2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312453355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2312453355
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2860716114
Short name T417
Test name
Test status
Simulation time 109471313 ps
CPU time 0.78 seconds
Started Jun 02 01:48:39 PM PDT 24
Finished Jun 02 01:48:40 PM PDT 24
Peak memory 205208 kb
Host smart-f6f19ae5-3ab0-45a2-b2a7-415179d6c4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860716114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2860716114
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2512834762
Short name T909
Test name
Test status
Simulation time 167778731 ps
CPU time 2.51 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:50 PM PDT 24
Peak memory 224084 kb
Host smart-0102d9ef-2529-4ede-891a-bed9740ce2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512834762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2512834762
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.176987366
Short name T597
Test name
Test status
Simulation time 13680244 ps
CPU time 0.76 seconds
Started Jun 02 01:48:46 PM PDT 24
Finished Jun 02 01:48:47 PM PDT 24
Peak memory 205196 kb
Host smart-c3420f0c-141d-4206-910e-f7ce906a547c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176987366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.176987366
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.170465673
Short name T752
Test name
Test status
Simulation time 116636072 ps
CPU time 2.61 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:51 PM PDT 24
Peak memory 220988 kb
Host smart-51ad357e-3586-4931-8c25-c5562a2e0d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170465673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.170465673
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2870612209
Short name T60
Test name
Test status
Simulation time 80923205 ps
CPU time 0.79 seconds
Started Jun 02 01:48:37 PM PDT 24
Finished Jun 02 01:48:38 PM PDT 24
Peak memory 206200 kb
Host smart-b15110ce-05f1-4751-b576-1ee75598f58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870612209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2870612209
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1674563083
Short name T228
Test name
Test status
Simulation time 24265546336 ps
CPU time 89.16 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:50:21 PM PDT 24
Peak memory 236548 kb
Host smart-0123551b-a6b9-4573-8307-8afa221e6204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674563083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1674563083
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2968783492
Short name T731
Test name
Test status
Simulation time 5957707275 ps
CPU time 69.47 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:49:59 PM PDT 24
Peak memory 255376 kb
Host smart-8fc3b878-1890-4d9b-a740-44117b81d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968783492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2968783492
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.993723190
Short name T330
Test name
Test status
Simulation time 2072800154 ps
CPU time 8.71 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:58 PM PDT 24
Peak memory 237996 kb
Host smart-613aaf9c-7743-44ce-bd81-2be3c1707c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993723190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.993723190
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2758360719
Short name T196
Test name
Test status
Simulation time 3570225530 ps
CPU time 4.41 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 235940 kb
Host smart-cf1d0adc-e331-4eee-9912-4b0daee29827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758360719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2758360719
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1674211477
Short name T232
Test name
Test status
Simulation time 2764740960 ps
CPU time 32 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:49:21 PM PDT 24
Peak memory 239288 kb
Host smart-5f78ef62-a1b4-4ee3-83cc-95d172477b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674211477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1674211477
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.62384969
Short name T678
Test name
Test status
Simulation time 27175573 ps
CPU time 1.09 seconds
Started Jun 02 01:48:42 PM PDT 24
Finished Jun 02 01:48:43 PM PDT 24
Peak memory 216148 kb
Host smart-8140bc8c-f9b7-4b6f-a5b8-5a7b97748fd9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62384969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.62384969
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3156372645
Short name T861
Test name
Test status
Simulation time 1500603969 ps
CPU time 6.34 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 233120 kb
Host smart-9a196d7e-f0e3-4d30-b03f-19f8d81e8ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156372645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3156372645
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2824385242
Short name T791
Test name
Test status
Simulation time 10548508493 ps
CPU time 10.38 seconds
Started Jun 02 01:48:44 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 235664 kb
Host smart-09e30e08-e1f2-4365-a988-bd9d951f38ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824385242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2824385242
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1845928268
Short name T82
Test name
Test status
Simulation time 918824705 ps
CPU time 10.27 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:59 PM PDT 24
Peak memory 218668 kb
Host smart-89082d5e-370a-462d-b1ad-64e2e711bbbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1845928268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1845928268
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2072867595
Short name T72
Test name
Test status
Simulation time 216089991 ps
CPU time 1.05 seconds
Started Jun 02 01:48:56 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 234912 kb
Host smart-05307dcf-434f-49e7-b032-11390fad86df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072867595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2072867595
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.879128738
Short name T712
Test name
Test status
Simulation time 6560482581 ps
CPU time 16.33 seconds
Started Jun 02 01:48:45 PM PDT 24
Finished Jun 02 01:49:01 PM PDT 24
Peak memory 237328 kb
Host smart-5b17323d-e48d-4bc3-b490-a3ca42ccf3ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879128738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.879128738
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.848859760
Short name T426
Test name
Test status
Simulation time 3194171798 ps
CPU time 5.9 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 216040 kb
Host smart-f2c25e8d-1d67-4fe5-ac9e-bbef6de22dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848859760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.848859760
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1334092179
Short name T527
Test name
Test status
Simulation time 1948168996 ps
CPU time 7.16 seconds
Started Jun 02 01:48:41 PM PDT 24
Finished Jun 02 01:48:49 PM PDT 24
Peak memory 215728 kb
Host smart-2c1a16fc-f143-4868-b5a9-b33c90cd196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334092179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1334092179
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3605825326
Short name T78
Test name
Test status
Simulation time 555702588 ps
CPU time 2.06 seconds
Started Jun 02 01:48:45 PM PDT 24
Finished Jun 02 01:48:48 PM PDT 24
Peak memory 215840 kb
Host smart-d7d79a3c-707e-42ed-b5e2-36a52024c8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605825326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3605825326
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.781456682
Short name T696
Test name
Test status
Simulation time 34616051 ps
CPU time 0.79 seconds
Started Jun 02 01:48:37 PM PDT 24
Finished Jun 02 01:48:38 PM PDT 24
Peak memory 205248 kb
Host smart-12fd133d-78b7-46ba-9d92-b9ee983c2b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781456682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.781456682
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2500913383
Short name T637
Test name
Test status
Simulation time 88633377 ps
CPU time 2.46 seconds
Started Jun 02 01:48:43 PM PDT 24
Finished Jun 02 01:48:46 PM PDT 24
Peak memory 220884 kb
Host smart-304f3613-1ba7-41c9-85df-bcbc6d37cc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500913383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2500913383
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1795549146
Short name T515
Test name
Test status
Simulation time 36699215 ps
CPU time 0.74 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:22 PM PDT 24
Peak memory 205200 kb
Host smart-f99762ec-a36c-4885-927a-620fef6fa66f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795549146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1795549146
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3805568579
Short name T470
Test name
Test status
Simulation time 525867096 ps
CPU time 2.6 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:23 PM PDT 24
Peak memory 218000 kb
Host smart-6dc344eb-afcb-47c0-acb6-61f075f4e659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805568579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3805568579
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1974157286
Short name T465
Test name
Test status
Simulation time 35403697 ps
CPU time 0.79 seconds
Started Jun 02 01:49:08 PM PDT 24
Finished Jun 02 01:49:10 PM PDT 24
Peak memory 205872 kb
Host smart-4ceaf302-3c51-465e-a997-a454aaa280ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974157286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1974157286
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.61604570
Short name T297
Test name
Test status
Simulation time 134023029246 ps
CPU time 287.44 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:54:03 PM PDT 24
Peak memory 256744 kb
Host smart-8dd572e0-10b0-4f0e-82b0-e21941b88a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61604570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.61604570
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3966461762
Short name T211
Test name
Test status
Simulation time 27999031690 ps
CPU time 319.95 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:54:35 PM PDT 24
Peak memory 265592 kb
Host smart-28412c72-246f-4bc3-a02f-53eaae8a08e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966461762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3966461762
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1810005143
Short name T204
Test name
Test status
Simulation time 3157807522 ps
CPU time 79.46 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:50:37 PM PDT 24
Peak memory 254760 kb
Host smart-98b7357d-895b-48ae-b635-f93f02b32a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810005143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1810005143
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2619343052
Short name T639
Test name
Test status
Simulation time 123734664 ps
CPU time 3.39 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:49:19 PM PDT 24
Peak memory 224084 kb
Host smart-f5db7780-1d2a-49a1-aa7f-db0a4c51b49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619343052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2619343052
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.930028811
Short name T638
Test name
Test status
Simulation time 2266740183 ps
CPU time 24.97 seconds
Started Jun 02 01:49:06 PM PDT 24
Finished Jun 02 01:49:32 PM PDT 24
Peak memory 233800 kb
Host smart-eb3d367d-646c-4d69-81b0-423828be7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930028811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.930028811
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3398505660
Short name T203
Test name
Test status
Simulation time 6054762874 ps
CPU time 23.69 seconds
Started Jun 02 01:49:16 PM PDT 24
Finished Jun 02 01:49:40 PM PDT 24
Peak memory 230936 kb
Host smart-805279bc-3451-4b92-8617-48b004ce76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398505660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3398505660
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3603905160
Short name T628
Test name
Test status
Simulation time 224543927 ps
CPU time 1.04 seconds
Started Jun 02 01:49:04 PM PDT 24
Finished Jun 02 01:49:06 PM PDT 24
Peak memory 217384 kb
Host smart-24e9b4a5-cf8b-43a2-bf7a-515ed727c2a2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603905160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3603905160
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2520441474
Short name T442
Test name
Test status
Simulation time 1982888286 ps
CPU time 13.66 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:49:23 PM PDT 24
Peak memory 233284 kb
Host smart-1cbeba7a-30d8-4eb6-9a30-c0d370e0c19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520441474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2520441474
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3418992671
Short name T250
Test name
Test status
Simulation time 133841156 ps
CPU time 2.63 seconds
Started Jun 02 01:49:08 PM PDT 24
Finished Jun 02 01:49:11 PM PDT 24
Peak memory 218328 kb
Host smart-5b58d773-329e-4314-92b5-ec66abdb22db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418992671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3418992671
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3587300323
Short name T887
Test name
Test status
Simulation time 824568878 ps
CPU time 10.04 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:49:25 PM PDT 24
Peak memory 219616 kb
Host smart-04105380-e391-48d4-9ce1-b507f6d2b81b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3587300323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3587300323
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.699066715
Short name T580
Test name
Test status
Simulation time 12549244567 ps
CPU time 17.27 seconds
Started Jun 02 01:49:08 PM PDT 24
Finished Jun 02 01:49:26 PM PDT 24
Peak memory 215860 kb
Host smart-2f509e30-4f01-44b0-aa9c-b17a50185420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699066715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.699066715
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1508344784
Short name T883
Test name
Test status
Simulation time 24232224556 ps
CPU time 4.04 seconds
Started Jun 02 01:49:08 PM PDT 24
Finished Jun 02 01:49:12 PM PDT 24
Peak memory 215604 kb
Host smart-4380cb0c-dfb9-470b-9d69-87d3753e7988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508344784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1508344784
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.941287664
Short name T717
Test name
Test status
Simulation time 41811955 ps
CPU time 0.81 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:49:11 PM PDT 24
Peak memory 206068 kb
Host smart-0012a0c2-de8d-4876-8e7e-4ba68345c530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941287664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.941287664
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1027485113
Short name T687
Test name
Test status
Simulation time 82319664 ps
CPU time 0.9 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:49:10 PM PDT 24
Peak memory 205576 kb
Host smart-7d97548f-ee13-4ebd-8184-109dec34a34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027485113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1027485113
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2379163047
Short name T834
Test name
Test status
Simulation time 9549553568 ps
CPU time 5.88 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:49:21 PM PDT 24
Peak memory 224224 kb
Host smart-c608622a-e066-4b83-81f6-921dcf297319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379163047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2379163047
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.586488448
Short name T415
Test name
Test status
Simulation time 12684309 ps
CPU time 0.7 seconds
Started Jun 02 01:49:18 PM PDT 24
Finished Jun 02 01:49:19 PM PDT 24
Peak memory 204088 kb
Host smart-d4b2c8b8-1915-4ffe-840e-6451ecde8e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586488448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.586488448
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2011570640
Short name T750
Test name
Test status
Simulation time 984175772 ps
CPU time 2.97 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:49:19 PM PDT 24
Peak memory 233400 kb
Host smart-13f93496-d847-4915-bcef-1e211a5cd0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011570640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2011570640
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.342592921
Short name T697
Test name
Test status
Simulation time 22323713 ps
CPU time 0.8 seconds
Started Jun 02 01:49:16 PM PDT 24
Finished Jun 02 01:49:17 PM PDT 24
Peak memory 205884 kb
Host smart-176e71e4-5190-4d4a-815a-8c62da35126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342592921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.342592921
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2415327984
Short name T273
Test name
Test status
Simulation time 47443840911 ps
CPU time 125.69 seconds
Started Jun 02 01:49:13 PM PDT 24
Finished Jun 02 01:51:19 PM PDT 24
Peak memory 252280 kb
Host smart-85943bcd-6d4c-4fe9-bdfc-d1e987bef373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415327984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2415327984
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.174271136
Short name T845
Test name
Test status
Simulation time 52422997900 ps
CPU time 155.82 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:51:51 PM PDT 24
Peak memory 251736 kb
Host smart-f3cf0152-5753-45fc-86a2-989c8003bec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174271136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.174271136
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3510726882
Short name T366
Test name
Test status
Simulation time 19599899323 ps
CPU time 68.01 seconds
Started Jun 02 01:49:12 PM PDT 24
Finished Jun 02 01:50:21 PM PDT 24
Peak memory 232396 kb
Host smart-bb189482-c95b-473e-bfbd-7146e8fbc83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510726882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3510726882
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.294875413
Short name T252
Test name
Test status
Simulation time 1199014272 ps
CPU time 7.86 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:49:26 PM PDT 24
Peak memory 233704 kb
Host smart-9c8f857c-b124-49d6-9e43-d6695b37d8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294875413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.294875413
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2085992019
Short name T588
Test name
Test status
Simulation time 3920857409 ps
CPU time 39.57 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:49:57 PM PDT 24
Peak memory 232256 kb
Host smart-91ad5d8c-0bfc-4028-ba03-cf51f72bfbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085992019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2085992019
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1017189308
Short name T758
Test name
Test status
Simulation time 45026861 ps
CPU time 0.99 seconds
Started Jun 02 01:49:14 PM PDT 24
Finished Jun 02 01:49:15 PM PDT 24
Peak memory 216140 kb
Host smart-958755b3-d420-4334-8c0d-3ce8c5e5611c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017189308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1017189308
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1018287036
Short name T609
Test name
Test status
Simulation time 818297541 ps
CPU time 5.18 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:49:24 PM PDT 24
Peak memory 237956 kb
Host smart-e707529e-91ca-4cbb-bda4-9c8ea22cc98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018287036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1018287036
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3692176836
Short name T932
Test name
Test status
Simulation time 386561278 ps
CPU time 4.07 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:25 PM PDT 24
Peak memory 218712 kb
Host smart-637b4f7b-6860-4b61-9724-9f3d235c5552
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3692176836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3692176836
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1479417114
Short name T936
Test name
Test status
Simulation time 7292022743 ps
CPU time 99.66 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:50:58 PM PDT 24
Peak memory 256972 kb
Host smart-1278521a-002a-4913-b664-fe9058be748a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479417114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1479417114
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1064743503
Short name T759
Test name
Test status
Simulation time 13416161 ps
CPU time 0.72 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:49:18 PM PDT 24
Peak memory 204968 kb
Host smart-29eaf146-42f6-4eb1-9adb-4c3483d885de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064743503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1064743503
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2521574525
Short name T714
Test name
Test status
Simulation time 10730313173 ps
CPU time 10.79 seconds
Started Jun 02 01:49:14 PM PDT 24
Finished Jun 02 01:49:25 PM PDT 24
Peak memory 215788 kb
Host smart-0e767bf9-466c-488a-beb0-3493449eaff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521574525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2521574525
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1480468202
Short name T476
Test name
Test status
Simulation time 188167957 ps
CPU time 1.32 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:49:19 PM PDT 24
Peak memory 215628 kb
Host smart-dba65cd6-d4c4-40b1-8a2b-a77cdac109c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480468202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1480468202
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1178523190
Short name T840
Test name
Test status
Simulation time 87360657 ps
CPU time 0.73 seconds
Started Jun 02 01:49:14 PM PDT 24
Finished Jun 02 01:49:15 PM PDT 24
Peak memory 205212 kb
Host smart-0d40498f-a3ac-46b8-9f52-def4ae6bac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178523190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1178523190
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3390373705
Short name T815
Test name
Test status
Simulation time 18245857866 ps
CPU time 21.66 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:49:37 PM PDT 24
Peak memory 238276 kb
Host smart-63b027b2-684e-4156-87e4-32550ccb0ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390373705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3390373705
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1500753761
Short name T64
Test name
Test status
Simulation time 33510652 ps
CPU time 0.68 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:49:20 PM PDT 24
Peak memory 204024 kb
Host smart-3af9d3de-3675-43d0-8ac8-cb112340680b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500753761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1500753761
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.496199087
Short name T925
Test name
Test status
Simulation time 113044029 ps
CPU time 2.65 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:49:20 PM PDT 24
Peak memory 232288 kb
Host smart-87596522-7b8c-478e-b92c-5bdf75857061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496199087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.496199087
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1429802592
Short name T494
Test name
Test status
Simulation time 49082015 ps
CPU time 0.79 seconds
Started Jun 02 01:49:14 PM PDT 24
Finished Jun 02 01:49:16 PM PDT 24
Peak memory 205868 kb
Host smart-26ceb590-22ec-485d-855e-b09333994f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429802592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1429802592
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4087939451
Short name T666
Test name
Test status
Simulation time 6304294160 ps
CPU time 84.46 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:50:42 PM PDT 24
Peak memory 262712 kb
Host smart-a918e6ef-4e2c-4160-828a-662a99800f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087939451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4087939451
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2324647641
Short name T521
Test name
Test status
Simulation time 8219683358 ps
CPU time 93.05 seconds
Started Jun 02 01:49:18 PM PDT 24
Finished Jun 02 01:50:51 PM PDT 24
Peak memory 249436 kb
Host smart-3cb605aa-4c53-4e7d-854f-c4e38dcce34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324647641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2324647641
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2477515234
Short name T248
Test name
Test status
Simulation time 35340258919 ps
CPU time 66.94 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:50:25 PM PDT 24
Peak memory 248736 kb
Host smart-39d2c092-60cd-40a5-a160-8c4973618606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477515234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2477515234
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1254204610
Short name T326
Test name
Test status
Simulation time 14328713344 ps
CPU time 35.62 seconds
Started Jun 02 01:49:18 PM PDT 24
Finished Jun 02 01:49:54 PM PDT 24
Peak memory 232332 kb
Host smart-765de78a-92b9-447b-8461-ac927b0ca875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254204610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1254204610
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.720030657
Short name T454
Test name
Test status
Simulation time 204029758 ps
CPU time 5.08 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:49:23 PM PDT 24
Peak memory 234076 kb
Host smart-a2a45010-aec1-485f-9e97-a82de31552ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720030657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.720030657
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3509379799
Short name T409
Test name
Test status
Simulation time 5258030988 ps
CPU time 16.28 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:36 PM PDT 24
Peak memory 233696 kb
Host smart-fa0b3c6d-6f91-46e8-b915-772ba2365c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509379799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3509379799
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.4087235793
Short name T966
Test name
Test status
Simulation time 89146598 ps
CPU time 1.07 seconds
Started Jun 02 01:49:18 PM PDT 24
Finished Jun 02 01:49:20 PM PDT 24
Peak memory 216140 kb
Host smart-68b579cf-c58e-4ad7-b22f-c6110def6a93
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087235793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.4087235793
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.75371548
Short name T274
Test name
Test status
Simulation time 1103630879 ps
CPU time 5.73 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:27 PM PDT 24
Peak memory 233400 kb
Host smart-bb722332-54ec-4345-80f6-8dce981df074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75371548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.75371548
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.715501928
Short name T255
Test name
Test status
Simulation time 11764193086 ps
CPU time 5 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:49:21 PM PDT 24
Peak memory 219384 kb
Host smart-30cff8de-5a0a-48e4-8c2e-f0968ba8297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715501928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.715501928
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1502340135
Short name T624
Test name
Test status
Simulation time 912987132 ps
CPU time 6.01 seconds
Started Jun 02 01:49:18 PM PDT 24
Finished Jun 02 01:49:25 PM PDT 24
Peak memory 220132 kb
Host smart-fff413e8-a963-47d7-96b8-1412e13bffd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1502340135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1502340135
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.187734038
Short name T466
Test name
Test status
Simulation time 2552285300 ps
CPU time 12.61 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:33 PM PDT 24
Peak memory 216320 kb
Host smart-77f1561b-3a39-4d79-aa53-997c0736ea11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187734038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.187734038
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3123703038
Short name T574
Test name
Test status
Simulation time 1111731134 ps
CPU time 7.63 seconds
Started Jun 02 01:49:18 PM PDT 24
Finished Jun 02 01:49:26 PM PDT 24
Peak memory 215728 kb
Host smart-e5bb4b07-0613-41ca-abfa-7fedc19b3c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123703038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3123703038
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.554820106
Short name T880
Test name
Test status
Simulation time 70884164 ps
CPU time 1.34 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:49:21 PM PDT 24
Peak memory 215904 kb
Host smart-a57fcda1-9c49-47ad-aae0-a4e7234897f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554820106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.554820106
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.865578437
Short name T467
Test name
Test status
Simulation time 604529421 ps
CPU time 0.95 seconds
Started Jun 02 01:49:16 PM PDT 24
Finished Jun 02 01:49:18 PM PDT 24
Peak memory 205224 kb
Host smart-82b7d9ca-0e38-4c98-a8c8-55c5634cf43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865578437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.865578437
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2604272310
Short name T585
Test name
Test status
Simulation time 68593111418 ps
CPU time 21.86 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:43 PM PDT 24
Peak memory 234808 kb
Host smart-1fead0d6-8205-4168-8788-9bcb8dbeff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604272310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2604272310
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3041005504
Short name T640
Test name
Test status
Simulation time 15273626 ps
CPU time 0.79 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:22 PM PDT 24
Peak memory 204208 kb
Host smart-6a8caa5e-5426-4ab6-8931-127437541493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041005504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3041005504
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1150917609
Short name T872
Test name
Test status
Simulation time 984925372 ps
CPU time 12.21 seconds
Started Jun 02 01:49:18 PM PDT 24
Finished Jun 02 01:49:31 PM PDT 24
Peak memory 219272 kb
Host smart-fe4bd903-1a27-4911-bf28-b83401821773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150917609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1150917609
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1392543270
Short name T945
Test name
Test status
Simulation time 20648468 ps
CPU time 0.76 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:49:20 PM PDT 24
Peak memory 205168 kb
Host smart-31fc714e-ad84-47d6-9c5e-4d4de68f2c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392543270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1392543270
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3082924577
Short name T721
Test name
Test status
Simulation time 38433777381 ps
CPU time 116.82 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:51:15 PM PDT 24
Peak memory 251904 kb
Host smart-2c6effc4-6cbc-459c-92f3-02e05825fe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082924577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3082924577
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.400781717
Short name T882
Test name
Test status
Simulation time 185254104 ps
CPU time 2.92 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:23 PM PDT 24
Peak memory 232316 kb
Host smart-2a7a2658-fe59-4f3d-86ca-594dee4dbfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400781717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.400781717
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2569013992
Short name T955
Test name
Test status
Simulation time 3880197007 ps
CPU time 5.79 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:26 PM PDT 24
Peak memory 218372 kb
Host smart-2eff242a-3a78-44da-b76f-23e9d6d36f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569013992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2569013992
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1294911239
Short name T190
Test name
Test status
Simulation time 9128896527 ps
CPU time 35.21 seconds
Started Jun 02 01:49:15 PM PDT 24
Finished Jun 02 01:49:51 PM PDT 24
Peak memory 233892 kb
Host smart-ced361c4-094f-4ccc-8407-d23e532cd379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294911239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1294911239
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3851669710
Short name T970
Test name
Test status
Simulation time 167842668 ps
CPU time 1.13 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:49:21 PM PDT 24
Peak memory 216148 kb
Host smart-fa8746d6-3df5-4933-962f-93c6bff86a86
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851669710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3851669710
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.150320224
Short name T132
Test name
Test status
Simulation time 2729697502 ps
CPU time 11.73 seconds
Started Jun 02 01:49:17 PM PDT 24
Finished Jun 02 01:49:30 PM PDT 24
Peak memory 237676 kb
Host smart-43166cb5-8774-4057-9ded-46c9e1b79618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150320224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.150320224
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2231920620
Short name T874
Test name
Test status
Simulation time 8632729680 ps
CPU time 15.9 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:37 PM PDT 24
Peak memory 228724 kb
Host smart-958b3d13-d1a7-483c-8eda-e2dbc1af4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231920620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2231920620
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3466655414
Short name T374
Test name
Test status
Simulation time 1035261628 ps
CPU time 14.28 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:49:34 PM PDT 24
Peak memory 218320 kb
Host smart-f2bd7f79-7022-4396-ade4-61523224d6e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3466655414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3466655414
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1882702025
Short name T141
Test name
Test status
Simulation time 9004750014 ps
CPU time 90.34 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:50:57 PM PDT 24
Peak memory 253128 kb
Host smart-6a1132f3-958e-4915-a0bf-5d83d1665196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882702025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1882702025
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3770740081
Short name T649
Test name
Test status
Simulation time 2705528062 ps
CPU time 17.03 seconds
Started Jun 02 01:49:14 PM PDT 24
Finished Jun 02 01:49:31 PM PDT 24
Peak memory 215872 kb
Host smart-4c6705f2-fbc0-4396-bcf3-a7626bd9722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770740081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3770740081
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.13567976
Short name T371
Test name
Test status
Simulation time 27604784516 ps
CPU time 19.74 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:49:40 PM PDT 24
Peak memory 215856 kb
Host smart-8fc9577c-e937-484b-99ee-86ba36a3eeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13567976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.13567976
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.725832800
Short name T355
Test name
Test status
Simulation time 255037746 ps
CPU time 2.81 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:23 PM PDT 24
Peak memory 215832 kb
Host smart-209b2fd9-12bd-456c-b17f-dcc662eae715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725832800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.725832800
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4099084606
Short name T444
Test name
Test status
Simulation time 93533900 ps
CPU time 0.75 seconds
Started Jun 02 01:49:19 PM PDT 24
Finished Jun 02 01:49:21 PM PDT 24
Peak memory 205184 kb
Host smart-1758dd08-a885-4576-ad8b-cbb93777ba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099084606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4099084606
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2502471920
Short name T55
Test name
Test status
Simulation time 1459995511 ps
CPU time 6.58 seconds
Started Jun 02 01:49:16 PM PDT 24
Finished Jun 02 01:49:23 PM PDT 24
Peak memory 228028 kb
Host smart-9f76b30a-c235-4108-93d1-b56bf0f5c54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502471920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2502471920
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1663362165
Short name T286
Test name
Test status
Simulation time 1677371393 ps
CPU time 8 seconds
Started Jun 02 01:49:23 PM PDT 24
Finished Jun 02 01:49:32 PM PDT 24
Peak memory 235320 kb
Host smart-5681e2c3-4d90-43d9-bf92-2d0bf194a587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663362165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1663362165
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4014571174
Short name T831
Test name
Test status
Simulation time 100574817 ps
CPU time 0.79 seconds
Started Jun 02 01:49:23 PM PDT 24
Finished Jun 02 01:49:24 PM PDT 24
Peak memory 206160 kb
Host smart-3752b724-f585-4500-aa08-600c5a8f36f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014571174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4014571174
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1148195374
Short name T304
Test name
Test status
Simulation time 10334423693 ps
CPU time 90.21 seconds
Started Jun 02 01:49:22 PM PDT 24
Finished Jun 02 01:50:53 PM PDT 24
Peak memory 256932 kb
Host smart-f031c51b-d603-4f56-a6ab-c735c9afa46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148195374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1148195374
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3006907570
Short name T892
Test name
Test status
Simulation time 6782225412 ps
CPU time 53.49 seconds
Started Jun 02 01:49:23 PM PDT 24
Finished Jun 02 01:50:16 PM PDT 24
Peak memory 249972 kb
Host smart-6eba511f-4ea5-4edc-8435-e8e0e99da693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006907570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3006907570
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1963204680
Short name T715
Test name
Test status
Simulation time 548527810 ps
CPU time 4.43 seconds
Started Jun 02 01:49:21 PM PDT 24
Finished Jun 02 01:49:26 PM PDT 24
Peak memory 232292 kb
Host smart-03af7f83-47ee-4901-af37-e48e1a9a9684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963204680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1963204680
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3111940627
Short name T763
Test name
Test status
Simulation time 1958565319 ps
CPU time 17.29 seconds
Started Jun 02 01:49:22 PM PDT 24
Finished Jun 02 01:49:40 PM PDT 24
Peak memory 218108 kb
Host smart-451e6d34-60d9-4ccc-beb6-41c019eb233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111940627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3111940627
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.550123968
Short name T282
Test name
Test status
Simulation time 5724101489 ps
CPU time 17.55 seconds
Started Jun 02 01:49:22 PM PDT 24
Finished Jun 02 01:49:40 PM PDT 24
Peak memory 236688 kb
Host smart-45d06e7b-8dd8-4153-8da9-77d6ded40475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550123968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.550123968
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.342847095
Short name T859
Test name
Test status
Simulation time 28180492 ps
CPU time 1.07 seconds
Started Jun 02 01:49:22 PM PDT 24
Finished Jun 02 01:49:24 PM PDT 24
Peak memory 217328 kb
Host smart-43705f65-b877-4677-bbf9-8ba150e7d6bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342847095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.342847095
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3406111241
Short name T312
Test name
Test status
Simulation time 3914773206 ps
CPU time 8.02 seconds
Started Jun 02 01:49:24 PM PDT 24
Finished Jun 02 01:49:32 PM PDT 24
Peak memory 233824 kb
Host smart-53d52314-f894-4a7e-b7f9-a21c47aea72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406111241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3406111241
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1940507395
Short name T77
Test name
Test status
Simulation time 3712024423 ps
CPU time 11.79 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:33 PM PDT 24
Peak memory 216500 kb
Host smart-79161e8d-3851-4550-8157-dbb27af81d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940507395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1940507395
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1805434988
Short name T594
Test name
Test status
Simulation time 35199882560 ps
CPU time 19.09 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:49:46 PM PDT 24
Peak memory 222420 kb
Host smart-aa37baf5-e674-4c9b-b0b9-bd7b090d7b28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1805434988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1805434988
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1091188804
Short name T916
Test name
Test status
Simulation time 34739527330 ps
CPU time 253.1 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:53:40 PM PDT 24
Peak memory 256956 kb
Host smart-a0c2957f-75d5-4108-84c1-c7bf215142c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091188804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1091188804
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1278549156
Short name T949
Test name
Test status
Simulation time 399536713 ps
CPU time 6.72 seconds
Started Jun 02 01:49:24 PM PDT 24
Finished Jun 02 01:49:31 PM PDT 24
Peak memory 215884 kb
Host smart-d637c602-83ab-4b31-a670-fd950f5588d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278549156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1278549156
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3519536605
Short name T816
Test name
Test status
Simulation time 868834533 ps
CPU time 2.66 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:49:31 PM PDT 24
Peak memory 215716 kb
Host smart-d592d354-8add-4a41-b696-cdc3b7c48b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519536605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3519536605
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1428681809
Short name T402
Test name
Test status
Simulation time 34793531 ps
CPU time 0.67 seconds
Started Jun 02 01:49:20 PM PDT 24
Finished Jun 02 01:49:21 PM PDT 24
Peak memory 204860 kb
Host smart-7c65f410-d35d-4586-91cb-6c6811d8fcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428681809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1428681809
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2752238386
Short name T853
Test name
Test status
Simulation time 147762300 ps
CPU time 0.86 seconds
Started Jun 02 01:49:23 PM PDT 24
Finished Jun 02 01:49:24 PM PDT 24
Peak memory 205228 kb
Host smart-e50ae707-d48e-4e6f-b9b5-a9a66c6e59a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752238386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2752238386
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.961199568
Short name T229
Test name
Test status
Simulation time 39629107625 ps
CPU time 34.45 seconds
Started Jun 02 01:49:22 PM PDT 24
Finished Jun 02 01:49:56 PM PDT 24
Peak memory 248796 kb
Host smart-d4026ec0-3728-4b48-9bdd-fc4a23391d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961199568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.961199568
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3255756294
Short name T379
Test name
Test status
Simulation time 31682507 ps
CPU time 0.72 seconds
Started Jun 02 01:49:29 PM PDT 24
Finished Jun 02 01:49:30 PM PDT 24
Peak memory 204780 kb
Host smart-3020966a-6694-45d7-a840-364340799b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255756294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3255756294
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1298512052
Short name T923
Test name
Test status
Simulation time 2186378128 ps
CPU time 16.84 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:49:45 PM PDT 24
Peak memory 234852 kb
Host smart-070ddbe2-6cb4-41e6-abe3-dcf34c047f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298512052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1298512052
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3219615625
Short name T502
Test name
Test status
Simulation time 51777259 ps
CPU time 0.72 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:49:29 PM PDT 24
Peak memory 205128 kb
Host smart-1bbec719-6201-4338-a077-7aaac007069d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219615625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3219615625
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1357198782
Short name T186
Test name
Test status
Simulation time 53385275210 ps
CPU time 189.1 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:52:37 PM PDT 24
Peak memory 256660 kb
Host smart-468caba6-d02e-4e22-afa3-6bb16471ee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357198782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1357198782
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.691103136
Short name T741
Test name
Test status
Simulation time 29612283882 ps
CPU time 279.62 seconds
Started Jun 02 01:49:29 PM PDT 24
Finished Jun 02 01:54:09 PM PDT 24
Peak memory 249124 kb
Host smart-f2e52ad0-7aca-4e00-85ec-5f3c26a229e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691103136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.691103136
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2116756493
Short name T948
Test name
Test status
Simulation time 2181198543 ps
CPU time 19.66 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:49:46 PM PDT 24
Peak memory 239100 kb
Host smart-3ede6a7c-94e2-4e4f-9cba-dd3aaadca3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116756493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2116756493
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3836899437
Short name T428
Test name
Test status
Simulation time 797790165 ps
CPU time 9.21 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:49:37 PM PDT 24
Peak memory 217952 kb
Host smart-aa9dc564-db99-4538-ba14-5e4c07eac569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836899437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3836899437
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2978891036
Short name T185
Test name
Test status
Simulation time 3687187660 ps
CPU time 35.14 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:50:03 PM PDT 24
Peak memory 233952 kb
Host smart-3c472580-88a3-4f84-958c-1d9a63153c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978891036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2978891036
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.4175209108
Short name T913
Test name
Test status
Simulation time 34478348 ps
CPU time 1.09 seconds
Started Jun 02 01:49:28 PM PDT 24
Finished Jun 02 01:49:29 PM PDT 24
Peak memory 216148 kb
Host smart-8eb7d82a-d8af-4631-8e95-2222268a6107
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175209108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.4175209108
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2848262447
Short name T290
Test name
Test status
Simulation time 42491342 ps
CPU time 2.7 seconds
Started Jun 02 01:49:28 PM PDT 24
Finished Jun 02 01:49:31 PM PDT 24
Peak memory 232280 kb
Host smart-2c09cb1a-fa7c-439e-a7cd-aa847dd82216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848262447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2848262447
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3012425364
Short name T786
Test name
Test status
Simulation time 575505072 ps
CPU time 6.66 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:49:39 PM PDT 24
Peak memory 218692 kb
Host smart-6c1859fe-7cd4-4b43-9332-dab24b33e96c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3012425364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3012425364
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2583409120
Short name T822
Test name
Test status
Simulation time 4730971580 ps
CPU time 22.2 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:49:49 PM PDT 24
Peak memory 215876 kb
Host smart-17cdde7e-5566-45ae-a1f9-5e97c23c331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583409120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2583409120
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3991037224
Short name T809
Test name
Test status
Simulation time 653174991 ps
CPU time 2.96 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 01:49:33 PM PDT 24
Peak memory 215664 kb
Host smart-31d231dd-25a2-45e5-9277-4eb5a79a3a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991037224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3991037224
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2259002023
Short name T376
Test name
Test status
Simulation time 13065408 ps
CPU time 0.73 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:49:27 PM PDT 24
Peak memory 205316 kb
Host smart-fe20f65c-00b7-4ce1-af82-0f9dedaeafd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259002023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2259002023
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2094185430
Short name T700
Test name
Test status
Simulation time 19819311 ps
CPU time 0.75 seconds
Started Jun 02 01:49:29 PM PDT 24
Finished Jun 02 01:49:30 PM PDT 24
Peak memory 204816 kb
Host smart-ef7954b7-8680-4002-9842-0bf6802fd5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094185430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2094185430
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3916122408
Short name T572
Test name
Test status
Simulation time 53389790 ps
CPU time 2.04 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:49:34 PM PDT 24
Peak memory 215648 kb
Host smart-c0623604-0f2f-4e20-905c-e4c43f6c51d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916122408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3916122408
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3031026858
Short name T404
Test name
Test status
Simulation time 13402309 ps
CPU time 0.71 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 01:49:31 PM PDT 24
Peak memory 204848 kb
Host smart-23682000-1570-4716-811c-f758836aa94f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031026858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3031026858
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3725579391
Short name T289
Test name
Test status
Simulation time 78716229 ps
CPU time 2.31 seconds
Started Jun 02 01:49:38 PM PDT 24
Finished Jun 02 01:49:41 PM PDT 24
Peak memory 218380 kb
Host smart-38e888a4-d652-483b-bb7f-0c55f5963108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725579391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3725579391
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1482758436
Short name T832
Test name
Test status
Simulation time 63266636 ps
CPU time 0.77 seconds
Started Jun 02 01:49:27 PM PDT 24
Finished Jun 02 01:49:29 PM PDT 24
Peak memory 205876 kb
Host smart-dbedd778-c2cf-4417-b184-2d804122ed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482758436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1482758436
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3601033575
Short name T7
Test name
Test status
Simulation time 2342683885 ps
CPU time 27.72 seconds
Started Jun 02 01:49:28 PM PDT 24
Finished Jun 02 01:49:56 PM PDT 24
Peak memory 237800 kb
Host smart-71bdd275-b566-463c-b460-ebb2272e7597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601033575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3601033575
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3635851808
Short name T485
Test name
Test status
Simulation time 2219420661 ps
CPU time 45.31 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:50:17 PM PDT 24
Peak memory 252116 kb
Host smart-ad05e31f-d5e2-4e5f-9cfa-7f4dbecfa17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635851808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3635851808
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2535251706
Short name T661
Test name
Test status
Simulation time 218781357708 ps
CPU time 247.64 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:53:35 PM PDT 24
Peak memory 248816 kb
Host smart-2e93486e-24d7-4cbf-9a9e-4d8ee3fa1c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535251706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2535251706
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.920134863
Short name T358
Test name
Test status
Simulation time 128256943 ps
CPU time 3.61 seconds
Started Jun 02 01:49:28 PM PDT 24
Finished Jun 02 01:49:32 PM PDT 24
Peak memory 224088 kb
Host smart-72094a40-782e-4d25-a1be-02051c9be89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920134863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.920134863
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1115709170
Short name T654
Test name
Test status
Simulation time 34506126 ps
CPU time 2.41 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 01:49:33 PM PDT 24
Peak memory 220340 kb
Host smart-e0bc93b2-d54a-4e8c-bff9-7816aa6810f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115709170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1115709170
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4176056532
Short name T205
Test name
Test status
Simulation time 2681378995 ps
CPU time 34.21 seconds
Started Jun 02 01:49:29 PM PDT 24
Finished Jun 02 01:50:04 PM PDT 24
Peak memory 218100 kb
Host smart-d067eb39-a17e-460a-9e59-227ef4e90cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176056532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4176056532
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3448356170
Short name T26
Test name
Test status
Simulation time 65384184 ps
CPU time 1.09 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:49:33 PM PDT 24
Peak memory 216124 kb
Host smart-208e8f20-3344-4618-abac-60cb4b110141
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448356170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3448356170
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3753326553
Short name T862
Test name
Test status
Simulation time 8653829914 ps
CPU time 25.5 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:49:57 PM PDT 24
Peak memory 232124 kb
Host smart-72afd3f5-1fa3-4d5e-a912-0f079be1ee80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753326553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3753326553
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.143399258
Short name T480
Test name
Test status
Simulation time 108211023 ps
CPU time 2.18 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:49:34 PM PDT 24
Peak memory 215644 kb
Host smart-cd16218e-2875-4b08-8c7e-5ae272a2ec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143399258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.143399258
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1722031158
Short name T163
Test name
Test status
Simulation time 719708936 ps
CPU time 9.07 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:49:36 PM PDT 24
Peak memory 222088 kb
Host smart-9ff4a4b6-d95a-48e3-bc45-cde4a30804e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1722031158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1722031158
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2481194043
Short name T56
Test name
Test status
Simulation time 19779338934 ps
CPU time 212.6 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 01:53:03 PM PDT 24
Peak memory 248736 kb
Host smart-4f43744c-d551-499e-a5f2-e5a98cb61428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481194043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2481194043
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.803325799
Short name T556
Test name
Test status
Simulation time 3858196268 ps
CPU time 30.88 seconds
Started Jun 02 01:49:25 PM PDT 24
Finished Jun 02 01:49:56 PM PDT 24
Peak memory 215860 kb
Host smart-5f4b2694-2b0d-4b82-aae1-808249089869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803325799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.803325799
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.206732432
Short name T354
Test name
Test status
Simulation time 967417259 ps
CPU time 6.66 seconds
Started Jun 02 01:49:36 PM PDT 24
Finished Jun 02 01:49:43 PM PDT 24
Peak memory 215716 kb
Host smart-f32d072d-4c8d-4a56-866d-37246b70553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206732432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.206732432
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3016530224
Short name T592
Test name
Test status
Simulation time 226242772 ps
CPU time 2.34 seconds
Started Jun 02 01:49:28 PM PDT 24
Finished Jun 02 01:49:31 PM PDT 24
Peak memory 216296 kb
Host smart-37c4d085-891b-4f42-b4cf-95024056571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016530224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3016530224
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3930558387
Short name T968
Test name
Test status
Simulation time 42817122 ps
CPU time 0.7 seconds
Started Jun 02 01:49:28 PM PDT 24
Finished Jun 02 01:49:29 PM PDT 24
Peak memory 205160 kb
Host smart-fd6960c1-1889-4f22-aba6-aa24ceb6d5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930558387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3930558387
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1603681538
Short name T900
Test name
Test status
Simulation time 3368476040 ps
CPU time 10.94 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 01:49:42 PM PDT 24
Peak memory 217356 kb
Host smart-49183ff6-313e-4f85-a342-b93430d2a2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603681538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1603681538
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1049591224
Short name T133
Test name
Test status
Simulation time 18736925 ps
CPU time 0.78 seconds
Started Jun 02 01:49:41 PM PDT 24
Finished Jun 02 01:49:42 PM PDT 24
Peak memory 205152 kb
Host smart-24523c95-0863-49fa-b476-0320d446e349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049591224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1049591224
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4252895434
Short name T411
Test name
Test status
Simulation time 1807871920 ps
CPU time 8.33 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:49:40 PM PDT 24
Peak memory 233320 kb
Host smart-d7fdfdb4-6afa-408f-a415-815e6dd724c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252895434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4252895434
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2971735217
Short name T787
Test name
Test status
Simulation time 17231943 ps
CPU time 0.77 seconds
Started Jun 02 01:49:26 PM PDT 24
Finished Jun 02 01:49:27 PM PDT 24
Peak memory 205828 kb
Host smart-45957b0e-13ad-416a-9a6a-92a73ea0549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971735217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2971735217
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1033664828
Short name T456
Test name
Test status
Simulation time 2399393246 ps
CPU time 33.08 seconds
Started Jun 02 01:49:41 PM PDT 24
Finished Jun 02 01:50:14 PM PDT 24
Peak memory 240384 kb
Host smart-850603e5-78f6-42dc-826f-3dfd3ffc5b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033664828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1033664828
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.886878007
Short name T143
Test name
Test status
Simulation time 4413901320 ps
CPU time 62.68 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 01:50:33 PM PDT 24
Peak memory 250256 kb
Host smart-ac961f18-b38e-4e0f-ae71-060634fadaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886878007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.886878007
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.561440612
Short name T514
Test name
Test status
Simulation time 1410139829 ps
CPU time 16.93 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:49:49 PM PDT 24
Peak memory 224032 kb
Host smart-9ae6b066-234c-4799-850f-64bae04b3c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561440612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.561440612
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2273618762
Short name T353
Test name
Test status
Simulation time 226182957 ps
CPU time 2.53 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:49:34 PM PDT 24
Peak memory 232312 kb
Host smart-d7e62b6f-094e-44c8-8f97-35eedffc8e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273618762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2273618762
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2465668965
Short name T373
Test name
Test status
Simulation time 7112156352 ps
CPU time 17.15 seconds
Started Jun 02 01:49:35 PM PDT 24
Finished Jun 02 01:49:52 PM PDT 24
Peak memory 234472 kb
Host smart-2f5d0e0d-ddd0-439c-a0d3-34865fecebad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465668965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2465668965
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1850331665
Short name T667
Test name
Test status
Simulation time 308891216 ps
CPU time 1.1 seconds
Started Jun 02 01:49:36 PM PDT 24
Finished Jun 02 01:49:37 PM PDT 24
Peak memory 216080 kb
Host smart-de564b0f-4f2e-48ba-a77a-1619eff63fd3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850331665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1850331665
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.709226253
Short name T477
Test name
Test status
Simulation time 26942673292 ps
CPU time 20.36 seconds
Started Jun 02 01:49:41 PM PDT 24
Finished Jun 02 01:50:01 PM PDT 24
Peak memory 239376 kb
Host smart-58b1781d-5cee-4752-b750-7d4b9d3f8fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709226253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.709226253
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2871541597
Short name T187
Test name
Test status
Simulation time 3800977755 ps
CPU time 10.71 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:49:42 PM PDT 24
Peak memory 217280 kb
Host smart-21a45996-efbb-4907-ade6-0b1c76dbb560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871541597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2871541597
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4012388702
Short name T794
Test name
Test status
Simulation time 16403595624 ps
CPU time 13.48 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:49:45 PM PDT 24
Peak memory 215896 kb
Host smart-edbb9153-ce60-4a56-934c-34a9dc26c71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012388702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4012388702
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.502037612
Short name T796
Test name
Test status
Simulation time 846956920 ps
CPU time 6.15 seconds
Started Jun 02 01:49:31 PM PDT 24
Finished Jun 02 01:49:38 PM PDT 24
Peak memory 215704 kb
Host smart-48e76951-1b92-49aa-bacd-394cb330e821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502037612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.502037612
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2927014535
Short name T812
Test name
Test status
Simulation time 120641202 ps
CPU time 1.61 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:49:34 PM PDT 24
Peak memory 215864 kb
Host smart-0040f31f-9b7c-487d-8358-cf791957d4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927014535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2927014535
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2610167332
Short name T462
Test name
Test status
Simulation time 50407492 ps
CPU time 0.89 seconds
Started Jun 02 01:49:33 PM PDT 24
Finished Jun 02 01:49:34 PM PDT 24
Peak memory 205232 kb
Host smart-cc59b9a3-d89d-4dc6-bf56-b4770f6af55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610167332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2610167332
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.990903571
Short name T599
Test name
Test status
Simulation time 2217895471 ps
CPU time 8.85 seconds
Started Jun 02 01:49:35 PM PDT 24
Finished Jun 02 01:49:44 PM PDT 24
Peak memory 224104 kb
Host smart-1b1dbe86-5127-4672-892a-fbf45ee88ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990903571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.990903571
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.908568903
Short name T688
Test name
Test status
Simulation time 11039796 ps
CPU time 0.7 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:49:33 PM PDT 24
Peak memory 204720 kb
Host smart-65bbb957-2e98-4bef-b695-f7d695694c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908568903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.908568903
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3134407319
Short name T530
Test name
Test status
Simulation time 245613659 ps
CPU time 4.4 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:49:37 PM PDT 24
Peak memory 219140 kb
Host smart-9ff5ef85-c44b-46bd-9019-e945293db1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134407319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3134407319
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4176693140
Short name T608
Test name
Test status
Simulation time 167894925 ps
CPU time 0.84 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:49:33 PM PDT 24
Peak memory 205872 kb
Host smart-0e2153a6-1992-4a64-bb27-da320e8b5f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176693140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4176693140
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.614120178
Short name T27
Test name
Test status
Simulation time 1390658607 ps
CPU time 14.37 seconds
Started Jun 02 01:49:37 PM PDT 24
Finished Jun 02 01:49:52 PM PDT 24
Peak memory 234500 kb
Host smart-a7dd313f-e9a7-4ec5-9236-098b1445c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614120178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.614120178
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3341806299
Short name T234
Test name
Test status
Simulation time 6071650709 ps
CPU time 69.7 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:50:43 PM PDT 24
Peak memory 256972 kb
Host smart-dc508f2d-ae03-4a3a-9eb1-c055bc03b4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341806299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3341806299
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.582978820
Short name T857
Test name
Test status
Simulation time 17208063255 ps
CPU time 66.92 seconds
Started Jun 02 01:49:35 PM PDT 24
Finished Jun 02 01:50:42 PM PDT 24
Peak memory 238880 kb
Host smart-7a659888-4325-4d3e-81f6-ed84d378e2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582978820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.582978820
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3379797248
Short name T148
Test name
Test status
Simulation time 11120953295 ps
CPU time 34.26 seconds
Started Jun 02 01:49:35 PM PDT 24
Finished Jun 02 01:50:09 PM PDT 24
Peak memory 234260 kb
Host smart-044958b7-a851-4f9f-bf89-c0f10016dd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379797248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3379797248
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.445448952
Short name T401
Test name
Test status
Simulation time 4658528121 ps
CPU time 12.98 seconds
Started Jun 02 01:49:33 PM PDT 24
Finished Jun 02 01:49:46 PM PDT 24
Peak memory 219776 kb
Host smart-5b9d1e5e-bdee-4df1-b040-e69866c0aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445448952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.445448952
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1684870978
Short name T713
Test name
Test status
Simulation time 42883564940 ps
CPU time 105.8 seconds
Started Jun 02 01:49:32 PM PDT 24
Finished Jun 02 01:51:18 PM PDT 24
Peak memory 230668 kb
Host smart-44a9ee3f-a6c1-4703-8f79-11ac3e84145b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684870978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1684870978
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.802902140
Short name T463
Test name
Test status
Simulation time 79381497 ps
CPU time 1.12 seconds
Started Jun 02 01:49:38 PM PDT 24
Finished Jun 02 01:49:40 PM PDT 24
Peak memory 216104 kb
Host smart-215076c1-2041-4f70-95d9-09437721589e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802902140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.802902140
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.786221911
Short name T724
Test name
Test status
Simulation time 9583521906 ps
CPU time 12.59 seconds
Started Jun 02 01:49:38 PM PDT 24
Finished Jun 02 01:49:52 PM PDT 24
Peak memory 223980 kb
Host smart-643553e5-c9cd-4f34-8dcb-9b1810d6154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786221911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.786221911
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2998894951
Short name T265
Test name
Test status
Simulation time 1582528165 ps
CPU time 3.13 seconds
Started Jun 02 01:49:34 PM PDT 24
Finished Jun 02 01:49:37 PM PDT 24
Peak memory 216412 kb
Host smart-32122293-7189-4833-86be-9ec0d4b70ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998894951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2998894951
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2262223122
Short name T755
Test name
Test status
Simulation time 362476312 ps
CPU time 5.66 seconds
Started Jun 02 01:49:39 PM PDT 24
Finished Jun 02 01:49:45 PM PDT 24
Peak memory 219616 kb
Host smart-b33a554f-1ce3-4d4e-9585-eb92530f2867
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262223122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2262223122
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1527103668
Short name T299
Test name
Test status
Simulation time 28666295941 ps
CPU time 252.13 seconds
Started Jun 02 01:49:40 PM PDT 24
Finished Jun 02 01:53:53 PM PDT 24
Peak memory 250352 kb
Host smart-8daeb872-8bac-46c2-8366-94518adec454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527103668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1527103668
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2972921280
Short name T965
Test name
Test status
Simulation time 4762499300 ps
CPU time 7.79 seconds
Started Jun 02 01:49:34 PM PDT 24
Finished Jun 02 01:49:42 PM PDT 24
Peak memory 215920 kb
Host smart-281e487e-708e-4993-9b97-ad7703e7bfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972921280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2972921280
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1090699725
Short name T531
Test name
Test status
Simulation time 2183725558 ps
CPU time 5.73 seconds
Started Jun 02 01:49:33 PM PDT 24
Finished Jun 02 01:49:39 PM PDT 24
Peak memory 215824 kb
Host smart-c2ebe1c6-3c11-424b-ac23-01225ba4fe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090699725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1090699725
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3672973601
Short name T911
Test name
Test status
Simulation time 18440456 ps
CPU time 0.82 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 01:49:32 PM PDT 24
Peak memory 206224 kb
Host smart-7c2d63c6-4d0c-4e9c-9266-c05313d9d43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672973601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3672973601
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.162168535
Short name T865
Test name
Test status
Simulation time 27698707 ps
CPU time 0.76 seconds
Started Jun 02 01:49:39 PM PDT 24
Finished Jun 02 01:49:40 PM PDT 24
Peak memory 205184 kb
Host smart-39bff33b-33a7-40ee-ad7b-e90a280cabd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162168535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.162168535
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2872208763
Short name T510
Test name
Test status
Simulation time 144619821 ps
CPU time 2.69 seconds
Started Jun 02 01:49:36 PM PDT 24
Finished Jun 02 01:49:39 PM PDT 24
Peak memory 224024 kb
Host smart-d82ae457-f3b4-4c16-8dda-94de54585ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872208763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2872208763
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.784494929
Short name T837
Test name
Test status
Simulation time 12788925 ps
CPU time 0.7 seconds
Started Jun 02 01:49:42 PM PDT 24
Finished Jun 02 01:49:43 PM PDT 24
Peak memory 204776 kb
Host smart-ec7a8c40-a004-4fcb-8949-34da715d062f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784494929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.784494929
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.430633970
Short name T542
Test name
Test status
Simulation time 11840874316 ps
CPU time 15.5 seconds
Started Jun 02 01:49:41 PM PDT 24
Finished Jun 02 01:49:57 PM PDT 24
Peak memory 218552 kb
Host smart-fee537fb-c436-4a6d-bc5f-da8b34f58b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430633970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.430633970
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2267487545
Short name T362
Test name
Test status
Simulation time 33373799 ps
CPU time 0.8 seconds
Started Jun 02 01:49:36 PM PDT 24
Finished Jun 02 01:49:37 PM PDT 24
Peak memory 205848 kb
Host smart-24d877f0-372a-484f-b0d5-3b30420cb15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267487545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2267487545
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1249496262
Short name T227
Test name
Test status
Simulation time 109806163624 ps
CPU time 93.73 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:51:19 PM PDT 24
Peak memory 265092 kb
Host smart-2ba8d247-abc5-4e50-af82-a04b0de82c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249496262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1249496262
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.155449397
Short name T680
Test name
Test status
Simulation time 4703297504 ps
CPU time 72.76 seconds
Started Jun 02 01:49:36 PM PDT 24
Finished Jun 02 01:50:49 PM PDT 24
Peak memory 248812 kb
Host smart-f20dd619-938d-43e8-a4d6-5807a259618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155449397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.155449397
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3792998861
Short name T797
Test name
Test status
Simulation time 4475860253 ps
CPU time 20.46 seconds
Started Jun 02 01:49:37 PM PDT 24
Finished Jun 02 01:49:58 PM PDT 24
Peak memory 233808 kb
Host smart-2a5575e2-ca61-4906-9fdf-9bd896bb8377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792998861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3792998861
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3467765382
Short name T220
Test name
Test status
Simulation time 21472897841 ps
CPU time 72.73 seconds
Started Jun 02 01:49:39 PM PDT 24
Finished Jun 02 01:50:52 PM PDT 24
Peak memory 228300 kb
Host smart-6ed597f2-b528-4a8a-972e-a73bcd42c91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467765382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3467765382
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4202090904
Short name T25
Test name
Test status
Simulation time 95399110 ps
CPU time 1.14 seconds
Started Jun 02 01:49:33 PM PDT 24
Finished Jun 02 01:49:35 PM PDT 24
Peak memory 216132 kb
Host smart-efaf513d-dc15-471c-9259-a2470fac745f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202090904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4202090904
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2142341895
Short name T277
Test name
Test status
Simulation time 109962146 ps
CPU time 2.46 seconds
Started Jun 02 01:49:41 PM PDT 24
Finished Jun 02 01:49:43 PM PDT 24
Peak memory 217964 kb
Host smart-c17297c6-ef96-4102-9f20-e70ba6329741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142341895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2142341895
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4115988050
Short name T119
Test name
Test status
Simulation time 9129627032 ps
CPU time 14.56 seconds
Started Jun 02 01:49:34 PM PDT 24
Finished Jun 02 01:49:49 PM PDT 24
Peak memory 232912 kb
Host smart-002e151b-4eba-4a82-87dc-edd850b72eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115988050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4115988050
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2005865465
Short name T744
Test name
Test status
Simulation time 1322846896 ps
CPU time 12.11 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:49:58 PM PDT 24
Peak memory 221292 kb
Host smart-5e2eb514-af38-4bf9-9d14-30732d9bc627
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2005865465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2005865465
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3891043184
Short name T738
Test name
Test status
Simulation time 2690391024 ps
CPU time 7.68 seconds
Started Jun 02 01:49:30 PM PDT 24
Finished Jun 02 01:49:38 PM PDT 24
Peak memory 215968 kb
Host smart-76aeb74d-dc14-4d84-8e25-9e86509c42d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891043184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3891043184
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3671345801
Short name T486
Test name
Test status
Simulation time 688185925 ps
CPU time 2.88 seconds
Started Jun 02 01:49:35 PM PDT 24
Finished Jun 02 01:49:38 PM PDT 24
Peak memory 215744 kb
Host smart-73a090b1-f93f-4b87-bd13-4020ef8364af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671345801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3671345801
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3836408406
Short name T767
Test name
Test status
Simulation time 87572175 ps
CPU time 1.72 seconds
Started Jun 02 01:49:34 PM PDT 24
Finished Jun 02 01:49:36 PM PDT 24
Peak memory 215924 kb
Host smart-1a555826-f6cc-466a-806b-85463ffb0b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836408406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3836408406
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1497196217
Short name T17
Test name
Test status
Simulation time 63756272 ps
CPU time 0.99 seconds
Started Jun 02 01:49:34 PM PDT 24
Finished Jun 02 01:49:35 PM PDT 24
Peak memory 206244 kb
Host smart-8b03d2dc-1754-4094-97a2-322427e2b132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497196217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1497196217
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1243094426
Short name T780
Test name
Test status
Simulation time 3490083852 ps
CPU time 12.43 seconds
Started Jun 02 01:49:37 PM PDT 24
Finished Jun 02 01:49:50 PM PDT 24
Peak memory 218408 kb
Host smart-17a44464-8f33-47ca-8ea0-267db880465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243094426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1243094426
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4083183071
Short name T632
Test name
Test status
Simulation time 34098197 ps
CPU time 0.76 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:48:53 PM PDT 24
Peak memory 204176 kb
Host smart-2122941c-e1b9-4940-a879-bf4f8eb7e112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083183071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
083183071
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2368488982
Short name T876
Test name
Test status
Simulation time 32113696 ps
CPU time 2.04 seconds
Started Jun 02 01:48:46 PM PDT 24
Finished Jun 02 01:48:48 PM PDT 24
Peak memory 215668 kb
Host smart-7502c398-7359-41b4-ba8f-b97b4f159d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368488982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2368488982
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.858860236
Short name T5
Test name
Test status
Simulation time 48563356 ps
CPU time 0.76 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:49 PM PDT 24
Peak memory 204752 kb
Host smart-732bfcec-b168-464d-a08b-adaca35c4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858860236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.858860236
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1034911991
Short name T491
Test name
Test status
Simulation time 3078655626 ps
CPU time 41.28 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:49:32 PM PDT 24
Peak memory 249072 kb
Host smart-bcd9f46d-aaa4-4d02-91fb-d153c1d46fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034911991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1034911991
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1290721932
Short name T217
Test name
Test status
Simulation time 57522846673 ps
CPU time 86.45 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:50:19 PM PDT 24
Peak memory 248764 kb
Host smart-a2196ef7-295b-4e1b-8ae4-689a14f3aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290721932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1290721932
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.530892815
Short name T890
Test name
Test status
Simulation time 6319884420 ps
CPU time 35.23 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:49:30 PM PDT 24
Peak memory 238016 kb
Host smart-b0c46478-a22d-47fb-88c7-82c33ba8c21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530892815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
530892815
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3936513426
Short name T399
Test name
Test status
Simulation time 5171235159 ps
CPU time 16.8 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:49:07 PM PDT 24
Peak memory 240552 kb
Host smart-48629019-afbb-47a1-b4d9-88ef315d8eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936513426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3936513426
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3439333039
Short name T264
Test name
Test status
Simulation time 977420250 ps
CPU time 4.02 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:48:55 PM PDT 24
Peak memory 234000 kb
Host smart-ebef8991-529e-4937-96d7-8573d2ab68d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439333039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3439333039
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3172440363
Short name T582
Test name
Test status
Simulation time 15352337463 ps
CPU time 38.6 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:49:28 PM PDT 24
Peak memory 229640 kb
Host smart-a3543d7f-e98f-4718-a222-c19bcc44f68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172440363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3172440363
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.153831559
Short name T24
Test name
Test status
Simulation time 25468962 ps
CPU time 1.11 seconds
Started Jun 02 01:48:53 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 216140 kb
Host smart-e5b6fc2e-3b9c-4763-ba67-ea807f363294
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153831559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.153831559
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3882246225
Short name T321
Test name
Test status
Simulation time 304937275 ps
CPU time 2.85 seconds
Started Jun 02 01:48:56 PM PDT 24
Finished Jun 02 01:48:59 PM PDT 24
Peak memory 218400 kb
Host smart-1224009b-ad90-4a7a-9547-636214c28fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882246225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3882246225
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.43173216
Short name T95
Test name
Test status
Simulation time 21879675615 ps
CPU time 15.88 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:49:07 PM PDT 24
Peak memory 219876 kb
Host smart-4a07840c-c210-4ab1-acc1-e15fd847875c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43173216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.43173216
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1813465200
Short name T539
Test name
Test status
Simulation time 2278927661 ps
CPU time 9.43 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:48:59 PM PDT 24
Peak memory 222828 kb
Host smart-dc81984c-3686-4baa-9d28-9c5437b5588b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1813465200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1813465200
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.792464960
Short name T70
Test name
Test status
Simulation time 249113334 ps
CPU time 0.95 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:50 PM PDT 24
Peak memory 234692 kb
Host smart-587021b2-c6f6-45c5-b604-c02ec5214439
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792464960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.792464960
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.628451494
Short name T18
Test name
Test status
Simulation time 3922974017 ps
CPU time 16.91 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:49:04 PM PDT 24
Peak memory 216104 kb
Host smart-23e03ac1-b1a1-4177-b810-8f723423aa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628451494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.628451494
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4061572675
Short name T761
Test name
Test status
Simulation time 10014576423 ps
CPU time 11.05 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:49:01 PM PDT 24
Peak memory 215808 kb
Host smart-77b62d44-3a77-4aae-9e79-38bff75bae74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061572675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4061572675
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2946999916
Short name T730
Test name
Test status
Simulation time 27087458 ps
CPU time 1.11 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:53 PM PDT 24
Peak memory 207368 kb
Host smart-8dc387e7-3faa-4eef-865a-6b403ffc1ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946999916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2946999916
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2935639257
Short name T799
Test name
Test status
Simulation time 187748038 ps
CPU time 0.91 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:49 PM PDT 24
Peak memory 206244 kb
Host smart-ee17507f-e6b1-48bd-aaf4-8e2ade5de904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935639257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2935639257
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2771658464
Short name T242
Test name
Test status
Simulation time 350085372 ps
CPU time 8.03 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:49:00 PM PDT 24
Peak memory 249144 kb
Host smart-3d96466e-1613-40c8-8033-0b96b4d39ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771658464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2771658464
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.276185111
Short name T62
Test name
Test status
Simulation time 140375059 ps
CPU time 0.75 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:49:44 PM PDT 24
Peak memory 204152 kb
Host smart-2ecc59ee-689f-41ab-a4d5-6d128f4d9d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276185111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.276185111
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1888414016
Short name T953
Test name
Test status
Simulation time 865635400 ps
CPU time 5.5 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:49:51 PM PDT 24
Peak memory 217280 kb
Host smart-593818ca-34b6-4b45-8ec8-46b1839164e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888414016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1888414016
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2371821930
Short name T825
Test name
Test status
Simulation time 34883116 ps
CPU time 0.77 seconds
Started Jun 02 01:49:40 PM PDT 24
Finished Jun 02 01:49:41 PM PDT 24
Peak memory 205884 kb
Host smart-5bb5be76-cb0f-4d8d-804a-9d1db0b68c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371821930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2371821930
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.485460198
Short name T954
Test name
Test status
Simulation time 14650355396 ps
CPU time 114.32 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:51:39 PM PDT 24
Peak memory 248752 kb
Host smart-f5b85fa4-61ad-4afd-8463-49a862c551b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485460198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.485460198
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2011353785
Short name T633
Test name
Test status
Simulation time 7433733825 ps
CPU time 93.62 seconds
Started Jun 02 01:49:38 PM PDT 24
Finished Jun 02 01:51:12 PM PDT 24
Peak memory 254672 kb
Host smart-617dc157-340c-471c-a859-2a32318a460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011353785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2011353785
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2962435058
Short name T272
Test name
Test status
Simulation time 18449505254 ps
CPU time 182.13 seconds
Started Jun 02 01:49:40 PM PDT 24
Finished Jun 02 01:52:43 PM PDT 24
Peak memory 238856 kb
Host smart-c6aeda47-e671-4843-98db-c1ef34bdb07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962435058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2962435058
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3656912914
Short name T838
Test name
Test status
Simulation time 309979177 ps
CPU time 9.71 seconds
Started Jun 02 01:49:38 PM PDT 24
Finished Jun 02 01:49:48 PM PDT 24
Peak memory 248720 kb
Host smart-fde1e2ab-8b16-41b2-9b4d-4e96d68f48b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656912914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3656912914
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.835975485
Short name T284
Test name
Test status
Simulation time 395726645 ps
CPU time 4.29 seconds
Started Jun 02 01:49:40 PM PDT 24
Finished Jun 02 01:49:44 PM PDT 24
Peak memory 232304 kb
Host smart-34919376-d62e-430d-9a55-2b2c0d6b834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835975485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.835975485
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.625591084
Short name T790
Test name
Test status
Simulation time 66869132394 ps
CPU time 130.69 seconds
Started Jun 02 01:49:40 PM PDT 24
Finished Jun 02 01:51:51 PM PDT 24
Peak memory 238788 kb
Host smart-95370e84-cbf4-4c4b-9ed1-327e1d364acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625591084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.625591084
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3588355768
Short name T584
Test name
Test status
Simulation time 417632061 ps
CPU time 2.56 seconds
Started Jun 02 01:49:40 PM PDT 24
Finished Jun 02 01:49:43 PM PDT 24
Peak memory 224004 kb
Host smart-c619d9fe-5c9f-4017-894f-899138ce0dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588355768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3588355768
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1225827562
Short name T285
Test name
Test status
Simulation time 3513585501 ps
CPU time 5.82 seconds
Started Jun 02 01:49:39 PM PDT 24
Finished Jun 02 01:49:45 PM PDT 24
Peak memory 233292 kb
Host smart-55d132ad-0377-4ce7-9404-87cb7a60730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225827562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1225827562
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.345353636
Short name T441
Test name
Test status
Simulation time 1826165188 ps
CPU time 17.42 seconds
Started Jun 02 01:49:41 PM PDT 24
Finished Jun 02 01:49:59 PM PDT 24
Peak memory 222360 kb
Host smart-7e31899c-084c-4745-a91e-c6cde347e44e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=345353636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.345353636
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3158367083
Short name T155
Test name
Test status
Simulation time 3118299084 ps
CPU time 62.19 seconds
Started Jun 02 01:49:37 PM PDT 24
Finished Jun 02 01:50:40 PM PDT 24
Peak memory 250784 kb
Host smart-c6b9e13e-43ad-4690-a9f0-4c13ba40b0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158367083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3158367083
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.665263398
Short name T806
Test name
Test status
Simulation time 5086416681 ps
CPU time 7.43 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:49:51 PM PDT 24
Peak memory 215932 kb
Host smart-c960ea68-c3bd-4ff9-b84e-f8848f105fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665263398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.665263398
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1073279725
Short name T523
Test name
Test status
Simulation time 2235492919 ps
CPU time 9.19 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:49:53 PM PDT 24
Peak memory 215828 kb
Host smart-eca55afa-554a-4ac8-a514-67f5a4b26089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073279725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1073279725
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.222444138
Short name T433
Test name
Test status
Simulation time 11139755 ps
CPU time 0.69 seconds
Started Jun 02 01:49:39 PM PDT 24
Finished Jun 02 01:49:40 PM PDT 24
Peak memory 204872 kb
Host smart-0449db02-8bf3-4616-af1c-f2e8fd806973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222444138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.222444138
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1393746997
Short name T630
Test name
Test status
Simulation time 20245717 ps
CPU time 0.81 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:49:46 PM PDT 24
Peak memory 205220 kb
Host smart-070e7831-21b6-4de2-be4c-0e6c8f4beb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393746997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1393746997
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4224901703
Short name T266
Test name
Test status
Simulation time 4802531123 ps
CPU time 9.49 seconds
Started Jun 02 01:49:40 PM PDT 24
Finished Jun 02 01:49:50 PM PDT 24
Peak memory 237464 kb
Host smart-23f54a6a-f217-41b5-b25d-75f6f69e52c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224901703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4224901703
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3132771394
Short name T381
Test name
Test status
Simulation time 48380337 ps
CPU time 0.73 seconds
Started Jun 02 01:49:48 PM PDT 24
Finished Jun 02 01:49:49 PM PDT 24
Peak memory 204840 kb
Host smart-be4984c7-70d5-406b-beb0-b9a090147b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132771394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3132771394
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1113792704
Short name T364
Test name
Test status
Simulation time 223109796 ps
CPU time 2.9 seconds
Started Jun 02 01:49:46 PM PDT 24
Finished Jun 02 01:49:49 PM PDT 24
Peak memory 218028 kb
Host smart-c9294701-16c5-4022-b215-84cb9797b8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113792704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1113792704
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3069747865
Short name T695
Test name
Test status
Simulation time 22430536 ps
CPU time 0.79 seconds
Started Jun 02 01:49:38 PM PDT 24
Finished Jun 02 01:49:39 PM PDT 24
Peak memory 205788 kb
Host smart-c73af3da-d502-48e8-b42a-b75cbee13cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069747865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3069747865
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3302105693
Short name T899
Test name
Test status
Simulation time 4696378040 ps
CPU time 62.78 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:50:46 PM PDT 24
Peak memory 249744 kb
Host smart-5a24f0dc-30bb-4d3d-99fa-b5903731b0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302105693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3302105693
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3611326013
Short name T212
Test name
Test status
Simulation time 83282812804 ps
CPU time 146.99 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:52:12 PM PDT 24
Peak memory 248824 kb
Host smart-44682746-4987-4653-90c7-3a030b1ee97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611326013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3611326013
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2208533235
Short name T686
Test name
Test status
Simulation time 376562244 ps
CPU time 4.89 seconds
Started Jun 02 01:49:46 PM PDT 24
Finished Jun 02 01:49:51 PM PDT 24
Peak memory 232260 kb
Host smart-0fd39912-1cde-4ce6-bf0f-6b7b8a9c3c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208533235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2208533235
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3546957997
Short name T802
Test name
Test status
Simulation time 28327512668 ps
CPU time 83.62 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:51:08 PM PDT 24
Peak memory 237300 kb
Host smart-72662095-5727-4990-a221-8e3d5235abe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546957997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3546957997
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1023771512
Short name T275
Test name
Test status
Simulation time 1995934601 ps
CPU time 3.58 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:49:49 PM PDT 24
Peak memory 218560 kb
Host smart-941d8a13-462a-4d3d-92d9-73a8a13e98f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023771512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1023771512
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.818295994
Short name T575
Test name
Test status
Simulation time 2022882596 ps
CPU time 3.57 seconds
Started Jun 02 01:49:47 PM PDT 24
Finished Jun 02 01:49:50 PM PDT 24
Peak memory 233624 kb
Host smart-4c390ea9-a694-4ffc-9e39-837748e61a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818295994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.818295994
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3066204687
Short name T535
Test name
Test status
Simulation time 2289032145 ps
CPU time 7.27 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:49:51 PM PDT 24
Peak memory 218228 kb
Host smart-488a5e54-6a87-493e-b376-d174a748bf35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3066204687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3066204687
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1309834159
Short name T751
Test name
Test status
Simulation time 132683483 ps
CPU time 1.16 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:49:46 PM PDT 24
Peak memory 207164 kb
Host smart-d88c6846-43f2-48c2-9d35-49f4b2fb6b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309834159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1309834159
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3369960955
Short name T691
Test name
Test status
Simulation time 532276043 ps
CPU time 2.35 seconds
Started Jun 02 01:49:39 PM PDT 24
Finished Jun 02 01:49:42 PM PDT 24
Peak memory 215860 kb
Host smart-d88867b4-6a21-45ca-ab07-274c24918269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369960955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3369960955
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.652581520
Short name T841
Test name
Test status
Simulation time 43976702402 ps
CPU time 18.34 seconds
Started Jun 02 01:49:41 PM PDT 24
Finished Jun 02 01:49:59 PM PDT 24
Peak memory 215796 kb
Host smart-388fa907-863d-4122-8e6d-65bcd2ade762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652581520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.652581520
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1740864733
Short name T418
Test name
Test status
Simulation time 21578710 ps
CPU time 0.69 seconds
Started Jun 02 01:49:42 PM PDT 24
Finished Jun 02 01:49:43 PM PDT 24
Peak memory 204856 kb
Host smart-08ce873e-a44c-4266-bbfc-a0293aeb02e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740864733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1740864733
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3515269072
Short name T870
Test name
Test status
Simulation time 57821497 ps
CPU time 0.86 seconds
Started Jun 02 01:49:37 PM PDT 24
Finished Jun 02 01:49:38 PM PDT 24
Peak memory 205228 kb
Host smart-c5dd00eb-13d3-472f-b8b7-e9c4f435181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515269072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3515269072
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2565176802
Short name T817
Test name
Test status
Simulation time 753197480 ps
CPU time 4.59 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:49:48 PM PDT 24
Peak memory 223116 kb
Host smart-9a3395cb-7d52-4d06-a92d-11fbbb75080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565176802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2565176802
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3055279728
Short name T742
Test name
Test status
Simulation time 10706507 ps
CPU time 0.69 seconds
Started Jun 02 01:49:50 PM PDT 24
Finished Jun 02 01:49:51 PM PDT 24
Peak memory 204052 kb
Host smart-39d2acbb-b5c6-45dd-a7ab-22e6846a12da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055279728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3055279728
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.150426567
Short name T581
Test name
Test status
Simulation time 109514968 ps
CPU time 2.42 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:49:48 PM PDT 24
Peak memory 218164 kb
Host smart-70253246-3b51-44ac-a614-c46eebe63084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150426567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.150426567
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1645268071
Short name T819
Test name
Test status
Simulation time 16522890 ps
CPU time 0.79 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:49:45 PM PDT 24
Peak memory 205868 kb
Host smart-94b5de0a-a5f2-4eff-8848-229f10ff2248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645268071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1645268071
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1068438970
Short name T166
Test name
Test status
Simulation time 110727918148 ps
CPU time 117.39 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:51:41 PM PDT 24
Peak memory 253832 kb
Host smart-3654a56d-cfe9-4864-8ee8-6181cd9715b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068438970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1068438970
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2396570446
Short name T583
Test name
Test status
Simulation time 361897706 ps
CPU time 5.5 seconds
Started Jun 02 01:49:44 PM PDT 24
Finished Jun 02 01:49:50 PM PDT 24
Peak memory 218312 kb
Host smart-1d655e09-93e8-4392-a452-2fd0228a7be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396570446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2396570446
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1073467439
Short name T897
Test name
Test status
Simulation time 2236520422 ps
CPU time 9.16 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:49:53 PM PDT 24
Peak memory 218184 kb
Host smart-f2d8af93-0a97-438d-9b43-5b2bd3b5770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073467439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1073467439
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.355752657
Short name T869
Test name
Test status
Simulation time 32532838156 ps
CPU time 20.47 seconds
Started Jun 02 01:49:48 PM PDT 24
Finished Jun 02 01:50:09 PM PDT 24
Peak memory 233444 kb
Host smart-fc3a8b0e-9cdb-4b84-adc3-9b832aecd54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355752657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.355752657
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.423866305
Short name T257
Test name
Test status
Simulation time 103493991 ps
CPU time 2.3 seconds
Started Jun 02 01:49:46 PM PDT 24
Finished Jun 02 01:49:49 PM PDT 24
Peak memory 218260 kb
Host smart-920b71db-3ab1-44bf-96d4-e21089a19bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423866305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.423866305
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.402725883
Short name T446
Test name
Test status
Simulation time 1152050734 ps
CPU time 9.83 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:49:54 PM PDT 24
Peak memory 222624 kb
Host smart-a0c4de3a-ba34-43f0-9c20-02a814d64c39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=402725883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.402725883
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2847673156
Short name T81
Test name
Test status
Simulation time 3612868182 ps
CPU time 34.83 seconds
Started Jun 02 01:49:50 PM PDT 24
Finished Jun 02 01:50:26 PM PDT 24
Peak memory 231264 kb
Host smart-35099a5f-8b5b-4ad7-a031-98b0eecf87ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847673156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2847673156
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4060032096
Short name T334
Test name
Test status
Simulation time 2994732967 ps
CPU time 30.44 seconds
Started Jun 02 01:49:43 PM PDT 24
Finished Jun 02 01:50:13 PM PDT 24
Peak memory 215880 kb
Host smart-b8c5a13f-e850-4a96-a837-f55ef55dde5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060032096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4060032096
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1405113162
Short name T610
Test name
Test status
Simulation time 6868786756 ps
CPU time 6.3 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:49:52 PM PDT 24
Peak memory 215772 kb
Host smart-ac4d10bf-733b-4c8a-83a1-ed6a0c0626d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405113162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1405113162
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2851634326
Short name T382
Test name
Test status
Simulation time 195065410 ps
CPU time 2.7 seconds
Started Jun 02 01:49:46 PM PDT 24
Finished Jun 02 01:49:49 PM PDT 24
Peak memory 215796 kb
Host smart-6f3f03ac-47ce-4179-80ce-d195dbc89a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851634326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2851634326
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2001102548
Short name T363
Test name
Test status
Simulation time 19769265 ps
CPU time 0.75 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:49:46 PM PDT 24
Peak memory 205208 kb
Host smart-3a1838dc-2abf-403c-8683-041cb73f095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001102548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2001102548
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3878312247
Short name T233
Test name
Test status
Simulation time 1915668196 ps
CPU time 14 seconds
Started Jun 02 01:49:45 PM PDT 24
Finished Jun 02 01:49:59 PM PDT 24
Peak memory 239216 kb
Host smart-712b8d0f-651e-4499-846b-cd23256bc551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878312247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3878312247
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3695657449
Short name T458
Test name
Test status
Simulation time 16815377 ps
CPU time 0.77 seconds
Started Jun 02 01:49:57 PM PDT 24
Finished Jun 02 01:49:58 PM PDT 24
Peak memory 204152 kb
Host smart-ba4df70d-ae39-4688-9540-e7c8616a6f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695657449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3695657449
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3451087930
Short name T775
Test name
Test status
Simulation time 4952383841 ps
CPU time 18.67 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:50:14 PM PDT 24
Peak memory 233852 kb
Host smart-44bcb91a-2c5b-45e6-b697-e82bd3c8049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451087930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3451087930
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3566583280
Short name T413
Test name
Test status
Simulation time 18335478 ps
CPU time 0.8 seconds
Started Jun 02 01:49:53 PM PDT 24
Finished Jun 02 01:49:55 PM PDT 24
Peak memory 205808 kb
Host smart-b667c236-9859-4ffd-852c-723c82953f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566583280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3566583280
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.294464910
Short name T517
Test name
Test status
Simulation time 28365233643 ps
CPU time 107.09 seconds
Started Jun 02 01:49:49 PM PDT 24
Finished Jun 02 01:51:36 PM PDT 24
Peak memory 240532 kb
Host smart-b695c477-3bb1-4ffb-b81f-337515e3cbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294464910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.294464910
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4198244181
Short name T937
Test name
Test status
Simulation time 59255014567 ps
CPU time 293.53 seconds
Started Jun 02 01:49:50 PM PDT 24
Finished Jun 02 01:54:44 PM PDT 24
Peak memory 254720 kb
Host smart-b1908fe6-10ed-4f69-b8b5-ff4a04189b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198244181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4198244181
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.627074860
Short name T753
Test name
Test status
Simulation time 2793081110 ps
CPU time 50.61 seconds
Started Jun 02 01:49:54 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 248980 kb
Host smart-b2f3af5b-7068-4961-bd46-107daa141e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627074860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.627074860
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.42787196
Short name T793
Test name
Test status
Simulation time 13273796470 ps
CPU time 32.54 seconds
Started Jun 02 01:49:57 PM PDT 24
Finished Jun 02 01:50:30 PM PDT 24
Peak memory 240556 kb
Host smart-c6d3c767-d69e-4f69-b121-49813a66dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42787196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.42787196
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.46238149
Short name T665
Test name
Test status
Simulation time 335845972 ps
CPU time 2.83 seconds
Started Jun 02 01:49:51 PM PDT 24
Finished Jun 02 01:49:54 PM PDT 24
Peak memory 216264 kb
Host smart-635f284f-3ff9-4da4-be83-da02ff98a011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46238149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.46238149
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1423404417
Short name T75
Test name
Test status
Simulation time 323176039 ps
CPU time 5.03 seconds
Started Jun 02 01:49:51 PM PDT 24
Finished Jun 02 01:49:57 PM PDT 24
Peak memory 218136 kb
Host smart-12ec7392-b913-443f-8480-e00ac0002545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423404417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1423404417
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.265930661
Short name T863
Test name
Test status
Simulation time 284839319 ps
CPU time 3.7 seconds
Started Jun 02 01:49:50 PM PDT 24
Finished Jun 02 01:49:54 PM PDT 24
Peak memory 218044 kb
Host smart-0f60bc6f-8988-412d-ad7b-ef81627c0d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265930661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.265930661
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4168816077
Short name T800
Test name
Test status
Simulation time 1015745195 ps
CPU time 9.07 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:50:04 PM PDT 24
Peak memory 240488 kb
Host smart-34129472-498b-4352-a685-8dfe1e73869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168816077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4168816077
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3143645479
Short name T801
Test name
Test status
Simulation time 8496278588 ps
CPU time 10.58 seconds
Started Jun 02 01:49:56 PM PDT 24
Finished Jun 02 01:50:07 PM PDT 24
Peak memory 218796 kb
Host smart-72802482-2cac-4999-be3e-1071311899e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3143645479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3143645479
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2471402867
Short name T311
Test name
Test status
Simulation time 75110657756 ps
CPU time 191.86 seconds
Started Jun 02 01:49:50 PM PDT 24
Finished Jun 02 01:53:03 PM PDT 24
Peak memory 257016 kb
Host smart-2b7161c1-fe64-4f95-924f-c90e18f1cda4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471402867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2471402867
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4251457041
Short name T631
Test name
Test status
Simulation time 1976741501 ps
CPU time 25.55 seconds
Started Jun 02 01:49:50 PM PDT 24
Finished Jun 02 01:50:16 PM PDT 24
Peak memory 215864 kb
Host smart-2296f0f4-4218-402c-9786-d7d99935ae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251457041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4251457041
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3092605142
Short name T655
Test name
Test status
Simulation time 183914824 ps
CPU time 2.08 seconds
Started Jun 02 01:49:54 PM PDT 24
Finished Jun 02 01:49:56 PM PDT 24
Peak memory 215484 kb
Host smart-ebc58a63-0fb0-4a20-83c2-dc72820a2f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092605142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3092605142
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1695611502
Short name T889
Test name
Test status
Simulation time 288909943 ps
CPU time 1.32 seconds
Started Jun 02 01:49:51 PM PDT 24
Finished Jun 02 01:49:53 PM PDT 24
Peak memory 215904 kb
Host smart-d9348d8d-542d-4f29-916d-591f7e3c3e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695611502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1695611502
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3632390721
Short name T906
Test name
Test status
Simulation time 25446258 ps
CPU time 0.74 seconds
Started Jun 02 01:49:52 PM PDT 24
Finished Jun 02 01:49:53 PM PDT 24
Peak memory 205160 kb
Host smart-5fb6bd68-ae09-467f-8506-9b744ca5fcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632390721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3632390721
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2803511276
Short name T54
Test name
Test status
Simulation time 1271112239 ps
CPU time 6.43 seconds
Started Jun 02 01:49:51 PM PDT 24
Finished Jun 02 01:49:58 PM PDT 24
Peak memory 218816 kb
Host smart-70f2c454-4678-4645-ab66-3247ce319f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803511276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2803511276
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2816087562
Short name T526
Test name
Test status
Simulation time 23288569 ps
CPU time 0.75 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:49:56 PM PDT 24
Peak memory 204776 kb
Host smart-403e6f46-52e5-4cf0-b063-269f80a1e8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816087562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2816087562
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2774769995
Short name T259
Test name
Test status
Simulation time 86370909 ps
CPU time 2.96 seconds
Started Jun 02 01:49:54 PM PDT 24
Finished Jun 02 01:49:58 PM PDT 24
Peak memory 233520 kb
Host smart-4333bdf6-c856-48f3-b184-281c816a84e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774769995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2774769995
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2317484755
Short name T540
Test name
Test status
Simulation time 25587591 ps
CPU time 0.74 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:49:56 PM PDT 24
Peak memory 204844 kb
Host smart-961fc03a-6371-4a4c-970a-a754a9611913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317484755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2317484755
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3980307894
Short name T974
Test name
Test status
Simulation time 39241081555 ps
CPU time 49.86 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 249800 kb
Host smart-1dc3c8ce-2231-419c-a85f-8aaf07e7a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980307894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3980307894
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2261277066
Short name T403
Test name
Test status
Simulation time 5189406593 ps
CPU time 20.15 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:50:16 PM PDT 24
Peak memory 217204 kb
Host smart-aa8f5628-5896-4f27-8a9d-d4e9d70f8ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261277066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2261277066
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4289375761
Short name T728
Test name
Test status
Simulation time 7899264929 ps
CPU time 21.6 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:50:17 PM PDT 24
Peak memory 224196 kb
Host smart-e8227335-d697-4b97-953e-c2d36c3903d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289375761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4289375761
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3023970403
Short name T181
Test name
Test status
Simulation time 580979277 ps
CPU time 3.37 seconds
Started Jun 02 01:49:57 PM PDT 24
Finished Jun 02 01:50:01 PM PDT 24
Peak memory 218096 kb
Host smart-d8e6680c-70c5-46d1-9548-b67de54a8263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023970403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3023970403
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3040368222
Short name T855
Test name
Test status
Simulation time 510522747 ps
CPU time 8.43 seconds
Started Jun 02 01:49:56 PM PDT 24
Finished Jun 02 01:50:05 PM PDT 24
Peak memory 240476 kb
Host smart-3734b72b-4f31-49f1-91b1-6ec4086346a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040368222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3040368222
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1038201518
Short name T764
Test name
Test status
Simulation time 1256176432 ps
CPU time 4.46 seconds
Started Jun 02 01:49:55 PM PDT 24
Finished Jun 02 01:50:00 PM PDT 24
Peak memory 232768 kb
Host smart-4030aa56-8dd5-40f8-a345-93df06247b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038201518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1038201518
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2286685661
Short name T769
Test name
Test status
Simulation time 2446962916 ps
CPU time 9.64 seconds
Started Jun 02 01:49:57 PM PDT 24
Finished Jun 02 01:50:07 PM PDT 24
Peak memory 239716 kb
Host smart-ab180f8f-5c21-4b52-b90e-b7c2bfdbdc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286685661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2286685661
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3157461572
Short name T549
Test name
Test status
Simulation time 774525235 ps
CPU time 10.63 seconds
Started Jun 02 01:50:00 PM PDT 24
Finished Jun 02 01:50:12 PM PDT 24
Peak memory 218604 kb
Host smart-ae1567db-0a86-47b3-8b20-acd1d0a8f021
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3157461572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3157461572
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1770581792
Short name T964
Test name
Test status
Simulation time 5524838675 ps
CPU time 77.67 seconds
Started Jun 02 01:49:57 PM PDT 24
Finished Jun 02 01:51:15 PM PDT 24
Peak memory 248776 kb
Host smart-7f90e1a9-41fe-481b-a1e1-f19e712ff44f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770581792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1770581792
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4141504834
Short name T478
Test name
Test status
Simulation time 35759086 ps
CPU time 0.69 seconds
Started Jun 02 01:50:00 PM PDT 24
Finished Jun 02 01:50:01 PM PDT 24
Peak memory 204944 kb
Host smart-75c2e7e7-deb0-4355-9153-cd217a6f57d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141504834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4141504834
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2833985481
Short name T134
Test name
Test status
Simulation time 10097814532 ps
CPU time 6.32 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:50:08 PM PDT 24
Peak memory 215968 kb
Host smart-7e70f688-f8eb-4745-a83a-c3a861179ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833985481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2833985481
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.6777314
Short name T16
Test name
Test status
Simulation time 75281520 ps
CPU time 1.43 seconds
Started Jun 02 01:49:53 PM PDT 24
Finished Jun 02 01:49:55 PM PDT 24
Peak memory 215748 kb
Host smart-507b6da5-e495-4b9e-a86c-3a2e0e6fd8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6777314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.6777314
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2253401128
Short name T692
Test name
Test status
Simulation time 92119733 ps
CPU time 0.8 seconds
Started Jun 02 01:49:57 PM PDT 24
Finished Jun 02 01:49:58 PM PDT 24
Peak memory 205236 kb
Host smart-94d7fc3e-1a20-4e2f-b813-ee7f5e4dc77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253401128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2253401128
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2937224559
Short name T558
Test name
Test status
Simulation time 5739476677 ps
CPU time 3.48 seconds
Started Jun 02 01:50:00 PM PDT 24
Finished Jun 02 01:50:03 PM PDT 24
Peak memory 224100 kb
Host smart-cfd0b4bc-6ff0-46bf-96c7-65f6a4f29740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937224559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2937224559
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3792943069
Short name T453
Test name
Test status
Simulation time 51117282 ps
CPU time 0.74 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:04 PM PDT 24
Peak memory 204836 kb
Host smart-af82cd4d-d5c4-4524-a237-8bc50d9bbd4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792943069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3792943069
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1133160688
Short name T842
Test name
Test status
Simulation time 259122381 ps
CPU time 2.82 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:50:05 PM PDT 24
Peak memory 233948 kb
Host smart-a133e1cd-70f9-4f6d-94ad-527eaf84ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133160688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1133160688
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3603294636
Short name T419
Test name
Test status
Simulation time 57053178 ps
CPU time 0.74 seconds
Started Jun 02 01:49:57 PM PDT 24
Finished Jun 02 01:49:58 PM PDT 24
Peak memory 206204 kb
Host smart-11fe4964-973d-441e-938e-fbd3b4c92cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603294636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3603294636
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3547137781
Short name T183
Test name
Test status
Simulation time 19494369447 ps
CPU time 53.35 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:56 PM PDT 24
Peak memory 240536 kb
Host smart-f81a5583-b251-49e7-b7d7-b0cab9fb6818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547137781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3547137781
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3871205895
Short name T917
Test name
Test status
Simulation time 6277457471 ps
CPU time 93.45 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:51:35 PM PDT 24
Peak memory 251528 kb
Host smart-5a5942ae-c49a-4ace-9ad9-c83084fd4314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871205895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3871205895
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3850949681
Short name T642
Test name
Test status
Simulation time 13537991078 ps
CPU time 52.58 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:55 PM PDT 24
Peak memory 252772 kb
Host smart-fea199a5-a1ed-444b-a510-6cbb19f9b173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850949681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3850949681
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.221693334
Short name T331
Test name
Test status
Simulation time 1300413845 ps
CPU time 3.74 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:50:06 PM PDT 24
Peak memory 224104 kb
Host smart-a08b533a-39e2-43d4-9021-fcba659bcd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221693334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.221693334
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.375066545
Short name T200
Test name
Test status
Simulation time 861481607 ps
CPU time 10.3 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:13 PM PDT 24
Peak memory 219696 kb
Host smart-6b588ab7-90f5-4d1f-b3be-54ab9c8ae336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375066545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.375066545
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2959241685
Short name T789
Test name
Test status
Simulation time 11682330484 ps
CPU time 103.29 seconds
Started Jun 02 01:50:03 PM PDT 24
Finished Jun 02 01:51:47 PM PDT 24
Peak memory 245624 kb
Host smart-c1905ffc-d47e-4974-a430-5e3f04c22ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959241685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2959241685
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.202356240
Short name T12
Test name
Test status
Simulation time 198033794 ps
CPU time 2.68 seconds
Started Jun 02 01:49:56 PM PDT 24
Finished Jun 02 01:49:59 PM PDT 24
Peak memory 232276 kb
Host smart-ed9645df-7c65-4518-899d-81e9b997932f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202356240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.202356240
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1775313757
Short name T552
Test name
Test status
Simulation time 2249344176 ps
CPU time 14.18 seconds
Started Jun 02 01:50:04 PM PDT 24
Finished Jun 02 01:50:19 PM PDT 24
Peak memory 220176 kb
Host smart-cfabdf2e-bcd9-4999-8737-367668bbfb5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1775313757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1775313757
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1327882113
Short name T171
Test name
Test status
Simulation time 13319835124 ps
CPU time 112.37 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:51:54 PM PDT 24
Peak memory 248380 kb
Host smart-88f78ea0-3ae0-40a6-9ff7-1181e870d36c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327882113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1327882113
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.186017525
Short name T546
Test name
Test status
Simulation time 17692041176 ps
CPU time 49.77 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:50:51 PM PDT 24
Peak memory 216060 kb
Host smart-649d512e-697d-4543-9d0f-e34c6aad1203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186017525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.186017525
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3825132110
Short name T450
Test name
Test status
Simulation time 4806625984 ps
CPU time 15.91 seconds
Started Jun 02 01:49:56 PM PDT 24
Finished Jun 02 01:50:12 PM PDT 24
Peak memory 215808 kb
Host smart-620f47be-fcac-4111-a674-19f3518c89ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825132110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3825132110
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2036174104
Short name T896
Test name
Test status
Simulation time 1559415029 ps
CPU time 2.74 seconds
Started Jun 02 01:49:58 PM PDT 24
Finished Jun 02 01:50:01 PM PDT 24
Peak memory 215824 kb
Host smart-5cefd915-c938-42cd-8103-7b4588bf2c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036174104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2036174104
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1175152920
Short name T565
Test name
Test status
Simulation time 170597105 ps
CPU time 1.14 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:04 PM PDT 24
Peak memory 205364 kb
Host smart-1e8504aa-ea4a-435f-8423-6d7135cb83ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175152920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1175152920
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1498026947
Short name T734
Test name
Test status
Simulation time 291579868 ps
CPU time 3.49 seconds
Started Jun 02 01:50:03 PM PDT 24
Finished Jun 02 01:50:07 PM PDT 24
Peak memory 224220 kb
Host smart-6237e116-d287-4d7e-ae6d-ee551e814643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498026947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1498026947
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1860273217
Short name T663
Test name
Test status
Simulation time 41644790 ps
CPU time 0.74 seconds
Started Jun 02 01:50:05 PM PDT 24
Finished Jun 02 01:50:06 PM PDT 24
Peak memory 205200 kb
Host smart-72e205f3-7991-4eab-8ab8-a460ffa2f417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860273217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1860273217
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2595754326
Short name T407
Test name
Test status
Simulation time 515414936 ps
CPU time 6.31 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:50:08 PM PDT 24
Peak memory 235000 kb
Host smart-bdbae242-503b-4f34-b0ce-9590bd5d732e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595754326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2595754326
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1550122100
Short name T922
Test name
Test status
Simulation time 60826280 ps
CPU time 0.82 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:03 PM PDT 24
Peak memory 205164 kb
Host smart-af911cba-6144-4b89-90ca-1dd3f327d347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550122100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1550122100
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.478891479
Short name T765
Test name
Test status
Simulation time 23901318442 ps
CPU time 167.69 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:52:49 PM PDT 24
Peak memory 251908 kb
Host smart-d602d343-dc03-4efb-b857-262f71c3f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478891479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.478891479
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3021617836
Short name T283
Test name
Test status
Simulation time 56983804376 ps
CPU time 165.97 seconds
Started Jun 02 01:50:03 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 253900 kb
Host smart-e7ee56e0-6bee-469f-ad8e-a260c09e717c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021617836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3021617836
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2328186100
Short name T269
Test name
Test status
Simulation time 30992053383 ps
CPU time 360.01 seconds
Started Jun 02 01:50:03 PM PDT 24
Finished Jun 02 01:56:04 PM PDT 24
Peak memory 254944 kb
Host smart-8cd59dff-7e9b-48e1-a4d5-2fb91656fe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328186100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2328186100
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1664025383
Short name T239
Test name
Test status
Simulation time 2019606383 ps
CPU time 29.72 seconds
Started Jun 02 01:50:00 PM PDT 24
Finished Jun 02 01:50:31 PM PDT 24
Peak memory 248676 kb
Host smart-c386dfd8-de64-482d-93a5-3c6b541d060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664025383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1664025383
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2380872666
Short name T346
Test name
Test status
Simulation time 119101719 ps
CPU time 3.47 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:50:05 PM PDT 24
Peak memory 218184 kb
Host smart-3ae701b1-30fc-464b-ad2e-f8670c40f776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380872666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2380872666
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1244680943
Short name T848
Test name
Test status
Simulation time 15160657033 ps
CPU time 28.2 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:31 PM PDT 24
Peak memory 229112 kb
Host smart-706511bc-9c6e-4b6b-aec2-306a49463bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244680943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1244680943
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2338775179
Short name T270
Test name
Test status
Simulation time 94712740023 ps
CPU time 18.33 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:50:20 PM PDT 24
Peak memory 236032 kb
Host smart-9f0cd622-bc7d-45a8-add6-18bc7198125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338775179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2338775179
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2013809829
Short name T506
Test name
Test status
Simulation time 6249219221 ps
CPU time 20.51 seconds
Started Jun 02 01:50:04 PM PDT 24
Finished Jun 02 01:50:25 PM PDT 24
Peak memory 227428 kb
Host smart-aa230e92-655a-404f-a2aa-dd185fedbd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013809829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2013809829
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2690589213
Short name T579
Test name
Test status
Simulation time 903045727 ps
CPU time 3.51 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:06 PM PDT 24
Peak memory 220116 kb
Host smart-581599b8-5f3c-4343-b53b-b63d527f3b77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2690589213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2690589213
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.23560531
Short name T319
Test name
Test status
Simulation time 2561313748 ps
CPU time 33.99 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:37 PM PDT 24
Peak memory 224284 kb
Host smart-2f793aac-a80c-48fa-8352-9a04f3e54b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23560531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress
_all.23560531
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.687881586
Short name T590
Test name
Test status
Simulation time 32572243 ps
CPU time 0.72 seconds
Started Jun 02 01:50:05 PM PDT 24
Finished Jun 02 01:50:06 PM PDT 24
Peak memory 204984 kb
Host smart-4c65e739-4653-4f34-a906-7d3338fb3fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687881586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.687881586
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.759853155
Short name T707
Test name
Test status
Simulation time 43907452 ps
CPU time 1.12 seconds
Started Jun 02 01:50:04 PM PDT 24
Finished Jun 02 01:50:05 PM PDT 24
Peak memory 206228 kb
Host smart-8d77cde5-4a51-47a6-b4b9-0faf9ac0787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759853155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.759853155
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.859997008
Short name T392
Test name
Test status
Simulation time 98150450 ps
CPU time 1.06 seconds
Started Jun 02 01:50:01 PM PDT 24
Finished Jun 02 01:50:03 PM PDT 24
Peak memory 207376 kb
Host smart-de781bdc-629c-4fb7-8d76-a38aa62b8d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859997008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.859997008
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3665867629
Short name T349
Test name
Test status
Simulation time 67732811 ps
CPU time 0.94 seconds
Started Jun 02 01:50:02 PM PDT 24
Finished Jun 02 01:50:04 PM PDT 24
Peak memory 205584 kb
Host smart-651b5ee8-2885-400c-b9b8-6e6b33cf98d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665867629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3665867629
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1821160441
Short name T226
Test name
Test status
Simulation time 3494223387 ps
CPU time 12.99 seconds
Started Jun 02 01:50:00 PM PDT 24
Finished Jun 02 01:50:13 PM PDT 24
Peak memory 218460 kb
Host smart-672721fe-3789-41b8-8802-dbede955b95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821160441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1821160441
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2178613096
Short name T904
Test name
Test status
Simulation time 13494898 ps
CPU time 0.74 seconds
Started Jun 02 01:50:08 PM PDT 24
Finished Jun 02 01:50:09 PM PDT 24
Peak memory 204856 kb
Host smart-b0a1a638-2d62-4ff5-8fd8-53e8b92bd13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178613096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2178613096
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.756616998
Short name T760
Test name
Test status
Simulation time 778546617 ps
CPU time 4.18 seconds
Started Jun 02 01:50:07 PM PDT 24
Finished Jun 02 01:50:12 PM PDT 24
Peak memory 233636 kb
Host smart-af7fb58e-4e4d-4b0a-ba95-7169b992394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756616998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.756616998
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3858329532
Short name T973
Test name
Test status
Simulation time 58625161 ps
CPU time 0.78 seconds
Started Jun 02 01:50:05 PM PDT 24
Finished Jun 02 01:50:07 PM PDT 24
Peak memory 204836 kb
Host smart-897038b7-29f8-4164-a854-b79633a6644d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858329532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3858329532
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2215357595
Short name T193
Test name
Test status
Simulation time 978490735 ps
CPU time 9.96 seconds
Started Jun 02 01:50:06 PM PDT 24
Finished Jun 02 01:50:16 PM PDT 24
Peak memory 224068 kb
Host smart-f6b95a09-acbe-4979-9d59-7317aa328887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215357595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2215357595
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2956238222
Short name T170
Test name
Test status
Simulation time 3890891616 ps
CPU time 78.48 seconds
Started Jun 02 01:50:08 PM PDT 24
Finished Jun 02 01:51:26 PM PDT 24
Peak memory 248816 kb
Host smart-6556de68-276a-47e7-a7c6-5c5fbea81624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956238222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2956238222
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1335898456
Short name T893
Test name
Test status
Simulation time 5242267023 ps
CPU time 6.53 seconds
Started Jun 02 01:50:06 PM PDT 24
Finished Jun 02 01:50:13 PM PDT 24
Peak memory 224124 kb
Host smart-6f2c12b7-351b-4ffc-a5ca-7d290a725f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335898456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1335898456
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1376868059
Short name T871
Test name
Test status
Simulation time 6183706623 ps
CPU time 34.41 seconds
Started Jun 02 01:50:13 PM PDT 24
Finished Jun 02 01:50:48 PM PDT 24
Peak memory 238728 kb
Host smart-0d79a653-4682-4117-9611-93a3317c8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376868059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1376868059
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2620199938
Short name T308
Test name
Test status
Simulation time 5094329242 ps
CPU time 11.05 seconds
Started Jun 02 01:50:08 PM PDT 24
Finished Jun 02 01:50:19 PM PDT 24
Peak memory 235036 kb
Host smart-4d5432bd-4e07-4b67-a2ae-469637e5a576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620199938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2620199938
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.38989634
Short name T690
Test name
Test status
Simulation time 19305206734 ps
CPU time 14.65 seconds
Started Jun 02 01:50:08 PM PDT 24
Finished Jun 02 01:50:23 PM PDT 24
Peak memory 232892 kb
Host smart-d4130be2-1190-4e85-8f5a-429a95e3439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38989634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.38989634
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1851854342
Short name T431
Test name
Test status
Simulation time 473517550 ps
CPU time 7.17 seconds
Started Jun 02 01:50:07 PM PDT 24
Finished Jun 02 01:50:14 PM PDT 24
Peak memory 222464 kb
Host smart-6ee4b6b3-9ef7-4154-9073-8e2e6249cab7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1851854342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1851854342
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3613217223
Short name T333
Test name
Test status
Simulation time 4660945948 ps
CPU time 27.67 seconds
Started Jun 02 01:50:05 PM PDT 24
Finished Jun 02 01:50:33 PM PDT 24
Peak memory 215896 kb
Host smart-911868de-9d5a-4635-8f3b-58d35c49ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613217223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3613217223
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.991087966
Short name T578
Test name
Test status
Simulation time 2745075928 ps
CPU time 8.24 seconds
Started Jun 02 01:50:09 PM PDT 24
Finished Jun 02 01:50:18 PM PDT 24
Peak memory 215788 kb
Host smart-3c2fe499-ebce-47ee-91b6-d85dae9166c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991087966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.991087966
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.506391951
Short name T386
Test name
Test status
Simulation time 510513598 ps
CPU time 2.01 seconds
Started Jun 02 01:50:07 PM PDT 24
Finished Jun 02 01:50:09 PM PDT 24
Peak memory 215792 kb
Host smart-9a64e7b8-e85b-46ab-b1a4-d6a1d875d74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506391951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.506391951
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.417318451
Short name T808
Test name
Test status
Simulation time 57522514 ps
CPU time 0.86 seconds
Started Jun 02 01:50:06 PM PDT 24
Finished Jun 02 01:50:07 PM PDT 24
Peak memory 205456 kb
Host smart-4f748296-fb51-4160-9693-2a05c772d65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417318451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.417318451
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.450932094
Short name T120
Test name
Test status
Simulation time 556650468 ps
CPU time 2.29 seconds
Started Jun 02 01:50:09 PM PDT 24
Finished Jun 02 01:50:12 PM PDT 24
Peak memory 215672 kb
Host smart-34a45117-69e5-43c0-b154-24b4fcdf0e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450932094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.450932094
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3031302546
Short name T63
Test name
Test status
Simulation time 44446613 ps
CPU time 0.71 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:50:12 PM PDT 24
Peak memory 204816 kb
Host smart-1cda9cc0-d583-463a-acc1-d1b307f53062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031302546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3031302546
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3701393788
Short name T434
Test name
Test status
Simulation time 327877019 ps
CPU time 3.4 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:50:15 PM PDT 24
Peak memory 233436 kb
Host smart-7dc6415a-bb55-4864-b731-693ab7e1761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701393788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3701393788
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3946508389
Short name T569
Test name
Test status
Simulation time 49660830 ps
CPU time 0.78 seconds
Started Jun 02 01:50:06 PM PDT 24
Finished Jun 02 01:50:08 PM PDT 24
Peak memory 205840 kb
Host smart-8ec2bd12-5d80-4d21-91ff-e65653127d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946508389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3946508389
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1765929539
Short name T776
Test name
Test status
Simulation time 14014667776 ps
CPU time 63.33 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:51:19 PM PDT 24
Peak memory 236800 kb
Host smart-a921c56f-8656-43b1-86b8-0e1684994770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765929539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1765929539
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.917114192
Short name T214
Test name
Test status
Simulation time 30336096238 ps
CPU time 156.12 seconds
Started Jun 02 01:50:13 PM PDT 24
Finished Jun 02 01:52:50 PM PDT 24
Peak memory 249568 kb
Host smart-730bfa21-deff-495d-898e-973941ad0e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917114192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.917114192
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4281943118
Short name T487
Test name
Test status
Simulation time 12420084913 ps
CPU time 105.01 seconds
Started Jun 02 01:50:10 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 256980 kb
Host smart-3c3f3586-95e5-4629-a1c5-bab761241afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281943118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4281943118
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3682652483
Short name T826
Test name
Test status
Simulation time 64126817 ps
CPU time 2.34 seconds
Started Jun 02 01:50:08 PM PDT 24
Finished Jun 02 01:50:11 PM PDT 24
Peak memory 224124 kb
Host smart-0879e9fe-eb59-4c97-badf-a81bc682af56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682652483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3682652483
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1058787843
Short name T238
Test name
Test status
Simulation time 587714978 ps
CPU time 3.94 seconds
Started Jun 02 01:50:06 PM PDT 24
Finished Jun 02 01:50:10 PM PDT 24
Peak memory 218056 kb
Host smart-8aa9fb5f-38cf-44bf-b8af-a58610a0ed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058787843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1058787843
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.342359426
Short name T201
Test name
Test status
Simulation time 1970529520 ps
CPU time 3.96 seconds
Started Jun 02 01:50:07 PM PDT 24
Finished Jun 02 01:50:11 PM PDT 24
Peak memory 232264 kb
Host smart-89301763-9b74-40ee-b04a-786614f1de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342359426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.342359426
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1639172982
Short name T302
Test name
Test status
Simulation time 2534636982 ps
CPU time 9.74 seconds
Started Jun 02 01:50:09 PM PDT 24
Finished Jun 02 01:50:19 PM PDT 24
Peak memory 231276 kb
Host smart-506636d0-a5f9-449f-9330-9ea203b76067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639172982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1639172982
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2409656447
Short name T495
Test name
Test status
Simulation time 162067323 ps
CPU time 3.13 seconds
Started Jun 02 01:50:07 PM PDT 24
Finished Jun 02 01:50:11 PM PDT 24
Peak memory 232880 kb
Host smart-88b76bb0-bbf6-432f-98ee-7752e28bdb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409656447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2409656447
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2711164240
Short name T457
Test name
Test status
Simulation time 624517263 ps
CPU time 5.88 seconds
Started Jun 02 01:50:07 PM PDT 24
Finished Jun 02 01:50:13 PM PDT 24
Peak memory 219824 kb
Host smart-a2486c41-f5a0-49cf-88ec-4b4ac25726c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2711164240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2711164240
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.838526675
Short name T152
Test name
Test status
Simulation time 8953632841 ps
CPU time 146.17 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:52:38 PM PDT 24
Peak memory 264984 kb
Host smart-f47560ab-4c61-41eb-bfc1-c60229c919a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838526675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.838526675
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1651610672
Short name T852
Test name
Test status
Simulation time 7613033518 ps
CPU time 42 seconds
Started Jun 02 01:50:07 PM PDT 24
Finished Jun 02 01:50:50 PM PDT 24
Peak memory 215884 kb
Host smart-9651b546-ff2b-4d2d-ad76-736b7e93065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651610672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1651610672
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1573124919
Short name T844
Test name
Test status
Simulation time 2307105662 ps
CPU time 6.37 seconds
Started Jun 02 01:50:08 PM PDT 24
Finished Jun 02 01:50:14 PM PDT 24
Peak memory 215868 kb
Host smart-73707528-a4b3-4934-968d-5308c5471a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573124919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1573124919
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3655650690
Short name T782
Test name
Test status
Simulation time 464692914 ps
CPU time 2.7 seconds
Started Jun 02 01:50:06 PM PDT 24
Finished Jun 02 01:50:09 PM PDT 24
Peak memory 215880 kb
Host smart-a0a5d819-a848-4482-980f-857fecea0785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655650690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3655650690
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1708093449
Short name T424
Test name
Test status
Simulation time 11119752 ps
CPU time 0.69 seconds
Started Jun 02 01:50:06 PM PDT 24
Finished Jun 02 01:50:07 PM PDT 24
Peak memory 204844 kb
Host smart-f4be2d53-4be3-4422-8df1-ac99f4736b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708093449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1708093449
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2538755510
Short name T643
Test name
Test status
Simulation time 329467460 ps
CPU time 3.69 seconds
Started Jun 02 01:50:07 PM PDT 24
Finished Jun 02 01:50:11 PM PDT 24
Peak memory 233320 kb
Host smart-8c520a6c-4934-4fae-b066-d007145418bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538755510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2538755510
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2052670945
Short name T65
Test name
Test status
Simulation time 24265514 ps
CPU time 0.69 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:50:13 PM PDT 24
Peak memory 204768 kb
Host smart-8726ebde-90ac-4c92-ae82-3f698718ad42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052670945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2052670945
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2220058557
Short name T944
Test name
Test status
Simulation time 2346754853 ps
CPU time 16.69 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:50:32 PM PDT 24
Peak memory 234872 kb
Host smart-2c7fdf54-7ca7-4630-9326-f2e89b9e3e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220058557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2220058557
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.517138612
Short name T342
Test name
Test status
Simulation time 30720517 ps
CPU time 0.78 seconds
Started Jun 02 01:50:13 PM PDT 24
Finished Jun 02 01:50:15 PM PDT 24
Peak memory 205836 kb
Host smart-4738ac82-7733-46c6-a0b8-f96344feaa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517138612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.517138612
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1469697685
Short name T571
Test name
Test status
Simulation time 179869516308 ps
CPU time 282.64 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:54:55 PM PDT 24
Peak memory 257024 kb
Host smart-d5b394d1-d518-4b7d-aa61-1b7da34d6fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469697685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1469697685
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3666448746
Short name T573
Test name
Test status
Simulation time 75119803611 ps
CPU time 101.28 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:51:53 PM PDT 24
Peak memory 249128 kb
Host smart-8787c599-e9cb-43a5-9d99-f1483da17ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666448746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3666448746
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3331974284
Short name T647
Test name
Test status
Simulation time 150079538 ps
CPU time 2.49 seconds
Started Jun 02 01:50:13 PM PDT 24
Finished Jun 02 01:50:15 PM PDT 24
Peak memory 218272 kb
Host smart-2f3a5e8c-3e3e-4784-8b62-1f11d58e4946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331974284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3331974284
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2044010633
Short name T262
Test name
Test status
Simulation time 342049589 ps
CPU time 2.25 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:50:13 PM PDT 24
Peak memory 218088 kb
Host smart-333a3bf8-dbf5-4b7f-89b5-d8d6378c3824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044010633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2044010633
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2029381166
Short name T240
Test name
Test status
Simulation time 7698837961 ps
CPU time 75.58 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:51:28 PM PDT 24
Peak memory 246112 kb
Host smart-3e3e16d1-651c-40ae-af96-c87c437120e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029381166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2029381166
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2097784537
Short name T34
Test name
Test status
Simulation time 27738250216 ps
CPU time 17.13 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:50:30 PM PDT 24
Peak memory 222948 kb
Host smart-4964ea94-28ac-494a-a583-7c191adcfa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097784537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2097784537
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3102265080
Short name T894
Test name
Test status
Simulation time 134206684 ps
CPU time 2.33 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:50:18 PM PDT 24
Peak memory 232312 kb
Host smart-43054aec-ca98-426c-90b5-b5393371c05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102265080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3102265080
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.865892910
Short name T395
Test name
Test status
Simulation time 1487492775 ps
CPU time 10.67 seconds
Started Jun 02 01:50:10 PM PDT 24
Finished Jun 02 01:50:21 PM PDT 24
Peak memory 219688 kb
Host smart-12387483-753d-4229-9030-2e99e63b4209
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=865892910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.865892910
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3382735587
Short name T504
Test name
Test status
Simulation time 3804690386 ps
CPU time 46.13 seconds
Started Jun 02 01:50:13 PM PDT 24
Finished Jun 02 01:51:00 PM PDT 24
Peak memory 238788 kb
Host smart-a102e8bb-cea0-4581-bcc5-9749420fa224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382735587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3382735587
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3586698749
Short name T53
Test name
Test status
Simulation time 11008788760 ps
CPU time 20.42 seconds
Started Jun 02 01:50:14 PM PDT 24
Finished Jun 02 01:50:34 PM PDT 24
Peak memory 215960 kb
Host smart-9b2e4d65-31b1-47c4-b859-2e3d9c87a63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586698749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3586698749
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4085194579
Short name T656
Test name
Test status
Simulation time 3132670543 ps
CPU time 4.73 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:50:16 PM PDT 24
Peak memory 215840 kb
Host smart-9cb23ec3-c612-47f3-a1ab-d4d3fb9f0fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085194579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4085194579
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.957917132
Short name T356
Test name
Test status
Simulation time 112695387 ps
CPU time 3.13 seconds
Started Jun 02 01:50:13 PM PDT 24
Finished Jun 02 01:50:16 PM PDT 24
Peak memory 215836 kb
Host smart-0901c9f1-6e24-4341-acad-0f3e151d2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957917132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.957917132
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1555695182
Short name T866
Test name
Test status
Simulation time 42417412 ps
CPU time 0.78 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:50:16 PM PDT 24
Peak memory 205508 kb
Host smart-8b90c1a9-d5b0-40d3-a546-63dbde6db87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555695182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1555695182
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3011321813
Short name T288
Test name
Test status
Simulation time 559339339 ps
CPU time 6.05 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:50:18 PM PDT 24
Peak memory 233760 kb
Host smart-21cde1ab-e8e0-45af-86e8-62a6d915d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011321813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3011321813
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1246437952
Short name T461
Test name
Test status
Simulation time 60736500 ps
CPU time 0.73 seconds
Started Jun 02 01:48:55 PM PDT 24
Finished Jun 02 01:48:56 PM PDT 24
Peak memory 204968 kb
Host smart-3d9e3111-f495-473f-89f5-44082ea3581e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246437952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
246437952
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1197349136
Short name T256
Test name
Test status
Simulation time 171294254 ps
CPU time 3.29 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:52 PM PDT 24
Peak memory 218256 kb
Host smart-2e2628e3-ef7b-4457-8b79-fe742e90b539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197349136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1197349136
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.621821451
Short name T135
Test name
Test status
Simulation time 17630727 ps
CPU time 0.77 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:48:50 PM PDT 24
Peak memory 205164 kb
Host smart-e2f2798c-c7a4-40e4-8f37-21d81f089169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621821451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.621821451
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3573248305
Short name T682
Test name
Test status
Simulation time 6689321701 ps
CPU time 46.79 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:49:36 PM PDT 24
Peak memory 253936 kb
Host smart-ac3808c7-a940-411b-811d-6251c20ec703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573248305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3573248305
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2474885608
Short name T905
Test name
Test status
Simulation time 12492403040 ps
CPU time 170.15 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 249032 kb
Host smart-4f786404-f9e6-42ea-8b48-2f6783cd9cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474885608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2474885608
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1390052801
Short name T950
Test name
Test status
Simulation time 27471197410 ps
CPU time 284.64 seconds
Started Jun 02 01:48:44 PM PDT 24
Finished Jun 02 01:53:29 PM PDT 24
Peak memory 258244 kb
Host smart-32344c20-df49-49ed-9e14-8d801744014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390052801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1390052801
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4278554934
Short name T471
Test name
Test status
Simulation time 11313330525 ps
CPU time 44.83 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:49:34 PM PDT 24
Peak memory 232376 kb
Host smart-2830c030-dd35-40f5-a30e-9c6e4bd7c21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278554934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4278554934
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3760420346
Short name T559
Test name
Test status
Simulation time 16913751844 ps
CPU time 15.36 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:49:04 PM PDT 24
Peak memory 219076 kb
Host smart-4adc4096-e9ae-4b26-bb4f-c50faad7a7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760420346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3760420346
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.425436651
Short name T4
Test name
Test status
Simulation time 7474638347 ps
CPU time 26.77 seconds
Started Jun 02 01:48:45 PM PDT 24
Finished Jun 02 01:49:13 PM PDT 24
Peak memory 238672 kb
Host smart-6093165d-7055-471e-b863-d52f954bc8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425436651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.425436651
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.4289474055
Short name T385
Test name
Test status
Simulation time 64168305 ps
CPU time 1 seconds
Started Jun 02 01:48:44 PM PDT 24
Finished Jun 02 01:48:45 PM PDT 24
Peak memory 216132 kb
Host smart-867843db-7971-4369-9c46-fc5197f20e4d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289474055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.4289474055
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1678313241
Short name T644
Test name
Test status
Simulation time 6793250225 ps
CPU time 16.15 seconds
Started Jun 02 01:48:55 PM PDT 24
Finished Jun 02 01:49:12 PM PDT 24
Peak memory 224104 kb
Host smart-c0fc5153-253a-4eb3-80bb-5b67202310a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678313241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1678313241
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.429224729
Short name T281
Test name
Test status
Simulation time 2173256444 ps
CPU time 11.14 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:49:03 PM PDT 24
Peak memory 233192 kb
Host smart-32227297-77f5-4117-9894-5c548fd5d82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429224729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.429224729
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2049938796
Short name T716
Test name
Test status
Simulation time 604143109 ps
CPU time 3.52 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:52 PM PDT 24
Peak memory 219892 kb
Host smart-23d9433f-22b5-4b17-af47-5cc1d96ef46d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2049938796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2049938796
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1786820778
Short name T877
Test name
Test status
Simulation time 214016707 ps
CPU time 1.06 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:50 PM PDT 24
Peak memory 206516 kb
Host smart-dc8e00fc-6e3b-4fec-a39f-15995f0cd62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786820778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1786820778
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.645079431
Short name T336
Test name
Test status
Simulation time 2503334026 ps
CPU time 19.61 seconds
Started Jun 02 01:48:45 PM PDT 24
Finished Jun 02 01:49:05 PM PDT 24
Peak memory 215940 kb
Host smart-a3bc6d71-1bf5-4fbb-b390-f08401f33d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645079431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.645079431
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3438251674
Short name T348
Test name
Test status
Simulation time 8048405877 ps
CPU time 18.9 seconds
Started Jun 02 01:48:43 PM PDT 24
Finished Jun 02 01:49:03 PM PDT 24
Peak memory 215820 kb
Host smart-97efec70-a62e-40cc-8f1f-26a6de669494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438251674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3438251674
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.423596881
Short name T447
Test name
Test status
Simulation time 13360101 ps
CPU time 0.69 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:48 PM PDT 24
Peak memory 204852 kb
Host smart-e4790b55-298c-4ff2-b5c0-74bb9622798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423596881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.423596881
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3000583
Short name T674
Test name
Test status
Simulation time 29055643 ps
CPU time 0.84 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:48:53 PM PDT 24
Peak memory 205256 kb
Host smart-6860d41f-3112-4d04-92e1-8c5a9b6e0894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3000583
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.589936245
Short name T939
Test name
Test status
Simulation time 1967709683 ps
CPU time 4.41 seconds
Started Jun 02 01:48:42 PM PDT 24
Finished Jun 02 01:48:47 PM PDT 24
Peak memory 233732 kb
Host smart-dd62ce3f-24a4-449e-8768-a0d19104ed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589936245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.589936245
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1597723646
Short name T406
Test name
Test status
Simulation time 19702860 ps
CPU time 0.71 seconds
Started Jun 02 01:50:16 PM PDT 24
Finished Jun 02 01:50:18 PM PDT 24
Peak memory 204824 kb
Host smart-edf3d98b-3e6c-4d23-bd07-53451879bb5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597723646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1597723646
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1984376818
Short name T260
Test name
Test status
Simulation time 5635940915 ps
CPU time 13.75 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:50:26 PM PDT 24
Peak memory 233508 kb
Host smart-2eb9698c-d0d3-42d9-8951-a976cc32c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984376818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1984376818
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1103711659
Short name T798
Test name
Test status
Simulation time 83456732 ps
CPU time 0.77 seconds
Started Jun 02 01:50:10 PM PDT 24
Finished Jun 02 01:50:11 PM PDT 24
Peak memory 205172 kb
Host smart-14c5ce78-d135-4daa-b1c9-f7c2cf44c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103711659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1103711659
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.917896512
Short name T673
Test name
Test status
Simulation time 1100101980 ps
CPU time 14.33 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:50:30 PM PDT 24
Peak memory 236784 kb
Host smart-8bec0386-ca89-4c03-972e-335e92aea2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917896512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.917896512
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2233627938
Short name T807
Test name
Test status
Simulation time 1708393100 ps
CPU time 33.24 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:56 PM PDT 24
Peak memory 248712 kb
Host smart-cb14f376-3583-4e69-a1a0-74a03632532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233627938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2233627938
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3254905578
Short name T40
Test name
Test status
Simulation time 12025580920 ps
CPU time 37.42 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:50:50 PM PDT 24
Peak memory 239528 kb
Host smart-4c808cf2-bb78-45f9-8021-eada3c1ede87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254905578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3254905578
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2522617303
Short name T496
Test name
Test status
Simulation time 1239015138 ps
CPU time 11.22 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:50:23 PM PDT 24
Peak memory 233644 kb
Host smart-f21233ad-552f-4565-9a20-6f29638142ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522617303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2522617303
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.771890480
Short name T671
Test name
Test status
Simulation time 9075588385 ps
CPU time 34.2 seconds
Started Jun 02 01:50:13 PM PDT 24
Finished Jun 02 01:50:48 PM PDT 24
Peak memory 230816 kb
Host smart-06aa7eae-5dac-404a-87bd-b928369fee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771890480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.771890480
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3892741370
Short name T11
Test name
Test status
Simulation time 300369830 ps
CPU time 5.6 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:50:18 PM PDT 24
Peak memory 222480 kb
Host smart-cffa7a99-ada4-469a-a6c6-6521ef7df380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892741370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3892741370
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.710918059
Short name T469
Test name
Test status
Simulation time 124913259 ps
CPU time 2.45 seconds
Started Jun 02 01:50:13 PM PDT 24
Finished Jun 02 01:50:16 PM PDT 24
Peak memory 232308 kb
Host smart-d3e9c054-cda6-464f-b219-d4a58e00ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710918059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.710918059
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2300336552
Short name T79
Test name
Test status
Simulation time 2680290164 ps
CPU time 8.31 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:50:21 PM PDT 24
Peak memory 218676 kb
Host smart-da941f4c-d29d-4e1e-b9de-b7c5a75af297
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2300336552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2300336552
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.736275211
Short name T881
Test name
Test status
Simulation time 182191970 ps
CPU time 1.39 seconds
Started Jun 02 01:50:21 PM PDT 24
Finished Jun 02 01:50:23 PM PDT 24
Peak memory 207200 kb
Host smart-8a91e0d0-c82c-4ef2-9c54-29a6ef507ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736275211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.736275211
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2674263001
Short name T619
Test name
Test status
Simulation time 2070035022 ps
CPU time 8.54 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:50:24 PM PDT 24
Peak memory 215856 kb
Host smart-c0038d8b-eef4-4080-9242-60243208d63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674263001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2674263001
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3751575115
Short name T662
Test name
Test status
Simulation time 9555810412 ps
CPU time 8.47 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:50:24 PM PDT 24
Peak memory 216140 kb
Host smart-0ede352b-609a-4076-b2aa-1e045502dbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751575115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3751575115
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1087849928
Short name T771
Test name
Test status
Simulation time 173947707 ps
CPU time 2.74 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:50:14 PM PDT 24
Peak memory 215824 kb
Host smart-4e9d1aad-00a7-4968-a8bc-55ee013e4261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087849928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1087849928
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3466775660
Short name T452
Test name
Test status
Simulation time 16188107 ps
CPU time 0.68 seconds
Started Jun 02 01:50:12 PM PDT 24
Finished Jun 02 01:50:13 PM PDT 24
Peak memory 204852 kb
Host smart-2451410d-b3f9-4bdc-ad25-9f7f75f86a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466775660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3466775660
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3783805490
Short name T833
Test name
Test status
Simulation time 681089472 ps
CPU time 2.95 seconds
Started Jun 02 01:50:11 PM PDT 24
Finished Jun 02 01:50:15 PM PDT 24
Peak memory 218280 kb
Host smart-43f5f786-1561-4859-9025-57662f1435ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783805490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3783805490
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3866940461
Short name T885
Test name
Test status
Simulation time 13218034 ps
CPU time 0.75 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:24 PM PDT 24
Peak memory 204148 kb
Host smart-27061779-7c60-4625-b311-5a48c388a8e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866940461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3866940461
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.236992854
Short name T648
Test name
Test status
Simulation time 144620135 ps
CPU time 2.01 seconds
Started Jun 02 01:50:14 PM PDT 24
Finished Jun 02 01:50:17 PM PDT 24
Peak memory 215664 kb
Host smart-1e60ec91-b066-4592-966e-6340df80f2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236992854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.236992854
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1176336518
Short name T51
Test name
Test status
Simulation time 16587783 ps
CPU time 0.74 seconds
Started Jun 02 01:50:19 PM PDT 24
Finished Jun 02 01:50:20 PM PDT 24
Peak memory 204760 kb
Host smart-0fbea289-c56e-4f78-9cb0-40282cab9b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176336518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1176336518
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.301811
Short name T681
Test name
Test status
Simulation time 45215484047 ps
CPU time 146.65 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:52:43 PM PDT 24
Peak memory 250008 kb
Host smart-944590f9-0f78-40a3-94c6-5030b9cae1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.301811
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1418017138
Short name T300
Test name
Test status
Simulation time 98930552818 ps
CPU time 275.88 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:54:58 PM PDT 24
Peak memory 253284 kb
Host smart-e8e090b8-77b1-4dc4-9ac8-64f410bbe474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418017138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1418017138
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.334694534
Short name T31
Test name
Test status
Simulation time 139531117825 ps
CPU time 357.8 seconds
Started Jun 02 01:50:24 PM PDT 24
Finished Jun 02 01:56:23 PM PDT 24
Peak memory 255304 kb
Host smart-fe0f5339-2d7c-450c-a358-1550778f7482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334694534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.334694534
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.731946619
Short name T529
Test name
Test status
Simulation time 204427141 ps
CPU time 9.58 seconds
Started Jun 02 01:50:16 PM PDT 24
Finished Jun 02 01:50:26 PM PDT 24
Peak memory 232092 kb
Host smart-90fc2883-d49f-4a9c-a9eb-598450a63a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731946619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.731946619
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2844238474
Short name T735
Test name
Test status
Simulation time 1532420741 ps
CPU time 14.7 seconds
Started Jun 02 01:50:14 PM PDT 24
Finished Jun 02 01:50:29 PM PDT 24
Peak memory 233368 kb
Host smart-c4dcb5bf-892f-4f31-bda7-5057c1313857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844238474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2844238474
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1969608604
Short name T191
Test name
Test status
Simulation time 1890516449 ps
CPU time 28.92 seconds
Started Jun 02 01:50:16 PM PDT 24
Finished Jun 02 01:50:46 PM PDT 24
Peak memory 240508 kb
Host smart-46ffdd7b-e3cd-45d5-aab8-06abf6b75fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969608604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1969608604
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2311643326
Short name T459
Test name
Test status
Simulation time 597399578 ps
CPU time 9.04 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:31 PM PDT 24
Peak memory 230616 kb
Host smart-9bc72e8a-d45b-4e75-a2ec-209e2158fe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311643326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2311643326
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1707869934
Short name T199
Test name
Test status
Simulation time 2000786442 ps
CPU time 8.13 seconds
Started Jun 02 01:50:16 PM PDT 24
Finished Jun 02 01:50:25 PM PDT 24
Peak memory 219304 kb
Host smart-0b8300de-ac39-407b-b562-8dc3b0231388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707869934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1707869934
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3624717391
Short name T538
Test name
Test status
Simulation time 4139011536 ps
CPU time 16.69 seconds
Started Jun 02 01:50:23 PM PDT 24
Finished Jun 02 01:50:40 PM PDT 24
Peak memory 220112 kb
Host smart-5e6ec7f5-0a71-4032-9c2f-793f51bf67f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3624717391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3624717391
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3562140409
Short name T891
Test name
Test status
Simulation time 32821809389 ps
CPU time 24.12 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:47 PM PDT 24
Peak memory 215932 kb
Host smart-2ba988c8-9cf4-4d30-9704-bd56c585ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562140409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3562140409
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4159530751
Short name T443
Test name
Test status
Simulation time 4499308959 ps
CPU time 3.39 seconds
Started Jun 02 01:50:21 PM PDT 24
Finished Jun 02 01:50:25 PM PDT 24
Peak memory 215884 kb
Host smart-3f188336-e911-4088-9678-dfc5a42a2f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159530751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4159530751
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4140256904
Short name T412
Test name
Test status
Simulation time 170699078 ps
CPU time 1.06 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:24 PM PDT 24
Peak memory 207432 kb
Host smart-51ecf106-8485-4db0-9399-bc975c6269f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140256904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4140256904
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.645964735
Short name T512
Test name
Test status
Simulation time 52049927 ps
CPU time 0.86 seconds
Started Jun 02 01:50:21 PM PDT 24
Finished Jun 02 01:50:22 PM PDT 24
Peak memory 205220 kb
Host smart-7c4034b5-d610-4176-8f45-89b23f276152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645964735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.645964735
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3183080354
Short name T368
Test name
Test status
Simulation time 445361671 ps
CPU time 2.54 seconds
Started Jun 02 01:50:15 PM PDT 24
Finished Jun 02 01:50:18 PM PDT 24
Peak memory 211788 kb
Host smart-60a47c4c-1c03-4f1a-ae08-60ff6edeeeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183080354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3183080354
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3252555859
Short name T719
Test name
Test status
Simulation time 90450928 ps
CPU time 0.73 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:23 PM PDT 24
Peak memory 204216 kb
Host smart-3390d2a6-d289-4b1c-8ac1-34a5261d344e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252555859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3252555859
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.175426874
Short name T723
Test name
Test status
Simulation time 447090502 ps
CPU time 6.31 seconds
Started Jun 02 01:50:23 PM PDT 24
Finished Jun 02 01:50:29 PM PDT 24
Peak memory 233640 kb
Host smart-1cca4922-0bfa-4cc3-bdaa-591a670decdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175426874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.175426874
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.484157992
Short name T586
Test name
Test status
Simulation time 65563289 ps
CPU time 0.75 seconds
Started Jun 02 01:50:16 PM PDT 24
Finished Jun 02 01:50:18 PM PDT 24
Peak memory 205096 kb
Host smart-b5494a17-5a92-44a9-a2ac-22242a5a8d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484157992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.484157992
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2034041828
Short name T316
Test name
Test status
Simulation time 37553172692 ps
CPU time 261.92 seconds
Started Jun 02 01:50:24 PM PDT 24
Finished Jun 02 01:54:46 PM PDT 24
Peak memory 251540 kb
Host smart-9492641c-bbc9-4feb-aa6b-4426fdac166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034041828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2034041828
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.583112554
Short name T245
Test name
Test status
Simulation time 2502670131 ps
CPU time 59.82 seconds
Started Jun 02 01:50:27 PM PDT 24
Finished Jun 02 01:51:28 PM PDT 24
Peak memory 252792 kb
Host smart-e9bad2db-de59-402f-8dd8-312e2f4fa065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583112554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.583112554
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1280039441
Short name T959
Test name
Test status
Simulation time 3118942165 ps
CPU time 47.68 seconds
Started Jun 02 01:50:24 PM PDT 24
Finished Jun 02 01:51:12 PM PDT 24
Peak memory 248816 kb
Host smart-55c6cda0-f175-4dc9-8065-dac8067d61ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280039441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1280039441
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1509513642
Short name T657
Test name
Test status
Simulation time 24358629243 ps
CPU time 78.21 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:51:41 PM PDT 24
Peak memory 238448 kb
Host smart-c2e14b7b-cd7e-4f91-8c14-900bbd94241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509513642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1509513642
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2722223941
Short name T577
Test name
Test status
Simulation time 10595949275 ps
CPU time 7.4 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:30 PM PDT 24
Peak memory 224080 kb
Host smart-b775862f-9fa7-4bba-95e7-ddbe04c61c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722223941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2722223941
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.77520947
Short name T606
Test name
Test status
Simulation time 5399180973 ps
CPU time 40.94 seconds
Started Jun 02 01:50:27 PM PDT 24
Finished Jun 02 01:51:08 PM PDT 24
Peak memory 240792 kb
Host smart-45791c61-0e0a-463c-9bcd-55ca39daf67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77520947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.77520947
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3217996858
Short name T811
Test name
Test status
Simulation time 8865638749 ps
CPU time 11.74 seconds
Started Jun 02 01:50:23 PM PDT 24
Finished Jun 02 01:50:35 PM PDT 24
Peak memory 232808 kb
Host smart-c98a4530-f1ba-4e08-b27f-414b1238e3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217996858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3217996858
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3777078155
Short name T437
Test name
Test status
Simulation time 8194093029 ps
CPU time 4.28 seconds
Started Jun 02 01:50:23 PM PDT 24
Finished Jun 02 01:50:28 PM PDT 24
Peak memory 218376 kb
Host smart-e8a2575c-774f-4aa8-8cba-3a1c9de16c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777078155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3777078155
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3517657700
Short name T736
Test name
Test status
Simulation time 3305725848 ps
CPU time 5.34 seconds
Started Jun 02 01:50:23 PM PDT 24
Finished Jun 02 01:50:28 PM PDT 24
Peak memory 222552 kb
Host smart-7728980e-cef9-4d58-a183-c45938b39630
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3517657700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3517657700
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1303687538
Short name T508
Test name
Test status
Simulation time 4532621959 ps
CPU time 10.92 seconds
Started Jun 02 01:50:16 PM PDT 24
Finished Jun 02 01:50:27 PM PDT 24
Peak memory 215872 kb
Host smart-5c467256-e93f-410c-b0cd-5ce98cc8d52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303687538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1303687538
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.958561480
Short name T658
Test name
Test status
Simulation time 14893056190 ps
CPU time 12.5 seconds
Started Jun 02 01:50:25 PM PDT 24
Finished Jun 02 01:50:38 PM PDT 24
Peak memory 215812 kb
Host smart-a1ddc777-5bd6-49b7-a8fd-d21909664dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958561480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.958561480
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.727077757
Short name T914
Test name
Test status
Simulation time 90611375 ps
CPU time 1.43 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:24 PM PDT 24
Peak memory 215896 kb
Host smart-e2eb4f7e-3f79-43a7-8afb-aebd26e19f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727077757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.727077757
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.106801329
Short name T612
Test name
Test status
Simulation time 95851394 ps
CPU time 1.01 seconds
Started Jun 02 01:50:25 PM PDT 24
Finished Jun 02 01:50:27 PM PDT 24
Peak memory 205452 kb
Host smart-d14b8b68-7f59-45d9-95d8-acfea6765776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106801329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.106801329
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.249234792
Short name T756
Test name
Test status
Simulation time 2567924102 ps
CPU time 7.21 seconds
Started Jun 02 01:50:24 PM PDT 24
Finished Jun 02 01:50:31 PM PDT 24
Peak memory 217156 kb
Host smart-6245c3e4-0de2-4607-8ae9-0dec9a0c695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249234792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.249234792
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3172657219
Short name T918
Test name
Test status
Simulation time 42175784 ps
CPU time 0.73 seconds
Started Jun 02 01:50:27 PM PDT 24
Finished Jun 02 01:50:29 PM PDT 24
Peak memory 204824 kb
Host smart-9235e395-6be8-426f-8deb-0bee8809e8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172657219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3172657219
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2824582997
Short name T587
Test name
Test status
Simulation time 7502748310 ps
CPU time 34.12 seconds
Started Jun 02 01:50:28 PM PDT 24
Finished Jun 02 01:51:02 PM PDT 24
Peak memory 220204 kb
Host smart-1f7732c1-8602-4950-8479-d0d90e1a8707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824582997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2824582997
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2038427927
Short name T550
Test name
Test status
Simulation time 88490835 ps
CPU time 0.77 seconds
Started Jun 02 01:50:23 PM PDT 24
Finished Jun 02 01:50:24 PM PDT 24
Peak memory 205776 kb
Host smart-115f7e17-743f-4aee-bda4-e999b0731307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038427927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2038427927
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.368138429
Short name T138
Test name
Test status
Simulation time 797992912 ps
CPU time 5.86 seconds
Started Jun 02 01:50:33 PM PDT 24
Finished Jun 02 01:50:39 PM PDT 24
Peak memory 240440 kb
Host smart-cea09ef1-788e-4a66-9ba4-7f6394bae506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368138429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.368138429
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.909496329
Short name T246
Test name
Test status
Simulation time 13352920255 ps
CPU time 103.06 seconds
Started Jun 02 01:50:30 PM PDT 24
Finished Jun 02 01:52:13 PM PDT 24
Peak memory 253832 kb
Host smart-d01217e6-7a8e-40f2-b96d-827dee9640aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909496329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.909496329
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4186685597
Short name T766
Test name
Test status
Simulation time 26733833391 ps
CPU time 61.92 seconds
Started Jun 02 01:50:33 PM PDT 24
Finished Jun 02 01:51:35 PM PDT 24
Peak memory 249844 kb
Host smart-4af277a4-4666-4d99-a1dc-7a2ebce0c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186685597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4186685597
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3560794250
Short name T393
Test name
Test status
Simulation time 825883772 ps
CPU time 13.38 seconds
Started Jun 02 01:50:28 PM PDT 24
Finished Jun 02 01:50:42 PM PDT 24
Peak memory 239232 kb
Host smart-35e151ce-78cb-4bc1-9c0a-98e5be4545a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560794250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3560794250
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.83305145
Short name T9
Test name
Test status
Simulation time 693178458 ps
CPU time 3.79 seconds
Started Jun 02 01:50:26 PM PDT 24
Finished Jun 02 01:50:30 PM PDT 24
Peak memory 218152 kb
Host smart-6afe8c96-5423-4fab-9108-648ac7f420a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83305145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.83305145
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1641491692
Short name T516
Test name
Test status
Simulation time 4920620529 ps
CPU time 48.78 seconds
Started Jun 02 01:50:27 PM PDT 24
Finished Jun 02 01:51:16 PM PDT 24
Peak memory 233348 kb
Host smart-4a15f951-0eaa-4ab3-bef9-1ccdfbd2c373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641491692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1641491692
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3811286439
Short name T589
Test name
Test status
Simulation time 185015724 ps
CPU time 4.26 seconds
Started Jun 02 01:50:27 PM PDT 24
Finished Jun 02 01:50:32 PM PDT 24
Peak memory 233152 kb
Host smart-780dd80b-119f-44c4-a461-f2531055e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811286439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3811286439
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.648726614
Short name T566
Test name
Test status
Simulation time 932943693 ps
CPU time 5.57 seconds
Started Jun 02 01:50:25 PM PDT 24
Finished Jun 02 01:50:31 PM PDT 24
Peak memory 227412 kb
Host smart-ce03edd4-9480-4d11-a064-544eb8b713aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648726614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.648726614
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2794113211
Short name T746
Test name
Test status
Simulation time 4080628359 ps
CPU time 11.31 seconds
Started Jun 02 01:50:26 PM PDT 24
Finished Jun 02 01:50:37 PM PDT 24
Peak memory 219836 kb
Host smart-bce5e491-50cb-4282-ad80-b056b3070c1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2794113211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2794113211
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.901406098
Short name T927
Test name
Test status
Simulation time 13819260376 ps
CPU time 108.59 seconds
Started Jun 02 01:50:29 PM PDT 24
Finished Jun 02 01:52:18 PM PDT 24
Peak memory 249784 kb
Host smart-868ff5e0-3441-48af-bd56-0f950aef8adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901406098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.901406098
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3501215597
Short name T743
Test name
Test status
Simulation time 16732788347 ps
CPU time 29.09 seconds
Started Jun 02 01:50:24 PM PDT 24
Finished Jun 02 01:50:53 PM PDT 24
Peak memory 215832 kb
Host smart-00145d68-f6ba-4be3-8710-5d43af4b686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501215597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3501215597
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2371068727
Short name T614
Test name
Test status
Simulation time 682022722 ps
CPU time 3.22 seconds
Started Jun 02 01:50:24 PM PDT 24
Finished Jun 02 01:50:28 PM PDT 24
Peak memory 215704 kb
Host smart-6577622e-8988-4372-a5b0-a4aade0be6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371068727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2371068727
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2126356075
Short name T928
Test name
Test status
Simulation time 19466252 ps
CPU time 1.35 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:24 PM PDT 24
Peak memory 215832 kb
Host smart-41a920b6-3669-45e7-a055-fb5e5d7baa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126356075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2126356075
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2135855389
Short name T380
Test name
Test status
Simulation time 174656273 ps
CPU time 0.82 seconds
Started Jun 02 01:50:22 PM PDT 24
Finished Jun 02 01:50:24 PM PDT 24
Peak memory 205152 kb
Host smart-3040aa93-4f5e-49b6-8009-054433b1b274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135855389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2135855389
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.250159917
Short name T247
Test name
Test status
Simulation time 44269368799 ps
CPU time 31.08 seconds
Started Jun 02 01:50:29 PM PDT 24
Finished Jun 02 01:51:01 PM PDT 24
Peak memory 218148 kb
Host smart-ecd9e233-4057-407d-baeb-d19f1e7f2db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250159917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.250159917
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3656240109
Short name T481
Test name
Test status
Simulation time 13100181 ps
CPU time 0.72 seconds
Started Jun 02 01:50:26 PM PDT 24
Finished Jun 02 01:50:27 PM PDT 24
Peak memory 204848 kb
Host smart-065dfb2f-863f-4576-9a0e-1f62e7ad3f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656240109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3656240109
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2230873343
Short name T651
Test name
Test status
Simulation time 1017767209 ps
CPU time 5.56 seconds
Started Jun 02 01:50:33 PM PDT 24
Finished Jun 02 01:50:39 PM PDT 24
Peak memory 224088 kb
Host smart-5645a27d-34ad-456f-8d50-f3393431fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230873343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2230873343
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2864892716
Short name T570
Test name
Test status
Simulation time 13663171 ps
CPU time 0.73 seconds
Started Jun 02 01:50:31 PM PDT 24
Finished Jun 02 01:50:32 PM PDT 24
Peak memory 205820 kb
Host smart-da8d3fbe-d796-423c-9586-bf69de5ace64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864892716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2864892716
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1287317146
Short name T372
Test name
Test status
Simulation time 50005893 ps
CPU time 0.76 seconds
Started Jun 02 01:50:26 PM PDT 24
Finished Jun 02 01:50:27 PM PDT 24
Peak memory 215376 kb
Host smart-e0b8fa88-4625-4e85-8d6a-4475144245a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287317146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1287317146
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4068049212
Short name T29
Test name
Test status
Simulation time 18882345369 ps
CPU time 9.21 seconds
Started Jun 02 01:50:25 PM PDT 24
Finished Jun 02 01:50:35 PM PDT 24
Peak memory 217096 kb
Host smart-2874c6d2-79bd-4f21-94ac-ce91558179b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068049212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4068049212
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.852172763
Short name T670
Test name
Test status
Simulation time 11262775446 ps
CPU time 36.27 seconds
Started Jun 02 01:50:25 PM PDT 24
Finished Jun 02 01:51:01 PM PDT 24
Peak memory 242188 kb
Host smart-1c58865a-e6c0-41f4-a3fd-3edab5736b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852172763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.852172763
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1070855077
Short name T762
Test name
Test status
Simulation time 107168208 ps
CPU time 2.38 seconds
Started Jun 02 01:50:29 PM PDT 24
Finished Jun 02 01:50:32 PM PDT 24
Peak memory 215628 kb
Host smart-90a86c24-40e4-4e08-b5ca-06eaecd864fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070855077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1070855077
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4157623849
Short name T218
Test name
Test status
Simulation time 8971535667 ps
CPU time 61.31 seconds
Started Jun 02 01:50:28 PM PDT 24
Finished Jun 02 01:51:29 PM PDT 24
Peak memory 239868 kb
Host smart-d2b96910-802e-48d4-b3ce-45bb28fe607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157623849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4157623849
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.199675880
Short name T864
Test name
Test status
Simulation time 4051203008 ps
CPU time 11.81 seconds
Started Jun 02 01:50:30 PM PDT 24
Finished Jun 02 01:50:43 PM PDT 24
Peak memory 219264 kb
Host smart-fdac3b33-6576-498a-a218-7370511a43ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199675880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.199675880
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4098007533
Short name T828
Test name
Test status
Simulation time 97153284 ps
CPU time 2.35 seconds
Started Jun 02 01:50:29 PM PDT 24
Finished Jun 02 01:50:32 PM PDT 24
Peak memory 216376 kb
Host smart-619af625-68b8-4f65-ba76-f7234997ba3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098007533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4098007533
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2602713346
Short name T432
Test name
Test status
Simulation time 231767559 ps
CPU time 4.33 seconds
Started Jun 02 01:50:27 PM PDT 24
Finished Jun 02 01:50:31 PM PDT 24
Peak memory 218340 kb
Host smart-631c8c12-86e4-4ee4-89bc-f81383fb1c57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2602713346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2602713346
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.120800347
Short name T225
Test name
Test status
Simulation time 39092994013 ps
CPU time 153.08 seconds
Started Jun 02 01:50:29 PM PDT 24
Finished Jun 02 01:53:02 PM PDT 24
Peak memory 253784 kb
Host smart-46f291b8-2790-4743-a30c-2f90ee7919d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120800347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.120800347
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1613252855
Short name T564
Test name
Test status
Simulation time 19749478797 ps
CPU time 24.98 seconds
Started Jun 02 01:50:27 PM PDT 24
Finished Jun 02 01:50:53 PM PDT 24
Peak memory 215920 kb
Host smart-c39e7cee-e2cf-46f6-ae78-5cdf7c87f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613252855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1613252855
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2082948547
Short name T611
Test name
Test status
Simulation time 24097392 ps
CPU time 1.49 seconds
Started Jun 02 01:50:33 PM PDT 24
Finished Jun 02 01:50:35 PM PDT 24
Peak memory 215772 kb
Host smart-7c34da65-701a-4aac-8b52-99538a1ae929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082948547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2082948547
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2143312560
Short name T847
Test name
Test status
Simulation time 86115451 ps
CPU time 0.82 seconds
Started Jun 02 01:50:29 PM PDT 24
Finished Jun 02 01:50:31 PM PDT 24
Peak memory 205220 kb
Host smart-c26481a2-8e47-48fc-9582-c59a6c123447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143312560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2143312560
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2778155913
Short name T846
Test name
Test status
Simulation time 561763613 ps
CPU time 7.23 seconds
Started Jun 02 01:50:29 PM PDT 24
Finished Jun 02 01:50:37 PM PDT 24
Peak memory 220676 kb
Host smart-5da2b490-c5c3-4b82-8392-760ebc53aaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778155913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2778155913
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4226240799
Short name T813
Test name
Test status
Simulation time 42176623 ps
CPU time 0.7 seconds
Started Jun 02 01:50:31 PM PDT 24
Finished Jun 02 01:50:33 PM PDT 24
Peak memory 204840 kb
Host smart-a4cd1a04-1cbf-4752-a9dc-d52c084f4b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226240799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4226240799
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2400513678
Short name T561
Test name
Test status
Simulation time 717619297 ps
CPU time 3.7 seconds
Started Jun 02 01:50:32 PM PDT 24
Finished Jun 02 01:50:36 PM PDT 24
Peak memory 234024 kb
Host smart-0aa338c5-f121-4028-8a29-55edf1d99022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400513678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2400513678
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3862964609
Short name T361
Test name
Test status
Simulation time 24578244 ps
CPU time 0.73 seconds
Started Jun 02 01:50:28 PM PDT 24
Finished Jun 02 01:50:30 PM PDT 24
Peak memory 205176 kb
Host smart-15b395bb-e941-4a9e-9a12-c561c557d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862964609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3862964609
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.291079478
Short name T729
Test name
Test status
Simulation time 1628274819 ps
CPU time 20.61 seconds
Started Jun 02 01:50:30 PM PDT 24
Finished Jun 02 01:50:51 PM PDT 24
Peak memory 234312 kb
Host smart-15870766-a841-471e-8ce9-c004d144c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291079478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.291079478
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.412278463
Short name T318
Test name
Test status
Simulation time 347495478001 ps
CPU time 337.15 seconds
Started Jun 02 01:50:31 PM PDT 24
Finished Jun 02 01:56:09 PM PDT 24
Peak memory 252456 kb
Host smart-f05c194d-ccc3-488d-ba5f-a37e2cf288ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412278463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.412278463
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4269472111
Short name T325
Test name
Test status
Simulation time 15801892567 ps
CPU time 81.97 seconds
Started Jun 02 01:50:32 PM PDT 24
Finished Jun 02 01:51:54 PM PDT 24
Peak memory 256648 kb
Host smart-54c14225-981e-487e-b102-02947bdd9715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269472111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4269472111
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2147558649
Short name T329
Test name
Test status
Simulation time 1795114114 ps
CPU time 17.01 seconds
Started Jun 02 01:50:30 PM PDT 24
Finished Jun 02 01:50:48 PM PDT 24
Peak memory 224104 kb
Host smart-faaa9c65-c019-4213-a120-6b15d7cf4b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147558649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2147558649
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.138050013
Short name T568
Test name
Test status
Simulation time 443718733 ps
CPU time 3.06 seconds
Started Jun 02 01:50:31 PM PDT 24
Finished Jun 02 01:50:34 PM PDT 24
Peak memory 233088 kb
Host smart-d03f7b12-c8fb-4333-90bd-f1613c61768a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138050013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.138050013
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1558189460
Short name T390
Test name
Test status
Simulation time 20262113701 ps
CPU time 23.81 seconds
Started Jun 02 01:50:33 PM PDT 24
Finished Jun 02 01:50:57 PM PDT 24
Peak memory 232340 kb
Host smart-16da1f67-81d5-4b3b-9dbc-ac88560fc4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558189460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1558189460
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.487073047
Short name T929
Test name
Test status
Simulation time 645650587 ps
CPU time 2.77 seconds
Started Jun 02 01:50:31 PM PDT 24
Finished Jun 02 01:50:35 PM PDT 24
Peak memory 218028 kb
Host smart-6d8f06b1-e0f0-47c7-ac51-6d4e35120168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487073047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.487073047
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1896372460
Short name T195
Test name
Test status
Simulation time 1040871973 ps
CPU time 7.76 seconds
Started Jun 02 01:50:30 PM PDT 24
Finished Jun 02 01:50:39 PM PDT 24
Peak memory 232532 kb
Host smart-bdbb7364-ff6a-440b-ad3a-1707ca47ed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896372460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1896372460
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.255205881
Short name T499
Test name
Test status
Simulation time 662030635 ps
CPU time 5.27 seconds
Started Jun 02 01:50:32 PM PDT 24
Finished Jun 02 01:50:38 PM PDT 24
Peak memory 218756 kb
Host smart-be30b5bf-5800-44a7-b084-c65289882064
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=255205881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.255205881
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2082491498
Short name T768
Test name
Test status
Simulation time 3416983827 ps
CPU time 3.38 seconds
Started Jun 02 01:50:26 PM PDT 24
Finished Jun 02 01:50:30 PM PDT 24
Peak memory 215932 kb
Host smart-24e9d3a1-ead2-41f4-987d-4d121ba32496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082491498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2082491498
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2553198262
Short name T343
Test name
Test status
Simulation time 2309154049 ps
CPU time 5.91 seconds
Started Jun 02 01:50:28 PM PDT 24
Finished Jun 02 01:50:35 PM PDT 24
Peak memory 215760 kb
Host smart-f694825d-b21a-4e42-82f9-810526480de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553198262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2553198262
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2478349787
Short name T439
Test name
Test status
Simulation time 2104764866 ps
CPU time 2.22 seconds
Started Jun 02 01:50:32 PM PDT 24
Finished Jun 02 01:50:35 PM PDT 24
Peak memory 215856 kb
Host smart-1bbf4db4-6a79-4975-ad35-1cf0742fae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478349787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2478349787
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.497922375
Short name T474
Test name
Test status
Simulation time 19034282 ps
CPU time 0.79 seconds
Started Jun 02 01:50:30 PM PDT 24
Finished Jun 02 01:50:32 PM PDT 24
Peak memory 205156 kb
Host smart-eab723d6-1f9e-4abb-a6fd-487679611036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497922375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.497922375
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2495124808
Short name T645
Test name
Test status
Simulation time 62487512206 ps
CPU time 16.54 seconds
Started Jun 02 01:50:30 PM PDT 24
Finished Jun 02 01:50:47 PM PDT 24
Peak memory 236036 kb
Host smart-3b7eb777-aa38-4f2c-95ee-62988f9c3b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495124808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2495124808
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1760956220
Short name T482
Test name
Test status
Simulation time 21390348 ps
CPU time 0.71 seconds
Started Jun 02 01:50:38 PM PDT 24
Finished Jun 02 01:50:39 PM PDT 24
Peak memory 204812 kb
Host smart-6e861a2d-30b2-4cb1-8885-2a7f1d446c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760956220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1760956220
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2773759081
Short name T520
Test name
Test status
Simulation time 113580668 ps
CPU time 2.55 seconds
Started Jun 02 01:50:37 PM PDT 24
Finished Jun 02 01:50:40 PM PDT 24
Peak memory 218472 kb
Host smart-062323ed-df74-4a42-b609-8b52145f0510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773759081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2773759081
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1230493174
Short name T347
Test name
Test status
Simulation time 144325674 ps
CPU time 0.76 seconds
Started Jun 02 01:50:33 PM PDT 24
Finished Jun 02 01:50:34 PM PDT 24
Peak memory 205832 kb
Host smart-d6d15c19-1614-47ae-a535-62f80a683508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230493174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1230493174
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2191280981
Short name T216
Test name
Test status
Simulation time 62447911715 ps
CPU time 114.66 seconds
Started Jun 02 01:50:41 PM PDT 24
Finished Jun 02 01:52:36 PM PDT 24
Peak memory 238024 kb
Host smart-03527edf-9622-486c-9150-c527a6031eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191280981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2191280981
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.123029818
Short name T169
Test name
Test status
Simulation time 31170066981 ps
CPU time 154.03 seconds
Started Jun 02 01:50:38 PM PDT 24
Finished Jun 02 01:53:12 PM PDT 24
Peak memory 248492 kb
Host smart-c28f975c-f3e6-4df2-ab1c-54ee6bffbc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123029818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.123029818
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2372928409
Short name T160
Test name
Test status
Simulation time 4421081728 ps
CPU time 70.54 seconds
Started Jun 02 01:50:38 PM PDT 24
Finished Jun 02 01:51:49 PM PDT 24
Peak memory 238832 kb
Host smart-96b1b263-abaa-450d-b194-08266a4c6c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372928409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2372928409
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2320200219
Short name T623
Test name
Test status
Simulation time 2866938768 ps
CPU time 15.02 seconds
Started Jun 02 01:50:37 PM PDT 24
Finished Jun 02 01:50:53 PM PDT 24
Peak memory 224144 kb
Host smart-54480415-fa57-47c0-aa45-8efc00240856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320200219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2320200219
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1424435535
Short name T684
Test name
Test status
Simulation time 225564002 ps
CPU time 4.86 seconds
Started Jun 02 01:50:36 PM PDT 24
Finished Jun 02 01:50:41 PM PDT 24
Peak memory 235356 kb
Host smart-ab604e9f-0a3e-443a-84b5-4cf3f8854732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424435535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1424435535
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.522563839
Short name T202
Test name
Test status
Simulation time 3434661783 ps
CPU time 11.71 seconds
Started Jun 02 01:50:33 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 218240 kb
Host smart-35182b58-b036-40db-b5da-7f49111c5428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522563839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.522563839
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4161107741
Short name T237
Test name
Test status
Simulation time 5467246991 ps
CPU time 7.74 seconds
Started Jun 02 01:50:37 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 235592 kb
Host smart-d5d1d75b-5400-4cc5-bfe7-61c5aa3650c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161107741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4161107741
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2580809571
Short name T37
Test name
Test status
Simulation time 2431393935 ps
CPU time 11.72 seconds
Started Jun 02 01:50:32 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 236712 kb
Host smart-159407a2-18e6-4a2b-999c-2a02e98e18b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580809571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2580809571
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1837730318
Short name T849
Test name
Test status
Simulation time 5091571760 ps
CPU time 6.53 seconds
Started Jun 02 01:50:37 PM PDT 24
Finished Jun 02 01:50:44 PM PDT 24
Peak memory 218412 kb
Host smart-770dd9d6-d59c-4b1e-97fc-f28bfbe9b45a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1837730318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1837730318
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3790788946
Short name T61
Test name
Test status
Simulation time 109814821 ps
CPU time 0.98 seconds
Started Jun 02 01:50:40 PM PDT 24
Finished Jun 02 01:50:42 PM PDT 24
Peak memory 204900 kb
Host smart-42894ac1-4276-45d8-9868-dab7f6c14152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790788946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3790788946
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2725049447
Short name T472
Test name
Test status
Simulation time 2244081380 ps
CPU time 6.08 seconds
Started Jun 02 01:50:35 PM PDT 24
Finished Jun 02 01:50:42 PM PDT 24
Peak memory 215912 kb
Host smart-5e968cc7-9aef-433e-9b23-44209adb77db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725049447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2725049447
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.163187654
Short name T754
Test name
Test status
Simulation time 2679522575 ps
CPU time 8.78 seconds
Started Jun 02 01:50:30 PM PDT 24
Finished Jun 02 01:50:40 PM PDT 24
Peak memory 215844 kb
Host smart-df932098-0cc9-4c48-a124-825730cd5ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163187654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.163187654
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1523252388
Short name T618
Test name
Test status
Simulation time 57214896 ps
CPU time 1.21 seconds
Started Jun 02 01:50:35 PM PDT 24
Finished Jun 02 01:50:37 PM PDT 24
Peak memory 215688 kb
Host smart-7af73cff-9d2e-40fc-889e-9364ba477391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523252388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1523252388
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4202942171
Short name T460
Test name
Test status
Simulation time 126458139 ps
CPU time 0.81 seconds
Started Jun 02 01:50:33 PM PDT 24
Finished Jun 02 01:50:35 PM PDT 24
Peak memory 205208 kb
Host smart-bd68ab51-c305-422e-a15e-742bf8f90b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202942171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4202942171
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2906099829
Short name T253
Test name
Test status
Simulation time 1251844663 ps
CPU time 3.14 seconds
Started Jun 02 01:50:31 PM PDT 24
Finished Jun 02 01:50:34 PM PDT 24
Peak memory 218200 kb
Host smart-e08ae431-0442-4aa4-8460-8f3e44f5b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906099829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2906099829
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1659323433
Short name T351
Test name
Test status
Simulation time 26168620 ps
CPU time 0.73 seconds
Started Jun 02 01:50:49 PM PDT 24
Finished Jun 02 01:50:50 PM PDT 24
Peak memory 204180 kb
Host smart-01d93ef9-1709-4c82-bfd3-4d821762a597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659323433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1659323433
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1128289079
Short name T591
Test name
Test status
Simulation time 32543651 ps
CPU time 2.09 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 215628 kb
Host smart-e2a69d05-aa28-48a3-a9c2-fbcb1095bcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128289079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1128289079
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.975876073
Short name T902
Test name
Test status
Simulation time 126423917 ps
CPU time 0.77 seconds
Started Jun 02 01:50:37 PM PDT 24
Finished Jun 02 01:50:38 PM PDT 24
Peak memory 204776 kb
Host smart-9ff376ae-df8c-47f2-9dd8-dbe758ce4cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975876073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.975876073
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3455870988
Short name T313
Test name
Test status
Simulation time 63191996587 ps
CPU time 164.21 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:53:27 PM PDT 24
Peak memory 251484 kb
Host smart-3d5fcd6a-b535-4a23-8c55-e905a5053b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455870988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3455870988
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.967417146
Short name T635
Test name
Test status
Simulation time 36996995512 ps
CPU time 96.59 seconds
Started Jun 02 01:50:45 PM PDT 24
Finished Jun 02 01:52:22 PM PDT 24
Peak memory 250040 kb
Host smart-36177e6e-abef-4c1e-869f-23ae4d5480e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967417146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.967417146
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3590249970
Short name T935
Test name
Test status
Simulation time 7354381373 ps
CPU time 80.07 seconds
Started Jun 02 01:50:44 PM PDT 24
Finished Jun 02 01:52:04 PM PDT 24
Peak memory 232376 kb
Host smart-0998da20-2b7f-4a32-bc54-8ac3090cfab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590249970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3590249970
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1413908596
Short name T492
Test name
Test status
Simulation time 1977611223 ps
CPU time 14.47 seconds
Started Jun 02 01:50:41 PM PDT 24
Finished Jun 02 01:50:56 PM PDT 24
Peak memory 240368 kb
Host smart-a6129922-b055-428f-ba75-6c854f35638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413908596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1413908596
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.453260420
Short name T369
Test name
Test status
Simulation time 1353619244 ps
CPU time 13.92 seconds
Started Jun 02 01:50:43 PM PDT 24
Finished Jun 02 01:50:57 PM PDT 24
Peak memory 220168 kb
Host smart-72d3eb38-e306-44ad-9369-983581fe3bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453260420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.453260420
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3409262042
Short name T544
Test name
Test status
Simulation time 1537038717 ps
CPU time 11.39 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:50:54 PM PDT 24
Peak memory 218192 kb
Host smart-585e643a-a3ea-4db5-9da6-da46a4203c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409262042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3409262042
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2048860289
Short name T301
Test name
Test status
Simulation time 258560714 ps
CPU time 3.08 seconds
Started Jun 02 01:50:39 PM PDT 24
Finished Jun 02 01:50:42 PM PDT 24
Peak memory 234444 kb
Host smart-4ee398c4-5732-48e8-a728-7b902850802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048860289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2048860289
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2334281140
Short name T159
Test name
Test status
Simulation time 1133739573 ps
CPU time 3.66 seconds
Started Jun 02 01:50:37 PM PDT 24
Finished Jun 02 01:50:41 PM PDT 24
Peak memory 218160 kb
Host smart-98fbe2d9-41bb-4811-a0bf-082f285c6fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334281140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2334281140
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1829574139
Short name T814
Test name
Test status
Simulation time 354512099 ps
CPU time 4.55 seconds
Started Jun 02 01:50:41 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 219612 kb
Host smart-3b698e7d-4e71-47cb-82ce-0f34c0663be2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1829574139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1829574139
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3161874281
Short name T156
Test name
Test status
Simulation time 6985076712 ps
CPU time 129.76 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:52:52 PM PDT 24
Peak memory 267536 kb
Host smart-b4d6c561-7453-47c8-999c-19534d433b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161874281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3161874281
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4068295597
Short name T46
Test name
Test status
Simulation time 2458218497 ps
CPU time 20.95 seconds
Started Jun 02 01:50:40 PM PDT 24
Finished Jun 02 01:51:01 PM PDT 24
Peak memory 215920 kb
Host smart-b1899b15-42a2-4842-9c6b-4d7f6cf4a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068295597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4068295597
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.809868855
Short name T13
Test name
Test status
Simulation time 53482326701 ps
CPU time 19.51 seconds
Started Jun 02 01:50:38 PM PDT 24
Finished Jun 02 01:50:58 PM PDT 24
Peak memory 215860 kb
Host smart-12c730cb-70f6-46ab-837c-518ff3f5ccec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809868855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.809868855
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3514823082
Short name T783
Test name
Test status
Simulation time 308248643 ps
CPU time 1.15 seconds
Started Jun 02 01:50:40 PM PDT 24
Finished Jun 02 01:50:42 PM PDT 24
Peak memory 207128 kb
Host smart-e97f1c1e-afb5-4814-814b-f4d820b46b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514823082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3514823082
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3715081263
Short name T90
Test name
Test status
Simulation time 40880369 ps
CPU time 0.79 seconds
Started Jun 02 01:50:38 PM PDT 24
Finished Jun 02 01:50:39 PM PDT 24
Peak memory 205208 kb
Host smart-eb71f57d-8733-498a-83be-95fd8d0c1a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715081263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3715081263
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2862898307
Short name T720
Test name
Test status
Simulation time 7262438429 ps
CPU time 32.18 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:51:14 PM PDT 24
Peak memory 236388 kb
Host smart-ed660c22-6397-420c-a20f-fd3486c17f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862898307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2862898307
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.373771475
Short name T930
Test name
Test status
Simulation time 17483925 ps
CPU time 0.72 seconds
Started Jun 02 01:50:40 PM PDT 24
Finished Jun 02 01:50:42 PM PDT 24
Peak memory 204864 kb
Host smart-fbe4699a-1c4f-4404-b74d-5e13fa62e343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373771475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.373771475
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.267634636
Short name T748
Test name
Test status
Simulation time 359275574 ps
CPU time 3.59 seconds
Started Jun 02 01:50:41 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 233112 kb
Host smart-316af776-c1a0-4d1c-a3a2-9053957e079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267634636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.267634636
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3692282933
Short name T511
Test name
Test status
Simulation time 17990112 ps
CPU time 0.81 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:50:44 PM PDT 24
Peak memory 205824 kb
Host smart-7584f65d-1656-42b1-91db-eac28753499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692282933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3692282933
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1540871100
Short name T322
Test name
Test status
Simulation time 37526674962 ps
CPU time 297.33 seconds
Started Jun 02 01:50:49 PM PDT 24
Finished Jun 02 01:55:46 PM PDT 24
Peak memory 251628 kb
Host smart-b883533e-3058-4b06-90d7-a9f1a57b60fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540871100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1540871100
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3409330646
Short name T548
Test name
Test status
Simulation time 3339592996 ps
CPU time 48.41 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:51:31 PM PDT 24
Peak memory 248820 kb
Host smart-4aeafc51-e96b-4e1b-8b01-32ce7396b03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409330646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3409330646
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3731928867
Short name T942
Test name
Test status
Simulation time 665430123 ps
CPU time 10.38 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:50:53 PM PDT 24
Peak memory 224124 kb
Host smart-686bf0a1-2f8f-4f84-8ab2-99a5f2c37b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731928867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3731928867
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1582541345
Short name T926
Test name
Test status
Simulation time 75334729 ps
CPU time 2.76 seconds
Started Jun 02 01:50:43 PM PDT 24
Finished Jun 02 01:50:46 PM PDT 24
Peak memory 233184 kb
Host smart-9cb3fa10-a2ac-4a7c-af7c-37885ae5cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582541345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1582541345
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2262633792
Short name T830
Test name
Test status
Simulation time 538873824 ps
CPU time 4.97 seconds
Started Jun 02 01:50:43 PM PDT 24
Finished Jun 02 01:50:48 PM PDT 24
Peak memory 218020 kb
Host smart-b3e664b3-de61-422e-bc00-c6a2d9ffb0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262633792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2262633792
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.746057956
Short name T192
Test name
Test status
Simulation time 49351385101 ps
CPU time 13.35 seconds
Started Jun 02 01:50:44 PM PDT 24
Finished Jun 02 01:50:57 PM PDT 24
Peak memory 239632 kb
Host smart-4a2c7e30-aef9-4ce6-be70-507bd3b1a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746057956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.746057956
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4101560695
Short name T969
Test name
Test status
Simulation time 169244023 ps
CPU time 4.78 seconds
Started Jun 02 01:50:44 PM PDT 24
Finished Jun 02 01:50:49 PM PDT 24
Peak memory 233228 kb
Host smart-7ec8457a-26d5-4a8e-b28c-328af4ab343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101560695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4101560695
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1129960405
Short name T161
Test name
Test status
Simulation time 1615870170 ps
CPU time 7.71 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:50:50 PM PDT 24
Peak memory 218708 kb
Host smart-e5740da7-10aa-4717-b51a-e7ed3ac150f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1129960405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1129960405
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.199719224
Short name T931
Test name
Test status
Simulation time 32054103711 ps
CPU time 315.98 seconds
Started Jun 02 01:50:49 PM PDT 24
Finished Jun 02 01:56:06 PM PDT 24
Peak memory 249212 kb
Host smart-bb4c9aec-3d56-4535-b71d-c7c2c78e0ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199719224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.199719224
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3611465883
Short name T888
Test name
Test status
Simulation time 82824662077 ps
CPU time 50.25 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:51:32 PM PDT 24
Peak memory 216036 kb
Host smart-fac0da61-b634-436a-8e03-2c57299f4543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611465883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3611465883
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2040455863
Short name T683
Test name
Test status
Simulation time 303390252 ps
CPU time 2.1 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:50:45 PM PDT 24
Peak memory 215528 kb
Host smart-7e4b87e9-81bf-4b18-9a64-b8399b40381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040455863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2040455863
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2557588810
Short name T497
Test name
Test status
Simulation time 118145160 ps
CPU time 1.21 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:50:44 PM PDT 24
Peak memory 207648 kb
Host smart-73a25c6a-718e-4dc3-823d-21b56cd4beea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557588810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2557588810
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2583797807
Short name T488
Test name
Test status
Simulation time 104831314 ps
CPU time 1.07 seconds
Started Jun 02 01:50:42 PM PDT 24
Finished Jun 02 01:50:44 PM PDT 24
Peak memory 206244 kb
Host smart-cf2346a0-809d-4d85-9da7-aea5afdc9acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583797807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2583797807
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2486536356
Short name T52
Test name
Test status
Simulation time 2588414245 ps
CPU time 10.19 seconds
Started Jun 02 01:50:43 PM PDT 24
Finished Jun 02 01:50:53 PM PDT 24
Peak memory 233600 kb
Host smart-0e43a537-d21c-406b-ad27-5d0b093dad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486536356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2486536356
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3689901283
Short name T57
Test name
Test status
Simulation time 23076256 ps
CPU time 0.78 seconds
Started Jun 02 01:50:45 PM PDT 24
Finished Jun 02 01:50:46 PM PDT 24
Peak memory 204216 kb
Host smart-0d3cd520-5645-41ee-af51-e046a678ed3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689901283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3689901283
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1922317280
Short name T268
Test name
Test status
Simulation time 5222207049 ps
CPU time 11.21 seconds
Started Jun 02 01:50:48 PM PDT 24
Finished Jun 02 01:51:00 PM PDT 24
Peak memory 218592 kb
Host smart-5dfae428-805f-4e98-b000-cfddb3cb6f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922317280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1922317280
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2991893554
Short name T524
Test name
Test status
Simulation time 19754770 ps
CPU time 0.79 seconds
Started Jun 02 01:50:48 PM PDT 24
Finished Jun 02 01:50:50 PM PDT 24
Peak memory 205844 kb
Host smart-105db660-1332-40fb-8471-1f8194346345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991893554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2991893554
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4122169098
Short name T36
Test name
Test status
Simulation time 16211086779 ps
CPU time 155.86 seconds
Started Jun 02 01:50:46 PM PDT 24
Finished Jun 02 01:53:22 PM PDT 24
Peak memory 248880 kb
Host smart-d8d57eeb-2723-412f-9f8f-399c4c6eba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122169098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4122169098
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3313376865
Short name T198
Test name
Test status
Simulation time 200594773744 ps
CPU time 287.04 seconds
Started Jun 02 01:50:47 PM PDT 24
Finished Jun 02 01:55:34 PM PDT 24
Peak memory 254376 kb
Host smart-409ca359-b12e-41bc-bf6d-8ace7803d137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313376865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3313376865
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4052693970
Short name T21
Test name
Test status
Simulation time 47411119144 ps
CPU time 97.85 seconds
Started Jun 02 01:50:46 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 248188 kb
Host smart-01720a02-47de-41f9-9987-edf847ce04db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052693970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4052693970
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2540909890
Short name T625
Test name
Test status
Simulation time 331691149 ps
CPU time 6.4 seconds
Started Jun 02 01:50:46 PM PDT 24
Finished Jun 02 01:50:52 PM PDT 24
Peak memory 232316 kb
Host smart-cadcf192-961f-4f54-b329-6b1486377bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540909890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2540909890
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1144437193
Short name T263
Test name
Test status
Simulation time 204211327 ps
CPU time 4.44 seconds
Started Jun 02 01:50:45 PM PDT 24
Finished Jun 02 01:50:50 PM PDT 24
Peak memory 233616 kb
Host smart-b32c1ece-0362-4e9f-b0e9-4a030eac8a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144437193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1144437193
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3076708216
Short name T513
Test name
Test status
Simulation time 4098180352 ps
CPU time 35.42 seconds
Started Jun 02 01:50:48 PM PDT 24
Finished Jun 02 01:51:23 PM PDT 24
Peak memory 247452 kb
Host smart-895f3ee5-b475-4d7e-a301-c014766b1dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076708216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3076708216
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4202228509
Short name T957
Test name
Test status
Simulation time 254297774 ps
CPU time 3.5 seconds
Started Jun 02 01:50:46 PM PDT 24
Finished Jun 02 01:50:50 PM PDT 24
Peak memory 216396 kb
Host smart-0e4044cb-4bdd-4775-9748-3ab96b39f210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202228509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4202228509
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4044482068
Short name T615
Test name
Test status
Simulation time 2610887705 ps
CPU time 8.25 seconds
Started Jun 02 01:50:45 PM PDT 24
Finished Jun 02 01:50:53 PM PDT 24
Peak memory 237992 kb
Host smart-0062f847-71d8-4f63-ac79-1361b3dd98d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044482068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4044482068
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.799015139
Short name T397
Test name
Test status
Simulation time 1137252955 ps
CPU time 15.37 seconds
Started Jun 02 01:50:48 PM PDT 24
Finished Jun 02 01:51:03 PM PDT 24
Peak memory 219860 kb
Host smart-6680bf92-506b-4595-a9af-369847dd2fde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=799015139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.799015139
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2926240311
Short name T154
Test name
Test status
Simulation time 2553282423 ps
CPU time 25.19 seconds
Started Jun 02 01:50:48 PM PDT 24
Finished Jun 02 01:51:14 PM PDT 24
Peak memory 248892 kb
Host smart-a697cca1-efbf-476f-bab3-a9d7c39e57d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926240311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2926240311
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.641660529
Short name T468
Test name
Test status
Simulation time 6516769012 ps
CPU time 21.6 seconds
Started Jun 02 01:50:47 PM PDT 24
Finished Jun 02 01:51:09 PM PDT 24
Peak memory 215964 kb
Host smart-c3d09f9a-0cc9-4b76-9137-2b68deb9040e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641660529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.641660529
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3351562163
Short name T884
Test name
Test status
Simulation time 6776598242 ps
CPU time 7.34 seconds
Started Jun 02 01:50:45 PM PDT 24
Finished Jun 02 01:50:52 PM PDT 24
Peak memory 215724 kb
Host smart-94bc783d-7a26-4b86-b5c7-3b5dec478539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351562163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3351562163
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.150675728
Short name T740
Test name
Test status
Simulation time 36252632 ps
CPU time 0.88 seconds
Started Jun 02 01:50:48 PM PDT 24
Finished Jun 02 01:50:49 PM PDT 24
Peak memory 206616 kb
Host smart-79cf5e0d-4f19-4b94-91da-f2c667b653a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150675728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.150675728
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2077085035
Short name T777
Test name
Test status
Simulation time 14461588 ps
CPU time 0.69 seconds
Started Jun 02 01:50:49 PM PDT 24
Finished Jun 02 01:50:50 PM PDT 24
Peak memory 205236 kb
Host smart-ab76c2e7-b70d-4102-b214-63bcc77737fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077085035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2077085035
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.49783777
Short name T261
Test name
Test status
Simulation time 1227645625 ps
CPU time 5.23 seconds
Started Jun 02 01:50:49 PM PDT 24
Finished Jun 02 01:50:54 PM PDT 24
Peak memory 218356 kb
Host smart-ddce1547-527e-4164-8910-26f77ef92486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49783777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.49783777
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3848993352
Short name T629
Test name
Test status
Simulation time 39185142 ps
CPU time 0.7 seconds
Started Jun 02 01:48:46 PM PDT 24
Finished Jun 02 01:48:47 PM PDT 24
Peak memory 205208 kb
Host smart-7cbca16f-edb2-461b-bef7-bd1398b65fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848993352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
848993352
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3867841374
Short name T136
Test name
Test status
Simulation time 175547829 ps
CPU time 3.83 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:48:59 PM PDT 24
Peak memory 218320 kb
Host smart-e514d867-98ca-4703-8def-0d398cf8480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867841374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3867841374
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1979667054
Short name T445
Test name
Test status
Simulation time 15860932 ps
CPU time 0.78 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:48:56 PM PDT 24
Peak memory 205956 kb
Host smart-823508bc-f277-4de3-80e3-0e465a4dcfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979667054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1979667054
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.702019984
Short name T451
Test name
Test status
Simulation time 31200662410 ps
CPU time 204.72 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:52:16 PM PDT 24
Peak memory 254012 kb
Host smart-cc69f2f7-68bc-467b-95dd-14ff7f7b93ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702019984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.702019984
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.130501418
Short name T971
Test name
Test status
Simulation time 8028529477 ps
CPU time 37.46 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:49:30 PM PDT 24
Peak memory 222660 kb
Host smart-51475237-a757-47c5-8505-7c1040f87b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130501418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
130501418
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2830795211
Short name T215
Test name
Test status
Simulation time 1515349084 ps
CPU time 22.91 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:49:18 PM PDT 24
Peak memory 240432 kb
Host smart-e3afb9b4-eaa4-4081-a3c7-ffa8bbac58f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830795211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2830795211
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1445035839
Short name T76
Test name
Test status
Simulation time 4515493571 ps
CPU time 18.54 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:49:09 PM PDT 24
Peak memory 218360 kb
Host smart-02025a0a-c031-4900-b12f-aa5dc398d375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445035839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1445035839
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4159882894
Short name T241
Test name
Test status
Simulation time 59635297522 ps
CPU time 43.39 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:49:36 PM PDT 24
Peak memory 238780 kb
Host smart-28cd86f5-b1e6-4403-9600-9e08604e5905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159882894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4159882894
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3830415340
Short name T963
Test name
Test status
Simulation time 25050468 ps
CPU time 1.05 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:48 PM PDT 24
Peak memory 217300 kb
Host smart-6e3860cc-6849-483d-95d5-2e5a53f6f1ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830415340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3830415340
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.884804412
Short name T962
Test name
Test status
Simulation time 115209322010 ps
CPU time 20.91 seconds
Started Jun 02 01:48:53 PM PDT 24
Finished Jun 02 01:49:14 PM PDT 24
Peak memory 234976 kb
Host smart-901b3f82-84a6-439b-be27-d453ebc176c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884804412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
884804412
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3704412831
Short name T3
Test name
Test status
Simulation time 14389753222 ps
CPU time 12.09 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:49:02 PM PDT 24
Peak memory 233288 kb
Host smart-697c2fe4-845e-4398-8dea-a4da47d09114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704412831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3704412831
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1208226636
Short name T975
Test name
Test status
Simulation time 1132347784 ps
CPU time 5.15 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:52 PM PDT 24
Peak memory 222444 kb
Host smart-39ada8f4-6b92-4a87-a6e0-15a6605982f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1208226636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1208226636
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3847299872
Short name T71
Test name
Test status
Simulation time 92410467 ps
CPU time 1.15 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:48:55 PM PDT 24
Peak memory 234612 kb
Host smart-bdab6fce-66d3-41e0-af9b-df97169874c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847299872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3847299872
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.162224848
Short name T563
Test name
Test status
Simulation time 42673292 ps
CPU time 1.04 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:50 PM PDT 24
Peak memory 206320 kb
Host smart-2bfbdbae-7173-4102-bb50-fd7fff13efa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162224848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.162224848
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1018583963
Short name T627
Test name
Test status
Simulation time 480839112 ps
CPU time 3.1 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 215892 kb
Host smart-572d40c3-4ebc-41a3-ba6f-8f4bb6288517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018583963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1018583963
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1187838835
Short name T669
Test name
Test status
Simulation time 1935194436 ps
CPU time 3.78 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:56 PM PDT 24
Peak memory 215688 kb
Host smart-51b6f156-9f15-44c1-bbc6-0bdd85a022d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187838835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1187838835
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1477184487
Short name T375
Test name
Test status
Simulation time 110938520 ps
CPU time 1.23 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:48 PM PDT 24
Peak memory 215900 kb
Host smart-4cc41e56-eedb-45e7-b4c6-0b648467d254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477184487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1477184487
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3978079081
Short name T8
Test name
Test status
Simulation time 187072896 ps
CPU time 0.85 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:48:55 PM PDT 24
Peak memory 205228 kb
Host smart-1dc0e73b-a5e3-40f1-993c-e535416abe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978079081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3978079081
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4289751939
Short name T528
Test name
Test status
Simulation time 974811038 ps
CPU time 5.7 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:49:00 PM PDT 24
Peak memory 218572 kb
Host smart-3dc1d017-d2e9-4f5f-a229-5b48d67cf8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289751939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4289751939
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1087333486
Short name T620
Test name
Test status
Simulation time 13224019 ps
CPU time 0.75 seconds
Started Jun 02 01:50:56 PM PDT 24
Finished Jun 02 01:50:57 PM PDT 24
Peak memory 204820 kb
Host smart-496d4758-f0cf-47cf-b8a2-604786a1f6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087333486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1087333486
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3762212224
Short name T706
Test name
Test status
Simulation time 164231200 ps
CPU time 2.38 seconds
Started Jun 02 01:50:53 PM PDT 24
Finished Jun 02 01:50:55 PM PDT 24
Peak memory 217180 kb
Host smart-0a08e916-4fa7-4225-9cb9-8720ad218141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762212224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3762212224
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1584431848
Short name T365
Test name
Test status
Simulation time 16596569 ps
CPU time 0.81 seconds
Started Jun 02 01:50:49 PM PDT 24
Finished Jun 02 01:50:51 PM PDT 24
Peak memory 205984 kb
Host smart-50fe8a3e-3f06-455b-8887-98e7c8ede5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584431848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1584431848
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2686206576
Short name T223
Test name
Test status
Simulation time 20999527505 ps
CPU time 106.57 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:52:41 PM PDT 24
Peak memory 251236 kb
Host smart-a2791b26-e9cf-49df-8869-7fae7975d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686206576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2686206576
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3854249371
Short name T827
Test name
Test status
Simulation time 24064285712 ps
CPU time 86.77 seconds
Started Jun 02 01:50:53 PM PDT 24
Finished Jun 02 01:52:20 PM PDT 24
Peak memory 248848 kb
Host smart-44272eb7-c05a-4e30-b997-f65247d8aee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854249371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3854249371
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1885385319
Short name T795
Test name
Test status
Simulation time 2942378544 ps
CPU time 28.66 seconds
Started Jun 02 01:50:56 PM PDT 24
Finished Jun 02 01:51:25 PM PDT 24
Peak memory 217252 kb
Host smart-8b5b92b7-9c4c-42b4-9282-3a627ef590de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885385319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1885385319
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2927613483
Short name T396
Test name
Test status
Simulation time 70050272 ps
CPU time 2.7 seconds
Started Jun 02 01:50:53 PM PDT 24
Finished Jun 02 01:50:56 PM PDT 24
Peak memory 232324 kb
Host smart-8ff0ff0f-1dfc-4422-a628-412fe38edddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927613483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2927613483
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4152256570
Short name T484
Test name
Test status
Simulation time 52395910 ps
CPU time 2.08 seconds
Started Jun 02 01:50:55 PM PDT 24
Finished Jun 02 01:50:57 PM PDT 24
Peak memory 215620 kb
Host smart-ed210331-8a4f-4565-8deb-66baa7d01e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152256570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4152256570
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2052700107
Short name T943
Test name
Test status
Simulation time 360333278 ps
CPU time 6.83 seconds
Started Jun 02 01:50:51 PM PDT 24
Finished Jun 02 01:50:58 PM PDT 24
Peak memory 222284 kb
Host smart-f91d2dd0-2d80-491a-b3d1-d2823425e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052700107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2052700107
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.523198700
Short name T162
Test name
Test status
Simulation time 40153242003 ps
CPU time 8.12 seconds
Started Jun 02 01:50:51 PM PDT 24
Finished Jun 02 01:50:59 PM PDT 24
Peak memory 224092 kb
Host smart-cde81f5b-64a2-4042-a767-f7a3964ee39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523198700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.523198700
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3488785854
Short name T422
Test name
Test status
Simulation time 3747986045 ps
CPU time 8.22 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:51:03 PM PDT 24
Peak memory 231184 kb
Host smart-2c241473-1764-4d79-8f18-c34c74d367ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488785854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3488785854
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3601729931
Short name T147
Test name
Test status
Simulation time 1759795886 ps
CPU time 10.6 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:51:04 PM PDT 24
Peak memory 222024 kb
Host smart-13f8f775-49d8-42d8-983a-042cc1033b25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3601729931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3601729931
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1509413297
Short name T165
Test name
Test status
Simulation time 49882066 ps
CPU time 1.07 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:50:55 PM PDT 24
Peak memory 207284 kb
Host smart-a0d14421-5fef-4b0c-b328-634b225a53ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509413297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1509413297
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.355547438
Short name T475
Test name
Test status
Simulation time 16981657750 ps
CPU time 22.67 seconds
Started Jun 02 01:50:47 PM PDT 24
Finished Jun 02 01:51:10 PM PDT 24
Peak memory 220192 kb
Host smart-de54bb42-e916-4f7a-a08e-7efbf1f53d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355547438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.355547438
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2991175600
Short name T854
Test name
Test status
Simulation time 1747170440 ps
CPU time 4.96 seconds
Started Jun 02 01:50:46 PM PDT 24
Finished Jun 02 01:50:51 PM PDT 24
Peak memory 215736 kb
Host smart-e6dc6717-c052-4814-b99e-bfbf23aae472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991175600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2991175600
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1749812361
Short name T856
Test name
Test status
Simulation time 113348586 ps
CPU time 2.11 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:50:57 PM PDT 24
Peak memory 215860 kb
Host smart-4a117a46-7d5d-4ccd-8fc0-7d6465512bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749812361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1749812361
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.608030962
Short name T448
Test name
Test status
Simulation time 97340802 ps
CPU time 0.88 seconds
Started Jun 02 01:50:53 PM PDT 24
Finished Jun 02 01:50:55 PM PDT 24
Peak memory 205160 kb
Host smart-94ba4d84-b44a-4778-9fb5-8c1d8d29a5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608030962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.608030962
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2766495639
Short name T19
Test name
Test status
Simulation time 175918923 ps
CPU time 2.99 seconds
Started Jun 02 01:50:53 PM PDT 24
Finished Jun 02 01:50:56 PM PDT 24
Peak memory 233060 kb
Host smart-3c7331eb-fc68-4d3c-a243-90178e571087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766495639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2766495639
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3022715262
Short name T507
Test name
Test status
Simulation time 12957014 ps
CPU time 0.72 seconds
Started Jun 02 01:51:02 PM PDT 24
Finished Jun 02 01:51:03 PM PDT 24
Peak memory 205212 kb
Host smart-dfb998d1-4c5e-4c63-b43c-89ccb9b22c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022715262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3022715262
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3741430530
Short name T93
Test name
Test status
Simulation time 12433585002 ps
CPU time 14.03 seconds
Started Jun 02 01:50:55 PM PDT 24
Finished Jun 02 01:51:09 PM PDT 24
Peak memory 219184 kb
Host smart-f1b54876-7c64-455b-ac7b-b64c1d9095e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741430530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3741430530
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.714657816
Short name T593
Test name
Test status
Simulation time 24558938 ps
CPU time 0.8 seconds
Started Jun 02 01:50:51 PM PDT 24
Finished Jun 02 01:50:52 PM PDT 24
Peak memory 205800 kb
Host smart-dcb5cf81-b14d-4c03-b421-c5931a42e3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714657816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.714657816
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3920017031
Short name T938
Test name
Test status
Simulation time 11512170852 ps
CPU time 90.26 seconds
Started Jun 02 01:50:52 PM PDT 24
Finished Jun 02 01:52:23 PM PDT 24
Peak memory 253988 kb
Host smart-ceb51b6a-13dc-43d2-852e-beee088fd38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920017031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3920017031
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.638991002
Short name T15
Test name
Test status
Simulation time 5305131569 ps
CPU time 48.26 seconds
Started Jun 02 01:50:52 PM PDT 24
Finished Jun 02 01:51:41 PM PDT 24
Peak memory 224220 kb
Host smart-49d88dc7-cdad-46f2-aa33-9662a2a116fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638991002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.638991002
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3738796406
Short name T785
Test name
Test status
Simulation time 22450618322 ps
CPU time 190.97 seconds
Started Jun 02 01:50:53 PM PDT 24
Finished Jun 02 01:54:05 PM PDT 24
Peak memory 251352 kb
Host smart-2a37289b-0253-4f62-a7e5-127c8458316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738796406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3738796406
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1666462347
Short name T781
Test name
Test status
Simulation time 3433953094 ps
CPU time 16.93 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:51:11 PM PDT 24
Peak memory 232324 kb
Host smart-866021c7-1033-42ea-a075-fa41179bcf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666462347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1666462347
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1312748243
Short name T231
Test name
Test status
Simulation time 1364797767 ps
CPU time 5 seconds
Started Jun 02 01:50:52 PM PDT 24
Finished Jun 02 01:50:58 PM PDT 24
Peak memory 217972 kb
Host smart-7089d449-20e2-42f6-b35b-a5b80b262420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312748243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1312748243
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.860464961
Short name T839
Test name
Test status
Simulation time 1186354123 ps
CPU time 12.98 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:51:07 PM PDT 24
Peak memory 233432 kb
Host smart-dd73231b-64a8-465e-a273-cca29fe049ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860464961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.860464961
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1030857419
Short name T243
Test name
Test status
Simulation time 4485386491 ps
CPU time 13.83 seconds
Started Jun 02 01:50:53 PM PDT 24
Finished Jun 02 01:51:07 PM PDT 24
Peak memory 229640 kb
Host smart-fe98ab76-b23e-4eb8-8e2f-47551f0728b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030857419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1030857419
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4125203291
Short name T293
Test name
Test status
Simulation time 164855272 ps
CPU time 2.5 seconds
Started Jun 02 01:50:56 PM PDT 24
Finished Jun 02 01:50:59 PM PDT 24
Peak memory 216452 kb
Host smart-21b9a4a3-16eb-477f-b708-d573388c0a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125203291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4125203291
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3870351081
Short name T42
Test name
Test status
Simulation time 1922061666 ps
CPU time 12.39 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:51:07 PM PDT 24
Peak memory 221892 kb
Host smart-bfa58475-ed68-4ee8-8538-f8161337aa00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3870351081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3870351081
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.257842084
Short name T153
Test name
Test status
Simulation time 18340855206 ps
CPU time 192.09 seconds
Started Jun 02 01:50:57 PM PDT 24
Finished Jun 02 01:54:09 PM PDT 24
Peak memory 251488 kb
Host smart-36fb936e-5dab-420c-9c9a-5e7e0f221c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257842084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.257842084
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1276221919
Short name T958
Test name
Test status
Simulation time 432084721 ps
CPU time 4.71 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:50:59 PM PDT 24
Peak memory 215860 kb
Host smart-8fb459e0-0a6c-477e-b280-84247b09c969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276221919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1276221919
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1232252553
Short name T858
Test name
Test status
Simulation time 3783474023 ps
CPU time 3.34 seconds
Started Jun 02 01:50:55 PM PDT 24
Finished Jun 02 01:50:58 PM PDT 24
Peak memory 215564 kb
Host smart-3b8d3fb4-0463-47b0-bb3a-9d68f05206da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232252553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1232252553
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1833780456
Short name T689
Test name
Test status
Simulation time 75396285 ps
CPU time 0.72 seconds
Started Jun 02 01:50:52 PM PDT 24
Finished Jun 02 01:50:53 PM PDT 24
Peak memory 204880 kb
Host smart-a401caba-ff93-48af-8088-4269256c1f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833780456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1833780456
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2735096763
Short name T739
Test name
Test status
Simulation time 55799941 ps
CPU time 0.87 seconds
Started Jun 02 01:50:52 PM PDT 24
Finished Jun 02 01:50:54 PM PDT 24
Peak memory 205224 kb
Host smart-c074c515-a746-4d14-8351-d86917d945ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735096763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2735096763
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3172084805
Short name T956
Test name
Test status
Simulation time 3467854679 ps
CPU time 6.86 seconds
Started Jun 02 01:50:54 PM PDT 24
Finished Jun 02 01:51:01 PM PDT 24
Peak memory 232316 kb
Host smart-23f67e85-a6e9-49f0-905a-60d756d6f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172084805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3172084805
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2034476011
Short name T551
Test name
Test status
Simulation time 40858939 ps
CPU time 0.73 seconds
Started Jun 02 01:50:56 PM PDT 24
Finished Jun 02 01:50:57 PM PDT 24
Peak memory 204856 kb
Host smart-1fdda00e-212d-4714-b207-1e42f90e974f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034476011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2034476011
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3650505526
Short name T641
Test name
Test status
Simulation time 163134599 ps
CPU time 3.02 seconds
Started Jun 02 01:50:59 PM PDT 24
Finished Jun 02 01:51:03 PM PDT 24
Peak memory 233628 kb
Host smart-ec8286f1-0280-471f-ab01-5a06081b23dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650505526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3650505526
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1223037645
Short name T708
Test name
Test status
Simulation time 31261449 ps
CPU time 0.78 seconds
Started Jun 02 01:50:58 PM PDT 24
Finished Jun 02 01:50:59 PM PDT 24
Peak memory 205856 kb
Host smart-815f6f13-3b02-4f11-9582-17e887747cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223037645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1223037645
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3546242288
Short name T20
Test name
Test status
Simulation time 41097662034 ps
CPU time 78.1 seconds
Started Jun 02 01:50:59 PM PDT 24
Finished Jun 02 01:52:18 PM PDT 24
Peak memory 248756 kb
Host smart-5b2a02fe-1f4c-487a-9d19-9c80316c8201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546242288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3546242288
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1667188129
Short name T23
Test name
Test status
Simulation time 49647361417 ps
CPU time 127.32 seconds
Started Jun 02 01:51:01 PM PDT 24
Finished Jun 02 01:53:09 PM PDT 24
Peak memory 249984 kb
Host smart-668a5dca-74fb-474d-9e66-0bb73c92ff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667188129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1667188129
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.410049510
Short name T803
Test name
Test status
Simulation time 107729586847 ps
CPU time 209.85 seconds
Started Jun 02 01:51:00 PM PDT 24
Finished Jun 02 01:54:30 PM PDT 24
Peak memory 248812 kb
Host smart-52bf010b-0239-4c6a-a5d8-2f52026a3c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410049510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.410049510
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.49245183
Short name T553
Test name
Test status
Simulation time 12033718894 ps
CPU time 58.67 seconds
Started Jun 02 01:50:57 PM PDT 24
Finished Jun 02 01:51:56 PM PDT 24
Peak memory 240528 kb
Host smart-1c25ceb2-6af1-4a79-94a1-596e525f59e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49245183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.49245183
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4054530315
Short name T291
Test name
Test status
Simulation time 704606421 ps
CPU time 3.89 seconds
Started Jun 02 01:50:57 PM PDT 24
Finished Jun 02 01:51:01 PM PDT 24
Peak memory 233616 kb
Host smart-ca797501-aa7f-4989-82de-c1f8877f4970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054530315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4054530315
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.748775133
Short name T294
Test name
Test status
Simulation time 7675726396 ps
CPU time 10.83 seconds
Started Jun 02 01:51:00 PM PDT 24
Finished Jun 02 01:51:11 PM PDT 24
Peak memory 224164 kb
Host smart-e31694d6-bfe2-430f-9829-39858ad18e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748775133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.748775133
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2655583711
Short name T718
Test name
Test status
Simulation time 5678110780 ps
CPU time 7.4 seconds
Started Jun 02 01:51:00 PM PDT 24
Finished Jun 02 01:51:08 PM PDT 24
Peak memory 233308 kb
Host smart-b0fd1baa-9f3e-4db0-ab2c-5f88ecdee1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655583711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2655583711
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4288608440
Short name T784
Test name
Test status
Simulation time 470514092 ps
CPU time 6.21 seconds
Started Jun 02 01:50:57 PM PDT 24
Finished Jun 02 01:51:04 PM PDT 24
Peak memory 233308 kb
Host smart-6f16109c-64b6-4375-8a60-4043ee2bcf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288608440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4288608440
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3070358771
Short name T672
Test name
Test status
Simulation time 740636723 ps
CPU time 9.59 seconds
Started Jun 02 01:50:57 PM PDT 24
Finished Jun 02 01:51:07 PM PDT 24
Peak memory 220824 kb
Host smart-49440cca-dd11-4b64-9a90-56d663a67e7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3070358771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3070358771
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3035959980
Short name T303
Test name
Test status
Simulation time 175355180428 ps
CPU time 497.32 seconds
Started Jun 02 01:50:56 PM PDT 24
Finished Jun 02 01:59:14 PM PDT 24
Peak memory 264776 kb
Host smart-d7df5a3b-b56c-434d-ab9b-5d6da934f63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035959980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3035959980
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.49303910
Short name T722
Test name
Test status
Simulation time 9319268220 ps
CPU time 47.39 seconds
Started Jun 02 01:51:00 PM PDT 24
Finished Jun 02 01:51:47 PM PDT 24
Peak memory 215900 kb
Host smart-c53e7ff3-39e8-45b7-887d-6f85e50d09d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49303910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.49303910
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1515347409
Short name T850
Test name
Test status
Simulation time 3080653783 ps
CPU time 8.86 seconds
Started Jun 02 01:50:56 PM PDT 24
Finished Jun 02 01:51:05 PM PDT 24
Peak memory 215828 kb
Host smart-67f90572-8e21-49d1-98e8-46f7a3c355e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515347409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1515347409
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2742404972
Short name T400
Test name
Test status
Simulation time 17658024 ps
CPU time 0.95 seconds
Started Jun 02 01:50:57 PM PDT 24
Finished Jun 02 01:50:58 PM PDT 24
Peak memory 206620 kb
Host smart-e934a712-e01c-455a-b921-2468217909c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742404972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2742404972
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3541639817
Short name T613
Test name
Test status
Simulation time 84033895 ps
CPU time 0.74 seconds
Started Jun 02 01:50:58 PM PDT 24
Finished Jun 02 01:50:59 PM PDT 24
Peak memory 205224 kb
Host smart-688b2fd0-5430-4ac5-9e81-04c7d707710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541639817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3541639817
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1932917804
Short name T449
Test name
Test status
Simulation time 8495767503 ps
CPU time 10.32 seconds
Started Jun 02 01:51:02 PM PDT 24
Finished Jun 02 01:51:12 PM PDT 24
Peak memory 218848 kb
Host smart-016835b5-f85f-4e60-ba6b-b4d8283c06eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932917804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1932917804
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2654607766
Short name T622
Test name
Test status
Simulation time 37282586 ps
CPU time 0.72 seconds
Started Jun 02 01:51:04 PM PDT 24
Finished Jun 02 01:51:05 PM PDT 24
Peak memory 205204 kb
Host smart-cab00844-a0f3-4653-b483-724db762e1d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654607766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2654607766
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.25637876
Short name T805
Test name
Test status
Simulation time 246815488 ps
CPU time 5.52 seconds
Started Jun 02 01:51:03 PM PDT 24
Finished Jun 02 01:51:09 PM PDT 24
Peak memory 219144 kb
Host smart-d70f9324-61f2-4e47-a267-683656f69a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25637876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.25637876
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1366723534
Short name T473
Test name
Test status
Simulation time 60762361 ps
CPU time 0.76 seconds
Started Jun 02 01:50:59 PM PDT 24
Finished Jun 02 01:51:00 PM PDT 24
Peak memory 205864 kb
Host smart-5908338c-23d0-4265-9822-1f4b2941e43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366723534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1366723534
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.54912797
Short name T501
Test name
Test status
Simulation time 7041687310 ps
CPU time 40.09 seconds
Started Jun 02 01:51:01 PM PDT 24
Finished Jun 02 01:51:42 PM PDT 24
Peak memory 249272 kb
Host smart-d7e2e026-4833-40de-9030-d2984420c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54912797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.54912797
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1566806618
Short name T83
Test name
Test status
Simulation time 87737421938 ps
CPU time 185.06 seconds
Started Jun 02 01:51:03 PM PDT 24
Finished Jun 02 01:54:09 PM PDT 24
Peak memory 249108 kb
Host smart-6778eb8b-119c-4238-b85b-8a65a2cce81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566806618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1566806618
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1428013203
Short name T139
Test name
Test status
Simulation time 6317928286 ps
CPU time 92.75 seconds
Started Jun 02 01:51:03 PM PDT 24
Finished Jun 02 01:52:36 PM PDT 24
Peak memory 255756 kb
Host smart-84cfc6bf-a31d-4377-86ac-4a192f7692cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428013203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1428013203
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1339603327
Short name T327
Test name
Test status
Simulation time 353194581 ps
CPU time 5.18 seconds
Started Jun 02 01:51:04 PM PDT 24
Finished Jun 02 01:51:09 PM PDT 24
Peak memory 232320 kb
Host smart-7e7d85cb-5bb8-4103-8b3d-579cc3a935b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339603327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1339603327
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1469765206
Short name T44
Test name
Test status
Simulation time 124641010 ps
CPU time 3.26 seconds
Started Jun 02 01:51:03 PM PDT 24
Finished Jun 02 01:51:07 PM PDT 24
Peak memory 218252 kb
Host smart-855c918b-3eb5-4cb1-8ea5-958c44cc5722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469765206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1469765206
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1497604836
Short name T621
Test name
Test status
Simulation time 57093021 ps
CPU time 2.63 seconds
Started Jun 02 01:51:03 PM PDT 24
Finished Jun 02 01:51:06 PM PDT 24
Peak memory 218136 kb
Host smart-19e0ac08-5942-4077-96d9-391c984ff574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497604836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1497604836
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.658626289
Short name T344
Test name
Test status
Simulation time 81610129 ps
CPU time 2.41 seconds
Started Jun 02 01:51:03 PM PDT 24
Finished Jun 02 01:51:06 PM PDT 24
Peak memory 220940 kb
Host smart-bd50b516-1899-442a-adc4-4d5bd70734fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658626289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.658626289
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.954140007
Short name T951
Test name
Test status
Simulation time 83700105277 ps
CPU time 13.07 seconds
Started Jun 02 01:51:04 PM PDT 24
Finished Jun 02 01:51:17 PM PDT 24
Peak memory 218020 kb
Host smart-7cc1281a-c56c-4787-ba3e-5835192708d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954140007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.954140007
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.120650968
Short name T389
Test name
Test status
Simulation time 512308740 ps
CPU time 7.57 seconds
Started Jun 02 01:51:02 PM PDT 24
Finished Jun 02 01:51:10 PM PDT 24
Peak memory 222368 kb
Host smart-cfd7bd9c-a83d-401e-9beb-60d7224d0f2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=120650968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.120650968
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2532973387
Short name T58
Test name
Test status
Simulation time 12652833466 ps
CPU time 190.76 seconds
Started Jun 02 01:51:02 PM PDT 24
Finished Jun 02 01:54:13 PM PDT 24
Peak memory 256944 kb
Host smart-0d9b4765-3b09-47ed-8fea-a50180d89208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532973387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2532973387
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3351407372
Short name T602
Test name
Test status
Simulation time 4128843609 ps
CPU time 23.04 seconds
Started Jun 02 01:51:00 PM PDT 24
Finished Jun 02 01:51:24 PM PDT 24
Peak memory 215884 kb
Host smart-b0f390f9-6e1f-45f2-9874-28b818e5ad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351407372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3351407372
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4135857990
Short name T576
Test name
Test status
Simulation time 46809783 ps
CPU time 0.77 seconds
Started Jun 02 01:50:57 PM PDT 24
Finished Jun 02 01:50:58 PM PDT 24
Peak memory 204924 kb
Host smart-5bb4dc37-7e57-4661-9888-a63ca13d8b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135857990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4135857990
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4083782457
Short name T702
Test name
Test status
Simulation time 18575407 ps
CPU time 0.73 seconds
Started Jun 02 01:51:03 PM PDT 24
Finished Jun 02 01:51:04 PM PDT 24
Peak memory 204888 kb
Host smart-8bf7e05a-13cc-40e7-b298-fc9987f2a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083782457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4083782457
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2269809760
Short name T818
Test name
Test status
Simulation time 65927326 ps
CPU time 0.97 seconds
Started Jun 02 01:51:00 PM PDT 24
Finished Jun 02 01:51:01 PM PDT 24
Peak memory 205252 kb
Host smart-41fa5881-8786-45aa-8a35-8ff491185499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269809760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2269809760
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2220982539
Short name T646
Test name
Test status
Simulation time 12515048599 ps
CPU time 48.21 seconds
Started Jun 02 01:51:05 PM PDT 24
Finished Jun 02 01:51:54 PM PDT 24
Peak memory 244564 kb
Host smart-724d7ba0-3754-4829-b2df-054cc7055d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220982539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2220982539
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1227319480
Short name T653
Test name
Test status
Simulation time 58282326 ps
CPU time 0.7 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:51:08 PM PDT 24
Peak memory 204836 kb
Host smart-2abc5549-e4d3-49ae-aa90-0b9b690902ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227319480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1227319480
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2712654120
Short name T770
Test name
Test status
Simulation time 138933917 ps
CPU time 2.33 seconds
Started Jun 02 01:51:10 PM PDT 24
Finished Jun 02 01:51:13 PM PDT 24
Peak memory 224012 kb
Host smart-76833d48-3f42-4764-a7d1-f4f39ae9d0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712654120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2712654120
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.380077172
Short name T505
Test name
Test status
Simulation time 68843599 ps
CPU time 0.79 seconds
Started Jun 02 01:51:04 PM PDT 24
Finished Jun 02 01:51:05 PM PDT 24
Peak memory 206124 kb
Host smart-fc76089e-606e-4b85-8373-8c6050127022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380077172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.380077172
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.419796087
Short name T792
Test name
Test status
Simulation time 3553857320 ps
CPU time 5.11 seconds
Started Jun 02 01:51:10 PM PDT 24
Finished Jun 02 01:51:16 PM PDT 24
Peak memory 224168 kb
Host smart-0b530c6a-778e-441d-b505-44bd813d2ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419796087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.419796087
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1355063903
Short name T873
Test name
Test status
Simulation time 17177767792 ps
CPU time 64.96 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:52:12 PM PDT 24
Peak memory 236708 kb
Host smart-d506a1d8-8860-4c2b-aec5-39a9366a2a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355063903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1355063903
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3050399186
Short name T137
Test name
Test status
Simulation time 1694136042 ps
CPU time 34.55 seconds
Started Jun 02 01:51:09 PM PDT 24
Finished Jun 02 01:51:44 PM PDT 24
Peak memory 248240 kb
Host smart-760126a1-ef02-4e45-8019-27e5991abc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050399186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3050399186
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3891526966
Short name T222
Test name
Test status
Simulation time 1713954722 ps
CPU time 22.74 seconds
Started Jun 02 01:51:11 PM PDT 24
Finished Jun 02 01:51:34 PM PDT 24
Peak memory 232876 kb
Host smart-131d895a-19bb-4f82-b7a6-888918ed2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891526966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3891526966
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2252213887
Short name T836
Test name
Test status
Simulation time 311060692 ps
CPU time 2.67 seconds
Started Jun 02 01:51:08 PM PDT 24
Finished Jun 02 01:51:11 PM PDT 24
Peak memory 232304 kb
Host smart-a7876b68-caef-4b40-99fc-a2018b379f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252213887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2252213887
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.712355202
Short name T733
Test name
Test status
Simulation time 41184234423 ps
CPU time 51.39 seconds
Started Jun 02 01:51:10 PM PDT 24
Finished Jun 02 01:52:02 PM PDT 24
Peak memory 219856 kb
Host smart-d6bf890c-414b-43d8-b4a9-304e5a709237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712355202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.712355202
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3639184619
Short name T522
Test name
Test status
Simulation time 1027150564 ps
CPU time 4.9 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:51:12 PM PDT 24
Peak memory 224124 kb
Host smart-9ba1db9e-28db-4018-a5df-3b086bb9f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639184619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3639184619
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.264713525
Short name T210
Test name
Test status
Simulation time 100388479 ps
CPU time 2.19 seconds
Started Jun 02 01:51:09 PM PDT 24
Finished Jun 02 01:51:12 PM PDT 24
Peak memory 218416 kb
Host smart-5f1a6957-a712-46af-899d-0a3650d1e9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264713525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.264713525
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3834072369
Short name T711
Test name
Test status
Simulation time 1191316523 ps
CPU time 4.27 seconds
Started Jun 02 01:51:09 PM PDT 24
Finished Jun 02 01:51:14 PM PDT 24
Peak memory 219384 kb
Host smart-1c7f3b2e-3bdd-4467-b764-b50efe0ba8e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3834072369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3834072369
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3771291450
Short name T921
Test name
Test status
Simulation time 1653424359 ps
CPU time 34.31 seconds
Started Jun 02 01:51:08 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 248680 kb
Host smart-55ed2b98-60d5-4e33-9a51-69c47cd3f05a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771291450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3771291450
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.112587165
Short name T74
Test name
Test status
Simulation time 2218647706 ps
CPU time 13.18 seconds
Started Jun 02 01:51:02 PM PDT 24
Finished Jun 02 01:51:16 PM PDT 24
Peak memory 215904 kb
Host smart-e096b013-db67-4568-9f5f-8ce54f3e5fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112587165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.112587165
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1349424845
Short name T414
Test name
Test status
Simulation time 21704131041 ps
CPU time 15.22 seconds
Started Jun 02 01:51:03 PM PDT 24
Finished Jun 02 01:51:19 PM PDT 24
Peak memory 215812 kb
Host smart-1085637e-36a2-49b2-8165-1b685e12a02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349424845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1349424845
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.8541675
Short name T6
Test name
Test status
Simulation time 42389051 ps
CPU time 0.98 seconds
Started Jun 02 01:51:09 PM PDT 24
Finished Jun 02 01:51:10 PM PDT 24
Peak memory 206220 kb
Host smart-db374368-1b75-49ab-8a82-13083744d06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8541675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.8541675
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1005860932
Short name T352
Test name
Test status
Simulation time 24678862 ps
CPU time 0.81 seconds
Started Jun 02 01:51:02 PM PDT 24
Finished Jun 02 01:51:04 PM PDT 24
Peak memory 205224 kb
Host smart-6ef6eaee-c0b7-4daf-9c9c-6493ad57270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005860932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1005860932
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.655789804
Short name T810
Test name
Test status
Simulation time 38495728 ps
CPU time 2.27 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:51:10 PM PDT 24
Peak memory 212704 kb
Host smart-71017104-c9ed-4df6-aec5-804f3fa13641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655789804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.655789804
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1383606414
Short name T359
Test name
Test status
Simulation time 29451841 ps
CPU time 0.7 seconds
Started Jun 02 01:51:14 PM PDT 24
Finished Jun 02 01:51:15 PM PDT 24
Peak memory 205204 kb
Host smart-c2931856-7b7b-4f86-aaf7-f8223322c10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383606414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1383606414
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3356199321
Short name T360
Test name
Test status
Simulation time 291292422 ps
CPU time 4.71 seconds
Started Jun 02 01:51:10 PM PDT 24
Finished Jun 02 01:51:15 PM PDT 24
Peak memory 219152 kb
Host smart-68bfc664-f767-4c23-92b7-4394ed2e27ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356199321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3356199321
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.16297803
Short name T650
Test name
Test status
Simulation time 55982986 ps
CPU time 0.74 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:51:08 PM PDT 24
Peak memory 204820 kb
Host smart-d8070c8f-987f-4dce-a6f6-32cecfdfaaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16297803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.16297803
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2394084703
Short name T323
Test name
Test status
Simulation time 150831814863 ps
CPU time 240.63 seconds
Started Jun 02 01:51:10 PM PDT 24
Finished Jun 02 01:55:11 PM PDT 24
Peak memory 271476 kb
Host smart-16deb71d-84c9-443b-83fa-fadb4443e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394084703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2394084703
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4131520745
Short name T668
Test name
Test status
Simulation time 743462631 ps
CPU time 2.05 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:17 PM PDT 24
Peak memory 216908 kb
Host smart-733275ae-927f-4681-93cb-96ca4ff1125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131520745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4131520745
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3232090671
Short name T820
Test name
Test status
Simulation time 2690104630 ps
CPU time 9.97 seconds
Started Jun 02 01:51:09 PM PDT 24
Finished Jun 02 01:51:20 PM PDT 24
Peak memory 224196 kb
Host smart-4d93cb52-a9c8-40b4-acef-92edeb6b3e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232090671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3232090671
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.551148271
Short name T91
Test name
Test status
Simulation time 467722654 ps
CPU time 4.27 seconds
Started Jun 02 01:51:06 PM PDT 24
Finished Jun 02 01:51:11 PM PDT 24
Peak memory 235992 kb
Host smart-6ecbace4-a54d-4ef1-99bc-227d20037e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551148271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.551148271
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2836671185
Short name T370
Test name
Test status
Simulation time 29677920266 ps
CPU time 54.24 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:52:01 PM PDT 24
Peak memory 233320 kb
Host smart-9ddc9b4f-e28c-4921-b95b-641ff2859b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836671185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2836671185
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2812595280
Short name T280
Test name
Test status
Simulation time 596459262 ps
CPU time 5.43 seconds
Started Jun 02 01:51:12 PM PDT 24
Finished Jun 02 01:51:18 PM PDT 24
Peak memory 233164 kb
Host smart-9d1202b4-d64c-4a2d-b4dd-18b5fa26b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812595280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2812595280
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2800318174
Short name T774
Test name
Test status
Simulation time 5139343881 ps
CPU time 3.46 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:51:11 PM PDT 24
Peak memory 224148 kb
Host smart-e1c825cf-1670-4f95-8b76-052c6d49ec67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800318174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2800318174
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3351831342
Short name T910
Test name
Test status
Simulation time 1578885581 ps
CPU time 4.7 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:51:13 PM PDT 24
Peak memory 218964 kb
Host smart-7fb025f2-3bf3-4541-b29c-2a87a1db5480
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3351831342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3351831342
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.265803419
Short name T50
Test name
Test status
Simulation time 54987178397 ps
CPU time 224.44 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:55:00 PM PDT 24
Peak memory 248340 kb
Host smart-e27d9624-1727-4de0-a853-3b433f33944a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265803419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.265803419
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3698568176
Short name T835
Test name
Test status
Simulation time 1071753553 ps
CPU time 16.11 seconds
Started Jun 02 01:51:10 PM PDT 24
Finished Jun 02 01:51:26 PM PDT 24
Peak memory 215856 kb
Host smart-bb59efbf-0548-4dd0-bdc7-8fade820a651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698568176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3698568176
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1591997710
Short name T703
Test name
Test status
Simulation time 1261293630 ps
CPU time 8.72 seconds
Started Jun 02 01:51:08 PM PDT 24
Finished Jun 02 01:51:17 PM PDT 24
Peak memory 215744 kb
Host smart-cf3a5c3d-d029-4a8d-b082-a5adc933f6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591997710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1591997710
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.823453438
Short name T879
Test name
Test status
Simulation time 10638754 ps
CPU time 0.69 seconds
Started Jun 02 01:51:09 PM PDT 24
Finished Jun 02 01:51:11 PM PDT 24
Peak memory 204904 kb
Host smart-f4b3b6ac-6019-4a0f-9726-725214daf939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823453438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.823453438
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.359096408
Short name T89
Test name
Test status
Simulation time 104577124 ps
CPU time 0.78 seconds
Started Jun 02 01:51:07 PM PDT 24
Finished Jun 02 01:51:08 PM PDT 24
Peak memory 205148 kb
Host smart-cc6380d2-3e36-4733-aff7-d973ea334057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359096408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.359096408
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4014766262
Short name T249
Test name
Test status
Simulation time 10685741759 ps
CPU time 13.16 seconds
Started Jun 02 01:51:08 PM PDT 24
Finished Jun 02 01:51:22 PM PDT 24
Peak memory 238416 kb
Host smart-1f9a3019-16aa-4b52-8345-2d540e78f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014766262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4014766262
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2739786002
Short name T436
Test name
Test status
Simulation time 23743103 ps
CPU time 0.72 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:16 PM PDT 24
Peak memory 204824 kb
Host smart-bd10db8e-5414-47fe-ba88-7966d030ae30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739786002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2739786002
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1797687457
Short name T895
Test name
Test status
Simulation time 146639356 ps
CPU time 2.9 seconds
Started Jun 02 01:51:14 PM PDT 24
Finished Jun 02 01:51:17 PM PDT 24
Peak memory 233092 kb
Host smart-e346a0d4-e8e3-44fa-80c6-b6526daa9201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797687457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1797687457
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1842835265
Short name T420
Test name
Test status
Simulation time 60418405 ps
CPU time 0.8 seconds
Started Jun 02 01:51:18 PM PDT 24
Finished Jun 02 01:51:19 PM PDT 24
Peak memory 204944 kb
Host smart-fc875b2c-0025-4714-8cda-846585795670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842835265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1842835265
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1287874570
Short name T698
Test name
Test status
Simulation time 7707793453 ps
CPU time 36.89 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:53 PM PDT 24
Peak memory 232340 kb
Host smart-2afca970-8917-4a5e-be62-cf88f4381ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287874570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1287874570
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2844433610
Short name T320
Test name
Test status
Simulation time 57284883778 ps
CPU time 230.63 seconds
Started Jun 02 01:51:14 PM PDT 24
Finished Jun 02 01:55:04 PM PDT 24
Peak memory 255492 kb
Host smart-1b214d5f-2c9f-46e2-ac23-9dc15e2d5ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844433610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2844433610
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3333348029
Short name T693
Test name
Test status
Simulation time 4865649814 ps
CPU time 11.73 seconds
Started Jun 02 01:51:16 PM PDT 24
Finished Jun 02 01:51:28 PM PDT 24
Peak memory 232380 kb
Host smart-17663a64-ae20-4f2f-a0fd-0ea97e51272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333348029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3333348029
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4183000003
Short name T705
Test name
Test status
Simulation time 3362503416 ps
CPU time 10.62 seconds
Started Jun 02 01:51:16 PM PDT 24
Finished Jun 02 01:51:27 PM PDT 24
Peak memory 234492 kb
Host smart-1952ac01-9678-4d72-9566-e4be73dd8ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183000003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4183000003
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4219515762
Short name T206
Test name
Test status
Simulation time 5296862325 ps
CPU time 65.18 seconds
Started Jun 02 01:51:16 PM PDT 24
Finished Jun 02 01:52:22 PM PDT 24
Peak memory 224128 kb
Host smart-44283714-d62c-4da0-84cb-a7bd828a21a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219515762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4219515762
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3344816615
Short name T685
Test name
Test status
Simulation time 3488689110 ps
CPU time 9.65 seconds
Started Jun 02 01:51:14 PM PDT 24
Finished Jun 02 01:51:24 PM PDT 24
Peak memory 218380 kb
Host smart-8aea68ad-6b92-4917-951d-f5242fdd6eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344816615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3344816615
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1503758094
Short name T600
Test name
Test status
Simulation time 476755195 ps
CPU time 2.15 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:18 PM PDT 24
Peak memory 216472 kb
Host smart-6d185336-9e31-4e7d-af49-f0ef1ddcbce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503758094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1503758094
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2820061770
Short name T875
Test name
Test status
Simulation time 6400760080 ps
CPU time 19.6 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:35 PM PDT 24
Peak memory 218804 kb
Host smart-497e0b47-f6e7-4b45-8b4d-5a17d8be288e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2820061770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2820061770
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3950748686
Short name T67
Test name
Test status
Simulation time 6331296888 ps
CPU time 65.02 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:52:21 PM PDT 24
Peak memory 250432 kb
Host smart-d26a8243-2bf2-4c39-b210-422750628ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950748686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3950748686
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3029264711
Short name T405
Test name
Test status
Simulation time 1139610113 ps
CPU time 5.91 seconds
Started Jun 02 01:51:17 PM PDT 24
Finished Jun 02 01:51:24 PM PDT 24
Peak memory 216080 kb
Host smart-418467c8-10d9-4e09-bb9b-f65891a71a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029264711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3029264711
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2191593634
Short name T732
Test name
Test status
Simulation time 22926803 ps
CPU time 0.69 seconds
Started Jun 02 01:51:14 PM PDT 24
Finished Jun 02 01:51:15 PM PDT 24
Peak memory 204960 kb
Host smart-64b71f14-e888-4977-9173-605230a412a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191593634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2191593634
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4128868665
Short name T737
Test name
Test status
Simulation time 199543259 ps
CPU time 1.13 seconds
Started Jun 02 01:51:13 PM PDT 24
Finished Jun 02 01:51:14 PM PDT 24
Peak memory 207400 kb
Host smart-9581e0fd-535f-4c32-bf21-105d840340cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128868665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4128868665
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4046174713
Short name T339
Test name
Test status
Simulation time 13255065 ps
CPU time 0.71 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:16 PM PDT 24
Peak memory 204804 kb
Host smart-1b9895b5-eef1-4592-a108-4a930ed02f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046174713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4046174713
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3884668913
Short name T679
Test name
Test status
Simulation time 509384563 ps
CPU time 2.82 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:18 PM PDT 24
Peak memory 218268 kb
Host smart-8dcf3687-79fa-4f97-9a58-f71833ea53b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884668913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3884668913
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1886550004
Short name T416
Test name
Test status
Simulation time 107651426 ps
CPU time 0.72 seconds
Started Jun 02 01:51:19 PM PDT 24
Finished Jun 02 01:51:20 PM PDT 24
Peak memory 204148 kb
Host smart-98908a7c-99ce-4c88-8436-5bb54b004d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886550004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1886550004
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2256293624
Short name T933
Test name
Test status
Simulation time 399838918 ps
CPU time 3.24 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:30 PM PDT 24
Peak memory 234176 kb
Host smart-cd7323ab-3a71-4438-a58b-945e660bf792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256293624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2256293624
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3714234306
Short name T536
Test name
Test status
Simulation time 13576709 ps
CPU time 0.77 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:17 PM PDT 24
Peak memory 206108 kb
Host smart-60418942-c0b3-40b1-9cb7-e19e4e788f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714234306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3714234306
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2863852676
Short name T489
Test name
Test status
Simulation time 147318285433 ps
CPU time 240.9 seconds
Started Jun 02 01:51:22 PM PDT 24
Finished Jun 02 01:55:23 PM PDT 24
Peak memory 248768 kb
Host smart-575d50c5-cf04-4988-8b8d-e54e5ba858a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863852676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2863852676
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2164579391
Short name T315
Test name
Test status
Simulation time 42220076324 ps
CPU time 167.54 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:54:09 PM PDT 24
Peak memory 256080 kb
Host smart-9fd7c06d-cac9-4107-a098-26b62b5e4ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164579391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2164579391
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1374521621
Short name T519
Test name
Test status
Simulation time 3874870197 ps
CPU time 32.48 seconds
Started Jun 02 01:51:22 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 240576 kb
Host smart-bfeb39a2-5001-45ad-9529-c7d06680e01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374521621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1374521621
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.925584574
Short name T525
Test name
Test status
Simulation time 287906633 ps
CPU time 5.52 seconds
Started Jun 02 01:51:28 PM PDT 24
Finished Jun 02 01:51:34 PM PDT 24
Peak memory 233548 kb
Host smart-88f7f163-38d5-48f2-973a-bc959305e9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925584574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.925584574
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.51723591
Short name T383
Test name
Test status
Simulation time 2836617566 ps
CPU time 23.44 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:51:45 PM PDT 24
Peak memory 234276 kb
Host smart-aab6eb95-2045-4023-9610-8ee8b61d7231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51723591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.51723591
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1947776661
Short name T725
Test name
Test status
Simulation time 545444966 ps
CPU time 3.92 seconds
Started Jun 02 01:51:19 PM PDT 24
Finished Jun 02 01:51:23 PM PDT 24
Peak memory 233736 kb
Host smart-ed96834d-f4f2-4ad2-aaff-f489ae9ada26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947776661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1947776661
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.960106561
Short name T851
Test name
Test status
Simulation time 5254244647 ps
CPU time 7.45 seconds
Started Jun 02 01:51:20 PM PDT 24
Finished Jun 02 01:51:28 PM PDT 24
Peak memory 233336 kb
Host smart-96077ac5-1a57-48b7-a603-52b16fa7afd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960106561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.960106561
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2944946602
Short name T41
Test name
Test status
Simulation time 7149243068 ps
CPU time 13.92 seconds
Started Jun 02 01:51:20 PM PDT 24
Finished Jun 02 01:51:35 PM PDT 24
Peak memory 219968 kb
Host smart-b6942373-e1bb-4083-9541-3ad0f6893f0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2944946602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2944946602
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.163631815
Short name T142
Test name
Test status
Simulation time 25647762831 ps
CPU time 145.8 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:53:47 PM PDT 24
Peak memory 263192 kb
Host smart-02ec835c-3737-4182-b933-747893b60987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163631815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.163631815
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3720605319
Short name T337
Test name
Test status
Simulation time 2805789942 ps
CPU time 21.84 seconds
Started Jun 02 01:51:16 PM PDT 24
Finished Jun 02 01:51:38 PM PDT 24
Peak memory 215920 kb
Host smart-2b093894-db4b-428f-a5fa-01bf9869c484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720605319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3720605319
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1830678461
Short name T675
Test name
Test status
Simulation time 1180374041 ps
CPU time 5.66 seconds
Started Jun 02 01:51:15 PM PDT 24
Finished Jun 02 01:51:21 PM PDT 24
Peak memory 215704 kb
Host smart-46d562a2-524c-44ec-a6a9-227e556e1f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830678461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1830678461
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.298004486
Short name T394
Test name
Test status
Simulation time 76120462 ps
CPU time 0.85 seconds
Started Jun 02 01:51:20 PM PDT 24
Finished Jun 02 01:51:21 PM PDT 24
Peak memory 205284 kb
Host smart-fd5818fb-b512-4f91-83a4-f7c57815e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298004486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.298004486
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1147552157
Short name T660
Test name
Test status
Simulation time 267584052 ps
CPU time 1.03 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:51:23 PM PDT 24
Peak memory 206244 kb
Host smart-8b08f175-2c57-4d03-83b6-b54896c14f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147552157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1147552157
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2421373572
Short name T912
Test name
Test status
Simulation time 509706972 ps
CPU time 8.41 seconds
Started Jun 02 01:51:20 PM PDT 24
Finished Jun 02 01:51:29 PM PDT 24
Peak memory 248504 kb
Host smart-f5d2f401-7d3a-4cd1-9b08-cb6cd5d14ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421373572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2421373572
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.102552098
Short name T843
Test name
Test status
Simulation time 30239701 ps
CPU time 0.7 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:51:27 PM PDT 24
Peak memory 204152 kb
Host smart-54182d23-3603-46b8-9ca8-864f95062934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102552098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.102552098
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3680007606
Short name T676
Test name
Test status
Simulation time 134746912 ps
CPU time 2.76 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:51:24 PM PDT 24
Peak memory 233436 kb
Host smart-36455053-45bc-4f30-a26a-fa4d87049915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680007606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3680007606
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2988162776
Short name T562
Test name
Test status
Simulation time 37806263 ps
CPU time 0.78 seconds
Started Jun 02 01:51:22 PM PDT 24
Finished Jun 02 01:51:23 PM PDT 24
Peak memory 206184 kb
Host smart-f11b1b25-acb4-4e67-9f69-13f1695504d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988162776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2988162776
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1222119566
Short name T310
Test name
Test status
Simulation time 252209719331 ps
CPU time 297.58 seconds
Started Jun 02 01:51:22 PM PDT 24
Finished Jun 02 01:56:20 PM PDT 24
Peak memory 240540 kb
Host smart-0e6a5979-fc3b-4af8-9cd1-afb422b3bc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222119566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1222119566
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.588055886
Short name T626
Test name
Test status
Simulation time 74271118615 ps
CPU time 194.29 seconds
Started Jun 02 01:51:22 PM PDT 24
Finished Jun 02 01:54:37 PM PDT 24
Peak memory 253840 kb
Host smart-26423d66-1f68-40b5-b45e-8617bc15fa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588055886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.588055886
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.506811112
Short name T518
Test name
Test status
Simulation time 47650497335 ps
CPU time 114.32 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:53:16 PM PDT 24
Peak memory 250696 kb
Host smart-a9530901-20db-4f59-9ff8-9fe235b4ce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506811112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.506811112
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3727373666
Short name T39
Test name
Test status
Simulation time 622246836 ps
CPU time 7.87 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:35 PM PDT 24
Peak memory 224084 kb
Host smart-a939c602-56ed-4020-9758-e069a6a928e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727373666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3727373666
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4082687832
Short name T189
Test name
Test status
Simulation time 890486026 ps
CPU time 2.94 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:51:25 PM PDT 24
Peak memory 216128 kb
Host smart-e8ce1670-3ca4-46f5-b40a-27acdb371fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082687832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4082687832
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.619850918
Short name T823
Test name
Test status
Simulation time 28941661837 ps
CPU time 38.25 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:52:00 PM PDT 24
Peak memory 235108 kb
Host smart-75c7e910-91c0-4ac0-bd71-77e2c718d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619850918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.619850918
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2719015110
Short name T920
Test name
Test status
Simulation time 400209696 ps
CPU time 2.96 seconds
Started Jun 02 01:51:20 PM PDT 24
Finished Jun 02 01:51:24 PM PDT 24
Peak memory 218112 kb
Host smart-67c85314-668e-435b-84e3-ed174c801025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719015110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2719015110
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3585840938
Short name T868
Test name
Test status
Simulation time 366804272 ps
CPU time 5.17 seconds
Started Jun 02 01:51:28 PM PDT 24
Finished Jun 02 01:51:34 PM PDT 24
Peak memory 233712 kb
Host smart-57a665e7-30c7-4e62-a00d-701dcbfabf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585840938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3585840938
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2330929866
Short name T94
Test name
Test status
Simulation time 1139920501 ps
CPU time 5.25 seconds
Started Jun 02 01:51:22 PM PDT 24
Finished Jun 02 01:51:27 PM PDT 24
Peak memory 222636 kb
Host smart-8a144c7b-c993-4518-9791-7fc613ea5431
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2330929866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2330929866
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1968276085
Short name T967
Test name
Test status
Simulation time 50324548 ps
CPU time 1.06 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:51:23 PM PDT 24
Peak memory 206372 kb
Host smart-14e96b4f-379d-4438-bd1f-0cb7e89ee9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968276085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1968276085
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1694363535
Short name T778
Test name
Test status
Simulation time 14433159738 ps
CPU time 45.66 seconds
Started Jun 02 01:51:22 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 215860 kb
Host smart-be24636e-eae3-4eb1-94c6-8fba1a7529fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694363535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1694363535
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2881340348
Short name T421
Test name
Test status
Simulation time 5241244295 ps
CPU time 5.99 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:51:27 PM PDT 24
Peak memory 215812 kb
Host smart-37b41831-c25f-463b-96e4-0172114829d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881340348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2881340348
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3604479760
Short name T438
Test name
Test status
Simulation time 28063900 ps
CPU time 1.07 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:51:22 PM PDT 24
Peak memory 206800 kb
Host smart-f46da14d-c755-4521-bae7-8dd7a9d4e95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604479760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3604479760
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3188206003
Short name T699
Test name
Test status
Simulation time 270488303 ps
CPU time 0.99 seconds
Started Jun 02 01:51:23 PM PDT 24
Finished Jun 02 01:51:24 PM PDT 24
Peak memory 206204 kb
Host smart-dec6d555-ed02-493b-ab20-84bf0e1e61c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188206003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3188206003
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2585939877
Short name T292
Test name
Test status
Simulation time 256502706 ps
CPU time 2.62 seconds
Started Jun 02 01:51:21 PM PDT 24
Finished Jun 02 01:51:24 PM PDT 24
Peak memory 224136 kb
Host smart-4215435e-4e0f-46a6-913b-6ecdb2b686fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585939877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2585939877
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.402659524
Short name T604
Test name
Test status
Simulation time 31202415 ps
CPU time 0.72 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:29 PM PDT 24
Peak memory 204188 kb
Host smart-c55ef0f2-479f-4035-941b-1a540b51324d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402659524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.402659524
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.886950733
Short name T509
Test name
Test status
Simulation time 5311424842 ps
CPU time 8.07 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:36 PM PDT 24
Peak memory 234376 kb
Host smart-4410999a-431b-4e50-b74d-7a5704e56a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886950733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.886950733
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4021948716
Short name T340
Test name
Test status
Simulation time 18482648 ps
CPU time 0.75 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:51:27 PM PDT 24
Peak memory 204768 kb
Host smart-1af72fd1-331f-492e-ab63-6a17d40a320f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021948716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4021948716
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.337276139
Short name T946
Test name
Test status
Simulation time 2084835964 ps
CPU time 28.08 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:56 PM PDT 24
Peak memory 248688 kb
Host smart-56a6b10f-1c11-43f0-8b61-09cd76f89f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337276139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.337276139
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2985191941
Short name T317
Test name
Test status
Simulation time 35048119317 ps
CPU time 340.69 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:57:09 PM PDT 24
Peak memory 249228 kb
Host smart-5ce10dce-cdb5-4604-986f-0f689cfa0141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985191941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2985191941
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1732934208
Short name T207
Test name
Test status
Simulation time 30003449306 ps
CPU time 126.19 seconds
Started Jun 02 01:51:28 PM PDT 24
Finished Jun 02 01:53:35 PM PDT 24
Peak memory 256060 kb
Host smart-eb156264-99f5-4888-b51c-a87f2904f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732934208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1732934208
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2929416383
Short name T172
Test name
Test status
Simulation time 1601918634 ps
CPU time 9.42 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:51:36 PM PDT 24
Peak memory 232216 kb
Host smart-7e7306d6-1b7b-42b0-8646-3fa5828a165b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929416383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2929416383
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.933864700
Short name T236
Test name
Test status
Simulation time 1474171837 ps
CPU time 15.11 seconds
Started Jun 02 01:51:28 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 233356 kb
Host smart-a29aab3f-212c-4af3-b037-dbd7b4594afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933864700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.933864700
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2473573030
Short name T43
Test name
Test status
Simulation time 9194264375 ps
CPU time 66.23 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:52:33 PM PDT 24
Peak memory 244696 kb
Host smart-ab2fc685-1bfe-418f-b9d2-480999ac1a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473573030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2473573030
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4030536747
Short name T278
Test name
Test status
Simulation time 8309589550 ps
CPU time 8.85 seconds
Started Jun 02 01:51:25 PM PDT 24
Finished Jun 02 01:51:34 PM PDT 24
Peak memory 222728 kb
Host smart-5a8339fa-c147-4015-9672-f64844c2d5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030536747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4030536747
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1647070659
Short name T167
Test name
Test status
Simulation time 29077603423 ps
CPU time 11.72 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:40 PM PDT 24
Peak memory 218920 kb
Host smart-5fd2fa1b-c49a-482e-b0bd-0c54dbf7b9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647070659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1647070659
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3835174254
Short name T425
Test name
Test status
Simulation time 4608348598 ps
CPU time 8.32 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:36 PM PDT 24
Peak memory 222536 kb
Host smart-7e698bbc-e105-4bff-91d7-052990886d1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3835174254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3835174254
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1122089311
Short name T677
Test name
Test status
Simulation time 333337352 ps
CPU time 1.09 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:51:28 PM PDT 24
Peak memory 206404 kb
Host smart-0378917e-0051-49cc-93dc-53ea76e9ec3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122089311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1122089311
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.216390449
Short name T860
Test name
Test status
Simulation time 22770439568 ps
CPU time 17.78 seconds
Started Jun 02 01:51:25 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 216336 kb
Host smart-fa319b3b-9f8b-43c3-aad8-455aa4815bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216390449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.216390449
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1002631227
Short name T429
Test name
Test status
Simulation time 1056564954 ps
CPU time 2.8 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:51:29 PM PDT 24
Peak memory 215736 kb
Host smart-e92ac818-b371-43fe-9177-d1a4c229df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002631227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1002631227
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1194446730
Short name T483
Test name
Test status
Simulation time 39389030 ps
CPU time 1.62 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:29 PM PDT 24
Peak memory 215788 kb
Host smart-5761906e-d7bb-44c7-97b5-f613545ebdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194446730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1194446730
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1916574345
Short name T960
Test name
Test status
Simulation time 112907210 ps
CPU time 0.78 seconds
Started Jun 02 01:51:25 PM PDT 24
Finished Jun 02 01:51:27 PM PDT 24
Peak memory 205220 kb
Host smart-d0fb67b9-79f4-4f06-81b3-675e0c19925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916574345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1916574345
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4264987400
Short name T652
Test name
Test status
Simulation time 632335974 ps
CPU time 4.43 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:51:31 PM PDT 24
Peak memory 233468 kb
Host smart-588ee51c-e811-412b-a09f-93425b2fd883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264987400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4264987400
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3442521688
Short name T886
Test name
Test status
Simulation time 49039782 ps
CPU time 0.72 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:48:52 PM PDT 24
Peak memory 205196 kb
Host smart-7050bac4-0eb2-4479-9959-f072a0b5ada8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442521688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
442521688
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3033295430
Short name T2
Test name
Test status
Simulation time 328296473 ps
CPU time 3.57 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:48:53 PM PDT 24
Peak memory 218436 kb
Host smart-0c438453-1497-4230-9082-79bffa2525a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033295430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3033295430
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2355947104
Short name T423
Test name
Test status
Simulation time 167635321 ps
CPU time 0.86 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:48:52 PM PDT 24
Peak memory 205844 kb
Host smart-3afe91ae-4d52-481d-b845-2ed9917404a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355947104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2355947104
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2704971953
Short name T545
Test name
Test status
Simulation time 3409638634 ps
CPU time 11.19 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:49:02 PM PDT 24
Peak memory 216928 kb
Host smart-b0594bbf-ac0f-4144-952e-5b635229507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704971953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2704971953
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.75333688
Short name T947
Test name
Test status
Simulation time 286003351 ps
CPU time 9.14 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 232240 kb
Host smart-8d8e3afa-1f68-4678-8349-a1c2dc02a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75333688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.75333688
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.435610495
Short name T440
Test name
Test status
Simulation time 1413501091 ps
CPU time 5.81 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 219088 kb
Host smart-cb69ac9a-2a68-494c-b1c7-8d6d518a90a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435610495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.435610495
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4082636159
Short name T251
Test name
Test status
Simulation time 1491818085 ps
CPU time 15.43 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:49:03 PM PDT 24
Peak memory 235020 kb
Host smart-ff2a028f-408e-49a6-bd41-fe16e4a24d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082636159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4082636159
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1699755403
Short name T745
Test name
Test status
Simulation time 114495898 ps
CPU time 1.05 seconds
Started Jun 02 01:48:55 PM PDT 24
Finished Jun 02 01:48:56 PM PDT 24
Peak memory 217500 kb
Host smart-025bcd1f-83a6-4366-a8f9-f5487090c358
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699755403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1699755403
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3667643944
Short name T345
Test name
Test status
Simulation time 122739218 ps
CPU time 2.39 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 221012 kb
Host smart-2569db6b-78e8-4bd0-b248-8098779b403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667643944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3667643944
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4112073800
Short name T601
Test name
Test status
Simulation time 946143707 ps
CPU time 4.83 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 237012 kb
Host smart-c26a8d28-fc3c-4adf-aec9-f22fd2e3ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112073800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4112073800
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3628122487
Short name T898
Test name
Test status
Simulation time 642872957 ps
CPU time 6.8 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 218736 kb
Host smart-3e6ed3a7-560f-44e0-be7e-ca2c933b7650
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3628122487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3628122487
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1298734853
Short name T158
Test name
Test status
Simulation time 17702873788 ps
CPU time 71.91 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:50:03 PM PDT 24
Peak memory 256756 kb
Host smart-481a8606-2fb4-4f59-9945-9e70a2951387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298734853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1298734853
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3817900495
Short name T335
Test name
Test status
Simulation time 7635905808 ps
CPU time 39.97 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:49:30 PM PDT 24
Peak memory 215940 kb
Host smart-b05fd7ae-4699-438e-ac3c-5ac01ffe3efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817900495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3817900495
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2457860200
Short name T387
Test name
Test status
Simulation time 912403929 ps
CPU time 3.85 seconds
Started Jun 02 01:48:53 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 215760 kb
Host smart-92b52fba-d239-4c87-b482-a16618a7f581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457860200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2457860200
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.959121027
Short name T357
Test name
Test status
Simulation time 157292425 ps
CPU time 0.68 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:48:51 PM PDT 24
Peak memory 204808 kb
Host smart-03fd5495-db13-4e31-bd46-103a3e12f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959121027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.959121027
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1017712806
Short name T821
Test name
Test status
Simulation time 84777751 ps
CPU time 0.97 seconds
Started Jun 02 01:48:49 PM PDT 24
Finished Jun 02 01:48:50 PM PDT 24
Peak memory 205224 kb
Host smart-aab7e679-52ab-495d-9c94-bf454f596c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017712806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1017712806
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3693467958
Short name T788
Test name
Test status
Simulation time 8877062688 ps
CPU time 10.87 seconds
Started Jun 02 01:48:55 PM PDT 24
Finished Jun 02 01:49:06 PM PDT 24
Peak memory 233776 kb
Host smart-a1b8a98b-e033-4895-9f5b-d9ac3f881e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693467958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3693467958
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1019320245
Short name T664
Test name
Test status
Simulation time 14859766 ps
CPU time 0.72 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:48:56 PM PDT 24
Peak memory 204828 kb
Host smart-c34c6cb2-e00b-4bf2-9917-73213d384612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019320245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
019320245
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3033535818
Short name T267
Test name
Test status
Simulation time 203133601 ps
CPU time 2.28 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:48:55 PM PDT 24
Peak memory 218092 kb
Host smart-1002d06a-963c-4c69-a4ac-5fbd670577f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033535818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3033535818
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3912678121
Short name T533
Test name
Test status
Simulation time 65225018 ps
CPU time 0.76 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:48:53 PM PDT 24
Peak memory 205836 kb
Host smart-2a3d4859-b23d-4ee2-a86f-7b6b1ca88a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912678121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3912678121
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.4081589684
Short name T244
Test name
Test status
Simulation time 50664696435 ps
CPU time 171.07 seconds
Started Jun 02 01:48:50 PM PDT 24
Finished Jun 02 01:51:42 PM PDT 24
Peak memory 248864 kb
Host smart-9a644d7c-bca4-4c92-a210-b362677ba861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081589684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.4081589684
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1878594222
Short name T213
Test name
Test status
Simulation time 6167118570 ps
CPU time 51.66 seconds
Started Jun 02 01:48:58 PM PDT 24
Finished Jun 02 01:49:50 PM PDT 24
Peak memory 231036 kb
Host smart-44133313-8d2d-495c-a734-ef1c422f9e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878594222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1878594222
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.179139933
Short name T271
Test name
Test status
Simulation time 12072230017 ps
CPU time 210.55 seconds
Started Jun 02 01:48:58 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 265172 kb
Host smart-37ac9abd-cee6-4c0d-b26d-e1a73fb7b2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179139933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
179139933
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.451137485
Short name T388
Test name
Test status
Simulation time 2050956972 ps
CPU time 15.98 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:49:07 PM PDT 24
Peak memory 236812 kb
Host smart-c3a79fff-9fa0-47bc-b8ab-821e00e22223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451137485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.451137485
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3384172083
Short name T757
Test name
Test status
Simulation time 438093895 ps
CPU time 7.38 seconds
Started Jun 02 01:48:53 PM PDT 24
Finished Jun 02 01:49:01 PM PDT 24
Peak memory 234296 kb
Host smart-c19b4d32-02d0-46ff-9661-3eae8c07d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384172083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3384172083
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1381217752
Short name T532
Test name
Test status
Simulation time 1212804701 ps
CPU time 4.15 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:56 PM PDT 24
Peak memory 218120 kb
Host smart-0b389e40-bfb4-4b66-8bf2-6909a5871615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381217752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1381217752
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3384389828
Short name T377
Test name
Test status
Simulation time 156367541 ps
CPU time 1.04 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:50 PM PDT 24
Peak memory 216100 kb
Host smart-f16d64dd-54b8-4fcb-99e8-a2679e62dbb3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384389828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3384389828
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1570619483
Short name T605
Test name
Test status
Simulation time 969221761 ps
CPU time 4.85 seconds
Started Jun 02 01:48:55 PM PDT 24
Finished Jun 02 01:49:00 PM PDT 24
Peak memory 218592 kb
Host smart-3251fc17-f9cb-4dd0-95d0-74ecd18361e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570619483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1570619483
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2607145746
Short name T80
Test name
Test status
Simulation time 262572414 ps
CPU time 2.61 seconds
Started Jun 02 01:48:48 PM PDT 24
Finished Jun 02 01:48:52 PM PDT 24
Peak memory 224044 kb
Host smart-1bb8e6c1-7b37-4146-b78e-7954db06f3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607145746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2607145746
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2202252528
Short name T541
Test name
Test status
Simulation time 710999100 ps
CPU time 4.73 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 219584 kb
Host smart-97956a95-6c9d-42a1-ad61-9a2b1fa9bd8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2202252528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2202252528
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1857253508
Short name T378
Test name
Test status
Simulation time 595725606 ps
CPU time 3.77 seconds
Started Jun 02 01:48:47 PM PDT 24
Finished Jun 02 01:48:51 PM PDT 24
Peak memory 215872 kb
Host smart-deb162c2-7f9b-474c-acf3-12ae3291b17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857253508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1857253508
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1494891441
Short name T398
Test name
Test status
Simulation time 1049249338 ps
CPU time 3.06 seconds
Started Jun 02 01:48:51 PM PDT 24
Finished Jun 02 01:48:55 PM PDT 24
Peak memory 215692 kb
Host smart-dddd4a42-dae1-44b6-af73-ef28e186870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494891441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1494891441
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1658209859
Short name T567
Test name
Test status
Simulation time 797572184 ps
CPU time 7.37 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:49:02 PM PDT 24
Peak memory 215848 kb
Host smart-556c69c1-0232-4a9d-85fc-191e636db654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658209859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1658209859
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.790477718
Short name T500
Test name
Test status
Simulation time 15664991 ps
CPU time 0.76 seconds
Started Jun 02 01:48:53 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 205232 kb
Host smart-4975fff3-f464-411b-8b03-76d59849b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790477718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.790477718
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.289351273
Short name T427
Test name
Test status
Simulation time 125020402 ps
CPU time 2.41 seconds
Started Jun 02 01:48:55 PM PDT 24
Finished Jun 02 01:48:58 PM PDT 24
Peak memory 215828 kb
Host smart-2165a766-4e03-4090-8a64-baee05471fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289351273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.289351273
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1589222508
Short name T543
Test name
Test status
Simulation time 19174339 ps
CPU time 0.7 seconds
Started Jun 02 01:48:59 PM PDT 24
Finished Jun 02 01:49:00 PM PDT 24
Peak memory 204832 kb
Host smart-b2cb1a67-e259-494d-af32-9056088b173d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589222508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
589222508
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.275613486
Short name T555
Test name
Test status
Simulation time 1463057368 ps
CPU time 4.95 seconds
Started Jun 02 01:48:53 PM PDT 24
Finished Jun 02 01:48:58 PM PDT 24
Peak memory 233936 kb
Host smart-5a6cb99f-12b2-41ca-8963-9c99b31e5ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275613486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.275613486
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1774411433
Short name T410
Test name
Test status
Simulation time 44798578 ps
CPU time 0.76 seconds
Started Jun 02 01:48:53 PM PDT 24
Finished Jun 02 01:48:54 PM PDT 24
Peak memory 204820 kb
Host smart-a644fcf6-f856-488e-af9c-44b26b18e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774411433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1774411433
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3872215869
Short name T941
Test name
Test status
Simulation time 11378409560 ps
CPU time 36.08 seconds
Started Jun 02 01:48:55 PM PDT 24
Finished Jun 02 01:49:31 PM PDT 24
Peak memory 234604 kb
Host smart-157fc580-e466-4f82-a220-73f1fefc5e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872215869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3872215869
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.499170432
Short name T408
Test name
Test status
Simulation time 457481031 ps
CPU time 5.7 seconds
Started Jun 02 01:48:56 PM PDT 24
Finished Jun 02 01:49:02 PM PDT 24
Peak memory 216880 kb
Host smart-8e2dd764-16d4-4fa5-ac5d-75d41f0b2af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499170432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.499170432
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.555664171
Short name T616
Test name
Test status
Simulation time 9640097922 ps
CPU time 86.33 seconds
Started Jun 02 01:49:12 PM PDT 24
Finished Jun 02 01:50:39 PM PDT 24
Peak memory 249764 kb
Host smart-706bdb57-daa9-4dda-9286-302d050b63c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555664171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
555664171
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2424985898
Short name T704
Test name
Test status
Simulation time 2468887412 ps
CPU time 23.92 seconds
Started Jun 02 01:48:58 PM PDT 24
Finished Jun 02 01:49:23 PM PDT 24
Peak memory 240500 kb
Host smart-42f89c7c-9b2c-4aa9-ae01-52e00a4eceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424985898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2424985898
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1717127754
Short name T867
Test name
Test status
Simulation time 168815166 ps
CPU time 3.89 seconds
Started Jun 02 01:48:57 PM PDT 24
Finished Jun 02 01:49:02 PM PDT 24
Peak memory 218260 kb
Host smart-e436a961-eda1-4753-97b8-cba3115cc379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717127754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1717127754
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1161550687
Short name T726
Test name
Test status
Simulation time 54966527 ps
CPU time 2.03 seconds
Started Jun 02 01:49:01 PM PDT 24
Finished Jun 02 01:49:03 PM PDT 24
Peak memory 215632 kb
Host smart-95d39e05-9a69-4fbc-b869-00f818b9ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161550687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1161550687
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2822680091
Short name T384
Test name
Test status
Simulation time 116530657 ps
CPU time 1.09 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:48:56 PM PDT 24
Peak memory 216080 kb
Host smart-27c8f2a2-e471-4328-9bae-4abe35a57e5e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822680091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2822680091
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.240147814
Short name T919
Test name
Test status
Simulation time 3394199692 ps
CPU time 4.01 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:48:59 PM PDT 24
Peak memory 218288 kb
Host smart-a3d77db2-7fbb-46c6-a809-2143cacf9c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240147814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
240147814
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3507551541
Short name T435
Test name
Test status
Simulation time 4560881097 ps
CPU time 5.16 seconds
Started Jun 02 01:48:52 PM PDT 24
Finished Jun 02 01:48:57 PM PDT 24
Peak memory 223956 kb
Host smart-a97c1080-3d86-4d43-9424-c77081189783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507551541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3507551541
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.9478590
Short name T903
Test name
Test status
Simulation time 336855834 ps
CPU time 3.74 seconds
Started Jun 02 01:48:58 PM PDT 24
Finished Jun 02 01:49:02 PM PDT 24
Peak memory 218328 kb
Host smart-0b8dbb01-1a9e-4e01-84e2-22446abea732
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=9478590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.9478590
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3106273441
Short name T309
Test name
Test status
Simulation time 85506623128 ps
CPU time 393.91 seconds
Started Jun 02 01:49:01 PM PDT 24
Finished Jun 02 01:55:36 PM PDT 24
Peak memory 256384 kb
Host smart-925287e6-d8b0-44f9-8749-da458ee38c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106273441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3106273441
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2375392511
Short name T710
Test name
Test status
Simulation time 3477313138 ps
CPU time 17 seconds
Started Jun 02 01:48:58 PM PDT 24
Finished Jun 02 01:49:16 PM PDT 24
Peak memory 215848 kb
Host smart-6b0f37c0-2d22-42ed-abd3-5e4a5bfaf42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375392511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2375392511
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1364836488
Short name T350
Test name
Test status
Simulation time 4552914725 ps
CPU time 10.93 seconds
Started Jun 02 01:48:54 PM PDT 24
Finished Jun 02 01:49:06 PM PDT 24
Peak memory 215808 kb
Host smart-d4a7753c-b341-4d32-9034-e7ed1860fbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364836488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1364836488
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1660369724
Short name T829
Test name
Test status
Simulation time 86468123 ps
CPU time 4.19 seconds
Started Jun 02 01:48:59 PM PDT 24
Finished Jun 02 01:49:04 PM PDT 24
Peak memory 215836 kb
Host smart-0d585ba8-5c3a-46b6-b7c6-e183fd3d6bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660369724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1660369724
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1253958745
Short name T537
Test name
Test status
Simulation time 132828002 ps
CPU time 0.77 seconds
Started Jun 02 01:49:02 PM PDT 24
Finished Jun 02 01:49:03 PM PDT 24
Peak memory 205228 kb
Host smart-f4e030f8-ef87-4ef0-ba00-4f4f4be2e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253958745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1253958745
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2072821307
Short name T547
Test name
Test status
Simulation time 6833768119 ps
CPU time 8.5 seconds
Started Jun 02 01:49:00 PM PDT 24
Finished Jun 02 01:49:08 PM PDT 24
Peak memory 224056 kb
Host smart-6906871b-4e61-4ff0-b320-145f383020ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072821307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2072821307
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1113861846
Short name T341
Test name
Test status
Simulation time 21840579 ps
CPU time 0.71 seconds
Started Jun 02 01:49:08 PM PDT 24
Finished Jun 02 01:49:09 PM PDT 24
Peak memory 204860 kb
Host smart-78504aa4-5f0e-4010-93b4-faccc94986f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113861846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
113861846
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1569021171
Short name T772
Test name
Test status
Simulation time 3307894527 ps
CPU time 18.45 seconds
Started Jun 02 01:49:05 PM PDT 24
Finished Jun 02 01:49:24 PM PDT 24
Peak memory 237276 kb
Host smart-0b106b02-1045-440f-a0ee-be6292e2fd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569021171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1569021171
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4099074702
Short name T907
Test name
Test status
Simulation time 25138214 ps
CPU time 0.77 seconds
Started Jun 02 01:49:02 PM PDT 24
Finished Jun 02 01:49:03 PM PDT 24
Peak memory 204784 kb
Host smart-2a3b07b0-2527-439e-930b-cb9bbaebb9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099074702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4099074702
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3003810202
Short name T338
Test name
Test status
Simulation time 27121948 ps
CPU time 0.71 seconds
Started Jun 02 01:49:05 PM PDT 24
Finished Jun 02 01:49:06 PM PDT 24
Peak memory 207160 kb
Host smart-f72f56ac-af21-4f4c-82e5-3a20c68969f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003810202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3003810202
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.519709086
Short name T230
Test name
Test status
Simulation time 31868458612 ps
CPU time 301.12 seconds
Started Jun 02 01:49:05 PM PDT 24
Finished Jun 02 01:54:07 PM PDT 24
Peak memory 232440 kb
Host smart-7fdabc2a-8ef9-41e2-b210-4e8a4757997a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519709086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.519709086
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3780407842
Short name T749
Test name
Test status
Simulation time 16251107156 ps
CPU time 77.53 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:50:26 PM PDT 24
Peak memory 251916 kb
Host smart-041bc8aa-65d6-4ce0-a1dd-bc1f4eb65cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780407842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3780407842
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1828442975
Short name T328
Test name
Test status
Simulation time 5363132114 ps
CPU time 68.57 seconds
Started Jun 02 01:49:08 PM PDT 24
Finished Jun 02 01:50:17 PM PDT 24
Peak memory 232332 kb
Host smart-0757de5d-8e89-4c46-a569-359ec4adf565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828442975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1828442975
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1907658680
Short name T554
Test name
Test status
Simulation time 60272852 ps
CPU time 3.25 seconds
Started Jun 02 01:49:06 PM PDT 24
Finished Jun 02 01:49:10 PM PDT 24
Peak memory 233760 kb
Host smart-7955ed7b-d4e9-4a57-9a8f-af666e6fbad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907658680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1907658680
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2989435336
Short name T184
Test name
Test status
Simulation time 4235545930 ps
CPU time 29.88 seconds
Started Jun 02 01:49:03 PM PDT 24
Finished Jun 02 01:49:33 PM PDT 24
Peak memory 249488 kb
Host smart-272c41f5-ece2-41b5-a557-821b5201a1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989435336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2989435336
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.73311895
Short name T878
Test name
Test status
Simulation time 15955759 ps
CPU time 1.06 seconds
Started Jun 02 01:49:01 PM PDT 24
Finished Jun 02 01:49:03 PM PDT 24
Peak memory 216160 kb
Host smart-eb3f7723-edf4-4345-aa89-c4210ff733ed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73311895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.73311895
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3505345827
Short name T490
Test name
Test status
Simulation time 797519341 ps
CPU time 3.34 seconds
Started Jun 02 01:49:03 PM PDT 24
Finished Jun 02 01:49:07 PM PDT 24
Peak memory 216360 kb
Host smart-cebb9fa8-36d9-46b3-bf4e-d3228818e5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505345827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3505345827
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4132274561
Short name T224
Test name
Test status
Simulation time 221674387 ps
CPU time 4.01 seconds
Started Jun 02 01:48:57 PM PDT 24
Finished Jun 02 01:49:01 PM PDT 24
Peak memory 219056 kb
Host smart-d05c4565-95e5-44be-b6a3-5a17f0cbe370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132274561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4132274561
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1118057578
Short name T901
Test name
Test status
Simulation time 1054468424 ps
CPU time 8.75 seconds
Started Jun 02 01:49:11 PM PDT 24
Finished Jun 02 01:49:20 PM PDT 24
Peak memory 222404 kb
Host smart-1937214e-6d62-45a0-b9c1-1face8b87f99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1118057578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1118057578
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3621314865
Short name T254
Test name
Test status
Simulation time 34781799586 ps
CPU time 122.3 seconds
Started Jun 02 01:49:08 PM PDT 24
Finished Jun 02 01:51:10 PM PDT 24
Peak memory 254640 kb
Host smart-dce0f98a-e056-487f-a6ea-ed7098cb2043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621314865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3621314865
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3295272086
Short name T595
Test name
Test status
Simulation time 5328451008 ps
CPU time 14.15 seconds
Started Jun 02 01:48:58 PM PDT 24
Finished Jun 02 01:49:13 PM PDT 24
Peak memory 215936 kb
Host smart-e5caedea-919c-449b-82bc-016bb92646fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295272086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3295272086
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1628782296
Short name T603
Test name
Test status
Simulation time 663827167 ps
CPU time 1.73 seconds
Started Jun 02 01:49:02 PM PDT 24
Finished Jun 02 01:49:04 PM PDT 24
Peak memory 207296 kb
Host smart-7007b63d-9aaa-4610-863f-67a7ab6f6328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628782296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1628782296
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3731429430
Short name T617
Test name
Test status
Simulation time 28549655 ps
CPU time 1.01 seconds
Started Jun 02 01:49:03 PM PDT 24
Finished Jun 02 01:49:04 PM PDT 24
Peak memory 206548 kb
Host smart-35b2836c-bdd8-4529-9af7-20c31d97d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731429430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3731429430
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.190036051
Short name T455
Test name
Test status
Simulation time 33383910 ps
CPU time 0.78 seconds
Started Jun 02 01:48:58 PM PDT 24
Finished Jun 02 01:48:59 PM PDT 24
Peak memory 205216 kb
Host smart-4f748e29-6bf6-4186-9d2f-67e33cfca708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190036051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.190036051
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.679154928
Short name T596
Test name
Test status
Simulation time 9573106109 ps
CPU time 31.48 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:49:41 PM PDT 24
Peak memory 239520 kb
Host smart-99c3c8df-03ec-4134-9546-b69f4a066574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679154928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.679154928
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.812452472
Short name T924
Test name
Test status
Simulation time 106334142 ps
CPU time 0.72 seconds
Started Jun 02 01:49:03 PM PDT 24
Finished Jun 02 01:49:04 PM PDT 24
Peak memory 204844 kb
Host smart-02a0c9cd-6f38-4407-8de6-b1929589a5a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812452472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.812452472
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3562244409
Short name T258
Test name
Test status
Simulation time 1217508651 ps
CPU time 4.42 seconds
Started Jun 02 01:49:08 PM PDT 24
Finished Jun 02 01:49:13 PM PDT 24
Peak memory 218360 kb
Host smart-fa6c2c15-a4c4-4106-ba62-6e441d36668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562244409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3562244409
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1779909704
Short name T934
Test name
Test status
Simulation time 15355559 ps
CPU time 0.78 seconds
Started Jun 02 01:49:04 PM PDT 24
Finished Jun 02 01:49:06 PM PDT 24
Peak memory 205864 kb
Host smart-ac5944a9-da0b-4eba-a478-4a49e22326df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779909704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1779909704
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1016607205
Short name T235
Test name
Test status
Simulation time 1614759247 ps
CPU time 34.9 seconds
Started Jun 02 01:49:05 PM PDT 24
Finished Jun 02 01:49:41 PM PDT 24
Peak memory 249804 kb
Host smart-191b1cd8-7984-49df-8950-234a63130d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016607205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1016607205
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2604867946
Short name T709
Test name
Test status
Simulation time 9391182114 ps
CPU time 89.99 seconds
Started Jun 02 01:49:06 PM PDT 24
Finished Jun 02 01:50:36 PM PDT 24
Peak memory 248832 kb
Host smart-a7a047b9-a79d-475f-900e-900bd18d0bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604867946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2604867946
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.393455481
Short name T607
Test name
Test status
Simulation time 1976740881 ps
CPU time 43.78 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:49:54 PM PDT 24
Peak memory 240516 kb
Host smart-b136d280-1b88-4d4b-b0e9-674314d2eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393455481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
393455481
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1956039628
Short name T804
Test name
Test status
Simulation time 258430495 ps
CPU time 2.71 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:49:12 PM PDT 24
Peak memory 232248 kb
Host smart-caa7fa2a-5098-4aab-ae56-4b4fdd98f3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956039628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1956039628
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3935511675
Short name T940
Test name
Test status
Simulation time 1227555840 ps
CPU time 6.41 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:49:16 PM PDT 24
Peak memory 218316 kb
Host smart-c47d1472-19f5-4a5b-baeb-4bc79e54a9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935511675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3935511675
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3486259758
Short name T287
Test name
Test status
Simulation time 2016405545 ps
CPU time 9.89 seconds
Started Jun 02 01:49:05 PM PDT 24
Finished Jun 02 01:49:15 PM PDT 24
Peak memory 231840 kb
Host smart-5745a4e2-a3eb-4f99-9971-b1a205c14f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486259758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3486259758
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1587825304
Short name T915
Test name
Test status
Simulation time 43767943 ps
CPU time 1.06 seconds
Started Jun 02 01:49:04 PM PDT 24
Finished Jun 02 01:49:06 PM PDT 24
Peak memory 216140 kb
Host smart-ff2be1a4-60ed-4608-87a2-563b62d60558
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587825304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1587825304
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3971261403
Short name T727
Test name
Test status
Simulation time 5177495365 ps
CPU time 17.45 seconds
Started Jun 02 01:49:05 PM PDT 24
Finished Jun 02 01:49:22 PM PDT 24
Peak memory 229512 kb
Host smart-b01ebfef-9cc8-48c3-8960-35366efcc699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971261403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3971261403
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2096309914
Short name T503
Test name
Test status
Simulation time 919756478 ps
CPU time 4.57 seconds
Started Jun 02 01:49:04 PM PDT 24
Finished Jun 02 01:49:09 PM PDT 24
Peak memory 232648 kb
Host smart-09f4bf6f-8b0c-4b31-be32-749ee1c0a7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096309914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2096309914
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3314354940
Short name T430
Test name
Test status
Simulation time 367900045 ps
CPU time 6.68 seconds
Started Jun 02 01:49:03 PM PDT 24
Finished Jun 02 01:49:10 PM PDT 24
Peak memory 219296 kb
Host smart-c89cd302-34ba-4904-aa6f-dd5ccbf15189
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3314354940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3314354940
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1262651021
Short name T598
Test name
Test status
Simulation time 40780100852 ps
CPU time 400.85 seconds
Started Jun 02 01:49:09 PM PDT 24
Finished Jun 02 01:55:50 PM PDT 24
Peak memory 255184 kb
Host smart-acc8b44b-801f-4f06-ad28-cbac4953600e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262651021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1262651021
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.226295760
Short name T391
Test name
Test status
Simulation time 44800293132 ps
CPU time 14.5 seconds
Started Jun 02 01:49:05 PM PDT 24
Finished Jun 02 01:49:20 PM PDT 24
Peak memory 215896 kb
Host smart-90d7a704-4425-4085-b52b-7b284855adf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226295760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.226295760
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2200289790
Short name T694
Test name
Test status
Simulation time 660685300 ps
CPU time 3.78 seconds
Started Jun 02 01:49:07 PM PDT 24
Finished Jun 02 01:49:11 PM PDT 24
Peak memory 215736 kb
Host smart-6b88249d-e281-4713-9b1b-e21bae3c835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200289790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2200289790
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.112464716
Short name T498
Test name
Test status
Simulation time 69570343 ps
CPU time 0.84 seconds
Started Jun 02 01:49:10 PM PDT 24
Finished Jun 02 01:49:11 PM PDT 24
Peak memory 205916 kb
Host smart-21a11096-2e17-4f60-9be6-56900576d4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112464716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.112464716
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3849420648
Short name T701
Test name
Test status
Simulation time 13456180 ps
CPU time 0.71 seconds
Started Jun 02 01:49:06 PM PDT 24
Finished Jun 02 01:49:07 PM PDT 24
Peak memory 204856 kb
Host smart-0af10df8-5e86-4be2-bf0e-9e6226fba25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849420648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3849420648
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3646204466
Short name T464
Test name
Test status
Simulation time 32924896835 ps
CPU time 18.13 seconds
Started Jun 02 01:49:06 PM PDT 24
Finished Jun 02 01:49:24 PM PDT 24
Peak memory 230128 kb
Host smart-22952028-6df2-4c16-9cb8-3c0e09273cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646204466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3646204466
Directory /workspace/9.spi_device_upload/latest
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