Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3358204	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3690185

1

T1

902

T2

890

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3948943	1			T1	36		T2	5		T3	1
values[0x0]	1548732	1			T1	443		T2	416		T3	5
values[0x1]	1550714	1			T1	450		T2	474		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2378831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4669558

1

T1

909

T2

891

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25493	1			T1	2		T4	1		T10	5
valid_sources[0x01]	30237	1			T1	5		T2	2		T4	1
valid_sources[0x02]	29839	1			T1	2		T2	1		T10	3
valid_sources[0x03]	25799	1			T1	1		T2	2		T4	2
valid_sources[0x04]	28973	1			T1	5		T2	1		T4	4
valid_sources[0x05]	26708	1			T1	6		T2	4		T4	7
valid_sources[0x06]	32784	1			T1	4		T2	2		T4	3
valid_sources[0x07]	26916	1			T1	3		T2	5		T4	2
valid_sources[0x08]	29449	1			T1	1		T2	3		T4	4
valid_sources[0x09]	25494	1			T1	2		T2	5		T4	1
valid_sources[0x0a]	26687	1			T1	8		T2	3		T4	6
valid_sources[0x0b]	28245	1			T1	2		T2	6		T4	1
valid_sources[0x0c]	26926	1			T1	2		T2	6		T4	1
valid_sources[0x0d]	29432	1			T1	1		T2	4		T4	4
valid_sources[0x0e]	29866	1			T1	6		T2	4		T4	6
valid_sources[0x0f]	25222	1			T1	4		T2	4		T4	4
valid_sources[0x10]	28131	1			T1	1		T2	5		T4	9
valid_sources[0x11]	24769	1			T1	5		T2	1		T4	2
valid_sources[0x12]	27665	1			T1	4		T2	6		T4	2
valid_sources[0x13]	29722	1			T1	9		T2	5		T4	3
valid_sources[0x14]	26122	1			T1	6		T2	4		T4	1
valid_sources[0x15]	24746	1			T1	3		T2	3		T4	3
valid_sources[0x16]	25463	1			T1	4		T2	3		T4	3
valid_sources[0x17]	25901	1			T1	5		T2	4		T4	4
valid_sources[0x18]	26072	1			T1	2		T2	2		T4	5
valid_sources[0x19]	29400	1			T1	8		T2	4		T4	1
valid_sources[0x1a]	25181	1			T1	4		T2	4		T4	1
valid_sources[0x1b]	26269	1			T1	8		T2	3		T4	1
valid_sources[0x1c]	29163	1			T1	2		T2	7		T10	2
valid_sources[0x1d]	28737	1			T1	4		T2	8		T4	3
valid_sources[0x1e]	27880	1			T1	4		T2	4		T4	4
valid_sources[0x1f]	30447	1			T1	1		T2	3		T4	4
valid_sources[0x20]	26112	1			T1	4		T10	10		T11	724
valid_sources[0x21]	25984	1			T1	7		T2	2		T4	5
valid_sources[0x22]	26741	1			T1	6		T2	8		T4	3
valid_sources[0x23]	26503	1			T1	9		T2	2		T4	1
valid_sources[0x24]	25832	1			T1	3		T2	3		T4	2
valid_sources[0x25]	30895	1			T1	1		T2	5		T10	3
valid_sources[0x26]	27182	1			T1	2		T2	5		T4	2
valid_sources[0x27]	25525	1			T1	3		T2	3		T4	3
valid_sources[0x28]	27098	1			T2	4		T4	2		T10	3
valid_sources[0x29]	28875	1			T2	4		T4	5		T10	1
valid_sources[0x2a]	25376	1			T1	2		T2	2		T4	3
valid_sources[0x2b]	26528	1			T1	8		T2	2		T4	3
valid_sources[0x2c]	26026	1			T1	1		T2	2		T4	2
valid_sources[0x2d]	23576	1			T1	2		T2	2		T4	1
valid_sources[0x2e]	31667	1			T1	1		T2	5		T4	4
valid_sources[0x2f]	24455	1			T1	3		T2	3		T4	3
valid_sources[0x30]	26263	1			T1	3		T2	1		T4	4
valid_sources[0x31]	28463	1			T1	4		T2	6		T4	4
valid_sources[0x32]	28767	1			T1	4		T2	3		T4	2
valid_sources[0x33]	26193	1			T1	7		T2	3		T4	3
valid_sources[0x34]	25178	1			T1	3		T2	5		T4	5
valid_sources[0x35]	26980	1			T2	4		T4	4		T10	4
valid_sources[0x36]	24914	1			T1	2		T2	5		T4	5
valid_sources[0x37]	24659	1			T1	7		T2	2		T4	6
valid_sources[0x38]	27478	1			T1	10		T2	5		T4	4
valid_sources[0x39]	27095	1			T1	10		T2	2		T4	4
valid_sources[0x3a]	27629	1			T1	3		T2	4		T4	4
valid_sources[0x3b]	24942	1			T1	2		T2	2		T4	4
valid_sources[0x3c]	25151	1			T1	5		T2	5		T4	4
valid_sources[0x3d]	26653	1			T1	7		T2	3		T4	4
valid_sources[0x3e]	27366	1			T1	2		T2	1		T4	3
valid_sources[0x3f]	25362	1			T1	2		T2	2		T4	2
valid_sources[0x40]	25537	1			T2	3		T4	1		T10	2
valid_sources[0x41]	27167	1			T1	2		T2	4		T4	1
valid_sources[0x42]	26613	1			T1	6		T2	3		T4	4
valid_sources[0x43]	27680	1			T1	2		T2	4		T4	8
valid_sources[0x44]	25759	1			T1	6		T2	4		T4	5
valid_sources[0x45]	27092	1			T1	10		T2	2		T4	1
valid_sources[0x46]	26492	1			T1	4		T2	4		T4	1
valid_sources[0x47]	26378	1			T1	1		T2	3		T4	1
valid_sources[0x48]	30772	1			T1	3		T2	6		T4	2
valid_sources[0x49]	27912	1			T1	3		T2	3		T4	3
valid_sources[0x4a]	27278	1			T1	1		T2	2		T4	8
valid_sources[0x4b]	25613	1			T1	3		T2	5		T4	2
valid_sources[0x4c]	28212	1			T1	6		T2	3		T10	3
valid_sources[0x4d]	26612	1			T4	4		T10	2		T11	593
valid_sources[0x4e]	28587	1			T1	6		T2	2		T10	6
valid_sources[0x4f]	30210	1			T1	2		T2	3		T4	1
valid_sources[0x50]	28024	1			T1	1		T2	1		T4	5
valid_sources[0x51]	25435	1			T1	8		T2	1		T4	2
valid_sources[0x52]	28165	1			T1	7		T2	6		T4	5
valid_sources[0x53]	28177	1			T1	5		T2	5		T4	2
valid_sources[0x54]	27106	1			T1	1		T2	4		T4	1
valid_sources[0x55]	24743	1			T1	5		T2	4		T4	1
valid_sources[0x56]	28448	1			T1	4		T2	1		T4	6
valid_sources[0x57]	27935	1			T1	2		T2	3		T10	9
valid_sources[0x58]	25601	1			T1	2		T2	1		T4	3
valid_sources[0x59]	27747	1			T1	2		T2	7		T4	1
valid_sources[0x5a]	28222	1			T1	3		T2	3		T4	3
valid_sources[0x5b]	30675	1			T1	3		T2	2		T4	2
valid_sources[0x5c]	27767	1			T1	7		T2	6		T4	5
valid_sources[0x5d]	27647	1			T1	6		T2	5		T4	4
valid_sources[0x5e]	26145	1			T1	5		T2	3		T4	4
valid_sources[0x5f]	26748	1			T1	5		T2	2		T4	3
valid_sources[0x60]	25955	1			T1	2		T2	5		T4	2
valid_sources[0x61]	34333	1			T1	1		T2	6		T4	2
valid_sources[0x62]	24964	1			T1	7		T2	7		T4	3
valid_sources[0x63]	24096	1			T1	2		T2	6		T4	3
valid_sources[0x64]	25600	1			T1	6		T2	6		T4	5
valid_sources[0x65]	25736	1			T1	1		T2	9		T4	3
valid_sources[0x66]	27449	1			T1	4		T2	2		T4	1
valid_sources[0x67]	23928	1			T1	7		T2	3		T4	4
valid_sources[0x68]	29648	1			T2	2		T4	2		T10	3
valid_sources[0x69]	33661	1			T1	5		T2	5		T4	5
valid_sources[0x6a]	25657	1			T1	4		T2	1		T4	1
valid_sources[0x6b]	25513	1			T2	2		T4	3		T10	3
valid_sources[0x6c]	27029	1			T1	10		T2	6		T4	2
valid_sources[0x6d]	27604	1			T1	1		T2	5		T4	7
valid_sources[0x6e]	26571	1			T1	2		T2	5		T4	4
valid_sources[0x6f]	30111	1			T1	1		T2	3		T4	5
valid_sources[0x70]	26950	1			T1	1		T2	4		T4	3
valid_sources[0x71]	25038	1			T1	2		T2	4		T4	3
valid_sources[0x72]	26093	1			T2	3		T4	4		T10	2
valid_sources[0x73]	28160	1			T1	6		T2	3		T4	2
valid_sources[0x74]	25722	1			T1	3		T2	3		T4	2
valid_sources[0x75]	41370	1			T1	2		T2	5		T4	4
valid_sources[0x76]	26101	1			T1	2		T2	2		T4	1
valid_sources[0x77]	32443	1			T1	10		T2	3		T4	2
valid_sources[0x78]	28186	1			T1	3		T2	4		T10	3
valid_sources[0x79]	28702	1			T1	10		T2	4		T4	7
valid_sources[0x7a]	29771	1			T2	6		T4	2		T10	4
valid_sources[0x7b]	31593	1			T1	3		T2	4		T4	1
valid_sources[0x7c]	24717	1			T1	4		T2	2		T4	5
valid_sources[0x7d]	27398	1			T1	1		T2	8		T4	5
valid_sources[0x7e]	32890	1			T2	1		T3	9		T4	5
valid_sources[0x7f]	25517	1			T1	4		T2	1		T4	4
valid_sources[0x80]	26687	1			T2	2		T4	4		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

915899

1

T1

15

T2

1

T6

1

values[0x0]

all_enables

biggest_size

1397736

1

T1

442

T2

416

T4

325

values[0x1]

all_enables

biggest_size

1376550

1

T1

445

T2

473

T3

2