Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3378419

1

T1

27

T2

5

T3

8

full_word

3689288

1

T1

902

T2

890

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7067387	1			T1	929		T2	895		T3	10
auto[TlIntgErrCmd]	101	1			T91	5		T96	2		T97	10
auto[TlIntgErrData]	102	1			T91	3		T96	6		T97	13
auto[TlIntgErrBoth]	117	1			T91	2		T96	2		T97	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3950336

1

T1

36

T2

5

T3

1

auto[1]

3117371

1

T1

893

T2

890

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3034219	1			T1	21		T2	4		T3	1
auto[TlIntgErrNone]	partial	auto[1]	343905	1			T1	6		T2	1		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	915978	1			T1	15		T2	1		T6	1
auto[TlIntgErrNone]	full_word	auto[1]	2773285	1			T1	887		T2	889		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T97	4		T108	1		T107	6
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T91	2		T96	2		T97	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T91	1		T97	1		T272	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T91	2		T97	1		T268	2
auto[TlIntgErrData]	partial	auto[0]	40	1			T96	3		T97	5		T108	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T91	2		T96	3		T97	7
auto[TlIntgErrData]	full_word	auto[0]	5	1			T91	1		T97	1		T267	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T107	2		T273	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T96	2		T97	5		T108	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T91	2		T97	2		T107	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T269	1		T268	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T107	1		T267	1		T268	1