Module Definition
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Module : prim_onehot_check
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check 100.00 100.00



Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 138 138 100.00
Total Bits 0->1 69 69 100.00
Total Bits 1->0 69 69 100.00

Ports 5 5 100.00
Port Bits 138 138 100.00
Port Bits 0->1 69 69 100.00
Port Bits 1->0 69 69 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T11,T12,T34 Yes T1,T2,T3 INPUT
oh_i[5:0] Yes Yes *T1,*T11,*T12 Yes T1,T11,T12 INPUT
oh_i[6] Unreachable Unreachable Unreachable INPUT
oh_i[8:7] Yes Yes T1,T7,T9 Yes T1,T7,T9 INPUT
oh_i[9] Unreachable Unreachable Unreachable INPUT
oh_i[14:10] Yes Yes T1,T9,T11 Yes T1,T9,T11 INPUT
oh_i[18:15] Unreachable Unreachable Unreachable INPUT
oh_i[58:19] Yes Yes *T1,*T2,T7 Yes T1,T2,T7 INPUT
oh_i[59] Unreachable Unreachable Unreachable INPUT
oh_i[70:60] Yes Yes *T4,*T5,*T8 Yes T4,T5,T8 INPUT
oh_i[71] Unreachable Unreachable Unreachable INPUT
oh_i[72] Yes Yes T11,T12,T30 Yes T11,T12,T30 INPUT
addr_i[6:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
err_o Yes Yes T65,T66,T67 Yes T65,T66,T67 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%