Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365504168	2340604	0	0
DepthKnown_A	365504168	365379538	0	0
RvalidKnown_A	365504168	365379538	0	0
WreadyKnown_A	365504168	365379538	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	2340604	0	0
T1	27302	832	0	0
T2	908450	832	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	1663	0	0
T8	11905	0	0	0
T9	81841	1663	0	0
T10	3642	832	0	0
T11	0	32467	0	0
T12	0	34964	0	0
T13	0	13317	0	0
T17	0	832	0	0
T21	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365504168	2613070	0	0
DepthKnown_A	365504168	365379538	0	0
RvalidKnown_A	365504168	365379538	0	0
WreadyKnown_A	365504168	365379538	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	2613070	0	0
T1	27302	832	0	0
T2	908450	3752	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	11905	0	0	0
T9	81841	832	0	0
T10	3642	832	0	0
T11	0	60618	0	0
T12	0	35106	0	0
T13	0	19784	0	0
T17	0	832	0	0
T21	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365504168	165378	0	0
DepthKnown_A	365504168	365379538	0	0
RvalidKnown_A	365504168	365379538	0	0
WreadyKnown_A	365504168	365379538	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	165378	0	0
T11	106717	2738	0	0
T12	752175	972	0	0
T13	136700	33	0	0
T14	1227	0	0	0
T15	1376	0	0	0
T16	5024	0	0	0
T17	39921	0	0	0
T21	19504	0	0	0
T29	0	131	0	0
T30	0	89	0	0
T31	0	64	0	0
T32	0	64	0	0
T33	0	451	0	0
T34	0	496	0	0
T35	0	167	0	0
T36	1301	0	0	0
T37	957	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365504168	389603	0	0
DepthKnown_A	365504168	365379538	0	0
RvalidKnown_A	365504168	365379538	0	0
WreadyKnown_A	365504168	365379538	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	389603	0	0
T11	106717	12473	0	0
T12	752175	3019	0	0
T13	136700	81	0	0
T14	1227	0	0	0
T15	1376	0	0	0
T16	5024	0	0	0
T17	39921	0	0	0
T21	19504	0	0	0
T29	0	419	0	0
T30	0	89	0	0
T31	0	64	0	0
T32	0	64	0	0
T33	0	451	0	0
T34	0	2366	0	0
T35	0	167	0	0
T36	1301	0	0	0
T37	957	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365504168	5739942	0	0
DepthKnown_A	365504168	365379538	0	0
RvalidKnown_A	365504168	365379538	0	0
WreadyKnown_A	365504168	365379538	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	5739942	0	0
T1	27302	97	0	0
T2	908450	63	0	0
T3	760	10	0	0
T4	267137	741	0	0
T5	260504	446	0	0
T6	685	2	0	0
T7	3438	49	0	0
T8	11905	26	0	0
T9	81841	3037	0	0
T10	3642	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365504168	12952328	0	0
DepthKnown_A	365504168	365379538	0	0
RvalidKnown_A	365504168	365379538	0	0
WreadyKnown_A	365504168	365379538	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	12952328	0	0
T1	27302	97	0	0
T2	908450	308	0	0
T3	760	10	0	0
T4	267137	741	0	0
T5	260504	446	0	0
T6	685	12	0	0
T7	3438	210	0	0
T8	11905	26	0	0
T9	81841	3037	0	0
T10	3642	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365504168	365379538	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0