Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T30
1	0	Covered	T11,T12,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Unreachable
1	1	Covered	T11,T12,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T1,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	617072828	488800131	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	617072828	3003276	0	0
GntImpliesValid_A	617072828	3003276	0	0
GrantKnown_A	617072828	488800131	0	0
IdxKnown_A	617072828	488800131	0	0
IndexIsCorrect_A	617072828	3003276	0	0
LockArbDecision_A	617072828	0	0	0
NoReadyValidNoGrant_A	617072828	0	0	0
ReadyAndValidImplyGrant_A	617072828	3003276	0	0
ReqAndReadyImplyGrant_A	617072828	3003276	0	0
ReqImpliesValid_A	617072828	3003276	0	0
ReqStaysHighUntilGranted0_M	617072828	0	0	0
RoundRobin_A	617072828	3	0	926
ValidKnown_A	617072828	488800131	0	0
gen_data_port_assertion.DataFlow_A	617072828	3003276	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	488800131	0	0
T1	31548	31489	0	0
T2	1020619	1020262	0	0
T3	760	706	0	0
T4	426173	342846	0	0
T5	363290	309233	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	14023	12430	0	0
T9	104181	92928	0	0
T10	3858	3671	0	0
T11	326676	438685	0	0
T12	379220	278249	0	0
T13	852024	423149	0	0
T16	742	648	0	0
T17	36944	36944	0	0
T18	0	936	0	0
T19	0	82392	0	0
T20	0	72	0	0
T21	0	11354	0	0
T22	0	4536	0	0
T46	0	864	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	3003276	0	0
T1	31548	840	0	0
T2	1020619	832	0	0
T3	760	0	0	0
T4	346655	0	0	0
T5	311897	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	12964	0	0	0
T9	93011	832	0	0
T10	3750	832	0	0
T11	326676	54926	0	0
T12	379220	34194	0	0
T13	852024	9345	0	0
T16	742	0	0	0
T17	36944	832	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	832	0	0
T22	4536	0	0	0
T29	0	884	0	0
T30	0	516	0	0
T31	0	259	0	0
T32	0	513	0	0
T34	0	6036	0	0
T35	0	848	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	3003276	0	0
T1	31548	840	0	0
T2	1020619	832	0	0
T3	760	0	0	0
T4	346655	0	0	0
T5	311897	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	12964	0	0	0
T9	93011	832	0	0
T10	3750	832	0	0
T11	326676	54926	0	0
T12	379220	34194	0	0
T13	852024	9345	0	0
T16	742	0	0	0
T17	36944	832	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	832	0	0
T22	4536	0	0	0
T29	0	884	0	0
T30	0	516	0	0
T31	0	259	0	0
T32	0	513	0	0
T34	0	6036	0	0
T35	0	848	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	488800131	0	0
T1	31548	31489	0	0
T2	1020619	1020262	0	0
T3	760	706	0	0
T4	426173	342846	0	0
T5	363290	309233	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	14023	12430	0	0
T9	104181	92928	0	0
T10	3858	3671	0	0
T11	326676	438685	0	0
T12	379220	278249	0	0
T13	852024	423149	0	0
T16	742	648	0	0
T17	36944	36944	0	0
T18	0	936	0	0
T19	0	82392	0	0
T20	0	72	0	0
T21	0	11354	0	0
T22	0	4536	0	0
T46	0	864	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	488800131	0	0
T1	31548	31489	0	0
T2	1020619	1020262	0	0
T3	760	706	0	0
T4	426173	342846	0	0
T5	363290	309233	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	14023	12430	0	0
T9	104181	92928	0	0
T10	3858	3671	0	0
T11	326676	438685	0	0
T12	379220	278249	0	0
T13	852024	423149	0	0
T16	742	648	0	0
T17	36944	36944	0	0
T18	0	936	0	0
T19	0	82392	0	0
T20	0	72	0	0
T21	0	11354	0	0
T22	0	4536	0	0
T46	0	864	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	3003276	0	0
T1	31548	840	0	0
T2	1020619	832	0	0
T3	760	0	0	0
T4	346655	0	0	0
T5	311897	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	12964	0	0	0
T9	93011	832	0	0
T10	3750	832	0	0
T11	326676	54926	0	0
T12	379220	34194	0	0
T13	852024	9345	0	0
T16	742	0	0	0
T17	36944	832	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	832	0	0
T22	4536	0	0	0
T29	0	884	0	0
T30	0	516	0	0
T31	0	259	0	0
T32	0	513	0	0
T34	0	6036	0	0
T35	0	848	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	3003276	0	0
T1	31548	840	0	0
T2	1020619	832	0	0
T3	760	0	0	0
T4	346655	0	0	0
T5	311897	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	12964	0	0	0
T9	93011	832	0	0
T10	3750	832	0	0
T11	326676	54926	0	0
T12	379220	34194	0	0
T13	852024	9345	0	0
T16	742	0	0	0
T17	36944	832	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	832	0	0
T22	4536	0	0	0
T29	0	884	0	0
T30	0	516	0	0
T31	0	259	0	0
T32	0	513	0	0
T34	0	6036	0	0
T35	0	848	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	3003276	0	0
T1	31548	840	0	0
T2	1020619	832	0	0
T3	760	0	0	0
T4	346655	0	0	0
T5	311897	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	12964	0	0	0
T9	93011	832	0	0
T10	3750	832	0	0
T11	326676	54926	0	0
T12	379220	34194	0	0
T13	852024	9345	0	0
T16	742	0	0	0
T17	36944	832	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	832	0	0
T22	4536	0	0	0
T29	0	884	0	0
T30	0	516	0	0
T31	0	259	0	0
T32	0	513	0	0
T34	0	6036	0	0
T35	0	848	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	3003276	0	0
T1	31548	840	0	0
T2	1020619	832	0	0
T3	760	0	0	0
T4	346655	0	0	0
T5	311897	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	12964	0	0	0
T9	93011	832	0	0
T10	3750	832	0	0
T11	326676	54926	0	0
T12	379220	34194	0	0
T13	852024	9345	0	0
T16	742	0	0	0
T17	36944	832	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	832	0	0
T22	4536	0	0	0
T29	0	884	0	0
T30	0	516	0	0
T31	0	259	0	0
T32	0	513	0	0
T34	0	6036	0	0
T35	0	848	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	3	0	926
T51	168433	1	0	1
T52	0	2	0	0
T53	185627	0	0	1
T54	234781	0	0	1
T55	130314	0	0	1
T56	53959	0	0	1
T57	53568	0	0	1
T58	34772	0	0	1
T59	717300	0	0	1
T60	327584	0	0	1
T61	22483	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	488800131	0	0
T1	31548	31489	0	0
T2	1020619	1020262	0	0
T3	760	706	0	0
T4	426173	342846	0	0
T5	363290	309233	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	14023	12430	0	0
T9	104181	92928	0	0
T10	3858	3671	0	0
T11	326676	438685	0	0
T12	379220	278249	0	0
T13	852024	423149	0	0
T16	742	648	0	0
T17	36944	36944	0	0
T18	0	936	0	0
T19	0	82392	0	0
T20	0	72	0	0
T21	0	11354	0	0
T22	0	4536	0	0
T46	0	864	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	617072828	3003276	0	0
T1	31548	840	0	0
T2	1020619	832	0	0
T3	760	0	0	0
T4	346655	0	0	0
T5	311897	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	12964	0	0	0
T9	93011	832	0	0
T10	3750	832	0	0
T11	326676	54926	0	0
T12	379220	34194	0	0
T13	852024	9345	0	0
T16	742	0	0	0
T17	36944	832	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	832	0	0
T22	4536	0	0	0
T29	0	884	0	0
T30	0	516	0	0
T31	0	259	0	0
T32	0	513	0	0
T34	0	6036	0	0
T35	0	848	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T30
1	0	Covered	T11,T12,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Unreachable
1	1	Covered	T11,T12,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T12,T30
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	126916676	31351693	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	126916676	674095	0	0
GntImpliesValid_A	126916676	674095	0	0
GrantKnown_A	126916676	31351693	0	0
IdxKnown_A	126916676	31351693	0	0
IndexIsCorrect_A	126916676	674095	0	0
LockArbDecision_A	126916676	0	0	0
NoReadyValidNoGrant_A	126916676	0	0	0
ReadyAndValidImplyGrant_A	126916676	674095	0	0
ReqAndReadyImplyGrant_A	126916676	674095	0	0
ReqImpliesValid_A	126916676	674095	0	0
ReqStaysHighUntilGranted0_M	126916676	0	0	0
RoundRobin_A	126916676	0	0	0
ValidKnown_A	126916676	31351693	0	0
gen_data_port_assertion.DataFlow_A	126916676	674095	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	31351693	0	0
T4	79518	75776	0	0
T5	51393	48808	0	0
T8	1059	576	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	307560	0	0
T12	189610	99464	0	0
T13	426012	0	0	0
T16	742	648	0	0
T17	36944	0	0	0
T18	0	936	0	0
T19	0	82392	0	0
T20	0	72	0	0
T46	0	864	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	674095	0	0
T11	163338	9850	0	0
T12	189610	2927	0	0
T13	426012	0	0	0
T16	742	0	0	0
T17	36944	0	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	0	0	0
T22	4536	0	0	0
T30	0	516	0	0
T34	0	2140	0	0
T35	0	591	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	674095	0	0
T11	163338	9850	0	0
T12	189610	2927	0	0
T13	426012	0	0	0
T16	742	0	0	0
T17	36944	0	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	0	0	0
T22	4536	0	0	0
T30	0	516	0	0
T34	0	2140	0	0
T35	0	591	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	31351693	0	0
T4	79518	75776	0	0
T5	51393	48808	0	0
T8	1059	576	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	307560	0	0
T12	189610	99464	0	0
T13	426012	0	0	0
T16	742	648	0	0
T17	36944	0	0	0
T18	0	936	0	0
T19	0	82392	0	0
T20	0	72	0	0
T46	0	864	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	31351693	0	0
T4	79518	75776	0	0
T5	51393	48808	0	0
T8	1059	576	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	307560	0	0
T12	189610	99464	0	0
T13	426012	0	0	0
T16	742	648	0	0
T17	36944	0	0	0
T18	0	936	0	0
T19	0	82392	0	0
T20	0	72	0	0
T46	0	864	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	674095	0	0
T11	163338	9850	0	0
T12	189610	2927	0	0
T13	426012	0	0	0
T16	742	0	0	0
T17	36944	0	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	0	0	0
T22	4536	0	0	0
T30	0	516	0	0
T34	0	2140	0	0
T35	0	591	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	674095	0	0
T11	163338	9850	0	0
T12	189610	2927	0	0
T13	426012	0	0	0
T16	742	0	0	0
T17	36944	0	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	0	0	0
T22	4536	0	0	0
T30	0	516	0	0
T34	0	2140	0	0
T35	0	591	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	674095	0	0
T11	163338	9850	0	0
T12	189610	2927	0	0
T13	426012	0	0	0
T16	742	0	0	0
T17	36944	0	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	0	0	0
T22	4536	0	0	0
T30	0	516	0	0
T34	0	2140	0	0
T35	0	591	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	674095	0	0
T11	163338	9850	0	0
T12	189610	2927	0	0
T13	426012	0	0	0
T16	742	0	0	0
T17	36944	0	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	0	0	0
T22	4536	0	0	0
T30	0	516	0	0
T34	0	2140	0	0
T35	0	591	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	31351693	0	0
T4	79518	75776	0	0
T5	51393	48808	0	0
T8	1059	576	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	307560	0	0
T12	189610	99464	0	0
T13	426012	0	0	0
T16	742	648	0	0
T17	36944	0	0	0
T18	0	936	0	0
T19	0	82392	0	0
T20	0	72	0	0
T46	0	864	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	674095	0	0
T11	163338	9850	0	0
T12	189610	2927	0	0
T13	426012	0	0	0
T16	742	0	0	0
T17	36944	0	0	0
T18	936	0	0	0
T19	87268	0	0	0
T20	72	0	0	0
T21	11435	0	0	0
T22	4536	0	0	0
T30	0	516	0	0
T34	0	2140	0	0
T35	0	591	0	0
T39	0	5017	0	0
T47	0	35	0	0
T48	0	4242	0	0
T49	0	6189	0	0
T50	0	108	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Unreachable
1	1	Covered	T1,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T11,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	126916676	94294782	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	126916676	444142	0	0
GntImpliesValid_A	126916676	444142	0	0
GrantKnown_A	126916676	94294782	0	0
IdxKnown_A	126916676	94294782	0	0
IndexIsCorrect_A	126916676	444142	0	0
LockArbDecision_A	126916676	0	0	0
NoReadyValidNoGrant_A	126916676	0	0	0
ReadyAndValidImplyGrant_A	126916676	444142	0	0
ReqAndReadyImplyGrant_A	126916676	444142	0	0
ReqImpliesValid_A	126916676	444142	0	0
ReqStaysHighUntilGranted0_M	126916676	0	0	0
RoundRobin_A	126916676	0	0	0
ValidKnown_A	126916676	94294782	0	0
gen_data_port_assertion.DataFlow_A	126916676	444142	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	94294782	0	0
T1	4246	4246	0	0
T2	112169	111898	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	11170	0	0
T10	108	108	0	0
T11	163338	131125	0	0
T12	189610	178785	0	0
T13	426012	423149	0	0
T17	0	36944	0	0
T21	0	11354	0	0
T22	0	4536	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	444142	0	0
T1	4246	4	0	0
T2	112169	0	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	17391	0	0
T12	189610	8517	0	0
T13	426012	147	0	0
T29	0	884	0	0
T31	0	259	0	0
T32	0	513	0	0
T33	0	2770	0	0
T34	0	3896	0	0
T35	0	257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	444142	0	0
T1	4246	4	0	0
T2	112169	0	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	17391	0	0
T12	189610	8517	0	0
T13	426012	147	0	0
T29	0	884	0	0
T31	0	259	0	0
T32	0	513	0	0
T33	0	2770	0	0
T34	0	3896	0	0
T35	0	257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	94294782	0	0
T1	4246	4246	0	0
T2	112169	111898	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	11170	0	0
T10	108	108	0	0
T11	163338	131125	0	0
T12	189610	178785	0	0
T13	426012	423149	0	0
T17	0	36944	0	0
T21	0	11354	0	0
T22	0	4536	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	94294782	0	0
T1	4246	4246	0	0
T2	112169	111898	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	11170	0	0
T10	108	108	0	0
T11	163338	131125	0	0
T12	189610	178785	0	0
T13	426012	423149	0	0
T17	0	36944	0	0
T21	0	11354	0	0
T22	0	4536	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	444142	0	0
T1	4246	4	0	0
T2	112169	0	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	17391	0	0
T12	189610	8517	0	0
T13	426012	147	0	0
T29	0	884	0	0
T31	0	259	0	0
T32	0	513	0	0
T33	0	2770	0	0
T34	0	3896	0	0
T35	0	257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	444142	0	0
T1	4246	4	0	0
T2	112169	0	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	17391	0	0
T12	189610	8517	0	0
T13	426012	147	0	0
T29	0	884	0	0
T31	0	259	0	0
T32	0	513	0	0
T33	0	2770	0	0
T34	0	3896	0	0
T35	0	257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	444142	0	0
T1	4246	4	0	0
T2	112169	0	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	17391	0	0
T12	189610	8517	0	0
T13	426012	147	0	0
T29	0	884	0	0
T31	0	259	0	0
T32	0	513	0	0
T33	0	2770	0	0
T34	0	3896	0	0
T35	0	257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	444142	0	0
T1	4246	4	0	0
T2	112169	0	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	17391	0	0
T12	189610	8517	0	0
T13	426012	147	0	0
T29	0	884	0	0
T31	0	259	0	0
T32	0	513	0	0
T33	0	2770	0	0
T34	0	3896	0	0
T35	0	257	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	94294782	0	0
T1	4246	4246	0	0
T2	112169	111898	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	11170	0	0
T10	108	108	0	0
T11	163338	131125	0	0
T12	189610	178785	0	0
T13	426012	423149	0	0
T17	0	36944	0	0
T21	0	11354	0	0
T22	0	4536	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126916676	444142	0	0
T1	4246	4	0	0
T2	112169	0	0	0
T4	79518	0	0	0
T5	51393	0	0	0
T8	1059	0	0	0
T9	11170	0	0	0
T10	108	0	0	0
T11	163338	17391	0	0
T12	189610	8517	0	0
T13	426012	147	0	0
T29	0	884	0	0
T31	0	259	0	0
T32	0	513	0	0
T33	0	2770	0	0
T34	0	3896	0	0
T35	0	257	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	363239476	363153656	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	363239476	1885039	0	0
GntImpliesValid_A	363239476	1885039	0	0
GrantKnown_A	363239476	363153656	0	0
IdxKnown_A	363239476	363153656	0	0
IndexIsCorrect_A	363239476	1885039	0	0
LockArbDecision_A	363239476	0	0	0
NoReadyValidNoGrant_A	363239476	0	0	0
ReadyAndValidImplyGrant_A	363239476	1885039	0	0
ReqAndReadyImplyGrant_A	363239476	1885039	0	0
ReqImpliesValid_A	363239476	1885039	0	0
ReqStaysHighUntilGranted0_M	363239476	0	0	0
RoundRobin_A	363239476	3	0	926
ValidKnown_A	363239476	363153656	0	0
gen_data_port_assertion.DataFlow_A	363239476	1885039	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	363153656	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	1885039	0	0
T1	27302	836	0	0
T2	908450	832	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	11905	0	0	0
T9	81841	832	0	0
T10	3642	832	0	0
T11	0	27685	0	0
T12	0	22750	0	0
T13	0	9198	0	0
T17	0	832	0	0
T21	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	1885039	0	0
T1	27302	836	0	0
T2	908450	832	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	11905	0	0	0
T9	81841	832	0	0
T10	3642	832	0	0
T11	0	27685	0	0
T12	0	22750	0	0
T13	0	9198	0	0
T17	0	832	0	0
T21	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	363153656	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	363153656	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	1885039	0	0
T1	27302	836	0	0
T2	908450	832	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	11905	0	0	0
T9	81841	832	0	0
T10	3642	832	0	0
T11	0	27685	0	0
T12	0	22750	0	0
T13	0	9198	0	0
T17	0	832	0	0
T21	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	1885039	0	0
T1	27302	836	0	0
T2	908450	832	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	11905	0	0	0
T9	81841	832	0	0
T10	3642	832	0	0
T11	0	27685	0	0
T12	0	22750	0	0
T13	0	9198	0	0
T17	0	832	0	0
T21	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	1885039	0	0
T1	27302	836	0	0
T2	908450	832	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	11905	0	0	0
T9	81841	832	0	0
T10	3642	832	0	0
T11	0	27685	0	0
T12	0	22750	0	0
T13	0	9198	0	0
T17	0	832	0	0
T21	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	1885039	0	0
T1	27302	836	0	0
T2	908450	832	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	11905	0	0	0
T9	81841	832	0	0
T10	3642	832	0	0
T11	0	27685	0	0
T12	0	22750	0	0
T13	0	9198	0	0
T17	0	832	0	0
T21	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	3	0	926
T51	168433	1	0	1
T52	0	2	0	0
T53	185627	0	0	1
T54	234781	0	0	1
T55	130314	0	0	1
T56	53959	0	0	1
T57	53568	0	0	1
T58	34772	0	0	1
T59	717300	0	0	1
T60	327584	0	0	1
T61	22483	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	363153656	0	0
T1	27302	27243	0	0
T2	908450	908364	0	0
T3	760	706	0	0
T4	267137	267070	0	0
T5	260504	260425	0	0
T6	685	626	0	0
T7	3438	3379	0	0
T8	11905	11854	0	0
T9	81841	81758	0	0
T10	3642	3563	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	363239476	1885039	0	0
T1	27302	836	0	0
T2	908450	832	0	0
T3	760	0	0	0
T4	267137	0	0	0
T5	260504	0	0	0
T6	685	0	0	0
T7	3438	832	0	0
T8	11905	0	0	0
T9	81841	832	0	0
T10	3642	832	0	0
T11	0	27685	0	0
T12	0	22750	0	0
T13	0	9198	0	0
T17	0	832	0	0
T21	0	832	0	0