Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3755 |
0 |
0 |
T91 |
27826 |
1 |
0 |
0 |
T92 |
4920 |
176 |
0 |
0 |
T93 |
2552 |
69 |
0 |
0 |
T94 |
3059 |
123 |
0 |
0 |
T95 |
7949 |
121 |
0 |
0 |
T96 |
10010 |
2 |
0 |
0 |
T97 |
98339 |
3 |
0 |
0 |
T100 |
15575 |
274 |
0 |
0 |
T105 |
8718 |
2 |
0 |
0 |
T106 |
5345 |
81 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1245 |
0 |
0 |
T97 |
98339 |
123 |
0 |
0 |
T108 |
31286 |
21 |
0 |
0 |
T113 |
73109 |
265 |
0 |
0 |
T116 |
12856 |
16 |
0 |
0 |
T122 |
7146 |
9 |
0 |
0 |
T140 |
20744 |
110 |
0 |
0 |
T152 |
7732 |
11 |
0 |
0 |
T153 |
18567 |
88 |
0 |
0 |
T154 |
7566 |
1 |
0 |
0 |
T155 |
30547 |
15 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1087 |
0 |
0 |
T97 |
98339 |
111 |
0 |
0 |
T108 |
31286 |
23 |
0 |
0 |
T113 |
73109 |
235 |
0 |
0 |
T116 |
12856 |
13 |
0 |
0 |
T122 |
7146 |
7 |
0 |
0 |
T140 |
20744 |
55 |
0 |
0 |
T152 |
7732 |
1 |
0 |
0 |
T153 |
18567 |
39 |
0 |
0 |
T154 |
7566 |
9 |
0 |
0 |
T155 |
30547 |
9 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1600 |
0 |
0 |
T97 |
98339 |
241 |
0 |
0 |
T108 |
31286 |
41 |
0 |
0 |
T113 |
73109 |
261 |
0 |
0 |
T116 |
12856 |
18 |
0 |
0 |
T122 |
7146 |
15 |
0 |
0 |
T140 |
20744 |
53 |
0 |
0 |
T152 |
7732 |
8 |
0 |
0 |
T153 |
18567 |
18 |
0 |
0 |
T155 |
30547 |
34 |
0 |
0 |
T156 |
10090 |
21 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
7701 |
0 |
0 |
T97 |
98339 |
1570 |
0 |
0 |
T108 |
31286 |
174 |
0 |
0 |
T113 |
73109 |
245 |
0 |
0 |
T116 |
12856 |
222 |
0 |
0 |
T122 |
7146 |
5 |
0 |
0 |
T140 |
20744 |
49 |
0 |
0 |
T152 |
7732 |
72 |
0 |
0 |
T153 |
18567 |
45 |
0 |
0 |
T154 |
7566 |
1 |
0 |
0 |
T155 |
30547 |
385 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
8808 |
0 |
0 |
T97 |
98339 |
1812 |
0 |
0 |
T108 |
31286 |
263 |
0 |
0 |
T113 |
73109 |
240 |
0 |
0 |
T116 |
12856 |
134 |
0 |
0 |
T122 |
7146 |
87 |
0 |
0 |
T140 |
20744 |
35 |
0 |
0 |
T152 |
7732 |
47 |
0 |
0 |
T153 |
18567 |
53 |
0 |
0 |
T154 |
7566 |
205 |
0 |
0 |
T155 |
30547 |
499 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
8210 |
0 |
0 |
T97 |
98339 |
1779 |
0 |
0 |
T108 |
31286 |
347 |
0 |
0 |
T113 |
73109 |
223 |
0 |
0 |
T116 |
12856 |
288 |
0 |
0 |
T122 |
7146 |
240 |
0 |
0 |
T140 |
20744 |
114 |
0 |
0 |
T152 |
7732 |
126 |
0 |
0 |
T153 |
18567 |
46 |
0 |
0 |
T154 |
7566 |
54 |
0 |
0 |
T155 |
30547 |
367 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
7787 |
0 |
0 |
T97 |
98339 |
1444 |
0 |
0 |
T108 |
31286 |
250 |
0 |
0 |
T113 |
73109 |
316 |
0 |
0 |
T116 |
12856 |
225 |
0 |
0 |
T122 |
7146 |
6 |
0 |
0 |
T140 |
20744 |
59 |
0 |
0 |
T152 |
7732 |
63 |
0 |
0 |
T153 |
18567 |
122 |
0 |
0 |
T154 |
7566 |
50 |
0 |
0 |
T155 |
30547 |
339 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
9046 |
0 |
0 |
T97 |
98339 |
2417 |
0 |
0 |
T108 |
31286 |
82 |
0 |
0 |
T113 |
73109 |
271 |
0 |
0 |
T116 |
12856 |
263 |
0 |
0 |
T122 |
7146 |
113 |
0 |
0 |
T140 |
20744 |
106 |
0 |
0 |
T152 |
7732 |
174 |
0 |
0 |
T153 |
18567 |
35 |
0 |
0 |
T154 |
7566 |
72 |
0 |
0 |
T155 |
30547 |
225 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
7495 |
0 |
0 |
T97 |
98339 |
1824 |
0 |
0 |
T108 |
31286 |
349 |
0 |
0 |
T113 |
73109 |
293 |
0 |
0 |
T116 |
12856 |
376 |
0 |
0 |
T122 |
7146 |
12 |
0 |
0 |
T140 |
20744 |
62 |
0 |
0 |
T152 |
7732 |
3 |
0 |
0 |
T153 |
18567 |
68 |
0 |
0 |
T154 |
7566 |
70 |
0 |
0 |
T155 |
30547 |
386 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
6905 |
0 |
0 |
T97 |
98339 |
2109 |
0 |
0 |
T108 |
31286 |
91 |
0 |
0 |
T113 |
73109 |
288 |
0 |
0 |
T116 |
12856 |
308 |
0 |
0 |
T122 |
7146 |
3 |
0 |
0 |
T140 |
20744 |
60 |
0 |
0 |
T153 |
18567 |
71 |
0 |
0 |
T154 |
7566 |
87 |
0 |
0 |
T155 |
30547 |
254 |
0 |
0 |
T156 |
10090 |
101 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
8973 |
0 |
0 |
T97 |
98339 |
1861 |
0 |
0 |
T108 |
31286 |
491 |
0 |
0 |
T113 |
73109 |
305 |
0 |
0 |
T116 |
12856 |
215 |
0 |
0 |
T122 |
7146 |
220 |
0 |
0 |
T140 |
20744 |
55 |
0 |
0 |
T152 |
7732 |
59 |
0 |
0 |
T153 |
18567 |
47 |
0 |
0 |
T154 |
7566 |
68 |
0 |
0 |
T155 |
30547 |
308 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4215 |
0 |
0 |
T97 |
98339 |
1026 |
0 |
0 |
T108 |
31286 |
198 |
0 |
0 |
T113 |
73109 |
255 |
0 |
0 |
T116 |
12856 |
37 |
0 |
0 |
T122 |
7146 |
44 |
0 |
0 |
T140 |
20744 |
86 |
0 |
0 |
T152 |
7732 |
41 |
0 |
0 |
T153 |
18567 |
75 |
0 |
0 |
T154 |
7566 |
9 |
0 |
0 |
T155 |
30547 |
144 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3232 |
0 |
0 |
T97 |
98339 |
569 |
0 |
0 |
T108 |
31286 |
163 |
0 |
0 |
T113 |
73109 |
269 |
0 |
0 |
T116 |
12856 |
65 |
0 |
0 |
T122 |
7146 |
84 |
0 |
0 |
T140 |
20744 |
64 |
0 |
0 |
T152 |
7732 |
50 |
0 |
0 |
T153 |
18567 |
26 |
0 |
0 |
T154 |
7566 |
14 |
0 |
0 |
T155 |
30547 |
116 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4053 |
0 |
0 |
T97 |
98339 |
871 |
0 |
0 |
T108 |
31286 |
193 |
0 |
0 |
T113 |
73109 |
312 |
0 |
0 |
T116 |
12856 |
103 |
0 |
0 |
T122 |
7146 |
67 |
0 |
0 |
T140 |
20744 |
49 |
0 |
0 |
T152 |
7732 |
62 |
0 |
0 |
T153 |
18567 |
109 |
0 |
0 |
T154 |
7566 |
43 |
0 |
0 |
T155 |
30547 |
97 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4491 |
0 |
0 |
T97 |
98339 |
792 |
0 |
0 |
T108 |
31286 |
216 |
0 |
0 |
T113 |
73109 |
287 |
0 |
0 |
T116 |
12856 |
13 |
0 |
0 |
T122 |
7146 |
51 |
0 |
0 |
T140 |
20744 |
87 |
0 |
0 |
T152 |
7732 |
49 |
0 |
0 |
T153 |
18567 |
71 |
0 |
0 |
T154 |
7566 |
34 |
0 |
0 |
T155 |
30547 |
110 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3992 |
0 |
0 |
T97 |
98339 |
707 |
0 |
0 |
T108 |
31286 |
140 |
0 |
0 |
T113 |
73109 |
265 |
0 |
0 |
T116 |
12856 |
134 |
0 |
0 |
T122 |
7146 |
73 |
0 |
0 |
T140 |
20744 |
38 |
0 |
0 |
T152 |
7732 |
66 |
0 |
0 |
T153 |
18567 |
60 |
0 |
0 |
T154 |
7566 |
29 |
0 |
0 |
T155 |
30547 |
117 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4340 |
0 |
0 |
T97 |
98339 |
922 |
0 |
0 |
T108 |
31286 |
118 |
0 |
0 |
T113 |
73109 |
318 |
0 |
0 |
T116 |
12856 |
117 |
0 |
0 |
T122 |
7146 |
95 |
0 |
0 |
T140 |
20744 |
73 |
0 |
0 |
T152 |
7732 |
25 |
0 |
0 |
T153 |
18567 |
83 |
0 |
0 |
T154 |
7566 |
48 |
0 |
0 |
T155 |
30547 |
172 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3925 |
0 |
0 |
T97 |
98339 |
594 |
0 |
0 |
T108 |
31286 |
171 |
0 |
0 |
T113 |
73109 |
248 |
0 |
0 |
T116 |
12856 |
45 |
0 |
0 |
T140 |
20744 |
47 |
0 |
0 |
T152 |
7732 |
50 |
0 |
0 |
T153 |
18567 |
61 |
0 |
0 |
T154 |
7566 |
4 |
0 |
0 |
T155 |
30547 |
196 |
0 |
0 |
T156 |
10090 |
52 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3961 |
0 |
0 |
T97 |
98339 |
776 |
0 |
0 |
T108 |
31286 |
175 |
0 |
0 |
T113 |
73109 |
293 |
0 |
0 |
T116 |
12856 |
5 |
0 |
0 |
T122 |
7146 |
42 |
0 |
0 |
T140 |
20744 |
74 |
0 |
0 |
T152 |
7732 |
44 |
0 |
0 |
T153 |
18567 |
73 |
0 |
0 |
T155 |
30547 |
145 |
0 |
0 |
T156 |
10090 |
13 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3897 |
0 |
0 |
T97 |
98339 |
725 |
0 |
0 |
T102 |
12603 |
1 |
0 |
0 |
T108 |
31286 |
127 |
0 |
0 |
T113 |
73109 |
344 |
0 |
0 |
T116 |
12856 |
54 |
0 |
0 |
T122 |
7146 |
9 |
0 |
0 |
T140 |
20744 |
20 |
0 |
0 |
T152 |
7732 |
37 |
0 |
0 |
T153 |
18567 |
41 |
0 |
0 |
T154 |
7566 |
27 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3956 |
0 |
0 |
T97 |
98339 |
832 |
0 |
0 |
T108 |
31286 |
226 |
0 |
0 |
T113 |
73109 |
238 |
0 |
0 |
T116 |
12856 |
55 |
0 |
0 |
T122 |
7146 |
46 |
0 |
0 |
T140 |
20744 |
110 |
0 |
0 |
T152 |
7732 |
43 |
0 |
0 |
T153 |
18567 |
59 |
0 |
0 |
T154 |
7566 |
38 |
0 |
0 |
T155 |
30547 |
156 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4300 |
0 |
0 |
T97 |
98339 |
693 |
0 |
0 |
T108 |
31286 |
212 |
0 |
0 |
T113 |
73109 |
309 |
0 |
0 |
T116 |
12856 |
159 |
0 |
0 |
T122 |
7146 |
55 |
0 |
0 |
T140 |
20744 |
67 |
0 |
0 |
T152 |
7732 |
28 |
0 |
0 |
T153 |
18567 |
83 |
0 |
0 |
T154 |
7566 |
38 |
0 |
0 |
T155 |
30547 |
140 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4275 |
0 |
0 |
T97 |
98339 |
811 |
0 |
0 |
T108 |
31286 |
120 |
0 |
0 |
T113 |
73109 |
348 |
0 |
0 |
T116 |
12856 |
164 |
0 |
0 |
T122 |
7146 |
94 |
0 |
0 |
T140 |
20744 |
65 |
0 |
0 |
T152 |
7732 |
45 |
0 |
0 |
T153 |
18567 |
26 |
0 |
0 |
T154 |
7566 |
31 |
0 |
0 |
T155 |
30547 |
242 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4143 |
0 |
0 |
T97 |
98339 |
771 |
0 |
0 |
T108 |
31286 |
159 |
0 |
0 |
T113 |
73109 |
306 |
0 |
0 |
T116 |
12856 |
88 |
0 |
0 |
T122 |
7146 |
91 |
0 |
0 |
T140 |
20744 |
85 |
0 |
0 |
T152 |
7732 |
32 |
0 |
0 |
T153 |
18567 |
41 |
0 |
0 |
T154 |
7566 |
45 |
0 |
0 |
T155 |
30547 |
160 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3492 |
0 |
0 |
T97 |
98339 |
687 |
0 |
0 |
T108 |
31286 |
209 |
0 |
0 |
T113 |
73109 |
264 |
0 |
0 |
T116 |
12856 |
94 |
0 |
0 |
T122 |
7146 |
18 |
0 |
0 |
T140 |
20744 |
71 |
0 |
0 |
T152 |
7732 |
10 |
0 |
0 |
T153 |
18567 |
36 |
0 |
0 |
T154 |
7566 |
28 |
0 |
0 |
T155 |
30547 |
62 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4093 |
0 |
0 |
T97 |
98339 |
834 |
0 |
0 |
T108 |
31286 |
129 |
0 |
0 |
T113 |
73109 |
281 |
0 |
0 |
T116 |
12856 |
72 |
0 |
0 |
T122 |
7146 |
99 |
0 |
0 |
T140 |
20744 |
48 |
0 |
0 |
T152 |
7732 |
75 |
0 |
0 |
T153 |
18567 |
61 |
0 |
0 |
T154 |
7566 |
44 |
0 |
0 |
T155 |
30547 |
168 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3951 |
0 |
0 |
T97 |
98339 |
678 |
0 |
0 |
T108 |
31286 |
113 |
0 |
0 |
T113 |
73109 |
313 |
0 |
0 |
T116 |
12856 |
93 |
0 |
0 |
T122 |
7146 |
88 |
0 |
0 |
T140 |
20744 |
120 |
0 |
0 |
T152 |
7732 |
78 |
0 |
0 |
T153 |
18567 |
81 |
0 |
0 |
T154 |
7566 |
38 |
0 |
0 |
T155 |
30547 |
72 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4206 |
0 |
0 |
T97 |
98339 |
692 |
0 |
0 |
T108 |
31286 |
228 |
0 |
0 |
T113 |
73109 |
256 |
0 |
0 |
T116 |
12856 |
121 |
0 |
0 |
T122 |
7146 |
32 |
0 |
0 |
T140 |
20744 |
49 |
0 |
0 |
T152 |
7732 |
25 |
0 |
0 |
T153 |
18567 |
42 |
0 |
0 |
T154 |
7566 |
51 |
0 |
0 |
T155 |
30547 |
167 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3516 |
0 |
0 |
T97 |
98339 |
699 |
0 |
0 |
T102 |
12603 |
5 |
0 |
0 |
T108 |
31286 |
107 |
0 |
0 |
T113 |
73109 |
253 |
0 |
0 |
T116 |
12856 |
119 |
0 |
0 |
T122 |
7146 |
58 |
0 |
0 |
T140 |
20744 |
67 |
0 |
0 |
T152 |
7732 |
36 |
0 |
0 |
T153 |
18567 |
91 |
0 |
0 |
T154 |
7566 |
45 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4216 |
0 |
0 |
T97 |
98339 |
1015 |
0 |
0 |
T108 |
31286 |
128 |
0 |
0 |
T113 |
73109 |
320 |
0 |
0 |
T116 |
12856 |
50 |
0 |
0 |
T122 |
7146 |
80 |
0 |
0 |
T140 |
20744 |
71 |
0 |
0 |
T152 |
7732 |
42 |
0 |
0 |
T153 |
18567 |
41 |
0 |
0 |
T154 |
7566 |
45 |
0 |
0 |
T155 |
30547 |
78 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4263 |
0 |
0 |
T97 |
98339 |
979 |
0 |
0 |
T108 |
31286 |
209 |
0 |
0 |
T113 |
73109 |
304 |
0 |
0 |
T116 |
12856 |
103 |
0 |
0 |
T122 |
7146 |
49 |
0 |
0 |
T140 |
20744 |
109 |
0 |
0 |
T152 |
7732 |
6 |
0 |
0 |
T153 |
18567 |
66 |
0 |
0 |
T154 |
7566 |
15 |
0 |
0 |
T155 |
30547 |
168 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3572 |
0 |
0 |
T97 |
98339 |
894 |
0 |
0 |
T108 |
31286 |
123 |
0 |
0 |
T113 |
73109 |
242 |
0 |
0 |
T116 |
12856 |
62 |
0 |
0 |
T122 |
7146 |
67 |
0 |
0 |
T140 |
20744 |
20 |
0 |
0 |
T152 |
7732 |
35 |
0 |
0 |
T153 |
18567 |
42 |
0 |
0 |
T154 |
7566 |
39 |
0 |
0 |
T155 |
30547 |
79 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4075 |
0 |
0 |
T97 |
98339 |
574 |
0 |
0 |
T108 |
31286 |
119 |
0 |
0 |
T113 |
73109 |
290 |
0 |
0 |
T116 |
12856 |
100 |
0 |
0 |
T122 |
7146 |
68 |
0 |
0 |
T140 |
20744 |
46 |
0 |
0 |
T152 |
7732 |
32 |
0 |
0 |
T153 |
18567 |
67 |
0 |
0 |
T154 |
7566 |
60 |
0 |
0 |
T155 |
30547 |
188 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4199 |
0 |
0 |
T97 |
98339 |
1056 |
0 |
0 |
T108 |
31286 |
68 |
0 |
0 |
T113 |
73109 |
232 |
0 |
0 |
T116 |
12856 |
87 |
0 |
0 |
T122 |
7146 |
74 |
0 |
0 |
T140 |
20744 |
44 |
0 |
0 |
T152 |
7732 |
12 |
0 |
0 |
T153 |
18567 |
84 |
0 |
0 |
T154 |
7566 |
66 |
0 |
0 |
T155 |
30547 |
134 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
4255 |
0 |
0 |
T97 |
98339 |
1124 |
0 |
0 |
T108 |
31286 |
82 |
0 |
0 |
T113 |
73109 |
272 |
0 |
0 |
T116 |
12856 |
78 |
0 |
0 |
T122 |
7146 |
101 |
0 |
0 |
T140 |
20744 |
70 |
0 |
0 |
T152 |
7732 |
69 |
0 |
0 |
T153 |
18567 |
71 |
0 |
0 |
T154 |
7566 |
28 |
0 |
0 |
T155 |
30547 |
144 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1396 |
0 |
0 |
T97 |
98339 |
155 |
0 |
0 |
T108 |
31286 |
14 |
0 |
0 |
T113 |
73109 |
327 |
0 |
0 |
T116 |
12856 |
25 |
0 |
0 |
T122 |
7146 |
11 |
0 |
0 |
T140 |
20744 |
103 |
0 |
0 |
T152 |
7732 |
2 |
0 |
0 |
T153 |
18567 |
76 |
0 |
0 |
T154 |
7566 |
10 |
0 |
0 |
T155 |
30547 |
52 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1550 |
0 |
0 |
T97 |
98339 |
179 |
0 |
0 |
T108 |
31286 |
26 |
0 |
0 |
T113 |
73109 |
277 |
0 |
0 |
T116 |
12856 |
21 |
0 |
0 |
T122 |
7146 |
10 |
0 |
0 |
T140 |
20744 |
111 |
0 |
0 |
T152 |
7732 |
7 |
0 |
0 |
T153 |
18567 |
47 |
0 |
0 |
T154 |
7566 |
8 |
0 |
0 |
T155 |
30547 |
45 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1275 |
0 |
0 |
T97 |
98339 |
153 |
0 |
0 |
T108 |
31286 |
20 |
0 |
0 |
T113 |
73109 |
274 |
0 |
0 |
T116 |
12856 |
23 |
0 |
0 |
T122 |
7146 |
8 |
0 |
0 |
T140 |
20744 |
76 |
0 |
0 |
T152 |
7732 |
3 |
0 |
0 |
T153 |
18567 |
85 |
0 |
0 |
T154 |
7566 |
10 |
0 |
0 |
T155 |
30547 |
33 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1366 |
0 |
0 |
T97 |
98339 |
182 |
0 |
0 |
T108 |
31286 |
51 |
0 |
0 |
T113 |
73109 |
297 |
0 |
0 |
T116 |
12856 |
20 |
0 |
0 |
T122 |
7146 |
14 |
0 |
0 |
T140 |
20744 |
78 |
0 |
0 |
T152 |
7732 |
7 |
0 |
0 |
T153 |
18567 |
37 |
0 |
0 |
T154 |
7566 |
10 |
0 |
0 |
T155 |
30547 |
32 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1915 |
0 |
0 |
T97 |
98339 |
370 |
0 |
0 |
T108 |
31286 |
38 |
0 |
0 |
T113 |
73109 |
314 |
0 |
0 |
T116 |
12856 |
14 |
0 |
0 |
T122 |
7146 |
22 |
0 |
0 |
T140 |
20744 |
86 |
0 |
0 |
T152 |
7732 |
11 |
0 |
0 |
T153 |
18567 |
55 |
0 |
0 |
T154 |
7566 |
19 |
0 |
0 |
T155 |
30547 |
61 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
3312 |
0 |
0 |
T12 |
752175 |
7 |
0 |
0 |
T13 |
136700 |
0 |
0 |
0 |
T14 |
1227 |
0 |
0 |
0 |
T15 |
1376 |
0 |
0 |
0 |
T16 |
5024 |
0 |
0 |
0 |
T17 |
39921 |
0 |
0 |
0 |
T21 |
19504 |
0 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T36 |
1301 |
0 |
0 |
0 |
T37 |
957 |
0 |
0 |
0 |
T39 |
0 |
8 |
0 |
0 |
T63 |
0 |
58 |
0 |
0 |
T150 |
923 |
0 |
0 |
0 |
T157 |
0 |
15 |
0 |
0 |
T158 |
0 |
8 |
0 |
0 |
T159 |
0 |
8 |
0 |
0 |
T160 |
0 |
25 |
0 |
0 |
T161 |
0 |
38 |
0 |
0 |
T162 |
0 |
14 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1352 |
0 |
0 |
T97 |
98339 |
155 |
0 |
0 |
T108 |
31286 |
20 |
0 |
0 |
T113 |
73109 |
292 |
0 |
0 |
T116 |
12856 |
11 |
0 |
0 |
T122 |
7146 |
8 |
0 |
0 |
T140 |
20744 |
62 |
0 |
0 |
T153 |
18567 |
59 |
0 |
0 |
T154 |
7566 |
5 |
0 |
0 |
T155 |
30547 |
30 |
0 |
0 |
T156 |
10090 |
3 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1484 |
0 |
0 |
T97 |
98339 |
174 |
0 |
0 |
T108 |
31286 |
28 |
0 |
0 |
T113 |
73109 |
292 |
0 |
0 |
T116 |
12856 |
9 |
0 |
0 |
T122 |
7146 |
3 |
0 |
0 |
T140 |
20744 |
75 |
0 |
0 |
T152 |
7732 |
2 |
0 |
0 |
T153 |
18567 |
80 |
0 |
0 |
T154 |
7566 |
1 |
0 |
0 |
T155 |
30547 |
23 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1125 |
0 |
0 |
T97 |
98339 |
134 |
0 |
0 |
T108 |
31286 |
43 |
0 |
0 |
T113 |
73109 |
274 |
0 |
0 |
T116 |
12856 |
16 |
0 |
0 |
T122 |
7146 |
13 |
0 |
0 |
T140 |
20744 |
28 |
0 |
0 |
T152 |
7732 |
2 |
0 |
0 |
T153 |
18567 |
59 |
0 |
0 |
T154 |
7566 |
1 |
0 |
0 |
T155 |
30547 |
13 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1084 |
0 |
0 |
T97 |
98339 |
85 |
0 |
0 |
T108 |
31286 |
21 |
0 |
0 |
T113 |
73109 |
314 |
0 |
0 |
T116 |
12856 |
16 |
0 |
0 |
T122 |
7146 |
15 |
0 |
0 |
T140 |
20744 |
69 |
0 |
0 |
T152 |
7732 |
5 |
0 |
0 |
T153 |
18567 |
17 |
0 |
0 |
T155 |
30547 |
26 |
0 |
0 |
T156 |
10090 |
12 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1329 |
0 |
0 |
T97 |
98339 |
125 |
0 |
0 |
T108 |
31286 |
33 |
0 |
0 |
T113 |
73109 |
319 |
0 |
0 |
T116 |
12856 |
24 |
0 |
0 |
T122 |
7146 |
8 |
0 |
0 |
T140 |
20744 |
68 |
0 |
0 |
T152 |
7732 |
2 |
0 |
0 |
T153 |
18567 |
81 |
0 |
0 |
T154 |
7566 |
12 |
0 |
0 |
T155 |
30547 |
12 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1125 |
0 |
0 |
T97 |
98339 |
99 |
0 |
0 |
T108 |
31286 |
21 |
0 |
0 |
T113 |
73109 |
298 |
0 |
0 |
T116 |
12856 |
16 |
0 |
0 |
T122 |
7146 |
8 |
0 |
0 |
T140 |
20744 |
97 |
0 |
0 |
T152 |
7732 |
8 |
0 |
0 |
T153 |
18567 |
58 |
0 |
0 |
T154 |
7566 |
10 |
0 |
0 |
T155 |
30547 |
11 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1740 |
0 |
0 |
T97 |
98339 |
270 |
0 |
0 |
T108 |
31286 |
28 |
0 |
0 |
T113 |
73109 |
297 |
0 |
0 |
T116 |
12856 |
18 |
0 |
0 |
T122 |
7146 |
18 |
0 |
0 |
T140 |
20744 |
37 |
0 |
0 |
T152 |
7732 |
15 |
0 |
0 |
T153 |
18567 |
34 |
0 |
0 |
T154 |
7566 |
17 |
0 |
0 |
T155 |
30547 |
30 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1106 |
0 |
0 |
T95 |
7949 |
5 |
0 |
0 |
T97 |
98339 |
107 |
0 |
0 |
T108 |
31286 |
10 |
0 |
0 |
T113 |
73109 |
316 |
0 |
0 |
T116 |
12856 |
12 |
0 |
0 |
T122 |
7146 |
6 |
0 |
0 |
T140 |
20744 |
31 |
0 |
0 |
T152 |
7732 |
4 |
0 |
0 |
T153 |
18567 |
63 |
0 |
0 |
T155 |
30547 |
15 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1974 |
0 |
0 |
T97 |
98339 |
274 |
0 |
0 |
T106 |
5345 |
5 |
0 |
0 |
T108 |
31286 |
42 |
0 |
0 |
T113 |
73109 |
292 |
0 |
0 |
T116 |
12856 |
24 |
0 |
0 |
T122 |
7146 |
5 |
0 |
0 |
T140 |
20744 |
100 |
0 |
0 |
T153 |
18567 |
106 |
0 |
0 |
T154 |
7566 |
17 |
0 |
0 |
T155 |
30547 |
45 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1425 |
0 |
0 |
T97 |
98339 |
177 |
0 |
0 |
T108 |
31286 |
8 |
0 |
0 |
T113 |
73109 |
263 |
0 |
0 |
T116 |
12856 |
9 |
0 |
0 |
T122 |
7146 |
9 |
0 |
0 |
T140 |
20744 |
80 |
0 |
0 |
T152 |
7732 |
16 |
0 |
0 |
T153 |
18567 |
70 |
0 |
0 |
T154 |
7566 |
4 |
0 |
0 |
T155 |
30547 |
35 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1260 |
0 |
0 |
T97 |
98339 |
126 |
0 |
0 |
T102 |
12603 |
5 |
0 |
0 |
T108 |
31286 |
17 |
0 |
0 |
T113 |
73109 |
286 |
0 |
0 |
T116 |
12856 |
17 |
0 |
0 |
T122 |
7146 |
6 |
0 |
0 |
T140 |
20744 |
65 |
0 |
0 |
T153 |
18567 |
116 |
0 |
0 |
T154 |
7566 |
8 |
0 |
0 |
T155 |
30547 |
26 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1154 |
0 |
0 |
T97 |
98339 |
113 |
0 |
0 |
T108 |
31286 |
10 |
0 |
0 |
T113 |
73109 |
301 |
0 |
0 |
T116 |
12856 |
8 |
0 |
0 |
T122 |
7146 |
10 |
0 |
0 |
T140 |
20744 |
63 |
0 |
0 |
T152 |
7732 |
1 |
0 |
0 |
T153 |
18567 |
105 |
0 |
0 |
T154 |
7566 |
9 |
0 |
0 |
T155 |
30547 |
30 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1102 |
0 |
0 |
T97 |
98339 |
95 |
0 |
0 |
T108 |
31286 |
11 |
0 |
0 |
T113 |
73109 |
287 |
0 |
0 |
T116 |
12856 |
12 |
0 |
0 |
T122 |
7146 |
9 |
0 |
0 |
T140 |
20744 |
38 |
0 |
0 |
T152 |
7732 |
4 |
0 |
0 |
T153 |
18567 |
52 |
0 |
0 |
T154 |
7566 |
7 |
0 |
0 |
T155 |
30547 |
29 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1195 |
0 |
0 |
T97 |
98339 |
102 |
0 |
0 |
T108 |
31286 |
21 |
0 |
0 |
T113 |
73109 |
273 |
0 |
0 |
T116 |
12856 |
16 |
0 |
0 |
T122 |
7146 |
6 |
0 |
0 |
T140 |
20744 |
58 |
0 |
0 |
T153 |
18567 |
42 |
0 |
0 |
T154 |
7566 |
1 |
0 |
0 |
T155 |
30547 |
17 |
0 |
0 |
T156 |
10090 |
12 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1166 |
0 |
0 |
T97 |
98339 |
92 |
0 |
0 |
T108 |
31286 |
28 |
0 |
0 |
T113 |
73109 |
287 |
0 |
0 |
T116 |
12856 |
15 |
0 |
0 |
T122 |
7146 |
5 |
0 |
0 |
T140 |
20744 |
47 |
0 |
0 |
T152 |
7732 |
3 |
0 |
0 |
T153 |
18567 |
61 |
0 |
0 |
T154 |
7566 |
1 |
0 |
0 |
T155 |
30547 |
7 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
365504168 |
1142 |
0 |
0 |
T97 |
98339 |
113 |
0 |
0 |
T108 |
31286 |
14 |
0 |
0 |
T113 |
73109 |
249 |
0 |
0 |
T116 |
12856 |
19 |
0 |
0 |
T122 |
7146 |
4 |
0 |
0 |
T140 |
20744 |
72 |
0 |
0 |
T152 |
7732 |
12 |
0 |
0 |
T153 |
18567 |
70 |
0 |
0 |
T154 |
7566 |
10 |
0 |
0 |
T155 |
30547 |
11 |
0 |
0 |