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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.11 98.35 94.21 98.61 89.36 97.23 95.82 99.20


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1013 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3108818736 Jun 04 12:46:51 PM PDT 24 Jun 04 12:46:54 PM PDT 24 204502795 ps
T1014 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3065430757 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:15 PM PDT 24 250208622 ps
T154 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2719416535 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:14 PM PDT 24 154445701 ps
T1015 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1360618616 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:15 PM PDT 24 40380859 ps
T1016 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.909550809 Jun 04 12:47:03 PM PDT 24 Jun 04 12:47:11 PM PDT 24 367271826 ps
T1017 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4154241080 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:16 PM PDT 24 54638772 ps
T1018 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.220184003 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:13 PM PDT 24 47370771 ps
T1019 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3423011913 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:16 PM PDT 24 15150634 ps
T84 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3094703817 Jun 04 12:46:59 PM PDT 24 Jun 04 12:47:01 PM PDT 24 33456108 ps
T1020 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3094569720 Jun 04 12:47:17 PM PDT 24 Jun 04 12:47:20 PM PDT 24 19843072 ps
T1021 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1961899736 Jun 04 12:47:01 PM PDT 24 Jun 04 12:47:09 PM PDT 24 1102213870 ps
T1022 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3254893014 Jun 04 12:47:07 PM PDT 24 Jun 04 12:47:08 PM PDT 24 22553124 ps
T102 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.273108269 Jun 04 12:47:03 PM PDT 24 Jun 04 12:47:08 PM PDT 24 600175957 ps
T155 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2234426054 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:11 PM PDT 24 1388599497 ps
T156 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4033793219 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:06 PM PDT 24 101940158 ps
T270 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.141793832 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:17 PM PDT 24 1297911275 ps
T1023 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3583728639 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:08 PM PDT 24 227476175 ps
T1024 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4117121549 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:15 PM PDT 24 91975937 ps
T1025 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2606993544 Jun 04 12:46:49 PM PDT 24 Jun 04 12:47:06 PM PDT 24 3771916953 ps
T1026 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.714258945 Jun 04 12:47:08 PM PDT 24 Jun 04 12:47:09 PM PDT 24 29344708 ps
T1027 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3489329465 Jun 04 12:46:53 PM PDT 24 Jun 04 12:46:56 PM PDT 24 30175431 ps
T1028 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2390442604 Jun 04 12:47:04 PM PDT 24 Jun 04 12:47:06 PM PDT 24 12392880 ps
T1029 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3105289643 Jun 04 12:46:50 PM PDT 24 Jun 04 12:47:18 PM PDT 24 2522303135 ps
T1030 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3822154530 Jun 04 12:47:05 PM PDT 24 Jun 04 12:47:09 PM PDT 24 41704285 ps
T1031 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1502631116 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:19 PM PDT 24 14793787 ps
T1032 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.821378736 Jun 04 12:46:52 PM PDT 24 Jun 04 12:47:02 PM PDT 24 269965152 ps
T1033 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2278186982 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:15 PM PDT 24 214531358 ps
T1034 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1263109291 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:17 PM PDT 24 15231196 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4069958889 Jun 04 12:46:52 PM PDT 24 Jun 04 12:46:55 PM PDT 24 258958038 ps
T1036 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1620885997 Jun 04 12:47:10 PM PDT 24 Jun 04 12:47:11 PM PDT 24 50362653 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2951999832 Jun 04 12:46:59 PM PDT 24 Jun 04 12:47:01 PM PDT 24 69186214 ps
T1038 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3591027584 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:13 PM PDT 24 36081690 ps
T1039 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.93449771 Jun 04 12:47:12 PM PDT 24 Jun 04 12:47:15 PM PDT 24 35622902 ps
T1040 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.813026572 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:16 PM PDT 24 339203269 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2779582152 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:10 PM PDT 24 111081244 ps
T1042 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2441218641 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:06 PM PDT 24 40393903 ps
T1043 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.534429986 Jun 04 12:47:01 PM PDT 24 Jun 04 12:47:05 PM PDT 24 234732525 ps
T1044 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3523368571 Jun 04 12:47:06 PM PDT 24 Jun 04 12:47:11 PM PDT 24 60587350 ps
T1045 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.21189732 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:16 PM PDT 24 339394651 ps
T1046 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.78453809 Jun 04 12:47:05 PM PDT 24 Jun 04 12:47:09 PM PDT 24 110786434 ps
T1047 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2158655070 Jun 04 12:46:54 PM PDT 24 Jun 04 12:47:31 PM PDT 24 7541522767 ps
T1048 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2950798698 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:20 PM PDT 24 15463062 ps
T1049 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2097134766 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:17 PM PDT 24 128898652 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1042217857 Jun 04 12:47:16 PM PDT 24 Jun 04 12:47:21 PM PDT 24 500726211 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.447049008 Jun 04 12:46:55 PM PDT 24 Jun 04 12:46:57 PM PDT 24 64920757 ps
T1052 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.893219635 Jun 04 12:47:17 PM PDT 24 Jun 04 12:47:20 PM PDT 24 19196692 ps
T1053 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3348493380 Jun 04 12:47:05 PM PDT 24 Jun 04 12:47:08 PM PDT 24 113991450 ps
T1054 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3503974579 Jun 04 12:47:08 PM PDT 24 Jun 04 12:47:10 PM PDT 24 15960173 ps
T1055 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2292158731 Jun 04 12:47:12 PM PDT 24 Jun 04 12:47:14 PM PDT 24 19485924 ps
T271 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3344433642 Jun 04 12:47:00 PM PDT 24 Jun 04 12:47:24 PM PDT 24 1953648710 ps
T103 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.101447023 Jun 04 12:46:50 PM PDT 24 Jun 04 12:46:57 PM PDT 24 85694053 ps
T265 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3738554881 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:06 PM PDT 24 422365371 ps
T1056 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1229783718 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:17 PM PDT 24 112318661 ps
T1057 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3671092096 Jun 04 12:47:04 PM PDT 24 Jun 04 12:47:09 PM PDT 24 52161893 ps
T1058 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4223589357 Jun 04 12:46:47 PM PDT 24 Jun 04 12:46:50 PM PDT 24 125431468 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.100967147 Jun 04 12:47:06 PM PDT 24 Jun 04 12:47:40 PM PDT 24 650168250 ps
T1060 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3597175408 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:17 PM PDT 24 16506312 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.192352954 Jun 04 12:46:56 PM PDT 24 Jun 04 12:47:09 PM PDT 24 6576061120 ps
T1062 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2901239898 Jun 04 12:47:05 PM PDT 24 Jun 04 12:47:11 PM PDT 24 844746624 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2005563504 Jun 04 12:47:01 PM PDT 24 Jun 04 12:47:22 PM PDT 24 1668289175 ps
T1064 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2673421782 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:19 PM PDT 24 435703775 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.39996730 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:08 PM PDT 24 205810445 ps
T1066 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3695717624 Jun 04 12:47:03 PM PDT 24 Jun 04 12:47:08 PM PDT 24 118525836 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3180742761 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:05 PM PDT 24 91018176 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2035334786 Jun 04 12:46:50 PM PDT 24 Jun 04 12:46:52 PM PDT 24 31421432 ps
T1069 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2337910157 Jun 04 12:47:06 PM PDT 24 Jun 04 12:47:14 PM PDT 24 55427963 ps
T1070 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2162833238 Jun 04 12:47:18 PM PDT 24 Jun 04 12:47:21 PM PDT 24 249391390 ps
T1071 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4051822711 Jun 04 12:47:01 PM PDT 24 Jun 04 12:47:05 PM PDT 24 77874407 ps
T1072 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.441650261 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:18 PM PDT 24 82209634 ps
T1073 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1729515064 Jun 04 12:47:01 PM PDT 24 Jun 04 12:47:04 PM PDT 24 175355955 ps
T1074 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1252916773 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:18 PM PDT 24 52391427 ps
T1075 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3814426298 Jun 04 12:47:03 PM PDT 24 Jun 04 12:47:09 PM PDT 24 419736939 ps
T1076 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3849039897 Jun 04 12:47:04 PM PDT 24 Jun 04 12:47:07 PM PDT 24 627019847 ps
T1077 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1647866826 Jun 04 12:47:17 PM PDT 24 Jun 04 12:47:20 PM PDT 24 40949739 ps
T1078 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3038254367 Jun 04 12:47:10 PM PDT 24 Jun 04 12:47:13 PM PDT 24 204199373 ps
T272 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.692188832 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:27 PM PDT 24 2919873347 ps
T1079 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1055418271 Jun 04 12:47:07 PM PDT 24 Jun 04 12:47:11 PM PDT 24 183686766 ps
T1080 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3494380649 Jun 04 12:47:12 PM PDT 24 Jun 04 12:47:14 PM PDT 24 42172466 ps
T266 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3660933912 Jun 04 12:47:05 PM PDT 24 Jun 04 12:47:14 PM PDT 24 577281292 ps
T1081 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2030681893 Jun 04 12:47:11 PM PDT 24 Jun 04 12:47:14 PM PDT 24 15124124 ps
T1082 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.841523150 Jun 04 12:47:10 PM PDT 24 Jun 04 12:47:12 PM PDT 24 12027526 ps
T1083 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2099871004 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:10 PM PDT 24 107257991 ps
T1084 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3432980281 Jun 04 12:47:13 PM PDT 24 Jun 04 12:47:18 PM PDT 24 132387113 ps
T1085 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.873553316 Jun 04 12:47:04 PM PDT 24 Jun 04 12:47:06 PM PDT 24 58520199 ps
T1086 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1384739998 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:17 PM PDT 24 4288977725 ps
T1087 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3230826151 Jun 04 12:47:12 PM PDT 24 Jun 04 12:47:14 PM PDT 24 17916898 ps
T1088 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1269427836 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:21 PM PDT 24 397895936 ps
T1089 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3118802424 Jun 04 12:46:51 PM PDT 24 Jun 04 12:46:54 PM PDT 24 233299471 ps
T1090 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.435784676 Jun 04 12:47:04 PM PDT 24 Jun 04 12:47:13 PM PDT 24 283086090 ps
T273 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3285633513 Jun 04 12:47:05 PM PDT 24 Jun 04 12:47:21 PM PDT 24 551159241 ps
T1091 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2280328646 Jun 04 12:47:14 PM PDT 24 Jun 04 12:47:17 PM PDT 24 13857153 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2739231898 Jun 04 12:47:00 PM PDT 24 Jun 04 12:47:07 PM PDT 24 102983499 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2512320474 Jun 04 12:46:53 PM PDT 24 Jun 04 12:46:55 PM PDT 24 14172810 ps
T1094 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1193281070 Jun 04 12:47:16 PM PDT 24 Jun 04 12:47:19 PM PDT 24 36645056 ps
T1095 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.815461442 Jun 04 12:47:08 PM PDT 24 Jun 04 12:47:10 PM PDT 24 22970821 ps
T1096 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4141843649 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:06 PM PDT 24 44358913 ps
T1097 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1322601820 Jun 04 12:47:01 PM PDT 24 Jun 04 12:47:05 PM PDT 24 211443199 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.952297364 Jun 04 12:47:08 PM PDT 24 Jun 04 12:47:16 PM PDT 24 107970719 ps
T1099 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2515499145 Jun 04 12:47:02 PM PDT 24 Jun 04 12:47:05 PM PDT 24 105421847 ps
T1100 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2901051571 Jun 04 12:46:50 PM PDT 24 Jun 04 12:46:54 PM PDT 24 60442345 ps
T1101 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.739365046 Jun 04 12:47:15 PM PDT 24 Jun 04 12:47:18 PM PDT 24 63334797 ps

Test location /workspace/coverage/default/22.spi_device_upload.1283508730
Short name T1
Test name
Test status
Simulation time 273054952 ps
CPU time 3.04 seconds
Started Jun 04 02:20:47 PM PDT 24
Finished Jun 04 02:20:51 PM PDT 24
Peak memory 218924 kb
Host smart-7ecf6917-a9d0-4bea-bad3-b0b853b0f3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283508730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1283508730
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4023569420
Short name T12
Test name
Test status
Simulation time 86455032129 ps
CPU time 682.51 seconds
Started Jun 04 02:20:12 PM PDT 24
Finished Jun 04 02:31:36 PM PDT 24
Peak memory 273468 kb
Host smart-df958a39-6acb-4540-af0e-29be1876ce66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023569420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4023569420
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1280857310
Short name T11
Test name
Test status
Simulation time 111167180149 ps
CPU time 1021.56 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:37:02 PM PDT 24
Peak memory 281672 kb
Host smart-564d633f-76ee-4fa0-a77f-688561389c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280857310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1280857310
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3190813522
Short name T80
Test name
Test status
Simulation time 21772420103 ps
CPU time 405.12 seconds
Started Jun 04 02:19:31 PM PDT 24
Finished Jun 04 02:26:17 PM PDT 24
Peak memory 288612 kb
Host smart-349630c9-cf56-4fac-afb8-52e026e8c96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190813522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3190813522
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4247833319
Short name T97
Test name
Test status
Simulation time 3933640441 ps
CPU time 20.29 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:24 PM PDT 24
Peak memory 216080 kb
Host smart-04e5fea4-a9d6-428a-ab15-6ca4bd0135aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247833319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4247833319
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1116678094
Short name T39
Test name
Test status
Simulation time 94112059728 ps
CPU time 430.57 seconds
Started Jun 04 02:20:58 PM PDT 24
Finished Jun 04 02:28:09 PM PDT 24
Peak memory 264720 kb
Host smart-9c0e3278-618e-4e81-b527-cbc2f93dfaa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116678094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1116678094
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4294499552
Short name T64
Test name
Test status
Simulation time 18286309 ps
CPU time 0.75 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 215688 kb
Host smart-0da299ea-f994-4390-a60a-c72cffe57791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294499552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4294499552
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1436194306
Short name T100
Test name
Test status
Simulation time 324488694 ps
CPU time 4.62 seconds
Started Jun 04 12:47:09 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 217740 kb
Host smart-3a9e5094-9530-4e02-b456-af8f129904d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436194306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1436194306
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.819431196
Short name T40
Test name
Test status
Simulation time 15548882300 ps
CPU time 114.02 seconds
Started Jun 04 02:22:12 PM PDT 24
Finished Jun 04 02:24:07 PM PDT 24
Peak memory 268996 kb
Host smart-3b32ed00-b3d1-4d05-b139-6199ce8b357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819431196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.819431196
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2872330635
Short name T133
Test name
Test status
Simulation time 130482855579 ps
CPU time 235.96 seconds
Started Jun 04 02:22:34 PM PDT 24
Finished Jun 04 02:26:31 PM PDT 24
Peak memory 249808 kb
Host smart-be8f4c49-2b8c-4eea-9750-1e787f978466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872330635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2872330635
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1494391483
Short name T65
Test name
Test status
Simulation time 274384576 ps
CPU time 1.13 seconds
Started Jun 04 02:19:01 PM PDT 24
Finished Jun 04 02:19:03 PM PDT 24
Peak memory 234708 kb
Host smart-5bd2b9fa-3e0b-4633-8616-a3dc4a263931
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494391483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1494391483
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3016524961
Short name T144
Test name
Test status
Simulation time 9327332456 ps
CPU time 64.09 seconds
Started Jun 04 02:22:32 PM PDT 24
Finished Jun 04 02:23:37 PM PDT 24
Peak memory 233780 kb
Host smart-c476d69a-5f68-43bb-a8cf-ca78c4285bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016524961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3016524961
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.930749961
Short name T178
Test name
Test status
Simulation time 293478589709 ps
CPU time 1217.93 seconds
Started Jun 04 02:20:20 PM PDT 24
Finished Jun 04 02:40:39 PM PDT 24
Peak memory 274980 kb
Host smart-aa485d78-6400-489c-9690-cae298f2a608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930749961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.930749961
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1701927067
Short name T82
Test name
Test status
Simulation time 53202377 ps
CPU time 0.94 seconds
Started Jun 04 12:46:59 PM PDT 24
Finished Jun 04 12:47:01 PM PDT 24
Peak memory 207004 kb
Host smart-56474d4f-03f8-4c13-aea3-7bdffeeefb06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701927067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1701927067
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.663918674
Short name T70
Test name
Test status
Simulation time 12613985826 ps
CPU time 205.52 seconds
Started Jun 04 02:19:00 PM PDT 24
Finished Jun 04 02:22:27 PM PDT 24
Peak memory 248876 kb
Host smart-572a7423-b0da-49cb-a83a-abbcebf5b245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663918674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.663918674
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3687775659
Short name T225
Test name
Test status
Simulation time 27464825504 ps
CPU time 272.5 seconds
Started Jun 04 02:19:22 PM PDT 24
Finished Jun 04 02:23:56 PM PDT 24
Peak memory 262184 kb
Host smart-5e4ccf95-9f3c-4405-aa84-0aaf7f61e8ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687775659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3687775659
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.816273061
Short name T445
Test name
Test status
Simulation time 151471519 ps
CPU time 1.03 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 217456 kb
Host smart-dbe8bba1-7df4-49bb-bc5e-5bd0e0f4d090
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816273061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.816273061
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1685303611
Short name T242
Test name
Test status
Simulation time 51293963537 ps
CPU time 268.3 seconds
Started Jun 04 02:19:51 PM PDT 24
Finished Jun 04 02:24:21 PM PDT 24
Peak memory 249852 kb
Host smart-2b93e031-2633-4d10-9ccc-8162e8f30dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685303611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1685303611
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.4026617072
Short name T199
Test name
Test status
Simulation time 101778175188 ps
CPU time 330.48 seconds
Started Jun 04 02:20:28 PM PDT 24
Finished Jun 04 02:25:59 PM PDT 24
Peak memory 249856 kb
Host smart-36532288-4521-4e5b-861e-8a4449fba6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026617072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4026617072
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3103828758
Short name T165
Test name
Test status
Simulation time 50127170717 ps
CPU time 69.61 seconds
Started Jun 04 02:22:10 PM PDT 24
Finished Jun 04 02:23:21 PM PDT 24
Peak memory 265580 kb
Host smart-e68509ec-1fcf-46fc-a8cc-6b8ef5b167c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103828758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3103828758
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2104011052
Short name T51
Test name
Test status
Simulation time 112289537793 ps
CPU time 215.02 seconds
Started Jun 04 02:22:05 PM PDT 24
Finished Jun 04 02:25:40 PM PDT 24
Peak memory 257100 kb
Host smart-bb58462e-ab91-4c69-abda-5942ec71489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104011052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2104011052
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2564094955
Short name T412
Test name
Test status
Simulation time 37979276 ps
CPU time 0.69 seconds
Started Jun 04 02:20:27 PM PDT 24
Finished Jun 04 02:20:29 PM PDT 24
Peak memory 204296 kb
Host smart-cba65148-ad50-4ed7-a7db-8eb83545d18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564094955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2564094955
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1021005282
Short name T23
Test name
Test status
Simulation time 6949176664 ps
CPU time 100.58 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:23:28 PM PDT 24
Peak memory 252344 kb
Host smart-d0af47fa-a648-4d59-ab14-94cfeecffaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021005282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1021005282
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.871736240
Short name T79
Test name
Test status
Simulation time 6453664213 ps
CPU time 28.11 seconds
Started Jun 04 02:20:48 PM PDT 24
Finished Jun 04 02:21:17 PM PDT 24
Peak memory 224304 kb
Host smart-01410ab3-75b5-489c-85da-98dbfa7f9e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871736240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.871736240
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2901239898
Short name T1062
Test name
Test status
Simulation time 844746624 ps
CPU time 5.38 seconds
Started Jun 04 12:47:05 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 215676 kb
Host smart-0ba01d12-9fa1-41bc-86bd-b2b43cb69228
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901239898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
901239898
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1412860944
Short name T233
Test name
Test status
Simulation time 22661793895 ps
CPU time 120.93 seconds
Started Jun 04 02:19:51 PM PDT 24
Finished Jun 04 02:21:53 PM PDT 24
Peak memory 255404 kb
Host smart-938e0fb8-0ba1-486c-b5bc-405bd8299a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412860944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1412860944
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2153541101
Short name T158
Test name
Test status
Simulation time 8745433923 ps
CPU time 125.31 seconds
Started Jun 04 02:22:32 PM PDT 24
Finished Jun 04 02:24:38 PM PDT 24
Peak memory 257088 kb
Host smart-7029cd85-7797-4c11-b2ec-f05589472c9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153541101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2153541101
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.247478476
Short name T54
Test name
Test status
Simulation time 97826470012 ps
CPU time 224.85 seconds
Started Jun 04 02:22:46 PM PDT 24
Finished Jun 04 02:26:32 PM PDT 24
Peak memory 255152 kb
Host smart-cde72554-163b-4997-8f01-84fa738c87fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247478476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.247478476
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.170306791
Short name T167
Test name
Test status
Simulation time 11114638944 ps
CPU time 188.82 seconds
Started Jun 04 02:19:52 PM PDT 24
Finished Jun 04 02:23:02 PM PDT 24
Peak memory 256480 kb
Host smart-08140ae3-f269-4b4a-8c5a-5aa87182f710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170306791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.170306791
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.695775716
Short name T166
Test name
Test status
Simulation time 31483578397 ps
CPU time 256.12 seconds
Started Jun 04 02:20:34 PM PDT 24
Finished Jun 04 02:24:51 PM PDT 24
Peak memory 256832 kb
Host smart-bbbc67b6-48b4-4c3a-8550-d81854b34b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695775716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.695775716
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1776311674
Short name T198
Test name
Test status
Simulation time 26572792259 ps
CPU time 321.03 seconds
Started Jun 04 02:21:55 PM PDT 24
Finished Jun 04 02:27:16 PM PDT 24
Peak memory 268432 kb
Host smart-0dfe9cf5-ede2-4df0-8034-5fea20bee80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776311674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1776311674
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3344433642
Short name T271
Test name
Test status
Simulation time 1953648710 ps
CPU time 22.68 seconds
Started Jun 04 12:47:00 PM PDT 24
Finished Jun 04 12:47:24 PM PDT 24
Peak memory 215988 kb
Host smart-7fb0d2f1-fd42-49c9-85f1-a173aa6b5cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344433642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3344433642
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1330176927
Short name T235
Test name
Test status
Simulation time 21372900308 ps
CPU time 170.96 seconds
Started Jun 04 02:19:45 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 257020 kb
Host smart-683c23f0-4d1d-48fb-9040-3a5542a3e6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330176927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1330176927
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1219026384
Short name T4
Test name
Test status
Simulation time 2968184279 ps
CPU time 11.11 seconds
Started Jun 04 02:20:03 PM PDT 24
Finished Jun 04 02:20:15 PM PDT 24
Peak memory 215892 kb
Host smart-4f0a3fea-f97a-46bd-833e-78b308f95326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219026384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1219026384
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3388831943
Short name T38
Test name
Test status
Simulation time 5888703016 ps
CPU time 54.07 seconds
Started Jun 04 02:18:59 PM PDT 24
Finished Jun 04 02:19:54 PM PDT 24
Peak memory 254416 kb
Host smart-5339d72d-0c60-4989-a349-48a9fb50173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388831943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3388831943
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1279047804
Short name T237
Test name
Test status
Simulation time 56486946370 ps
CPU time 331.36 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:27:06 PM PDT 24
Peak memory 253604 kb
Host smart-b3e67d71-081d-4bf0-abbf-ad7907e54aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279047804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1279047804
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1943456231
Short name T310
Test name
Test status
Simulation time 5920643682 ps
CPU time 40.9 seconds
Started Jun 04 02:22:59 PM PDT 24
Finished Jun 04 02:23:42 PM PDT 24
Peak memory 232472 kb
Host smart-50b2e858-b767-4a00-b0de-0ceefa421858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943456231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1943456231
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.735240904
Short name T24
Test name
Test status
Simulation time 132097177890 ps
CPU time 429.67 seconds
Started Jun 04 02:19:39 PM PDT 24
Finished Jun 04 02:26:50 PM PDT 24
Peak memory 256624 kb
Host smart-eb1ee4b3-2358-4388-bd86-3f1843984fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735240904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.735240904
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3635712917
Short name T89
Test name
Test status
Simulation time 228705371 ps
CPU time 6.14 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:18:59 PM PDT 24
Peak memory 220028 kb
Host smart-99887b39-e725-4478-8aa8-1fc6512e89df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3635712917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3635712917
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.695154520
Short name T195
Test name
Test status
Simulation time 7071538194 ps
CPU time 6.6 seconds
Started Jun 04 02:20:03 PM PDT 24
Finished Jun 04 02:20:10 PM PDT 24
Peak memory 219332 kb
Host smart-347a40ce-8df6-4f36-a79f-65a49d5db086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695154520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.695154520
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1237695989
Short name T142
Test name
Test status
Simulation time 811080342 ps
CPU time 8.86 seconds
Started Jun 04 02:21:40 PM PDT 24
Finished Jun 04 02:21:50 PM PDT 24
Peak memory 236832 kb
Host smart-d4ed5784-1ae6-46e5-a4b9-0f909675af46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237695989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1237695989
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.778072545
Short name T268
Test name
Test status
Simulation time 1594046993 ps
CPU time 20.75 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:33 PM PDT 24
Peak memory 215384 kb
Host smart-2dcab7bc-c36b-4b3f-b66e-44c204b184e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778072545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.778072545
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3660933912
Short name T266
Test name
Test status
Simulation time 577281292 ps
CPU time 3.67 seconds
Started Jun 04 12:47:05 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 215532 kb
Host smart-dd3c4739-c5f1-4965-aa76-2b52421d81af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660933912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
660933912
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3285633513
Short name T273
Test name
Test status
Simulation time 551159241 ps
CPU time 14.96 seconds
Started Jun 04 12:47:05 PM PDT 24
Finished Jun 04 12:47:21 PM PDT 24
Peak memory 215420 kb
Host smart-00c33ee8-d7f5-40af-a8ab-33b9d7859457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285633513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3285633513
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2606496579
Short name T215
Test name
Test status
Simulation time 24942002763 ps
CPU time 20.61 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:19:07 PM PDT 24
Peak memory 229696 kb
Host smart-956bf6ee-08eb-460c-a4a4-31951e99d2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606496579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2606496579
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.540982966
Short name T25
Test name
Test status
Simulation time 61730097949 ps
CPU time 47.14 seconds
Started Jun 04 02:20:04 PM PDT 24
Finished Jun 04 02:20:52 PM PDT 24
Peak memory 224288 kb
Host smart-be561fa9-8d34-4744-a437-3935d895486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540982966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.540982966
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3675242163
Short name T313
Test name
Test status
Simulation time 613507844 ps
CPU time 11.07 seconds
Started Jun 04 02:20:41 PM PDT 24
Finished Jun 04 02:20:52 PM PDT 24
Peak memory 224168 kb
Host smart-031001b7-d7ae-4a47-a7c2-f3186e670ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675242163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3675242163
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1302187696
Short name T228
Test name
Test status
Simulation time 3636892514 ps
CPU time 8.64 seconds
Started Jun 04 02:20:43 PM PDT 24
Finished Jun 04 02:20:52 PM PDT 24
Peak memory 233412 kb
Host smart-81c49c21-f16a-4656-9bf2-e54e673038ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302187696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1302187696
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3746542581
Short name T840
Test name
Test status
Simulation time 316412132 ps
CPU time 5.94 seconds
Started Jun 04 02:20:44 PM PDT 24
Finished Jun 04 02:20:50 PM PDT 24
Peak memory 217984 kb
Host smart-f8fd0f8c-9a85-40a6-ac6f-a84ae2a89a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746542581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3746542581
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2956429127
Short name T227
Test name
Test status
Simulation time 30564598388 ps
CPU time 345.88 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:27:34 PM PDT 24
Peak memory 256592 kb
Host smart-494e2a06-bec3-41bc-8cc4-1e3d10816e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956429127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2956429127
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3100716828
Short name T252
Test name
Test status
Simulation time 11844391837 ps
CPU time 79.32 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:23:24 PM PDT 24
Peak memory 250820 kb
Host smart-0bbf7bba-f354-49e5-bd1b-4a25ba301a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100716828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3100716828
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3678279100
Short name T274
Test name
Test status
Simulation time 2650020596 ps
CPU time 14.95 seconds
Started Jun 04 02:22:03 PM PDT 24
Finished Jun 04 02:22:19 PM PDT 24
Peak memory 227748 kb
Host smart-215df7d6-0ba7-42da-b3ee-017e4f714714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678279100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3678279100
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3657610776
Short name T248
Test name
Test status
Simulation time 68461099038 ps
CPU time 562.73 seconds
Started Jun 04 02:22:23 PM PDT 24
Finished Jun 04 02:31:46 PM PDT 24
Peak memory 265664 kb
Host smart-05c5ad8f-1451-47f5-8c16-79c0554b83b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657610776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3657610776
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3094703817
Short name T84
Test name
Test status
Simulation time 33456108 ps
CPU time 1.19 seconds
Started Jun 04 12:46:59 PM PDT 24
Finished Jun 04 12:47:01 PM PDT 24
Peak memory 207236 kb
Host smart-60514bdc-ae70-48da-a4c4-49b9df28e790
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094703817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3094703817
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2606993544
Short name T1025
Test name
Test status
Simulation time 3771916953 ps
CPU time 16.66 seconds
Started Jun 04 12:46:49 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 215420 kb
Host smart-2cd0f9eb-cf58-4d0a-b7a3-32095ab77ece
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606993544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2606993544
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1384739998
Short name T1086
Test name
Test status
Simulation time 4288977725 ps
CPU time 12.93 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 207372 kb
Host smart-b3636e15-80c0-4d56-b843-9c07eb42eb2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384739998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1384739998
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1988547404
Short name T998
Test name
Test status
Simulation time 27174037 ps
CPU time 1.79 seconds
Started Jun 04 12:46:49 PM PDT 24
Finished Jun 04 12:46:52 PM PDT 24
Peak memory 215480 kb
Host smart-bf2c5f53-459b-4400-8278-4e2753fa4aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988547404 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1988547404
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.447049008
Short name T1051
Test name
Test status
Simulation time 64920757 ps
CPU time 1.22 seconds
Started Jun 04 12:46:55 PM PDT 24
Finished Jun 04 12:46:57 PM PDT 24
Peak memory 207200 kb
Host smart-c22939c9-7836-4c7a-8a12-45f0d3c72d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447049008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.447049008
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1553994976
Short name T990
Test name
Test status
Simulation time 31327839 ps
CPU time 0.74 seconds
Started Jun 04 12:46:50 PM PDT 24
Finished Jun 04 12:46:52 PM PDT 24
Peak memory 203688 kb
Host smart-06d1a32c-7f8a-49c3-807e-bb68a1669d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553994976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
553994976
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4223589357
Short name T1058
Test name
Test status
Simulation time 125431468 ps
CPU time 1.65 seconds
Started Jun 04 12:46:47 PM PDT 24
Finished Jun 04 12:46:50 PM PDT 24
Peak memory 215628 kb
Host smart-ccbf7b16-7c55-4e53-9045-5d2a0741402a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223589357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4223589357
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1378057828
Short name T987
Test name
Test status
Simulation time 47253917 ps
CPU time 0.7 seconds
Started Jun 04 12:46:44 PM PDT 24
Finished Jun 04 12:46:45 PM PDT 24
Peak memory 203652 kb
Host smart-4e333e38-c0dc-455b-bb9d-af9a48402169
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378057828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1378057828
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2901051571
Short name T1100
Test name
Test status
Simulation time 60442345 ps
CPU time 1.83 seconds
Started Jun 04 12:46:50 PM PDT 24
Finished Jun 04 12:46:54 PM PDT 24
Peak memory 215456 kb
Host smart-8887aa09-8323-4bd7-b15f-8f8dfbefa43c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901051571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2901051571
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2378849147
Short name T120
Test name
Test status
Simulation time 3466876780 ps
CPU time 22.27 seconds
Started Jun 04 12:46:51 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 215416 kb
Host smart-d54f0bc6-24f3-4aac-9662-355d5cdf99ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378849147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2378849147
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2158655070
Short name T1047
Test name
Test status
Simulation time 7541522767 ps
CPU time 35.92 seconds
Started Jun 04 12:46:54 PM PDT 24
Finished Jun 04 12:47:31 PM PDT 24
Peak memory 206776 kb
Host smart-e3b11390-bddc-4bb6-b82d-3add02c1ca83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158655070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2158655070
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3777204531
Short name T81
Test name
Test status
Simulation time 73026860 ps
CPU time 1.42 seconds
Started Jun 04 12:47:05 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 207196 kb
Host smart-7c0684bb-3f2e-465d-a9e6-b007ac98f422
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777204531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3777204531
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4033793219
Short name T156
Test name
Test status
Simulation time 101940158 ps
CPU time 2.75 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 217964 kb
Host smart-66bd1e73-4a28-4f9b-a5cb-7945583a13dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033793219 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4033793219
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2582947686
Short name T139
Test name
Test status
Simulation time 42006045 ps
CPU time 1.45 seconds
Started Jun 04 12:46:56 PM PDT 24
Finished Jun 04 12:46:59 PM PDT 24
Peak memory 215376 kb
Host smart-a18e51a2-36f7-4607-8ebd-33d178b93ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582947686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
582947686
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2951999832
Short name T1037
Test name
Test status
Simulation time 69186214 ps
CPU time 0.74 seconds
Started Jun 04 12:46:59 PM PDT 24
Finished Jun 04 12:47:01 PM PDT 24
Peak memory 203648 kb
Host smart-007546f8-04f4-4ec7-abee-5d684911be99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951999832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
951999832
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3180742761
Short name T1067
Test name
Test status
Simulation time 91018176 ps
CPU time 1.96 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:05 PM PDT 24
Peak memory 215492 kb
Host smart-29f82b3a-7b7a-40b2-9363-2fea05ffb941
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180742761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3180742761
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.195972799
Short name T1006
Test name
Test status
Simulation time 33442895 ps
CPU time 0.68 seconds
Started Jun 04 12:46:53 PM PDT 24
Finished Jun 04 12:46:55 PM PDT 24
Peak memory 203688 kb
Host smart-b3eca9a6-56c5-456e-b0aa-7437a54e5900
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195972799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.195972799
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3489329465
Short name T1027
Test name
Test status
Simulation time 30175431 ps
CPU time 1.76 seconds
Started Jun 04 12:46:53 PM PDT 24
Finished Jun 04 12:46:56 PM PDT 24
Peak memory 215532 kb
Host smart-5ed695e6-dcb9-4d2f-aa61-0f693305eaf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489329465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3489329465
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.101447023
Short name T103
Test name
Test status
Simulation time 85694053 ps
CPU time 5.52 seconds
Started Jun 04 12:46:50 PM PDT 24
Finished Jun 04 12:46:57 PM PDT 24
Peak memory 215652 kb
Host smart-01799831-d5d4-4051-922d-8587bf68770b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101447023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.101447023
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2739231898
Short name T1092
Test name
Test status
Simulation time 102983499 ps
CPU time 6.55 seconds
Started Jun 04 12:47:00 PM PDT 24
Finished Jun 04 12:47:07 PM PDT 24
Peak memory 215428 kb
Host smart-6659bea9-9121-4c93-a711-30f2df91f964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739231898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2739231898
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2441218641
Short name T1042
Test name
Test status
Simulation time 40393903 ps
CPU time 2.6 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 216560 kb
Host smart-2df1a170-f0d0-47ac-8fc5-83970bf35d42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441218641 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2441218641
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1205559635
Short name T119
Test name
Test status
Simulation time 37875937 ps
CPU time 2.42 seconds
Started Jun 04 12:47:07 PM PDT 24
Finished Jun 04 12:47:10 PM PDT 24
Peak memory 215420 kb
Host smart-c9c984c3-03b3-47cd-904c-d35876b27eed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205559635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1205559635
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2030681893
Short name T1081
Test name
Test status
Simulation time 15124124 ps
CPU time 0.77 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 203676 kb
Host smart-f5f8587a-e468-41cf-bfa2-0acad33a8bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030681893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2030681893
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4141843649
Short name T1096
Test name
Test status
Simulation time 44358913 ps
CPU time 2.8 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 215416 kb
Host smart-3b674e44-ded2-4323-8985-345e1605b9fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141843649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4141843649
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4051822711
Short name T1071
Test name
Test status
Simulation time 77874407 ps
CPU time 2.09 seconds
Started Jun 04 12:47:01 PM PDT 24
Finished Jun 04 12:47:05 PM PDT 24
Peak memory 215584 kb
Host smart-30bae1df-0c51-4c9b-83ea-ec7ba845f2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051822711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4051822711
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.141793832
Short name T270
Test name
Test status
Simulation time 1297911275 ps
CPU time 14.08 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 216844 kb
Host smart-b9a117e2-1702-48e1-985b-255d775c9bae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141793832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.141793832
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2097134766
Short name T1049
Test name
Test status
Simulation time 128898652 ps
CPU time 3.74 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 217144 kb
Host smart-cb908a30-3cdf-4d4b-9eb4-18ae0ae405bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097134766 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2097134766
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4117121549
Short name T1024
Test name
Test status
Simulation time 91975937 ps
CPU time 2.58 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 215388 kb
Host smart-72dc8bb1-1345-48cc-bf8d-30272eb65dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117121549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4117121549
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.856055839
Short name T988
Test name
Test status
Simulation time 16699112 ps
CPU time 0.74 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 203672 kb
Host smart-10759dad-344a-40a5-92cc-2f705ce9dd09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856055839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.856055839
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.39996730
Short name T1065
Test name
Test status
Simulation time 205810445 ps
CPU time 4.31 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 215188 kb
Host smart-ac060716-efbc-4c48-898e-9400a2cdb895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39996730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sp
i_device_same_csr_outstanding.39996730
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3814426298
Short name T1075
Test name
Test status
Simulation time 419736939 ps
CPU time 4.81 seconds
Started Jun 04 12:47:03 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 216696 kb
Host smart-acfbb4a5-faa8-4dfd-8beb-1c8978e37382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814426298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3814426298
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2234426054
Short name T155
Test name
Test status
Simulation time 1388599497 ps
CPU time 7.73 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 215960 kb
Host smart-385a86ff-5f0f-45bd-b023-0c405ed602ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234426054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2234426054
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3348493380
Short name T1053
Test name
Test status
Simulation time 113991450 ps
CPU time 1.86 seconds
Started Jun 04 12:47:05 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 216532 kb
Host smart-774f1a96-ed77-42e4-bf3d-61f3c21bdb34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348493380 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3348493380
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2515499145
Short name T1099
Test name
Test status
Simulation time 105421847 ps
CPU time 1.46 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:05 PM PDT 24
Peak memory 207388 kb
Host smart-df4a7495-2499-4073-8d17-7ec180104d68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515499145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2515499145
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3933273609
Short name T986
Test name
Test status
Simulation time 13751154 ps
CPU time 0.71 seconds
Started Jun 04 12:47:07 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 203652 kb
Host smart-3382bfb8-af0d-43ce-9e6b-4b3073d08707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933273609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3933273609
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4158064978
Short name T1002
Test name
Test status
Simulation time 107672047 ps
CPU time 3.08 seconds
Started Jun 04 12:47:09 PM PDT 24
Finished Jun 04 12:47:13 PM PDT 24
Peak memory 215212 kb
Host smart-8f7cb17c-b626-4814-965c-900dbcdf248f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158064978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4158064978
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3769796146
Short name T93
Test name
Test status
Simulation time 25550865 ps
CPU time 1.65 seconds
Started Jun 04 12:47:00 PM PDT 24
Finished Jun 04 12:47:03 PM PDT 24
Peak memory 216728 kb
Host smart-dc17f668-d01b-4434-9546-bb6eb2dc0798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769796146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3769796146
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1081984436
Short name T91
Test name
Test status
Simulation time 3091909140 ps
CPU time 7.68 seconds
Started Jun 04 12:47:06 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 215484 kb
Host smart-08afe7d4-5424-4ee2-8e14-db3f2fe654c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081984436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1081984436
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2278186982
Short name T1033
Test name
Test status
Simulation time 214531358 ps
CPU time 2.7 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 216908 kb
Host smart-50adb779-bd67-4678-9c32-8bdc161477c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278186982 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2278186982
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.534429986
Short name T1043
Test name
Test status
Simulation time 234732525 ps
CPU time 2.61 seconds
Started Jun 04 12:47:01 PM PDT 24
Finished Jun 04 12:47:05 PM PDT 24
Peak memory 215420 kb
Host smart-c12aeecc-4189-4837-baf7-930d2b64f88b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534429986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.534429986
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2390442604
Short name T1028
Test name
Test status
Simulation time 12392880 ps
CPU time 0.69 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 203672 kb
Host smart-ad39366b-08e3-4b84-bea4-df1d85bff4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390442604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2390442604
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1729515064
Short name T1073
Test name
Test status
Simulation time 175355955 ps
CPU time 1.8 seconds
Started Jun 04 12:47:01 PM PDT 24
Finished Jun 04 12:47:04 PM PDT 24
Peak memory 215412 kb
Host smart-7df045b2-4243-44f2-a801-af17448b0ff1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729515064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1729515064
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3849039897
Short name T1076
Test name
Test status
Simulation time 627019847 ps
CPU time 2.14 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:07 PM PDT 24
Peak memory 216624 kb
Host smart-8e6fd537-298f-4fdb-98ba-7871b573a7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849039897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3849039897
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3038254367
Short name T1078
Test name
Test status
Simulation time 204199373 ps
CPU time 2.64 seconds
Started Jun 04 12:47:10 PM PDT 24
Finished Jun 04 12:47:13 PM PDT 24
Peak memory 216672 kb
Host smart-485cff50-b151-4ed1-8091-5dc612b04cdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038254367 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3038254367
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.308502117
Short name T116
Test name
Test status
Simulation time 183693933 ps
CPU time 2.98 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 215432 kb
Host smart-3c9b5132-f504-4533-8981-397e2537b72a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308502117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.308502117
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.220184003
Short name T1018
Test name
Test status
Simulation time 47370771 ps
CPU time 0.69 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:13 PM PDT 24
Peak memory 203644 kb
Host smart-0fd356e5-a4dd-495b-a3ba-2f576079f3ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220184003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.220184003
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3065430757
Short name T1014
Test name
Test status
Simulation time 250208622 ps
CPU time 1.94 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 215388 kb
Host smart-5e608a50-2edb-404c-8125-4b607f6532e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065430757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3065430757
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.273108269
Short name T102
Test name
Test status
Simulation time 600175957 ps
CPU time 3.3 seconds
Started Jun 04 12:47:03 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 215636 kb
Host smart-850a8ec9-8d4f-4c81-ab58-f8b026826517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273108269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.273108269
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2099871004
Short name T1083
Test name
Test status
Simulation time 107257991 ps
CPU time 6.7 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:10 PM PDT 24
Peak memory 215172 kb
Host smart-7b988f19-cce9-4af7-8c27-6f43b6fb12c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099871004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2099871004
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3822154530
Short name T1030
Test name
Test status
Simulation time 41704285 ps
CPU time 2.62 seconds
Started Jun 04 12:47:05 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 216600 kb
Host smart-4d3735b6-de2c-4224-95b0-e0ceb33c519f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822154530 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3822154530
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1625140779
Short name T122
Test name
Test status
Simulation time 285883436 ps
CPU time 2.01 seconds
Started Jun 04 12:47:08 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 215432 kb
Host smart-9f13af2c-64eb-4973-9899-1dc14f6d03c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625140779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1625140779
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3254893014
Short name T1022
Test name
Test status
Simulation time 22553124 ps
CPU time 0.74 seconds
Started Jun 04 12:47:07 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 203700 kb
Host smart-c0fb0fce-e5a2-4ea6-82db-082c3964e198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254893014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3254893014
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.78453809
Short name T1046
Test name
Test status
Simulation time 110786434 ps
CPU time 2.73 seconds
Started Jun 04 12:47:05 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 215420 kb
Host smart-c61a7391-3572-4298-a1a1-e2c96cbea362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78453809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sp
i_device_same_csr_outstanding.78453809
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3464609220
Short name T106
Test name
Test status
Simulation time 55711216 ps
CPU time 1.55 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:05 PM PDT 24
Peak memory 216684 kb
Host smart-e2d3d8a6-6acc-4690-be9f-9cab049183d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464609220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3464609220
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.952297364
Short name T1098
Test name
Test status
Simulation time 107970719 ps
CPU time 6.89 seconds
Started Jun 04 12:47:08 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 215432 kb
Host smart-d8f3588b-553c-4d9b-af1f-b2b0e0989e24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952297364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.952297364
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1055418271
Short name T1079
Test name
Test status
Simulation time 183686766 ps
CPU time 2.82 seconds
Started Jun 04 12:47:07 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 217156 kb
Host smart-d8e623b6-6c88-47f7-9fc9-7162f0394655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055418271 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1055418271
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2719416535
Short name T154
Test name
Test status
Simulation time 154445701 ps
CPU time 1.9 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 207172 kb
Host smart-49269367-7f07-425e-b0d2-5c36e93018cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719416535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2719416535
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3503974579
Short name T1054
Test name
Test status
Simulation time 15960173 ps
CPU time 0.7 seconds
Started Jun 04 12:47:08 PM PDT 24
Finished Jun 04 12:47:10 PM PDT 24
Peak memory 203788 kb
Host smart-47f75a46-88eb-4f16-a4af-7c557addc865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503974579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3503974579
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1381761419
Short name T153
Test name
Test status
Simulation time 773689770 ps
CPU time 3.85 seconds
Started Jun 04 12:47:05 PM PDT 24
Finished Jun 04 12:47:10 PM PDT 24
Peak memory 215408 kb
Host smart-e3da1037-87b1-4cc6-87c3-0d07e7e52fad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381761419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1381761419
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1229783718
Short name T1056
Test name
Test status
Simulation time 112318661 ps
CPU time 2.73 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 216552 kb
Host smart-48122fbb-849b-4f44-82f9-4e67f43c4be6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229783718 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1229783718
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2475038251
Short name T1011
Test name
Test status
Simulation time 55351469 ps
CPU time 1.31 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 215412 kb
Host smart-2fe469aa-9dbe-4b41-acf8-6ef9b841ffc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475038251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2475038251
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3743660380
Short name T983
Test name
Test status
Simulation time 15923149 ps
CPU time 0.75 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 203916 kb
Host smart-ce15880f-9ec1-4bbb-b66c-095326cb3594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743660380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3743660380
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1269427836
Short name T1088
Test name
Test status
Simulation time 397895936 ps
CPU time 4.45 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:21 PM PDT 24
Peak memory 215364 kb
Host smart-5d1af732-50dd-4dda-ab6f-f46c2bcb5b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269427836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1269427836
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1042217857
Short name T1050
Test name
Test status
Simulation time 500726211 ps
CPU time 3.03 seconds
Started Jun 04 12:47:16 PM PDT 24
Finished Jun 04 12:47:21 PM PDT 24
Peak memory 215512 kb
Host smart-de8a1019-ffcc-4f2d-a82b-a2e0067e04f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042217857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1042217857
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.687417182
Short name T269
Test name
Test status
Simulation time 110695436 ps
CPU time 6.97 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:22 PM PDT 24
Peak memory 215384 kb
Host smart-805ec48d-8cf8-483f-8ae2-77dd51aff5c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687417182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.687417182
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.441650261
Short name T1072
Test name
Test status
Simulation time 82209634 ps
CPU time 2.54 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 216588 kb
Host smart-04d781ab-a9c9-4764-b011-c721c0772f42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441650261 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.441650261
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.21189732
Short name T1045
Test name
Test status
Simulation time 339394651 ps
CPU time 1.84 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 207160 kb
Host smart-6033946d-8fc1-4026-9742-eea047db183f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21189732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.21189732
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1016372787
Short name T994
Test name
Test status
Simulation time 42536938 ps
CPU time 0.71 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 203772 kb
Host smart-e2b154fd-3a69-45ce-af8e-7259093c6747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016372787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1016372787
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.289112453
Short name T981
Test name
Test status
Simulation time 343055082 ps
CPU time 2.79 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 215472 kb
Host smart-20a0c513-64eb-4f10-ac56-10a27b650965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289112453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.289112453
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2673421782
Short name T1064
Test name
Test status
Simulation time 435703775 ps
CPU time 4.56 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 215740 kb
Host smart-cb8f1bc8-52ef-451d-80bb-1472c6c317cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673421782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2673421782
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.692188832
Short name T272
Test name
Test status
Simulation time 2919873347 ps
CPU time 15.86 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:27 PM PDT 24
Peak memory 215516 kb
Host smart-5a2da87b-9c1a-44aa-ab5e-33716b1cd838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692188832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.692188832
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2162833238
Short name T1070
Test name
Test status
Simulation time 249391390 ps
CPU time 1.96 seconds
Started Jun 04 12:47:18 PM PDT 24
Finished Jun 04 12:47:21 PM PDT 24
Peak memory 216548 kb
Host smart-9bef9b35-0b03-4e3e-9987-3b60fed9d297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162833238 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2162833238
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.813026572
Short name T1040
Test name
Test status
Simulation time 339203269 ps
CPU time 2.95 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 215404 kb
Host smart-1fc8ded8-e19c-4e84-92be-533a70beac70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813026572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.813026572
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1502631116
Short name T1031
Test name
Test status
Simulation time 14793787 ps
CPU time 0.72 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 203648 kb
Host smart-ae9129a3-d690-4efa-b82e-15ce2005cd11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502631116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1502631116
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1771993177
Short name T1001
Test name
Test status
Simulation time 621830375 ps
CPU time 3.97 seconds
Started Jun 04 12:47:16 PM PDT 24
Finished Jun 04 12:47:23 PM PDT 24
Peak memory 215360 kb
Host smart-0b6aa41b-1f62-4734-9d42-648504119112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771993177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1771993177
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3432980281
Short name T1084
Test name
Test status
Simulation time 132387113 ps
CPU time 3.69 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 215540 kb
Host smart-4d388e3c-fdb8-46ea-af4e-0135c71acc86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432980281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3432980281
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1802193276
Short name T267
Test name
Test status
Simulation time 1069100969 ps
CPU time 7.67 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:21 PM PDT 24
Peak memory 215840 kb
Host smart-51c7f32e-8f9d-46d9-9d61-c87cc7b5e25c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802193276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1802193276
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2791616839
Short name T113
Test name
Test status
Simulation time 731119811 ps
CPU time 15.78 seconds
Started Jun 04 12:46:50 PM PDT 24
Finished Jun 04 12:47:07 PM PDT 24
Peak memory 207144 kb
Host smart-282b28e8-7f44-4f30-866c-166f8f33d359
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791616839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2791616839
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.100967147
Short name T1059
Test name
Test status
Simulation time 650168250 ps
CPU time 33.25 seconds
Started Jun 04 12:47:06 PM PDT 24
Finished Jun 04 12:47:40 PM PDT 24
Peak memory 207272 kb
Host smart-9d4cd986-e444-4e66-a40c-c09ff22313ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100967147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.100967147
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1560432603
Short name T83
Test name
Test status
Simulation time 144899420 ps
CPU time 1.44 seconds
Started Jun 04 12:46:54 PM PDT 24
Finished Jun 04 12:46:57 PM PDT 24
Peak memory 207296 kb
Host smart-e4dea226-f4b1-4939-9a43-fb473569bc44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560432603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1560432603
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2985295773
Short name T1003
Test name
Test status
Simulation time 53807552 ps
CPU time 1.87 seconds
Started Jun 04 12:46:59 PM PDT 24
Finished Jun 04 12:47:02 PM PDT 24
Peak memory 215504 kb
Host smart-9f224924-e21f-49f8-b866-8b23cdffee75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985295773 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2985295773
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3088029322
Short name T118
Test name
Test status
Simulation time 31806002 ps
CPU time 1.21 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 215432 kb
Host smart-b33fcfaa-c2de-4062-bb2d-4ebfb352bd5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088029322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
088029322
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3609407241
Short name T999
Test name
Test status
Simulation time 22818633 ps
CPU time 0.72 seconds
Started Jun 04 12:46:52 PM PDT 24
Finished Jun 04 12:46:54 PM PDT 24
Peak memory 203704 kb
Host smart-f87e8988-ecb4-4299-b6c9-160ae3862e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609407241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
609407241
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2863674492
Short name T123
Test name
Test status
Simulation time 17353651 ps
CPU time 1.26 seconds
Started Jun 04 12:46:53 PM PDT 24
Finished Jun 04 12:46:55 PM PDT 24
Peak memory 215444 kb
Host smart-9443421d-1c7e-4eac-84e8-5fc733e00e52
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863674492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2863674492
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.570578790
Short name T1007
Test name
Test status
Simulation time 19846282 ps
CPU time 0.65 seconds
Started Jun 04 12:46:53 PM PDT 24
Finished Jun 04 12:46:55 PM PDT 24
Peak memory 203548 kb
Host smart-59dd1035-9d6c-4c2a-a3f2-37fb60545660
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570578790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.570578790
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.890646971
Short name T989
Test name
Test status
Simulation time 375755066 ps
CPU time 2.59 seconds
Started Jun 04 12:46:49 PM PDT 24
Finished Jun 04 12:46:52 PM PDT 24
Peak memory 215504 kb
Host smart-65bee5ec-f6c2-46d4-82b7-a51f6faaf404
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890646971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.890646971
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3118802424
Short name T1089
Test name
Test status
Simulation time 233299471 ps
CPU time 1.93 seconds
Started Jun 04 12:46:51 PM PDT 24
Finished Jun 04 12:46:54 PM PDT 24
Peak memory 215536 kb
Host smart-f5a55c8d-a0c3-4ffd-8058-4c80ff78c5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118802424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
118802424
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.909550809
Short name T1016
Test name
Test status
Simulation time 367271826 ps
CPU time 6.97 seconds
Started Jun 04 12:47:03 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 215340 kb
Host smart-b212e246-7812-4d6b-83af-52c520a6eb4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909550809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.909550809
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1360618616
Short name T1015
Test name
Test status
Simulation time 40380859 ps
CPU time 0.75 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 203952 kb
Host smart-3a16b1dd-e454-4f8f-9fd5-22e98e2a4336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360618616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1360618616
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1620885997
Short name T1036
Test name
Test status
Simulation time 50362653 ps
CPU time 0.75 seconds
Started Jun 04 12:47:10 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 203764 kb
Host smart-10a0f977-e4ca-4f99-96dd-85867647e498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620885997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1620885997
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2163476999
Short name T978
Test name
Test status
Simulation time 27054826 ps
CPU time 0.71 seconds
Started Jun 04 12:47:27 PM PDT 24
Finished Jun 04 12:47:30 PM PDT 24
Peak memory 203700 kb
Host smart-be00efab-5fc2-48ad-ab25-46e8b77888e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163476999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2163476999
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1193281070
Short name T1094
Test name
Test status
Simulation time 36645056 ps
CPU time 0.75 seconds
Started Jun 04 12:47:16 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 203644 kb
Host smart-84832559-7e00-473b-a168-932d76f4baa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193281070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1193281070
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.992698186
Short name T1008
Test name
Test status
Simulation time 14563449 ps
CPU time 0.75 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 204072 kb
Host smart-6b348cb6-c412-4a61-ba99-82bc9942c462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992698186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.992698186
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3494380649
Short name T1080
Test name
Test status
Simulation time 42172466 ps
CPU time 0.73 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 203664 kb
Host smart-79d9e2f3-95bd-4c13-80af-0c337f38c721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494380649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3494380649
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.93449771
Short name T1039
Test name
Test status
Simulation time 35622902 ps
CPU time 0.83 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 203876 kb
Host smart-45a3f10a-dbf9-4dac-9bae-5578d1656044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93449771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.93449771
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1263109291
Short name T1034
Test name
Test status
Simulation time 15231196 ps
CPU time 0.75 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 203928 kb
Host smart-3521968f-912a-45ca-9269-2c8f0393c510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263109291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1263109291
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4154241080
Short name T1017
Test name
Test status
Simulation time 54638772 ps
CPU time 0.67 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 203984 kb
Host smart-66dd2a83-414b-409c-9a0b-c4af5efe0b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154241080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4154241080
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3094569720
Short name T1020
Test name
Test status
Simulation time 19843072 ps
CPU time 0.76 seconds
Started Jun 04 12:47:17 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 202936 kb
Host smart-b16310e6-fece-4b88-b076-b4c267e8545b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094569720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3094569720
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.821378736
Short name T1032
Test name
Test status
Simulation time 269965152 ps
CPU time 8.08 seconds
Started Jun 04 12:46:52 PM PDT 24
Finished Jun 04 12:47:02 PM PDT 24
Peak memory 215540 kb
Host smart-c6c26ac8-a12b-4b35-b679-8ad116bb2dab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821378736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.821378736
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3105289643
Short name T1029
Test name
Test status
Simulation time 2522303135 ps
CPU time 25.74 seconds
Started Jun 04 12:46:50 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 207284 kb
Host smart-fe87bdf3-b646-4cbc-a3bd-e4491e886e1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105289643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3105289643
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3972750936
Short name T117
Test name
Test status
Simulation time 17915603 ps
CPU time 1.14 seconds
Started Jun 04 12:46:54 PM PDT 24
Finished Jun 04 12:46:56 PM PDT 24
Peak memory 206896 kb
Host smart-a3eb9ed1-ee0f-43be-89e2-6eed3a58445a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972750936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3972750936
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4069958889
Short name T1035
Test name
Test status
Simulation time 258958038 ps
CPU time 1.67 seconds
Started Jun 04 12:46:52 PM PDT 24
Finished Jun 04 12:46:55 PM PDT 24
Peak memory 215484 kb
Host smart-8777885d-0b67-4a9d-aee7-02331124cc11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069958889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4069958889
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2563227601
Short name T1010
Test name
Test status
Simulation time 409093182 ps
CPU time 1.32 seconds
Started Jun 04 12:46:54 PM PDT 24
Finished Jun 04 12:46:56 PM PDT 24
Peak memory 207240 kb
Host smart-0fd6627f-e703-4817-a642-8c4c36e809d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563227601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
563227601
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2512320474
Short name T1093
Test name
Test status
Simulation time 14172810 ps
CPU time 0.71 seconds
Started Jun 04 12:46:53 PM PDT 24
Finished Jun 04 12:46:55 PM PDT 24
Peak memory 203560 kb
Host smart-adfee68c-5f71-42ff-9d26-f993a5e46270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512320474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
512320474
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3778926885
Short name T114
Test name
Test status
Simulation time 40201182 ps
CPU time 1.71 seconds
Started Jun 04 12:46:59 PM PDT 24
Finished Jun 04 12:47:02 PM PDT 24
Peak memory 215528 kb
Host smart-208d35ab-88d9-42f3-8d3f-1e9f2f6432de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778926885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3778926885
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2035334786
Short name T1068
Test name
Test status
Simulation time 31421432 ps
CPU time 0.66 seconds
Started Jun 04 12:46:50 PM PDT 24
Finished Jun 04 12:46:52 PM PDT 24
Peak memory 203608 kb
Host smart-4ffcf939-c1b0-4452-bf06-1dd6ff974739
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035334786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2035334786
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.873553316
Short name T1085
Test name
Test status
Simulation time 58520199 ps
CPU time 1.75 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 207132 kb
Host smart-3c1519e0-7d98-4cfb-a82a-3e4fc3f643e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873553316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.873553316
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4034297803
Short name T104
Test name
Test status
Simulation time 226916389 ps
CPU time 3.87 seconds
Started Jun 04 12:47:03 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 215596 kb
Host smart-c71011d7-65ef-4fd2-99ea-42d67214eec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034297803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
034297803
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2005563504
Short name T1063
Test name
Test status
Simulation time 1668289175 ps
CPU time 18.89 seconds
Started Jun 04 12:47:01 PM PDT 24
Finished Jun 04 12:47:22 PM PDT 24
Peak memory 215452 kb
Host smart-e7d7b117-4153-4348-ace1-a81c267a3957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005563504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2005563504
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2950798698
Short name T1048
Test name
Test status
Simulation time 15463062 ps
CPU time 0.75 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 203992 kb
Host smart-54b68e0c-6c54-4410-b270-c00f0bf1ba29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950798698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2950798698
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1252916773
Short name T1074
Test name
Test status
Simulation time 52391427 ps
CPU time 0.73 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 203556 kb
Host smart-1cb76298-6021-47b8-a851-6e04c642d656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252916773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1252916773
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2292158731
Short name T1055
Test name
Test status
Simulation time 19485924 ps
CPU time 0.77 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 203708 kb
Host smart-cf06caf2-5f48-4aff-a8a5-96e875923081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292158731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2292158731
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3591027584
Short name T1038
Test name
Test status
Simulation time 36081690 ps
CPU time 0.72 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:13 PM PDT 24
Peak memory 203728 kb
Host smart-6b1708dc-78be-4801-8d56-cfefc4b02cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591027584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3591027584
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2280328646
Short name T1091
Test name
Test status
Simulation time 13857153 ps
CPU time 0.74 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 203700 kb
Host smart-899e525a-06d2-4e1c-839d-613d8e877b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280328646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2280328646
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1939038941
Short name T975
Test name
Test status
Simulation time 16830285 ps
CPU time 0.77 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 203608 kb
Host smart-c23baf76-a2d6-47eb-89a7-ba8d4fa41016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939038941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1939038941
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3809805364
Short name T985
Test name
Test status
Simulation time 15735951 ps
CPU time 0.75 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 204064 kb
Host smart-113f4f8a-bf27-4f74-8666-3d8873500e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809805364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3809805364
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3230826151
Short name T1087
Test name
Test status
Simulation time 17916898 ps
CPU time 0.78 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 203984 kb
Host smart-43ef7209-5067-484e-9a6f-deff017a1dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230826151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3230826151
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2935218128
Short name T1000
Test name
Test status
Simulation time 25627898 ps
CPU time 0.68 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 203676 kb
Host smart-8032b037-14f8-42bf-b6c2-879dcca458c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935218128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2935218128
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.893219635
Short name T1052
Test name
Test status
Simulation time 19196692 ps
CPU time 0.72 seconds
Started Jun 04 12:47:17 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 203644 kb
Host smart-9cef7b62-2be2-4853-ae3a-cae21ff86051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893219635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.893219635
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2779582152
Short name T1041
Test name
Test status
Simulation time 111081244 ps
CPU time 7.13 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:10 PM PDT 24
Peak memory 207136 kb
Host smart-317e187f-7ff5-4fe0-a196-6cc9ed0e8b8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779582152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2779582152
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.192352954
Short name T1061
Test name
Test status
Simulation time 6576061120 ps
CPU time 12.88 seconds
Started Jun 04 12:46:56 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 207356 kb
Host smart-d87f0727-e5fe-4dee-8120-4f8066be3b66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192352954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.192352954
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.85080002
Short name T1005
Test name
Test status
Simulation time 28084919 ps
CPU time 1.72 seconds
Started Jun 04 12:47:07 PM PDT 24
Finished Jun 04 12:47:12 PM PDT 24
Peak memory 215572 kb
Host smart-d38a76a9-b171-4c00-9c73-7c4a3c0441c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85080002 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.85080002
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1188678029
Short name T112
Test name
Test status
Simulation time 129552514 ps
CPU time 2.79 seconds
Started Jun 04 12:47:06 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 215468 kb
Host smart-6dbbe037-7fa2-4562-aeb3-66f966b5f58c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188678029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
188678029
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1987821708
Short name T979
Test name
Test status
Simulation time 12432222 ps
CPU time 0.75 seconds
Started Jun 04 12:46:48 PM PDT 24
Finished Jun 04 12:46:50 PM PDT 24
Peak memory 203692 kb
Host smart-bb5b3ab4-ce7c-4dee-993e-cdfebcecdcba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987821708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
987821708
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3108818736
Short name T1013
Test name
Test status
Simulation time 204502795 ps
CPU time 1.73 seconds
Started Jun 04 12:46:51 PM PDT 24
Finished Jun 04 12:46:54 PM PDT 24
Peak memory 215456 kb
Host smart-73e67cc2-c745-4f11-b36e-21fde71670d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108818736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3108818736
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.714258945
Short name T1026
Test name
Test status
Simulation time 29344708 ps
CPU time 0.67 seconds
Started Jun 04 12:47:08 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 203580 kb
Host smart-8afb6a83-2760-45ed-a187-f88e03cceab8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714258945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.714258945
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1322601820
Short name T1097
Test name
Test status
Simulation time 211443199 ps
CPU time 3.08 seconds
Started Jun 04 12:47:01 PM PDT 24
Finished Jun 04 12:47:05 PM PDT 24
Peak memory 215364 kb
Host smart-5a3ea015-dcee-4a78-a5cd-ff9b0446ba77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322601820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1322601820
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2382361088
Short name T101
Test name
Test status
Simulation time 57623562 ps
CPU time 4.05 seconds
Started Jun 04 12:46:48 PM PDT 24
Finished Jun 04 12:46:53 PM PDT 24
Peak memory 215632 kb
Host smart-8753b95c-4cc6-4928-a30e-f32b1f69aabc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382361088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
382361088
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.601602345
Short name T108
Test name
Test status
Simulation time 1251514922 ps
CPU time 7.46 seconds
Started Jun 04 12:47:06 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 215340 kb
Host smart-2f3f66c6-fb11-4a8e-812b-68c0f213c8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601602345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.601602345
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.177097412
Short name T992
Test name
Test status
Simulation time 14955984 ps
CPU time 0.72 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 203728 kb
Host smart-5e2c29ff-d02a-4bab-b4e4-f58442771908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177097412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.177097412
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.739365046
Short name T1101
Test name
Test status
Simulation time 63334797 ps
CPU time 0.76 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 203716 kb
Host smart-7f043acd-5b96-4706-8ceb-75e3f1d92986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739365046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.739365046
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.841523150
Short name T1082
Test name
Test status
Simulation time 12027526 ps
CPU time 0.73 seconds
Started Jun 04 12:47:10 PM PDT 24
Finished Jun 04 12:47:12 PM PDT 24
Peak memory 203680 kb
Host smart-4385178c-7759-41e2-982f-cbb357201564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841523150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.841523150
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2856133261
Short name T1004
Test name
Test status
Simulation time 20183523 ps
CPU time 0.77 seconds
Started Jun 04 12:47:15 PM PDT 24
Finished Jun 04 12:47:18 PM PDT 24
Peak memory 203872 kb
Host smart-c5574d4a-717a-4ee9-8579-334b8b3aa314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856133261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2856133261
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2671859329
Short name T980
Test name
Test status
Simulation time 23964572 ps
CPU time 0.83 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 203640 kb
Host smart-f2f74410-a4cf-4469-81de-f7e4b197370e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671859329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2671859329
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3597175408
Short name T1060
Test name
Test status
Simulation time 16506312 ps
CPU time 0.75 seconds
Started Jun 04 12:47:14 PM PDT 24
Finished Jun 04 12:47:17 PM PDT 24
Peak memory 203804 kb
Host smart-545bb67a-5566-4c07-b2fa-018b7139e419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597175408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3597175408
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1647866826
Short name T1077
Test name
Test status
Simulation time 40949739 ps
CPU time 0.74 seconds
Started Jun 04 12:47:17 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 203612 kb
Host smart-2ed1acea-e2ae-4f0d-881a-e1e536c503f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647866826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1647866826
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3423011913
Short name T1019
Test name
Test status
Simulation time 15150634 ps
CPU time 0.73 seconds
Started Jun 04 12:47:13 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 203656 kb
Host smart-583d9291-3b6e-444d-b3b9-661603799459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423011913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3423011913
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2815441454
Short name T977
Test name
Test status
Simulation time 45301755 ps
CPU time 0.7 seconds
Started Jun 04 12:47:17 PM PDT 24
Finished Jun 04 12:47:20 PM PDT 24
Peak memory 203252 kb
Host smart-d3f745b4-cc4d-4ab7-8468-32a5f2c437c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815441454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2815441454
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2388733477
Short name T1012
Test name
Test status
Simulation time 50650751 ps
CPU time 0.81 seconds
Started Jun 04 12:47:12 PM PDT 24
Finished Jun 04 12:47:15 PM PDT 24
Peak memory 203696 kb
Host smart-a8bdaba0-1117-45d2-8ba4-e92bd694d1fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388733477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2388733477
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2951484739
Short name T1009
Test name
Test status
Simulation time 74244591 ps
CPU time 2.64 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 216968 kb
Host smart-a58318a2-8019-4d33-89bd-0e283630c80e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951484739 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2951484739
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2849474475
Short name T121
Test name
Test status
Simulation time 62918923 ps
CPU time 1.73 seconds
Started Jun 04 12:46:52 PM PDT 24
Finished Jun 04 12:46:55 PM PDT 24
Peak memory 215548 kb
Host smart-43220611-983f-4f9a-a612-dd752c58bd93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849474475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
849474475
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1359377783
Short name T982
Test name
Test status
Simulation time 99698336 ps
CPU time 0.71 seconds
Started Jun 04 12:46:50 PM PDT 24
Finished Jun 04 12:46:52 PM PDT 24
Peak memory 203960 kb
Host smart-8cd44f57-03f4-4ef8-b852-bd49190e6d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359377783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
359377783
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.733563706
Short name T995
Test name
Test status
Simulation time 1794654631 ps
CPU time 3.11 seconds
Started Jun 04 12:46:52 PM PDT 24
Finished Jun 04 12:46:57 PM PDT 24
Peak memory 215532 kb
Host smart-b51eeb85-2a6c-4538-9b6d-dde115922dca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733563706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.733563706
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.117733413
Short name T95
Test name
Test status
Simulation time 79523278 ps
CPU time 2.16 seconds
Started Jun 04 12:46:58 PM PDT 24
Finished Jun 04 12:47:01 PM PDT 24
Peak memory 215552 kb
Host smart-a6cbae91-5a3f-4c8d-80f6-599e7efc68bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117733413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.117733413
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1961899736
Short name T1021
Test name
Test status
Simulation time 1102213870 ps
CPU time 6.93 seconds
Started Jun 04 12:47:01 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 216028 kb
Host smart-a6470ccb-9123-443c-b7aa-954c695cd98b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961899736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1961899736
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2337910157
Short name T1069
Test name
Test status
Simulation time 55427963 ps
CPU time 3.89 seconds
Started Jun 04 12:47:06 PM PDT 24
Finished Jun 04 12:47:14 PM PDT 24
Peak memory 218484 kb
Host smart-6f941d86-1772-476a-901e-99e9a7c2f094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337910157 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2337910157
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.958927638
Short name T115
Test name
Test status
Simulation time 64211842 ps
CPU time 2.46 seconds
Started Jun 04 12:47:03 PM PDT 24
Finished Jun 04 12:47:07 PM PDT 24
Peak memory 215616 kb
Host smart-c721f0e3-4b87-4ebd-887b-ffe9fd7d82ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958927638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.958927638
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.752127983
Short name T984
Test name
Test status
Simulation time 53317320 ps
CPU time 0.75 seconds
Started Jun 04 12:47:00 PM PDT 24
Finished Jun 04 12:47:02 PM PDT 24
Peak memory 203676 kb
Host smart-7029d68e-2424-4f5e-b4d7-3dd24675672f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752127983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.752127983
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3583728639
Short name T1023
Test name
Test status
Simulation time 227476175 ps
CPU time 3.9 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 215448 kb
Host smart-fa4d3d25-e8f4-4c7f-ae37-ff4b4fbf9406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583728639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3583728639
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.435784676
Short name T1090
Test name
Test status
Simulation time 283086090 ps
CPU time 7.71 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:13 PM PDT 24
Peak memory 215540 kb
Host smart-45d2c785-2a67-44d7-8523-0e7b8656fa23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435784676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.435784676
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3671092096
Short name T1057
Test name
Test status
Simulation time 52161893 ps
CPU time 3.24 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 217336 kb
Host smart-302912c8-3d1e-436f-868d-43a6103b1167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671092096 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3671092096
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.682840989
Short name T152
Test name
Test status
Simulation time 80569924 ps
CPU time 2.09 seconds
Started Jun 04 12:47:09 PM PDT 24
Finished Jun 04 12:47:12 PM PDT 24
Peak memory 207216 kb
Host smart-ee92e1ed-7c02-44b8-bbda-cd95f85265d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682840989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.682840989
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3500658298
Short name T993
Test name
Test status
Simulation time 18516899 ps
CPU time 0.67 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 204084 kb
Host smart-4cfe2feb-21e2-4458-a9c6-bd03d99f12f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500658298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
500658298
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2361357977
Short name T140
Test name
Test status
Simulation time 628654027 ps
CPU time 4.56 seconds
Started Jun 04 12:47:06 PM PDT 24
Finished Jun 04 12:47:12 PM PDT 24
Peak memory 215548 kb
Host smart-4a3892de-efae-4adf-976e-a075be259ca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361357977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2361357977
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3893353010
Short name T92
Test name
Test status
Simulation time 49230893 ps
CPU time 2.85 seconds
Started Jun 04 12:47:11 PM PDT 24
Finished Jun 04 12:47:16 PM PDT 24
Peak memory 216608 kb
Host smart-fee7775f-4dae-45cb-a2e1-3f8fc2fccdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893353010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
893353010
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3523368571
Short name T1044
Test name
Test status
Simulation time 60587350 ps
CPU time 4.03 seconds
Started Jun 04 12:47:06 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 217800 kb
Host smart-f263c7cb-7386-4ad3-b870-0186f4d331fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523368571 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3523368571
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3372030234
Short name T991
Test name
Test status
Simulation time 85836085 ps
CPU time 2.46 seconds
Started Jun 04 12:47:07 PM PDT 24
Finished Jun 04 12:47:11 PM PDT 24
Peak memory 207252 kb
Host smart-ac555592-d4c1-45ee-9350-eb0370a0fac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372030234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
372030234
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.815461442
Short name T1095
Test name
Test status
Simulation time 22970821 ps
CPU time 0.69 seconds
Started Jun 04 12:47:08 PM PDT 24
Finished Jun 04 12:47:10 PM PDT 24
Peak memory 203976 kb
Host smart-bc0abb2e-e48d-4f1d-8f74-77621f92ef36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815461442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.815461442
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.296000373
Short name T997
Test name
Test status
Simulation time 96340041 ps
CPU time 1.86 seconds
Started Jun 04 12:47:00 PM PDT 24
Finished Jun 04 12:47:03 PM PDT 24
Peak memory 215452 kb
Host smart-ad02680f-c2ff-4828-bb29-c5894e4d0283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296000373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.296000373
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3738554881
Short name T265
Test name
Test status
Simulation time 422365371 ps
CPU time 2.8 seconds
Started Jun 04 12:47:02 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 215696 kb
Host smart-959ac5b3-ee05-4948-bb5d-2940f91645f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738554881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
738554881
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2843270877
Short name T96
Test name
Test status
Simulation time 417194405 ps
CPU time 6.92 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:12 PM PDT 24
Peak memory 215744 kb
Host smart-71f3ed61-431e-4263-85c8-dc3c1629e5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843270877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2843270877
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1991912198
Short name T105
Test name
Test status
Simulation time 174391118 ps
CPU time 2.86 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:13 PM PDT 24
Peak memory 216524 kb
Host smart-478e09a1-f4ff-4762-950b-5529c61d68d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991912198 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1991912198
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1805062250
Short name T996
Test name
Test status
Simulation time 31937367 ps
CPU time 1.75 seconds
Started Jun 04 12:47:03 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 207196 kb
Host smart-fed5f489-6100-45d6-ae42-53bcf803ee13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805062250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
805062250
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3390245214
Short name T976
Test name
Test status
Simulation time 14426138 ps
CPU time 0.76 seconds
Started Jun 04 12:47:04 PM PDT 24
Finished Jun 04 12:47:06 PM PDT 24
Peak memory 203712 kb
Host smart-527d1f9e-ec02-451c-b82f-f64b0ae1df60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390245214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
390245214
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3695717624
Short name T1066
Test name
Test status
Simulation time 118525836 ps
CPU time 4 seconds
Started Jun 04 12:47:03 PM PDT 24
Finished Jun 04 12:47:08 PM PDT 24
Peak memory 215100 kb
Host smart-ff997d85-932c-4d5d-b5db-4c8b02b12e63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695717624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3695717624
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4006275768
Short name T94
Test name
Test status
Simulation time 122435253 ps
CPU time 2.21 seconds
Started Jun 04 12:47:06 PM PDT 24
Finished Jun 04 12:47:09 PM PDT 24
Peak memory 216488 kb
Host smart-5d463c74-4e2f-46af-b84a-f3ca311f9814
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006275768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
006275768
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3329871097
Short name T107
Test name
Test status
Simulation time 223136535 ps
CPU time 10.86 seconds
Started Jun 04 12:47:07 PM PDT 24
Finished Jun 04 12:47:19 PM PDT 24
Peak memory 215456 kb
Host smart-dc2bbf61-398f-4ed6-bd6c-8df2c0acf5fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329871097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3329871097
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3706668171
Short name T814
Test name
Test status
Simulation time 14691819 ps
CPU time 0.75 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:18:46 PM PDT 24
Peak memory 204284 kb
Host smart-53e63d12-2071-435b-bf79-66f8c7a914fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706668171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
706668171
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.594213602
Short name T598
Test name
Test status
Simulation time 160667242 ps
CPU time 2.89 seconds
Started Jun 04 02:18:44 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 233936 kb
Host smart-867b541e-3ea0-46de-91b7-7d9596e5f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594213602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.594213602
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2674494848
Short name T444
Test name
Test status
Simulation time 184375348 ps
CPU time 0.76 seconds
Started Jun 04 02:18:42 PM PDT 24
Finished Jun 04 02:18:43 PM PDT 24
Peak memory 205236 kb
Host smart-bcadbb6a-8010-4b98-8137-7fbfccf78eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674494848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2674494848
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2990521825
Short name T797
Test name
Test status
Simulation time 27653305 ps
CPU time 0.75 seconds
Started Jun 04 02:18:43 PM PDT 24
Finished Jun 04 02:18:44 PM PDT 24
Peak memory 215416 kb
Host smart-691fa6e0-e6c3-4cad-8909-f16c498cf341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990521825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2990521825
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2451898462
Short name T253
Test name
Test status
Simulation time 62780407679 ps
CPU time 149.84 seconds
Started Jun 04 02:18:42 PM PDT 24
Finished Jun 04 02:21:13 PM PDT 24
Peak memory 240708 kb
Host smart-3479b11a-78a5-4f0d-a212-de90331c96ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451898462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2451898462
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1424592587
Short name T135
Test name
Test status
Simulation time 11560282870 ps
CPU time 134.55 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:21:00 PM PDT 24
Peak memory 250852 kb
Host smart-bdc6f62f-9032-4e29-95b9-b4c072aa3ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424592587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1424592587
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1849007531
Short name T312
Test name
Test status
Simulation time 4261442083 ps
CPU time 14.6 seconds
Started Jun 04 02:18:43 PM PDT 24
Finished Jun 04 02:18:58 PM PDT 24
Peak memory 235480 kb
Host smart-224db969-091b-4717-9d0b-c0bae8450dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849007531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1849007531
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1040441816
Short name T847
Test name
Test status
Simulation time 1051523145 ps
CPU time 3.68 seconds
Started Jun 04 02:18:48 PM PDT 24
Finished Jun 04 02:18:52 PM PDT 24
Peak memory 218140 kb
Host smart-938ee3de-de3a-449f-9c26-da00f115cc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040441816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1040441816
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1054032911
Short name T466
Test name
Test status
Simulation time 17946730161 ps
CPU time 48.68 seconds
Started Jun 04 02:18:44 PM PDT 24
Finished Jun 04 02:19:34 PM PDT 24
Peak memory 234980 kb
Host smart-a2399772-27a0-4d4a-a449-b0c50aa9f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054032911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1054032911
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2499318126
Short name T924
Test name
Test status
Simulation time 87704228 ps
CPU time 1.03 seconds
Started Jun 04 02:18:43 PM PDT 24
Finished Jun 04 02:18:45 PM PDT 24
Peak memory 216208 kb
Host smart-992ce3ae-2a24-4b56-9758-aadeea00d845
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499318126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2499318126
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3540976377
Short name T41
Test name
Test status
Simulation time 3684512190 ps
CPU time 5.07 seconds
Started Jun 04 02:18:43 PM PDT 24
Finished Jun 04 02:18:49 PM PDT 24
Peak memory 218356 kb
Host smart-4603d134-d85b-4af4-a1ab-36ed09e2d0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540976377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3540976377
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3994287416
Short name T527
Test name
Test status
Simulation time 1075316468 ps
CPU time 5.58 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:18:52 PM PDT 24
Peak memory 233896 kb
Host smart-df58e733-8f65-4d55-bdcb-a10f00a50b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994287416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3994287416
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1386324896
Short name T45
Test name
Test status
Simulation time 2932765337 ps
CPU time 17.64 seconds
Started Jun 04 02:18:44 PM PDT 24
Finished Jun 04 02:19:03 PM PDT 24
Peak memory 219112 kb
Host smart-a79182c3-92ae-4bc7-9526-2424dd440d92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1386324896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1386324896
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.645300164
Short name T69
Test name
Test status
Simulation time 370363658 ps
CPU time 1.19 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 236324 kb
Host smart-99c9a767-50ba-47ae-9e76-4439b9887bc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645300164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.645300164
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1839197136
Short name T669
Test name
Test status
Simulation time 41140454461 ps
CPU time 424.43 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:25:51 PM PDT 24
Peak memory 272432 kb
Host smart-0b5a3e26-9bfe-4ab4-baf5-c0d6c571a7bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839197136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1839197136
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.783096365
Short name T141
Test name
Test status
Simulation time 43290854 ps
CPU time 0.72 seconds
Started Jun 04 02:18:48 PM PDT 24
Finished Jun 04 02:18:49 PM PDT 24
Peak memory 205052 kb
Host smart-c394014f-8bf2-417a-a4fc-db41b08e9f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783096365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.783096365
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1409875509
Short name T891
Test name
Test status
Simulation time 4632354765 ps
CPU time 13.53 seconds
Started Jun 04 02:18:44 PM PDT 24
Finished Jun 04 02:18:58 PM PDT 24
Peak memory 215892 kb
Host smart-094107da-faca-48e4-a1a6-78bdebe6e495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409875509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1409875509
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1767951026
Short name T342
Test name
Test status
Simulation time 13310636 ps
CPU time 0.68 seconds
Started Jun 04 02:18:43 PM PDT 24
Finished Jun 04 02:18:45 PM PDT 24
Peak memory 204920 kb
Host smart-04696637-6a20-4a3a-8e46-3537d29b7e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767951026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1767951026
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1837749887
Short name T417
Test name
Test status
Simulation time 69955968 ps
CPU time 0.88 seconds
Started Jun 04 02:18:42 PM PDT 24
Finished Jun 04 02:18:44 PM PDT 24
Peak memory 205276 kb
Host smart-ab0b5209-c240-4519-8ae9-e1c7f4f4c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837749887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1837749887
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1976420163
Short name T294
Test name
Test status
Simulation time 1509930935 ps
CPU time 4.57 seconds
Started Jun 04 02:18:43 PM PDT 24
Finished Jun 04 02:18:49 PM PDT 24
Peak memory 217372 kb
Host smart-18b73f5d-1637-4c4f-a468-1b60c89b5566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976420163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1976420163
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3958818234
Short name T734
Test name
Test status
Simulation time 12248079 ps
CPU time 0.82 seconds
Started Jun 04 02:18:55 PM PDT 24
Finished Jun 04 02:18:57 PM PDT 24
Peak memory 204964 kb
Host smart-abb52d31-8c47-45ba-ab8f-60bcec88926a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958818234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
958818234
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1336025429
Short name T75
Test name
Test status
Simulation time 446046442 ps
CPU time 2.75 seconds
Started Jun 04 02:18:53 PM PDT 24
Finished Jun 04 02:18:56 PM PDT 24
Peak memory 233376 kb
Host smart-6bcdd273-2aa2-458d-8376-b2f47d05059a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336025429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1336025429
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2224592311
Short name T820
Test name
Test status
Simulation time 31714375 ps
CPU time 0.78 seconds
Started Jun 04 02:18:46 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 206260 kb
Host smart-f8a7c476-ab36-40f8-b9ab-2baa78a4e434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224592311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2224592311
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3879014243
Short name T502
Test name
Test status
Simulation time 2606099124 ps
CPU time 33.44 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:19:26 PM PDT 24
Peak memory 249840 kb
Host smart-7630cc54-f000-4b9e-9de5-1e928b380630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879014243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3879014243
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2513815732
Short name T169
Test name
Test status
Simulation time 15836502583 ps
CPU time 151.29 seconds
Started Jun 04 02:18:55 PM PDT 24
Finished Jun 04 02:21:27 PM PDT 24
Peak memory 248876 kb
Host smart-bf73d3f7-4a48-4603-a125-fc7574ba08df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513815732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2513815732
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2949825332
Short name T222
Test name
Test status
Simulation time 147049062016 ps
CPU time 436.98 seconds
Started Jun 04 02:18:50 PM PDT 24
Finished Jun 04 02:26:08 PM PDT 24
Peak memory 271000 kb
Host smart-d4d6ecc1-2086-4ed5-8b5a-3569ffeb9706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949825332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2949825332
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.213983966
Short name T911
Test name
Test status
Simulation time 1678169910 ps
CPU time 16.68 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:19:09 PM PDT 24
Peak memory 237120 kb
Host smart-e7166b4a-d4fb-4541-9e93-c1e6772d10b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213983966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.213983966
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1751852892
Short name T415
Test name
Test status
Simulation time 1448908824 ps
CPU time 4.15 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:18:56 PM PDT 24
Peak memory 218096 kb
Host smart-d94e9b94-7e82-463d-a201-b76bac06bd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751852892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1751852892
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.647149426
Short name T291
Test name
Test status
Simulation time 1312067852 ps
CPU time 18.76 seconds
Started Jun 04 02:18:54 PM PDT 24
Finished Jun 04 02:19:14 PM PDT 24
Peak memory 233748 kb
Host smart-3d69cf83-84c7-4b03-a8a9-76ca7269632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647149426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.647149426
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4090731491
Short name T838
Test name
Test status
Simulation time 106004276 ps
CPU time 2.46 seconds
Started Jun 04 02:18:43 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 220460 kb
Host smart-210242e5-7003-4f1b-8c16-e0a0d2ecda7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090731491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4090731491
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2443396650
Short name T67
Test name
Test status
Simulation time 67403716 ps
CPU time 1 seconds
Started Jun 04 02:18:53 PM PDT 24
Finished Jun 04 02:18:55 PM PDT 24
Peak memory 234716 kb
Host smart-868db48e-b6eb-4d9a-9ab4-27914bd2430d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443396650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2443396650
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1845679660
Short name T138
Test name
Test status
Simulation time 103446153568 ps
CPU time 279.73 seconds
Started Jun 04 02:18:51 PM PDT 24
Finished Jun 04 02:23:31 PM PDT 24
Peak memory 254400 kb
Host smart-403c7559-00c9-4446-a1f9-fd282395b581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845679660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1845679660
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3251612152
Short name T874
Test name
Test status
Simulation time 14296568993 ps
CPU time 42.89 seconds
Started Jun 04 02:18:46 PM PDT 24
Finished Jun 04 02:19:29 PM PDT 24
Peak memory 215988 kb
Host smart-c44e64b6-acbc-4275-a9fe-cbef4f171f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251612152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3251612152
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3804888528
Short name T355
Test name
Test status
Simulation time 664602873 ps
CPU time 2.83 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:18:49 PM PDT 24
Peak memory 215868 kb
Host smart-b1ca3dce-5d0d-4fb9-ab43-2945c57f156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804888528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3804888528
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2730125886
Short name T584
Test name
Test status
Simulation time 266913881 ps
CPU time 4.12 seconds
Started Jun 04 02:18:47 PM PDT 24
Finished Jun 04 02:18:51 PM PDT 24
Peak memory 215864 kb
Host smart-78dff55f-c1e5-4b8d-99ef-c415b8e95f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730125886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2730125886
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3244801173
Short name T468
Test name
Test status
Simulation time 69543970 ps
CPU time 0.78 seconds
Started Jun 04 02:18:45 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 205252 kb
Host smart-4edf1c92-f34f-4caa-8ffa-4e9f7bcf40d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244801173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3244801173
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2928140285
Short name T798
Test name
Test status
Simulation time 747543123 ps
CPU time 2.81 seconds
Started Jun 04 02:18:55 PM PDT 24
Finished Jun 04 02:18:58 PM PDT 24
Peak memory 232384 kb
Host smart-f688fe74-20ff-445f-bbbb-b55fdaa63f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928140285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2928140285
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.8135111
Short name T634
Test name
Test status
Simulation time 63133870 ps
CPU time 0.75 seconds
Started Jun 04 02:19:43 PM PDT 24
Finished Jun 04 02:19:44 PM PDT 24
Peak memory 204200 kb
Host smart-d89e0f90-74c7-4d37-8ddf-3451a445c0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8135111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.8135111
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.180203859
Short name T563
Test name
Test status
Simulation time 509266776 ps
CPU time 5.08 seconds
Started Jun 04 02:19:47 PM PDT 24
Finished Jun 04 02:19:53 PM PDT 24
Peak memory 233292 kb
Host smart-b41703a7-794b-4442-b75d-78b70806c6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180203859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.180203859
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.837615393
Short name T463
Test name
Test status
Simulation time 13336950 ps
CPU time 0.79 seconds
Started Jun 04 02:19:37 PM PDT 24
Finished Jun 04 02:19:39 PM PDT 24
Peak memory 204888 kb
Host smart-c41298b2-392e-4f08-952e-cee1d8d55d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837615393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.837615393
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2632040162
Short name T574
Test name
Test status
Simulation time 21588231779 ps
CPU time 62.42 seconds
Started Jun 04 02:19:46 PM PDT 24
Finished Jun 04 02:20:49 PM PDT 24
Peak memory 250736 kb
Host smart-08faf96a-104f-48fc-bd58-691b15e6fd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632040162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2632040162
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2684508744
Short name T263
Test name
Test status
Simulation time 12102364479 ps
CPU time 122.07 seconds
Started Jun 04 02:19:43 PM PDT 24
Finished Jun 04 02:21:46 PM PDT 24
Peak memory 253280 kb
Host smart-8110fbc1-74dd-475a-a7d4-00617712a0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684508744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2684508744
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1212917765
Short name T839
Test name
Test status
Simulation time 464056135 ps
CPU time 8.67 seconds
Started Jun 04 02:19:42 PM PDT 24
Finished Jun 04 02:19:51 PM PDT 24
Peak memory 224180 kb
Host smart-98ac7481-7b59-453d-b0e3-2f7f1df56db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212917765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1212917765
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1083170059
Short name T856
Test name
Test status
Simulation time 337627318 ps
CPU time 5.43 seconds
Started Jun 04 02:19:39 PM PDT 24
Finished Jun 04 02:19:45 PM PDT 24
Peak memory 234872 kb
Host smart-90e6127b-01e9-4ee3-b94c-ce61d4ff03f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083170059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1083170059
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2428578946
Short name T800
Test name
Test status
Simulation time 1692806351 ps
CPU time 11.85 seconds
Started Jun 04 02:19:37 PM PDT 24
Finished Jun 04 02:19:50 PM PDT 24
Peak memory 233360 kb
Host smart-69cd1676-9a81-43ad-9ffe-2056b74509c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428578946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2428578946
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2985951479
Short name T28
Test name
Test status
Simulation time 92874311 ps
CPU time 1.1 seconds
Started Jun 04 02:19:42 PM PDT 24
Finished Jun 04 02:19:43 PM PDT 24
Peak memory 216220 kb
Host smart-4bd29c33-1507-436e-a815-a4bb262789ae
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985951479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2985951479
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1944837099
Short name T71
Test name
Test status
Simulation time 4729568361 ps
CPU time 18.98 seconds
Started Jun 04 02:19:37 PM PDT 24
Finished Jun 04 02:19:57 PM PDT 24
Peak memory 248540 kb
Host smart-fcfe94d0-9798-488a-b162-11ebacdd0c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944837099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1944837099
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.223139013
Short name T556
Test name
Test status
Simulation time 31680681 ps
CPU time 2.6 seconds
Started Jun 04 02:19:37 PM PDT 24
Finished Jun 04 02:19:41 PM PDT 24
Peak memory 220876 kb
Host smart-4df53af2-e5bc-46a8-9e8e-e4b840a48557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223139013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.223139013
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2591886679
Short name T356
Test name
Test status
Simulation time 229867034 ps
CPU time 4.67 seconds
Started Jun 04 02:19:45 PM PDT 24
Finished Jun 04 02:19:51 PM PDT 24
Peak memory 222600 kb
Host smart-f6e03938-7d28-4427-8408-6edde93538b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2591886679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2591886679
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1824083467
Short name T407
Test name
Test status
Simulation time 68163738 ps
CPU time 1.17 seconds
Started Jun 04 02:19:47 PM PDT 24
Finished Jun 04 02:19:49 PM PDT 24
Peak memory 206432 kb
Host smart-2d41f342-7203-41da-bff2-1116ad894110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824083467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1824083467
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3929766007
Short name T892
Test name
Test status
Simulation time 21579881968 ps
CPU time 20.35 seconds
Started Jun 04 02:19:38 PM PDT 24
Finished Jun 04 02:19:59 PM PDT 24
Peak memory 219508 kb
Host smart-c957992f-83ef-4b04-9f28-3fc811fba04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929766007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3929766007
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1400552607
Short name T785
Test name
Test status
Simulation time 11397089903 ps
CPU time 5.77 seconds
Started Jun 04 02:19:39 PM PDT 24
Finished Jun 04 02:19:46 PM PDT 24
Peak memory 215796 kb
Host smart-39671965-4955-4c4c-bdc4-658eba4a9d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400552607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1400552607
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2535343482
Short name T398
Test name
Test status
Simulation time 270362494 ps
CPU time 1.24 seconds
Started Jun 04 02:19:36 PM PDT 24
Finished Jun 04 02:19:39 PM PDT 24
Peak memory 207440 kb
Host smart-8d947c56-657b-4191-821a-4e5226d5e333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535343482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2535343482
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.388082343
Short name T363
Test name
Test status
Simulation time 12322174 ps
CPU time 0.74 seconds
Started Jun 04 02:19:40 PM PDT 24
Finished Jun 04 02:19:42 PM PDT 24
Peak memory 204928 kb
Host smart-44d6a1b0-fc80-4d4b-b1ad-b717bb8d7980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388082343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.388082343
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1950948581
Short name T281
Test name
Test status
Simulation time 12146308383 ps
CPU time 24.28 seconds
Started Jun 04 02:19:44 PM PDT 24
Finished Jun 04 02:20:09 PM PDT 24
Peak memory 238828 kb
Host smart-9cb7df3b-315a-464f-a2f4-8e7c7ceca27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950948581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1950948581
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2643632154
Short name T942
Test name
Test status
Simulation time 26409948 ps
CPU time 0.71 seconds
Started Jun 04 02:19:53 PM PDT 24
Finished Jun 04 02:19:55 PM PDT 24
Peak memory 204848 kb
Host smart-52f6f767-75b6-4603-b365-a090cc2abffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643632154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2643632154
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.765142383
Short name T920
Test name
Test status
Simulation time 173608519 ps
CPU time 3.44 seconds
Started Jun 04 02:19:50 PM PDT 24
Finished Jun 04 02:19:54 PM PDT 24
Peak memory 233500 kb
Host smart-c15b72e7-32f0-41b1-82f6-9a54d2f1aec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765142383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.765142383
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1423600551
Short name T829
Test name
Test status
Simulation time 107348944 ps
CPU time 0.77 seconds
Started Jun 04 02:19:47 PM PDT 24
Finished Jun 04 02:19:49 PM PDT 24
Peak memory 204840 kb
Host smart-45152a55-f3df-4ee0-b270-1476d125d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423600551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1423600551
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3859959523
Short name T399
Test name
Test status
Simulation time 17922509 ps
CPU time 0.79 seconds
Started Jun 04 02:19:53 PM PDT 24
Finished Jun 04 02:19:54 PM PDT 24
Peak memory 215436 kb
Host smart-8632b3a6-bb56-49f2-86ba-819f3dc6b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859959523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3859959523
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.833888090
Short name T763
Test name
Test status
Simulation time 19100726451 ps
CPU time 16.19 seconds
Started Jun 04 02:19:52 PM PDT 24
Finished Jun 04 02:20:09 PM PDT 24
Peak memory 224196 kb
Host smart-a1188528-c602-42a9-ab38-ca5d829d6d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833888090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.833888090
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4017864757
Short name T297
Test name
Test status
Simulation time 7620589385 ps
CPU time 18.71 seconds
Started Jun 04 02:19:49 PM PDT 24
Finished Jun 04 02:20:09 PM PDT 24
Peak memory 219596 kb
Host smart-9aeecfa0-104e-4761-b288-18408ab2cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017864757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4017864757
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.830247679
Short name T772
Test name
Test status
Simulation time 341925449 ps
CPU time 7.55 seconds
Started Jun 04 02:19:50 PM PDT 24
Finished Jun 04 02:19:59 PM PDT 24
Peak memory 233636 kb
Host smart-a24cdc5b-7b36-4268-8574-05c38dc62429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830247679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.830247679
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.686635504
Short name T537
Test name
Test status
Simulation time 44818201 ps
CPU time 0.99 seconds
Started Jun 04 02:19:46 PM PDT 24
Finished Jun 04 02:19:47 PM PDT 24
Peak memory 216216 kb
Host smart-b279e8d2-26a8-4f49-8e1b-a2d5253e49fd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686635504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.686635504
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2441327110
Short name T831
Test name
Test status
Simulation time 4544116337 ps
CPU time 9.72 seconds
Started Jun 04 02:19:45 PM PDT 24
Finished Jun 04 02:19:56 PM PDT 24
Peak memory 233612 kb
Host smart-52de67a0-b005-481d-bed6-bbf3e878828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441327110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2441327110
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.501367338
Short name T196
Test name
Test status
Simulation time 7052646530 ps
CPU time 12.36 seconds
Started Jun 04 02:19:44 PM PDT 24
Finished Jun 04 02:19:58 PM PDT 24
Peak memory 233464 kb
Host smart-b626fbb9-2e81-479b-a3b5-dddc1f135161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501367338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.501367338
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.532647510
Short name T954
Test name
Test status
Simulation time 1381604410 ps
CPU time 12.69 seconds
Started Jun 04 02:19:50 PM PDT 24
Finished Jun 04 02:20:04 PM PDT 24
Peak memory 218972 kb
Host smart-646e20d9-5273-4f89-82c1-80f7bb047aae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=532647510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.532647510
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1620800863
Short name T562
Test name
Test status
Simulation time 820851010 ps
CPU time 6.02 seconds
Started Jun 04 02:19:45 PM PDT 24
Finished Jun 04 02:19:51 PM PDT 24
Peak memory 215948 kb
Host smart-191f0e3e-bab3-4137-af38-07927d87cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620800863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1620800863
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1239452621
Short name T450
Test name
Test status
Simulation time 5833147308 ps
CPU time 6.44 seconds
Started Jun 04 02:19:44 PM PDT 24
Finished Jun 04 02:19:51 PM PDT 24
Peak memory 215892 kb
Host smart-6001b30d-2308-4e48-b172-f87f0105203d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239452621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1239452621
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2640251780
Short name T47
Test name
Test status
Simulation time 17038706 ps
CPU time 0.89 seconds
Started Jun 04 02:19:45 PM PDT 24
Finished Jun 04 02:19:46 PM PDT 24
Peak memory 205940 kb
Host smart-f41d713b-fbbe-466e-9922-15e59e8578b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640251780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2640251780
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1886593616
Short name T471
Test name
Test status
Simulation time 61080985 ps
CPU time 0.72 seconds
Started Jun 04 02:19:44 PM PDT 24
Finished Jun 04 02:19:46 PM PDT 24
Peak memory 205300 kb
Host smart-33a504da-12e3-4e27-8e67-de65f8bd5cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886593616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1886593616
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1755419098
Short name T200
Test name
Test status
Simulation time 465366534 ps
CPU time 4.53 seconds
Started Jun 04 02:19:50 PM PDT 24
Finished Jun 04 02:19:56 PM PDT 24
Peak memory 217308 kb
Host smart-4b29ba72-04d1-4a4a-96b9-43e5a3e5ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755419098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1755419098
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3800178741
Short name T886
Test name
Test status
Simulation time 43359432 ps
CPU time 0.75 seconds
Started Jun 04 02:20:02 PM PDT 24
Finished Jun 04 02:20:04 PM PDT 24
Peak memory 204292 kb
Host smart-0ea80dde-531a-4cdf-b03e-49a38518393d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800178741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3800178741
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2974402328
Short name T461
Test name
Test status
Simulation time 314443544 ps
CPU time 3.13 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:03 PM PDT 24
Peak memory 233608 kb
Host smart-cabce7f5-e0f0-4c49-83eb-d876dc41944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974402328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2974402328
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3213688395
Short name T391
Test name
Test status
Simulation time 256959793 ps
CPU time 0.77 seconds
Started Jun 04 02:19:51 PM PDT 24
Finished Jun 04 02:19:53 PM PDT 24
Peak memory 205884 kb
Host smart-892e6220-3a9d-452f-8ea0-e1af819e1818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213688395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3213688395
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2212261832
Short name T131
Test name
Test status
Simulation time 8794132130 ps
CPU time 25.26 seconds
Started Jun 04 02:20:01 PM PDT 24
Finished Jun 04 02:20:28 PM PDT 24
Peak memory 240624 kb
Host smart-a62215d1-0780-403e-9a09-a8a476489585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212261832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2212261832
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3453339076
Short name T900
Test name
Test status
Simulation time 4633755779 ps
CPU time 32.14 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:32 PM PDT 24
Peak memory 237084 kb
Host smart-22979e9c-aa2d-4adc-9d33-69f34d393745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453339076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3453339076
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2777039592
Short name T432
Test name
Test status
Simulation time 3724320482 ps
CPU time 20.83 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:22 PM PDT 24
Peak memory 217028 kb
Host smart-43e25cf3-5b17-4ebd-aa7c-fdd245871103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777039592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2777039592
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1660566007
Short name T308
Test name
Test status
Simulation time 342211741 ps
CPU time 9.49 seconds
Started Jun 04 02:20:01 PM PDT 24
Finished Jun 04 02:20:12 PM PDT 24
Peak memory 224140 kb
Host smart-1f93275d-1f24-4958-922e-5fb22172d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660566007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1660566007
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2829494532
Short name T184
Test name
Test status
Simulation time 320878747 ps
CPU time 5.07 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:11 PM PDT 24
Peak memory 217140 kb
Host smart-187edd1a-6246-4a4b-a9d6-daaad85c903b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829494532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2829494532
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.272698985
Short name T566
Test name
Test status
Simulation time 3224595632 ps
CPU time 25.68 seconds
Started Jun 04 02:20:03 PM PDT 24
Finished Jun 04 02:20:29 PM PDT 24
Peak memory 234636 kb
Host smart-2f51d8f4-9ede-4a3f-afc1-8cb196a82c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272698985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.272698985
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3074013811
Short name T421
Test name
Test status
Simulation time 139250837 ps
CPU time 1.03 seconds
Started Jun 04 02:19:50 PM PDT 24
Finished Jun 04 02:19:52 PM PDT 24
Peak memory 217464 kb
Host smart-4404cbd3-5084-4785-900c-2f4469f63bf3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074013811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3074013811
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4077188379
Short name T304
Test name
Test status
Simulation time 262877715 ps
CPU time 3.88 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:03 PM PDT 24
Peak memory 219352 kb
Host smart-a553a01b-a572-45d1-8216-c39c810f1e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077188379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4077188379
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2515037902
Short name T473
Test name
Test status
Simulation time 25998652526 ps
CPU time 34.69 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:36 PM PDT 24
Peak memory 240228 kb
Host smart-b2a28ecd-c64a-4219-bd02-be33a3b12583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515037902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2515037902
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4125144765
Short name T529
Test name
Test status
Simulation time 4006575673 ps
CPU time 13.88 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:14 PM PDT 24
Peak memory 218992 kb
Host smart-b75731d1-8169-4a6a-985c-294b9c76caef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4125144765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4125144765
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2089640037
Short name T159
Test name
Test status
Simulation time 76197222 ps
CPU time 1.18 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:02 PM PDT 24
Peak memory 214812 kb
Host smart-3e96b36b-cd58-4d7e-8573-381bd1d31587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089640037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2089640037
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1989140857
Short name T592
Test name
Test status
Simulation time 2977250742 ps
CPU time 18.94 seconds
Started Jun 04 02:19:51 PM PDT 24
Finished Jun 04 02:20:11 PM PDT 24
Peak memory 215964 kb
Host smart-6e1a00e5-480c-4f2c-b156-21662986ce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989140857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1989140857
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4031592294
Short name T447
Test name
Test status
Simulation time 6676234238 ps
CPU time 5.26 seconds
Started Jun 04 02:19:50 PM PDT 24
Finished Jun 04 02:19:56 PM PDT 24
Peak memory 215880 kb
Host smart-accba4de-d9d8-4f36-8de7-8b52a8552076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031592294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4031592294
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2222896259
Short name T646
Test name
Test status
Simulation time 17537922 ps
CPU time 0.75 seconds
Started Jun 04 02:19:51 PM PDT 24
Finished Jun 04 02:19:52 PM PDT 24
Peak memory 205324 kb
Host smart-3a60ed15-52ac-404b-b001-352ebe15254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222896259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2222896259
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.925549884
Short name T703
Test name
Test status
Simulation time 134992725 ps
CPU time 0.94 seconds
Started Jun 04 02:19:51 PM PDT 24
Finished Jun 04 02:19:53 PM PDT 24
Peak memory 205528 kb
Host smart-40e60fec-39c4-4957-b1b2-9b8fb29092ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925549884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.925549884
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2927796076
Short name T658
Test name
Test status
Simulation time 2278588241 ps
CPU time 4.65 seconds
Started Jun 04 02:20:01 PM PDT 24
Finished Jun 04 02:20:07 PM PDT 24
Peak memory 218352 kb
Host smart-bf0def81-ebdc-4c63-b583-1dc98ccf2e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927796076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2927796076
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1245984011
Short name T946
Test name
Test status
Simulation time 13555607 ps
CPU time 0.73 seconds
Started Jun 04 02:20:02 PM PDT 24
Finished Jun 04 02:20:03 PM PDT 24
Peak memory 205264 kb
Host smart-c2426df9-16a3-41c0-9f1d-8ca415a64fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245984011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1245984011
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3393956645
Short name T88
Test name
Test status
Simulation time 226074411 ps
CPU time 4.88 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:04 PM PDT 24
Peak memory 220884 kb
Host smart-879976cc-12e9-4113-bf2c-2e8fc54ca20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393956645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3393956645
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1832114283
Short name T809
Test name
Test status
Simulation time 32431492 ps
CPU time 0.74 seconds
Started Jun 04 02:20:02 PM PDT 24
Finished Jun 04 02:20:03 PM PDT 24
Peak memory 204884 kb
Host smart-c6773121-fc91-49d5-b715-c18a70dd357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832114283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1832114283
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.599739345
Short name T254
Test name
Test status
Simulation time 5246362489 ps
CPU time 98.14 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:21:37 PM PDT 24
Peak memory 255148 kb
Host smart-4e6d99b7-0fc6-4dbd-af28-5006e8806fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599739345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.599739345
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.864787086
Short name T738
Test name
Test status
Simulation time 44834233455 ps
CPU time 172.92 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:22:54 PM PDT 24
Peak memory 249272 kb
Host smart-00986577-9a4c-4a9b-b147-600a2fe7bcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864787086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.864787086
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1497498933
Short name T214
Test name
Test status
Simulation time 13188260302 ps
CPU time 43.58 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:44 PM PDT 24
Peak memory 233724 kb
Host smart-b4070906-b502-4302-bf7b-689389d89e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497498933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1497498933
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.939418122
Short name T351
Test name
Test status
Simulation time 213049089 ps
CPU time 4.85 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:06 PM PDT 24
Peak memory 232384 kb
Host smart-aef9df2c-a5f9-494d-994c-6113abea8f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939418122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.939418122
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.324982527
Short name T402
Test name
Test status
Simulation time 2972700121 ps
CPU time 29.86 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:31 PM PDT 24
Peak memory 234976 kb
Host smart-482e0d13-a703-4026-b26b-24a2801c7db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324982527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.324982527
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1174202545
Short name T688
Test name
Test status
Simulation time 135235121 ps
CPU time 2.45 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:03 PM PDT 24
Peak memory 220984 kb
Host smart-00fbe34e-94f4-4e3d-ad76-2778e5c49861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174202545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1174202545
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2333370114
Short name T542
Test name
Test status
Simulation time 51956779 ps
CPU time 1.03 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:01 PM PDT 24
Peak memory 217432 kb
Host smart-a6c1dbf5-9248-4deb-9385-f3360ceb41a4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333370114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2333370114
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1490982361
Short name T857
Test name
Test status
Simulation time 369919442 ps
CPU time 5.92 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:07 PM PDT 24
Peak memory 234092 kb
Host smart-9a992f7f-7116-46e3-8352-707dfc043a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490982361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1490982361
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1445930996
Short name T333
Test name
Test status
Simulation time 197350066 ps
CPU time 3.25 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:03 PM PDT 24
Peak memory 232348 kb
Host smart-160dc43f-8684-4325-b0fd-6f403d08e140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445930996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1445930996
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3216642303
Short name T462
Test name
Test status
Simulation time 5473117077 ps
CPU time 9.92 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:10 PM PDT 24
Peak memory 220156 kb
Host smart-daf7e7ad-33a6-4eb1-92ff-9747df5ac9f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3216642303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3216642303
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2645851315
Short name T486
Test name
Test status
Simulation time 400870256 ps
CPU time 5.77 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:07 PM PDT 24
Peak memory 217760 kb
Host smart-57cf6b9d-1fec-498e-bc00-9f006ab94554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645851315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2645851315
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.530592520
Short name T465
Test name
Test status
Simulation time 6958651971 ps
CPU time 6.62 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:07 PM PDT 24
Peak memory 215888 kb
Host smart-67a20520-5dbb-4302-82e4-efeeb02d6160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530592520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.530592520
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2571292389
Short name T852
Test name
Test status
Simulation time 80048845 ps
CPU time 0.78 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:02 PM PDT 24
Peak memory 205380 kb
Host smart-e3372acc-e7f7-4a56-a545-fb87053fbbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571292389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2571292389
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3866173699
Short name T16
Test name
Test status
Simulation time 50271902 ps
CPU time 0.89 seconds
Started Jun 04 02:19:59 PM PDT 24
Finished Jun 04 02:20:01 PM PDT 24
Peak memory 205288 kb
Host smart-fe641137-697c-43d8-84a6-9200bee6116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866173699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3866173699
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2851654353
Short name T571
Test name
Test status
Simulation time 48444571734 ps
CPU time 23.79 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:30 PM PDT 24
Peak memory 224276 kb
Host smart-50bf7a71-ef45-45e7-a8a2-9009f051b597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851654353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2851654353
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1155532220
Short name T877
Test name
Test status
Simulation time 14332807 ps
CPU time 0.74 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:07 PM PDT 24
Peak memory 204268 kb
Host smart-1324d809-8b65-4dc9-bed2-fb06e9ce21fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155532220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1155532220
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3876316104
Short name T457
Test name
Test status
Simulation time 3000014787 ps
CPU time 8.45 seconds
Started Jun 04 02:20:03 PM PDT 24
Finished Jun 04 02:20:13 PM PDT 24
Peak memory 234596 kb
Host smart-00107297-eff4-47a9-a903-05b08df92e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876316104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3876316104
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.363585686
Short name T378
Test name
Test status
Simulation time 56682268 ps
CPU time 0.82 seconds
Started Jun 04 02:20:00 PM PDT 24
Finished Jun 04 02:20:02 PM PDT 24
Peak memory 206268 kb
Host smart-cd470454-8991-4b1d-8a42-b2c5cff99f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363585686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.363585686
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.244631273
Short name T796
Test name
Test status
Simulation time 861200353169 ps
CPU time 326.25 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:25:33 PM PDT 24
Peak memory 248940 kb
Host smart-4891d036-a0c9-4991-9fec-f20acae3d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244631273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.244631273
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.865271849
Short name T773
Test name
Test status
Simulation time 158786797913 ps
CPU time 122.15 seconds
Started Jun 04 02:20:04 PM PDT 24
Finished Jun 04 02:22:07 PM PDT 24
Peak memory 239044 kb
Host smart-00e61e59-36ba-4efb-8f70-bb0162233ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865271849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.865271849
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.503382269
Short name T627
Test name
Test status
Simulation time 189122729 ps
CPU time 5.49 seconds
Started Jun 04 02:20:07 PM PDT 24
Finished Jun 04 02:20:14 PM PDT 24
Peak memory 224116 kb
Host smart-8308e094-de40-4158-931a-3bbb2e59e673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503382269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.503382269
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1216804055
Short name T550
Test name
Test status
Simulation time 747192110 ps
CPU time 9.8 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:16 PM PDT 24
Peak memory 236000 kb
Host smart-b024759f-fe99-4663-90de-5777b5fc3c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216804055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1216804055
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.119405239
Short name T887
Test name
Test status
Simulation time 72776496592 ps
CPU time 147.96 seconds
Started Jun 04 02:20:04 PM PDT 24
Finished Jun 04 02:22:33 PM PDT 24
Peak memory 248180 kb
Host smart-0eef3db7-a3c7-480c-9029-167aeeed0623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119405239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.119405239
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1880467687
Short name T870
Test name
Test status
Simulation time 17680041 ps
CPU time 1.03 seconds
Started Jun 04 02:20:06 PM PDT 24
Finished Jun 04 02:20:08 PM PDT 24
Peak memory 217448 kb
Host smart-56f81a28-171e-437b-8ad2-f0d5445c7218
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880467687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1880467687
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4111030460
Short name T970
Test name
Test status
Simulation time 4492966136 ps
CPU time 11.98 seconds
Started Jun 04 02:20:04 PM PDT 24
Finished Jun 04 02:20:17 PM PDT 24
Peak memory 224208 kb
Host smart-14b24cc3-b5de-4bca-8fe0-c562f984f13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111030460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4111030460
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1552761753
Short name T956
Test name
Test status
Simulation time 1404477043 ps
CPU time 6.73 seconds
Started Jun 04 02:20:08 PM PDT 24
Finished Jun 04 02:20:15 PM PDT 24
Peak memory 227380 kb
Host smart-0ea3ddd0-d872-4f4f-bbda-c52efe753448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552761753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1552761753
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1372984113
Short name T702
Test name
Test status
Simulation time 3505664693 ps
CPU time 11.41 seconds
Started Jun 04 02:20:03 PM PDT 24
Finished Jun 04 02:20:16 PM PDT 24
Peak memory 218560 kb
Host smart-13224a5a-3095-42ad-bc8b-b533047e2227
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1372984113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1372984113
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3695284563
Short name T915
Test name
Test status
Simulation time 293041367303 ps
CPU time 346.56 seconds
Started Jun 04 02:20:04 PM PDT 24
Finished Jun 04 02:25:52 PM PDT 24
Peak memory 270252 kb
Host smart-1f3d737c-0153-4355-b310-c0361f7f6049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695284563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3695284563
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2357566924
Short name T320
Test name
Test status
Simulation time 2040744646 ps
CPU time 3.97 seconds
Started Jun 04 02:20:03 PM PDT 24
Finished Jun 04 02:20:08 PM PDT 24
Peak memory 215960 kb
Host smart-5016c739-c1dc-4340-bdda-dc5486e17118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357566924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2357566924
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3714492811
Short name T943
Test name
Test status
Simulation time 36078742 ps
CPU time 0.93 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:08 PM PDT 24
Peak memory 206360 kb
Host smart-22fd14fc-06ea-44c6-b490-baad748ae7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714492811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3714492811
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3559128854
Short name T589
Test name
Test status
Simulation time 25562217 ps
CPU time 0.71 seconds
Started Jun 04 02:20:04 PM PDT 24
Finished Jun 04 02:20:06 PM PDT 24
Peak memory 205272 kb
Host smart-b5f30f6c-c5b3-4b32-b920-3dd1f356d925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559128854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3559128854
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1025529945
Short name T823
Test name
Test status
Simulation time 8405667376 ps
CPU time 8.3 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:14 PM PDT 24
Peak memory 218688 kb
Host smart-39e68767-7144-4e43-a8bd-64d2f3cca8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025529945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1025529945
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.225301389
Short name T511
Test name
Test status
Simulation time 55242837 ps
CPU time 0.73 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:14 PM PDT 24
Peak memory 204908 kb
Host smart-36fad965-ac4d-4416-9cc6-1bbc46d26f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225301389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.225301389
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3008973588
Short name T528
Test name
Test status
Simulation time 123277373 ps
CPU time 2.52 seconds
Started Jun 04 02:20:07 PM PDT 24
Finished Jun 04 02:20:11 PM PDT 24
Peak memory 233880 kb
Host smart-b8f22cbe-7ec0-474b-b4fc-b478596bc312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008973588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3008973588
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3597751001
Short name T578
Test name
Test status
Simulation time 31401813 ps
CPU time 0.73 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:07 PM PDT 24
Peak memory 205244 kb
Host smart-f63294fd-ab29-4861-8d81-05b7b538d566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597751001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3597751001
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.502319901
Short name T867
Test name
Test status
Simulation time 4511780636 ps
CPU time 94.06 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:21:47 PM PDT 24
Peak memory 272216 kb
Host smart-8f761327-2620-49db-95cd-15ba484ef216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502319901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.502319901
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4230666505
Short name T319
Test name
Test status
Simulation time 4553309892 ps
CPU time 33.85 seconds
Started Jun 04 02:20:12 PM PDT 24
Finished Jun 04 02:20:47 PM PDT 24
Peak memory 224300 kb
Host smart-8759b55f-3aba-4ff6-a085-9d0134f62e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230666505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4230666505
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2116522413
Short name T561
Test name
Test status
Simulation time 9622743080 ps
CPU time 30.43 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:43 PM PDT 24
Peak memory 240688 kb
Host smart-c120216a-0f1b-4835-bc2b-78d553ca8b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116522413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2116522413
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3074685303
Short name T567
Test name
Test status
Simulation time 1351298975 ps
CPU time 13.49 seconds
Started Jun 04 02:20:10 PM PDT 24
Finished Jun 04 02:20:25 PM PDT 24
Peak memory 250224 kb
Host smart-118cee70-fd06-4f1e-b1e6-0d0a32f1fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074685303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3074685303
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.879621712
Short name T907
Test name
Test status
Simulation time 19763697518 ps
CPU time 15.49 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:22 PM PDT 24
Peak memory 233308 kb
Host smart-c4328485-1caf-41b8-802e-f50545c1f219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879621712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.879621712
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.973463339
Short name T787
Test name
Test status
Simulation time 1305158976 ps
CPU time 8.89 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:15 PM PDT 24
Peak memory 237736 kb
Host smart-f0990ba3-7388-47a2-87d3-78c877476203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973463339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.973463339
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1214766789
Short name T27
Test name
Test status
Simulation time 89627368 ps
CPU time 1.01 seconds
Started Jun 04 02:20:01 PM PDT 24
Finished Jun 04 02:20:03 PM PDT 24
Peak memory 217380 kb
Host smart-a309152c-d61f-44ca-ae84-750f2130d187
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214766789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1214766789
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3893410658
Short name T940
Test name
Test status
Simulation time 363813507 ps
CPU time 2.85 seconds
Started Jun 04 02:20:02 PM PDT 24
Finished Jun 04 02:20:05 PM PDT 24
Peak memory 233300 kb
Host smart-26434ec8-53bf-4c49-8696-20e9fdf90c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893410658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3893410658
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3683252332
Short name T403
Test name
Test status
Simulation time 2289289877 ps
CPU time 14.53 seconds
Started Jun 04 02:20:10 PM PDT 24
Finished Jun 04 02:20:26 PM PDT 24
Peak memory 221092 kb
Host smart-bb27da69-a0d1-42dd-a991-f6d2d1c73190
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3683252332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3683252332
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2584725175
Short name T626
Test name
Test status
Simulation time 3186104713 ps
CPU time 24.44 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:31 PM PDT 24
Peak memory 216052 kb
Host smart-220e5457-9f62-4e5e-9004-cb2f008fc147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584725175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2584725175
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1874675868
Short name T348
Test name
Test status
Simulation time 285063529 ps
CPU time 2.56 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:09 PM PDT 24
Peak memory 215812 kb
Host smart-e82ffaf1-cf51-4a65-b654-da333456ef3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874675868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1874675868
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1147946796
Short name T459
Test name
Test status
Simulation time 953258256 ps
CPU time 4.15 seconds
Started Jun 04 02:20:06 PM PDT 24
Finished Jun 04 02:20:11 PM PDT 24
Peak memory 215960 kb
Host smart-c952eed8-9b6d-46a5-bfca-24e79701f48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147946796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1147946796
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.500275078
Short name T72
Test name
Test status
Simulation time 32318627 ps
CPU time 0.84 seconds
Started Jun 04 02:20:05 PM PDT 24
Finished Jun 04 02:20:08 PM PDT 24
Peak memory 206320 kb
Host smart-ed377d35-a2cf-4228-ab67-edc29b58cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500275078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.500275078
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3743197178
Short name T624
Test name
Test status
Simulation time 132382065 ps
CPU time 2.54 seconds
Started Jun 04 02:20:06 PM PDT 24
Finished Jun 04 02:20:10 PM PDT 24
Peak memory 217060 kb
Host smart-05dcf2e2-4256-4df6-a8e6-e9d8137c44c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743197178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3743197178
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.804700586
Short name T771
Test name
Test status
Simulation time 19780945 ps
CPU time 0.72 seconds
Started Jun 04 02:20:20 PM PDT 24
Finished Jun 04 02:20:22 PM PDT 24
Peak memory 204896 kb
Host smart-29889eb4-4588-4bc4-aca1-759cea775fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804700586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.804700586
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4220892826
Short name T638
Test name
Test status
Simulation time 699900655 ps
CPU time 5.2 seconds
Started Jun 04 02:20:12 PM PDT 24
Finished Jun 04 02:20:19 PM PDT 24
Peak memory 219356 kb
Host smart-2a83339c-04f0-4a6b-9692-e82c28fd3884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220892826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4220892826
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2529178382
Short name T652
Test name
Test status
Simulation time 16260992 ps
CPU time 0.79 seconds
Started Jun 04 02:20:13 PM PDT 24
Finished Jun 04 02:20:15 PM PDT 24
Peak memory 204896 kb
Host smart-50dc3e31-bbf8-42df-bd3b-ea221c217ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529178382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2529178382
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.112986103
Short name T636
Test name
Test status
Simulation time 8956012446 ps
CPU time 21.74 seconds
Started Jun 04 02:20:13 PM PDT 24
Finished Jun 04 02:20:36 PM PDT 24
Peak memory 234492 kb
Host smart-b2619f73-5bca-4892-a6d0-b9185a8398d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112986103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.112986103
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2939040696
Short name T247
Test name
Test status
Simulation time 249143899623 ps
CPU time 423.66 seconds
Started Jun 04 02:20:09 PM PDT 24
Finished Jun 04 02:27:14 PM PDT 24
Peak memory 253720 kb
Host smart-cd5141bd-7ad1-4e28-9ec8-624c5dae6293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939040696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2939040696
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4119072995
Short name T742
Test name
Test status
Simulation time 4470082504 ps
CPU time 43.55 seconds
Started Jun 04 02:20:10 PM PDT 24
Finished Jun 04 02:20:54 PM PDT 24
Peak memory 248852 kb
Host smart-84d7efcc-6f38-4d18-ac3b-650a8999f650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119072995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4119072995
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2501339589
Short name T905
Test name
Test status
Simulation time 2877247903 ps
CPU time 12.99 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:26 PM PDT 24
Peak memory 224252 kb
Host smart-eed8964c-f7a0-43e1-98a3-383dc5b1b6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501339589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2501339589
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2518760324
Short name T682
Test name
Test status
Simulation time 266699067 ps
CPU time 2.62 seconds
Started Jun 04 02:20:10 PM PDT 24
Finished Jun 04 02:20:14 PM PDT 24
Peak memory 218052 kb
Host smart-4d6f9386-0076-4067-b54e-da2339bbe5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518760324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2518760324
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1336310423
Short name T689
Test name
Test status
Simulation time 228120991 ps
CPU time 3.57 seconds
Started Jun 04 02:20:10 PM PDT 24
Finished Jun 04 02:20:14 PM PDT 24
Peak memory 224132 kb
Host smart-4a006436-5bc0-4180-b133-d764334f4ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336310423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1336310423
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.4194489903
Short name T499
Test name
Test status
Simulation time 16745322 ps
CPU time 0.97 seconds
Started Jun 04 02:20:10 PM PDT 24
Finished Jun 04 02:20:11 PM PDT 24
Peak memory 217432 kb
Host smart-916f25ed-9a9e-4051-b007-a8d5ee35412a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194489903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.4194489903
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2790478218
Short name T189
Test name
Test status
Simulation time 160016172 ps
CPU time 2.79 seconds
Started Jun 04 02:20:13 PM PDT 24
Finished Jun 04 02:20:17 PM PDT 24
Peak memory 218200 kb
Host smart-cc3d7682-34df-4c1a-83f2-e6851b9c1a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790478218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2790478218
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2108077050
Short name T541
Test name
Test status
Simulation time 12275044669 ps
CPU time 6.1 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:18 PM PDT 24
Peak memory 233808 kb
Host smart-7b9d7e67-3dc2-47a8-8fae-65f6f55f71d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108077050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2108077050
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4016277823
Short name T143
Test name
Test status
Simulation time 208093694 ps
CPU time 3.84 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:16 PM PDT 24
Peak memory 218848 kb
Host smart-807f6b3c-d956-4bae-8f7f-0cc7116f093f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4016277823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4016277823
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3826394491
Short name T30
Test name
Test status
Simulation time 1723585374 ps
CPU time 3.09 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:16 PM PDT 24
Peak memory 215884 kb
Host smart-0be6ae72-0543-4396-9d9b-cacc12112f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826394491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3826394491
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2503944472
Short name T349
Test name
Test status
Simulation time 22317910313 ps
CPU time 6.21 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:19 PM PDT 24
Peak memory 215856 kb
Host smart-7d2d4f01-01c2-4bf3-b1e3-6b676bd63407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503944472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2503944472
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3448214095
Short name T835
Test name
Test status
Simulation time 317235928 ps
CPU time 2.43 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:15 PM PDT 24
Peak memory 215976 kb
Host smart-0584a7be-efed-4a74-b5a0-958f9ff267ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448214095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3448214095
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4115886407
Short name T20
Test name
Test status
Simulation time 27826144 ps
CPU time 0.74 seconds
Started Jun 04 02:20:11 PM PDT 24
Finished Jun 04 02:20:12 PM PDT 24
Peak memory 205252 kb
Host smart-86ba929c-a38a-4cc1-a99b-afdc181e7d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115886407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4115886407
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2060362375
Short name T799
Test name
Test status
Simulation time 3949802341 ps
CPU time 17.31 seconds
Started Jun 04 02:20:13 PM PDT 24
Finished Jun 04 02:20:31 PM PDT 24
Peak memory 236336 kb
Host smart-fb263e05-fd67-43a8-ad18-e582ba72a390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060362375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2060362375
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1283529354
Short name T830
Test name
Test status
Simulation time 1711348173 ps
CPU time 4.9 seconds
Started Jun 04 02:20:18 PM PDT 24
Finished Jun 04 02:20:24 PM PDT 24
Peak memory 234208 kb
Host smart-abb1edd2-eb67-461c-b899-039453e34b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283529354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1283529354
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1999177532
Short name T504
Test name
Test status
Simulation time 53578256 ps
CPU time 0.81 seconds
Started Jun 04 02:20:19 PM PDT 24
Finished Jun 04 02:20:21 PM PDT 24
Peak memory 205916 kb
Host smart-63647fa7-7532-46ca-af99-cc92d6f2cfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999177532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1999177532
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1810109772
Short name T181
Test name
Test status
Simulation time 7955930730 ps
CPU time 62.73 seconds
Started Jun 04 02:20:20 PM PDT 24
Finished Jun 04 02:21:24 PM PDT 24
Peak memory 248820 kb
Host smart-df4643a0-0f36-48eb-afaa-d32e4eb94fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810109772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1810109772
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1217861447
Short name T722
Test name
Test status
Simulation time 7979682299 ps
CPU time 126.24 seconds
Started Jun 04 02:20:29 PM PDT 24
Finished Jun 04 02:22:36 PM PDT 24
Peak memory 257016 kb
Host smart-b5a3009c-12b6-4f6a-b6fa-674f0c2920aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217861447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1217861447
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.395837646
Short name T666
Test name
Test status
Simulation time 25280561996 ps
CPU time 83.73 seconds
Started Jun 04 02:20:27 PM PDT 24
Finished Jun 04 02:21:52 PM PDT 24
Peak memory 257060 kb
Host smart-a57d4b3d-c592-4889-a617-c5fea5cf819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395837646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.395837646
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2428229506
Short name T148
Test name
Test status
Simulation time 2234986636 ps
CPU time 9.06 seconds
Started Jun 04 02:20:21 PM PDT 24
Finished Jun 04 02:20:31 PM PDT 24
Peak memory 232464 kb
Host smart-1a1eefb3-85cc-4918-abb8-488c46562a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428229506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2428229506
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3410761735
Short name T883
Test name
Test status
Simulation time 1191894589 ps
CPU time 11.27 seconds
Started Jun 04 02:20:19 PM PDT 24
Finished Jun 04 02:20:32 PM PDT 24
Peak memory 233840 kb
Host smart-2efcad15-b797-4564-827f-e0e117068859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410761735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3410761735
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.455735072
Short name T898
Test name
Test status
Simulation time 823792268 ps
CPU time 3.84 seconds
Started Jun 04 02:20:21 PM PDT 24
Finished Jun 04 02:20:26 PM PDT 24
Peak memory 234004 kb
Host smart-1e7c7347-8d1e-4f19-844a-b383b21113d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455735072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.455735072
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3914847252
Short name T963
Test name
Test status
Simulation time 33714386 ps
CPU time 1.11 seconds
Started Jun 04 02:20:18 PM PDT 24
Finished Jun 04 02:20:21 PM PDT 24
Peak memory 216192 kb
Host smart-9e36a998-2106-4ca1-83df-366f8cff2490
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914847252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3914847252
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1703118628
Short name T437
Test name
Test status
Simulation time 31426633991 ps
CPU time 15.18 seconds
Started Jun 04 02:20:19 PM PDT 24
Finished Jun 04 02:20:36 PM PDT 24
Peak memory 233420 kb
Host smart-380e27e3-3c43-483c-b313-6bf509720a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703118628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1703118628
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2290635850
Short name T190
Test name
Test status
Simulation time 13748547600 ps
CPU time 28.45 seconds
Started Jun 04 02:20:19 PM PDT 24
Finished Jun 04 02:20:49 PM PDT 24
Peak memory 232728 kb
Host smart-ad79acf2-a2a8-45a9-af41-11c88b4f26e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290635850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2290635850
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1094062154
Short name T834
Test name
Test status
Simulation time 5269353217 ps
CPU time 20.74 seconds
Started Jun 04 02:20:20 PM PDT 24
Finished Jun 04 02:20:43 PM PDT 24
Peak memory 222624 kb
Host smart-0a229974-9de9-4601-9620-1ba7fb73dc0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1094062154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1094062154
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.835796757
Short name T744
Test name
Test status
Simulation time 27374301090 ps
CPU time 32.68 seconds
Started Jun 04 02:20:29 PM PDT 24
Finished Jun 04 02:21:02 PM PDT 24
Peak memory 224260 kb
Host smart-aa69d02d-4f60-4978-be07-d5558664b212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835796757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.835796757
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2360444361
Short name T726
Test name
Test status
Simulation time 10376527649 ps
CPU time 49.65 seconds
Started Jun 04 02:20:21 PM PDT 24
Finished Jun 04 02:21:12 PM PDT 24
Peak memory 216024 kb
Host smart-a007c25b-cc25-43e6-a501-7cfc181fa39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360444361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2360444361
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.181664722
Short name T328
Test name
Test status
Simulation time 4699855909 ps
CPU time 13.39 seconds
Started Jun 04 02:20:19 PM PDT 24
Finished Jun 04 02:20:34 PM PDT 24
Peak memory 215864 kb
Host smart-ea8122f4-a3e6-45af-9aab-4c2cf9c6a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181664722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.181664722
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1683910287
Short name T352
Test name
Test status
Simulation time 29032000 ps
CPU time 1.71 seconds
Started Jun 04 02:20:19 PM PDT 24
Finished Jun 04 02:20:22 PM PDT 24
Peak memory 207708 kb
Host smart-048a91e8-03a7-46b4-8c88-bd8029c0fa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683910287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1683910287
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2408233622
Short name T716
Test name
Test status
Simulation time 120720220 ps
CPU time 0.68 seconds
Started Jun 04 02:20:21 PM PDT 24
Finished Jun 04 02:20:23 PM PDT 24
Peak memory 204956 kb
Host smart-cb0266d8-5c0f-402d-b6be-73e42969a45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408233622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2408233622
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3623423837
Short name T719
Test name
Test status
Simulation time 2491166905 ps
CPU time 4.74 seconds
Started Jun 04 02:20:18 PM PDT 24
Finished Jun 04 02:20:24 PM PDT 24
Peak memory 219812 kb
Host smart-34317d8a-3be4-4631-a213-f34bc7dfb6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623423837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3623423837
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3140981557
Short name T697
Test name
Test status
Simulation time 36391314 ps
CPU time 0.73 seconds
Started Jun 04 02:20:27 PM PDT 24
Finished Jun 04 02:20:29 PM PDT 24
Peak memory 204944 kb
Host smart-2a1a2925-590d-43a2-a2ff-627dd22a66d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140981557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3140981557
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2240553575
Short name T709
Test name
Test status
Simulation time 797160001 ps
CPU time 4.34 seconds
Started Jun 04 02:20:28 PM PDT 24
Finished Jun 04 02:20:33 PM PDT 24
Peak memory 233488 kb
Host smart-12257103-1150-4589-baa8-8f6ad38fc12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240553575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2240553575
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2192107238
Short name T790
Test name
Test status
Simulation time 204712812 ps
CPU time 0.77 seconds
Started Jun 04 02:20:29 PM PDT 24
Finished Jun 04 02:20:30 PM PDT 24
Peak memory 206256 kb
Host smart-38d352fd-3cd7-41b3-bb7e-5185bfa03f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192107238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2192107238
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2983159973
Short name T244
Test name
Test status
Simulation time 10577473727 ps
CPU time 172.65 seconds
Started Jun 04 02:20:28 PM PDT 24
Finished Jun 04 02:23:21 PM PDT 24
Peak memory 265124 kb
Host smart-caa7adad-43e0-4add-86c3-ef219676323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983159973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2983159973
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.45194390
Short name T454
Test name
Test status
Simulation time 5964055099 ps
CPU time 20.54 seconds
Started Jun 04 02:20:28 PM PDT 24
Finished Jun 04 02:20:50 PM PDT 24
Peak memory 216976 kb
Host smart-b5fe1d00-ad5f-4ee3-a5a5-5ecbd212afe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45194390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.45194390
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1434493673
Short name T613
Test name
Test status
Simulation time 184941883 ps
CPU time 5.23 seconds
Started Jun 04 02:20:30 PM PDT 24
Finished Jun 04 02:20:36 PM PDT 24
Peak memory 224092 kb
Host smart-67b3dd28-be1c-488d-9099-97bf2e9023ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434493673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1434493673
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.460042081
Short name T99
Test name
Test status
Simulation time 449416917 ps
CPU time 6.09 seconds
Started Jun 04 02:20:30 PM PDT 24
Finished Jun 04 02:20:37 PM PDT 24
Peak memory 237624 kb
Host smart-4ef51990-d491-4f7f-9495-60106a03b446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460042081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.460042081
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3110450422
Short name T306
Test name
Test status
Simulation time 1627804119 ps
CPU time 10.46 seconds
Started Jun 04 02:20:28 PM PDT 24
Finished Jun 04 02:20:40 PM PDT 24
Peak memory 232320 kb
Host smart-ba0e7240-1390-4ecf-bac9-7a65a1ac6fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110450422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3110450422
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1656390518
Short name T491
Test name
Test status
Simulation time 16256066 ps
CPU time 0.99 seconds
Started Jun 04 02:20:31 PM PDT 24
Finished Jun 04 02:20:32 PM PDT 24
Peak memory 216136 kb
Host smart-0422761a-a18f-48f3-902d-1e3f876d4189
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656390518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1656390518
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1543300354
Short name T259
Test name
Test status
Simulation time 296648931 ps
CPU time 4.98 seconds
Started Jun 04 02:20:28 PM PDT 24
Finished Jun 04 02:20:34 PM PDT 24
Peak memory 224164 kb
Host smart-dcfbd604-aa6c-40d0-a88a-6a9c170478b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543300354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1543300354
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1266344549
Short name T295
Test name
Test status
Simulation time 321199970 ps
CPU time 3.12 seconds
Started Jun 04 02:20:26 PM PDT 24
Finished Jun 04 02:20:30 PM PDT 24
Peak memory 218056 kb
Host smart-a4d9d20e-429c-4d24-abeb-c0253f4d0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266344549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1266344549
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1821515591
Short name T145
Test name
Test status
Simulation time 3589048321 ps
CPU time 8.86 seconds
Started Jun 04 02:20:30 PM PDT 24
Finished Jun 04 02:20:39 PM PDT 24
Peak memory 222488 kb
Host smart-304c8ded-6cfc-44da-b56e-ca8fb4cf035b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1821515591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1821515591
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.952537116
Short name T137
Test name
Test status
Simulation time 74612981515 ps
CPU time 352.73 seconds
Started Jun 04 02:20:27 PM PDT 24
Finished Jun 04 02:26:20 PM PDT 24
Peak memory 248860 kb
Host smart-7babd03b-4f0e-41e1-8678-c186bebef17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952537116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.952537116
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2757252596
Short name T513
Test name
Test status
Simulation time 2231298013 ps
CPU time 27.55 seconds
Started Jun 04 02:20:31 PM PDT 24
Finished Jun 04 02:20:59 PM PDT 24
Peak memory 215992 kb
Host smart-3639f7f9-abfe-4069-be27-920fa486d136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757252596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2757252596
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.841593474
Short name T917
Test name
Test status
Simulation time 982519342 ps
CPU time 3.01 seconds
Started Jun 04 02:20:25 PM PDT 24
Finished Jun 04 02:20:29 PM PDT 24
Peak memory 215844 kb
Host smart-392c44a7-c96a-4dee-b91a-bc77fd5f530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841593474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.841593474
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.476712071
Short name T359
Test name
Test status
Simulation time 234267702 ps
CPU time 3.2 seconds
Started Jun 04 02:20:26 PM PDT 24
Finished Jun 04 02:20:30 PM PDT 24
Peak memory 215940 kb
Host smart-d00d93a4-cd89-499f-8914-20e64303e9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476712071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.476712071
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.818404314
Short name T762
Test name
Test status
Simulation time 47365730 ps
CPU time 0.77 seconds
Started Jun 04 02:20:27 PM PDT 24
Finished Jun 04 02:20:29 PM PDT 24
Peak memory 205220 kb
Host smart-04e21f65-e4e2-432e-b00f-3f361566afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818404314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.818404314
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4178539006
Short name T906
Test name
Test status
Simulation time 1773177110 ps
CPU time 6.18 seconds
Started Jun 04 02:20:30 PM PDT 24
Finished Jun 04 02:20:37 PM PDT 24
Peak memory 225652 kb
Host smart-72353327-af36-4840-a30b-246934423c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178539006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4178539006
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1900893418
Short name T774
Test name
Test status
Simulation time 12327440 ps
CPU time 0.7 seconds
Started Jun 04 02:20:36 PM PDT 24
Finished Jun 04 02:20:37 PM PDT 24
Peak memory 204144 kb
Host smart-46872d84-9649-4b94-8162-c4084117d592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900893418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1900893418
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.337013491
Short name T558
Test name
Test status
Simulation time 308189769 ps
CPU time 2.65 seconds
Started Jun 04 02:20:37 PM PDT 24
Finished Jun 04 02:20:40 PM PDT 24
Peak memory 233476 kb
Host smart-da206f93-ed4f-4a2b-a3e6-f920cd27d8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337013491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.337013491
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2527498376
Short name T130
Test name
Test status
Simulation time 19806679 ps
CPU time 0.77 seconds
Started Jun 04 02:20:33 PM PDT 24
Finished Jun 04 02:20:35 PM PDT 24
Peak memory 205920 kb
Host smart-3e8a2b70-6b34-47d7-8bea-383feda700e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527498376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2527498376
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3068110506
Short name T231
Test name
Test status
Simulation time 7584583093 ps
CPU time 103.87 seconds
Started Jun 04 02:20:33 PM PDT 24
Finished Jun 04 02:22:17 PM PDT 24
Peak memory 250156 kb
Host smart-5397fb23-356a-4c58-9708-fda248c5d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068110506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3068110506
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3303658418
Short name T687
Test name
Test status
Simulation time 45833999936 ps
CPU time 82.6 seconds
Started Jun 04 02:20:33 PM PDT 24
Finished Jun 04 02:21:57 PM PDT 24
Peak memory 232500 kb
Host smart-5873dbfc-16f5-485f-b413-ad63ff52a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303658418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3303658418
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3826341340
Short name T612
Test name
Test status
Simulation time 210768579 ps
CPU time 4.22 seconds
Started Jun 04 02:20:33 PM PDT 24
Finished Jun 04 02:20:38 PM PDT 24
Peak memory 224204 kb
Host smart-4c040c17-a204-4688-b39e-9f99d6ba59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826341340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3826341340
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.294962902
Short name T90
Test name
Test status
Simulation time 96665974 ps
CPU time 3.74 seconds
Started Jun 04 02:20:37 PM PDT 24
Finished Jun 04 02:20:41 PM PDT 24
Peak memory 233120 kb
Host smart-74c2994a-5184-4265-af96-83d8b4ac6868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294962902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.294962902
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1251863500
Short name T279
Test name
Test status
Simulation time 9665767357 ps
CPU time 9.93 seconds
Started Jun 04 02:20:33 PM PDT 24
Finished Jun 04 02:20:43 PM PDT 24
Peak memory 220740 kb
Host smart-b7c3657c-ffe8-4948-a086-74556c83cab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251863500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1251863500
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4142023965
Short name T674
Test name
Test status
Simulation time 30439409 ps
CPU time 1.04 seconds
Started Jun 04 02:20:38 PM PDT 24
Finished Jun 04 02:20:39 PM PDT 24
Peak memory 217568 kb
Host smart-f3e47c03-97df-4c3e-b822-e022700cc079
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142023965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4142023965
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2023799432
Short name T224
Test name
Test status
Simulation time 1697560378 ps
CPU time 8.19 seconds
Started Jun 04 02:20:34 PM PDT 24
Finished Jun 04 02:20:43 PM PDT 24
Peak memory 238216 kb
Host smart-4c6410be-4e7b-4bc5-bb93-e1ffa38b2961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023799432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2023799432
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3439669440
Short name T293
Test name
Test status
Simulation time 74962626 ps
CPU time 2.47 seconds
Started Jun 04 02:20:34 PM PDT 24
Finished Jun 04 02:20:38 PM PDT 24
Peak memory 232844 kb
Host smart-48a42885-369e-496b-b127-7fc2200ec106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439669440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3439669440
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3238751911
Short name T699
Test name
Test status
Simulation time 1172017977 ps
CPU time 4.97 seconds
Started Jun 04 02:20:34 PM PDT 24
Finished Jun 04 02:20:40 PM PDT 24
Peak memory 218296 kb
Host smart-5d01e0fb-c24d-4e3e-84b5-4abab5446fd7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3238751911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3238751911
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2427833897
Short name T778
Test name
Test status
Simulation time 115933177838 ps
CPU time 445.42 seconds
Started Jun 04 02:20:35 PM PDT 24
Finished Jun 04 02:28:01 PM PDT 24
Peak memory 255516 kb
Host smart-fe514157-114f-4814-9e6f-0668b33e0237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427833897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2427833897
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2162898402
Short name T897
Test name
Test status
Simulation time 42034414 ps
CPU time 0.7 seconds
Started Jun 04 02:20:34 PM PDT 24
Finished Jun 04 02:20:35 PM PDT 24
Peak memory 205056 kb
Host smart-01e04bf9-8abf-4387-a44e-332fb95380e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162898402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2162898402
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.124752572
Short name T968
Test name
Test status
Simulation time 3630384085 ps
CPU time 10.43 seconds
Started Jun 04 02:20:34 PM PDT 24
Finished Jun 04 02:20:45 PM PDT 24
Peak memory 215940 kb
Host smart-3fdcbe68-dab4-4ae7-a09a-5940547c71fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124752572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.124752572
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3195049934
Short name T345
Test name
Test status
Simulation time 227640145 ps
CPU time 5.52 seconds
Started Jun 04 02:20:33 PM PDT 24
Finished Jun 04 02:20:40 PM PDT 24
Peak memory 215936 kb
Host smart-8feea7b7-1209-4b7c-89ad-11e354a5d4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195049934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3195049934
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3508244185
Short name T705
Test name
Test status
Simulation time 18479831 ps
CPU time 0.77 seconds
Started Jun 04 02:20:35 PM PDT 24
Finished Jun 04 02:20:37 PM PDT 24
Peak memory 205296 kb
Host smart-f061eb49-0ad0-468b-92ef-de2f40fdda50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508244185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3508244185
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2799600169
Short name T422
Test name
Test status
Simulation time 2452132436 ps
CPU time 4.95 seconds
Started Jun 04 02:20:34 PM PDT 24
Finished Jun 04 02:20:39 PM PDT 24
Peak memory 217804 kb
Host smart-9d5f3c72-0379-46d1-b4c9-269517211cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799600169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2799600169
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1257639594
Short name T949
Test name
Test status
Simulation time 28222731 ps
CPU time 0.68 seconds
Started Jun 04 02:18:59 PM PDT 24
Finished Jun 04 02:19:00 PM PDT 24
Peak memory 204912 kb
Host smart-66e2aec1-115d-4e7d-939c-45cf7f6ab0d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257639594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
257639594
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1386318947
Short name T58
Test name
Test status
Simulation time 1448953413 ps
CPU time 6.96 seconds
Started Jun 04 02:19:00 PM PDT 24
Finished Jun 04 02:19:08 PM PDT 24
Peak memory 219952 kb
Host smart-19153761-573b-4d5d-a0ad-7345354d8bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386318947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1386318947
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1922306647
Short name T644
Test name
Test status
Simulation time 68075636 ps
CPU time 0.82 seconds
Started Jun 04 02:18:50 PM PDT 24
Finished Jun 04 02:18:52 PM PDT 24
Peak memory 205932 kb
Host smart-a0f6e1ca-20e6-431b-bf20-a116c5cf6d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922306647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1922306647
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1276275284
Short name T653
Test name
Test status
Simulation time 253084921120 ps
CPU time 189.23 seconds
Started Jun 04 02:19:01 PM PDT 24
Finished Jun 04 02:22:11 PM PDT 24
Peak memory 238208 kb
Host smart-b0e377ae-fbfd-4ba2-8e9a-1b9456ac7020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276275284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1276275284
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2829229995
Short name T307
Test name
Test status
Simulation time 357658493 ps
CPU time 9.33 seconds
Started Jun 04 02:19:00 PM PDT 24
Finished Jun 04 02:19:11 PM PDT 24
Peak memory 224156 kb
Host smart-91a7a004-1ccf-4234-bb35-a3d54e30393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829229995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2829229995
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3590621140
Short name T187
Test name
Test status
Simulation time 3414063153 ps
CPU time 13.27 seconds
Started Jun 04 02:19:00 PM PDT 24
Finished Jun 04 02:19:14 PM PDT 24
Peak memory 233416 kb
Host smart-02e41063-ea9e-4dc5-8b6c-520761e924b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590621140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3590621140
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1035873618
Short name T344
Test name
Test status
Simulation time 7015199395 ps
CPU time 17.31 seconds
Started Jun 04 02:18:59 PM PDT 24
Finished Jun 04 02:19:17 PM PDT 24
Peak memory 239548 kb
Host smart-64803bdc-db76-4c06-83c2-03b2403dd807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035873618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1035873618
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1842108683
Short name T844
Test name
Test status
Simulation time 120213435 ps
CPU time 1.11 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:18:54 PM PDT 24
Peak memory 216196 kb
Host smart-381a7292-d6da-4ed2-8907-89b07743565c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842108683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1842108683
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1096584548
Short name T405
Test name
Test status
Simulation time 6386069002 ps
CPU time 16.09 seconds
Started Jun 04 02:19:00 PM PDT 24
Finished Jun 04 02:19:17 PM PDT 24
Peak memory 234584 kb
Host smart-27ded201-dfde-4c9f-b33b-7d8cb12f7a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096584548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1096584548
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3421595755
Short name T478
Test name
Test status
Simulation time 19600635048 ps
CPU time 29.41 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:19:22 PM PDT 24
Peak memory 248668 kb
Host smart-c61b3aeb-570e-4849-820e-e9561244d156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421595755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3421595755
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2752365464
Short name T452
Test name
Test status
Simulation time 1744512064 ps
CPU time 6.17 seconds
Started Jun 04 02:18:59 PM PDT 24
Finished Jun 04 02:19:06 PM PDT 24
Peak memory 222536 kb
Host smart-d57f3e79-3c41-4206-9924-85a92e2c3209
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2752365464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2752365464
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.287328182
Short name T781
Test name
Test status
Simulation time 277156643 ps
CPU time 1.11 seconds
Started Jun 04 02:19:00 PM PDT 24
Finished Jun 04 02:19:02 PM PDT 24
Peak memory 214732 kb
Host smart-4a89dae7-ac0b-4480-bdce-529e9215845e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287328182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.287328182
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3036369734
Short name T317
Test name
Test status
Simulation time 7504003409 ps
CPU time 34.71 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:19:27 PM PDT 24
Peak memory 215908 kb
Host smart-d4c12bf1-5b73-42bb-ae59-1d76120d6727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036369734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3036369734
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.115390324
Short name T446
Test name
Test status
Simulation time 19601248 ps
CPU time 0.72 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:18:53 PM PDT 24
Peak memory 205016 kb
Host smart-7ed0a20b-205d-417a-8083-e84b0dae9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115390324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.115390324
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2348062205
Short name T321
Test name
Test status
Simulation time 633943942 ps
CPU time 3.08 seconds
Started Jun 04 02:18:52 PM PDT 24
Finished Jun 04 02:18:56 PM PDT 24
Peak memory 215848 kb
Host smart-1b8246f5-0509-4e42-aff8-c8e17183e1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348062205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2348062205
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3876684498
Short name T410
Test name
Test status
Simulation time 136255599 ps
CPU time 0.92 seconds
Started Jun 04 02:18:51 PM PDT 24
Finished Jun 04 02:18:52 PM PDT 24
Peak memory 206372 kb
Host smart-12e1a8e2-cccd-4416-8bf6-0d8fb4a980ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876684498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3876684498
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2492850936
Short name T60
Test name
Test status
Simulation time 12599575564 ps
CPU time 14.04 seconds
Started Jun 04 02:19:00 PM PDT 24
Finished Jun 04 02:19:15 PM PDT 24
Peak memory 235792 kb
Host smart-b6767624-05f2-41c5-a1de-b06509a08d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492850936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2492850936
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3338980319
Short name T442
Test name
Test status
Simulation time 23084872 ps
CPU time 0.74 seconds
Started Jun 04 02:20:44 PM PDT 24
Finished Jun 04 02:20:45 PM PDT 24
Peak memory 204900 kb
Host smart-3d95c9d0-1bb7-4f54-975a-ceadf916d3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338980319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3338980319
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1492972946
Short name T361
Test name
Test status
Simulation time 796076220 ps
CPU time 3.15 seconds
Started Jun 04 02:20:42 PM PDT 24
Finished Jun 04 02:20:46 PM PDT 24
Peak memory 218532 kb
Host smart-33284938-c2ff-431d-a93e-e4793dee7526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492972946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1492972946
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1659632172
Short name T15
Test name
Test status
Simulation time 59883263 ps
CPU time 0.8 seconds
Started Jun 04 02:20:35 PM PDT 24
Finished Jun 04 02:20:36 PM PDT 24
Peak memory 205884 kb
Host smart-e1969897-4669-4df3-9103-79f9a6d43cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659632172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1659632172
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2591476725
Short name T179
Test name
Test status
Simulation time 210435417551 ps
CPU time 384.74 seconds
Started Jun 04 02:20:40 PM PDT 24
Finished Jun 04 02:27:05 PM PDT 24
Peak memory 250580 kb
Host smart-b909337d-1f86-4106-afda-a9b221ef4b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591476725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2591476725
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.794775213
Short name T676
Test name
Test status
Simulation time 2787802907 ps
CPU time 10.29 seconds
Started Jun 04 02:20:43 PM PDT 24
Finished Jun 04 02:20:54 PM PDT 24
Peak memory 217016 kb
Host smart-c2519306-16cb-4479-9e85-334ad4dc9228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794775213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.794775213
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1493665019
Short name T201
Test name
Test status
Simulation time 58651774431 ps
CPU time 259.77 seconds
Started Jun 04 02:20:41 PM PDT 24
Finished Jun 04 02:25:02 PM PDT 24
Peak memory 240716 kb
Host smart-b4025c05-b9a7-4d0b-b75d-c6d8c88d6dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493665019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1493665019
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1971785236
Short name T439
Test name
Test status
Simulation time 2238257190 ps
CPU time 7.45 seconds
Started Jun 04 02:20:40 PM PDT 24
Finished Jun 04 02:20:48 PM PDT 24
Peak memory 219368 kb
Host smart-cae93d4a-ee19-4ade-bcf6-99fab7c61b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971785236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1971785236
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.762678757
Short name T860
Test name
Test status
Simulation time 1931587025 ps
CPU time 13.54 seconds
Started Jun 04 02:20:43 PM PDT 24
Finished Jun 04 02:20:58 PM PDT 24
Peak memory 232084 kb
Host smart-bce4bfea-9874-4ac7-a262-2ccde9fc11f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762678757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.762678757
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4286042969
Short name T383
Test name
Test status
Simulation time 107090091 ps
CPU time 2.35 seconds
Started Jun 04 02:20:41 PM PDT 24
Finished Jun 04 02:20:44 PM PDT 24
Peak memory 215736 kb
Host smart-55ccbd86-f83a-4273-ab64-fbdfb5cb9d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286042969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4286042969
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4149343899
Short name T928
Test name
Test status
Simulation time 4915347122 ps
CPU time 13.34 seconds
Started Jun 04 02:20:42 PM PDT 24
Finished Jun 04 02:20:55 PM PDT 24
Peak memory 222784 kb
Host smart-0b2401f4-b2dc-47b9-a179-9cee747ab675
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149343899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4149343899
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.127598035
Short name T904
Test name
Test status
Simulation time 80924671 ps
CPU time 0.91 seconds
Started Jun 04 02:20:41 PM PDT 24
Finished Jun 04 02:20:42 PM PDT 24
Peak memory 206336 kb
Host smart-6e7cda5b-ff8d-420a-bb7f-cc293856b3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127598035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.127598035
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2541921311
Short name T836
Test name
Test status
Simulation time 1849220327 ps
CPU time 23.44 seconds
Started Jun 04 02:20:33 PM PDT 24
Finished Jun 04 02:20:57 PM PDT 24
Peak memory 219032 kb
Host smart-4c6d51cb-0487-49b0-bf98-c991edee6ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541921311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2541921311
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.884571727
Short name T878
Test name
Test status
Simulation time 704149428 ps
CPU time 4.12 seconds
Started Jun 04 02:20:34 PM PDT 24
Finished Jun 04 02:20:39 PM PDT 24
Peak memory 215828 kb
Host smart-eceed234-4b6f-4a60-825f-d14a0bb92a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884571727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.884571727
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3413092362
Short name T372
Test name
Test status
Simulation time 341553307 ps
CPU time 1.64 seconds
Started Jun 04 02:20:41 PM PDT 24
Finished Jun 04 02:20:43 PM PDT 24
Peak memory 215896 kb
Host smart-0455d76d-d917-44c9-934f-fb22eac29a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413092362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3413092362
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4150628522
Short name T379
Test name
Test status
Simulation time 15090752 ps
CPU time 0.72 seconds
Started Jun 04 02:20:43 PM PDT 24
Finished Jun 04 02:20:44 PM PDT 24
Peak memory 205288 kb
Host smart-1aacaddf-1c13-4747-b6e5-d06bb34fbd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150628522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4150628522
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.812231760
Short name T794
Test name
Test status
Simulation time 35380986 ps
CPU time 2.38 seconds
Started Jun 04 02:20:45 PM PDT 24
Finished Jun 04 02:20:48 PM PDT 24
Peak memory 212656 kb
Host smart-3a1881ee-db66-4856-a4ed-ab69744bf041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812231760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.812231760
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2496915852
Short name T535
Test name
Test status
Simulation time 13316961 ps
CPU time 0.74 seconds
Started Jun 04 02:20:50 PM PDT 24
Finished Jun 04 02:20:51 PM PDT 24
Peak memory 205212 kb
Host smart-8f4a6ed6-a3a1-4e94-b3ac-e2bac602e96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496915852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2496915852
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1742595672
Short name T365
Test name
Test status
Simulation time 512483725 ps
CPU time 5.37 seconds
Started Jun 04 02:20:47 PM PDT 24
Finished Jun 04 02:20:53 PM PDT 24
Peak memory 233656 kb
Host smart-49218fd4-9f57-4ad5-93e2-02a44720117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742595672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1742595672
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3308567376
Short name T619
Test name
Test status
Simulation time 51440856 ps
CPU time 0.78 seconds
Started Jun 04 02:20:41 PM PDT 24
Finished Jun 04 02:20:43 PM PDT 24
Peak memory 205216 kb
Host smart-877d7399-bf69-40a5-b843-53d3c125918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308567376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3308567376
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.766758312
Short name T170
Test name
Test status
Simulation time 26958796535 ps
CPU time 192.16 seconds
Started Jun 04 02:20:47 PM PDT 24
Finished Jun 04 02:24:00 PM PDT 24
Peak memory 248836 kb
Host smart-608d1576-074a-44ea-853c-bd6bf09bedb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766758312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.766758312
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.687593745
Short name T893
Test name
Test status
Simulation time 26679103067 ps
CPU time 57.82 seconds
Started Jun 04 02:20:50 PM PDT 24
Finished Jun 04 02:21:48 PM PDT 24
Peak memory 248964 kb
Host smart-4c1239a2-ac09-4294-bf8a-c8012d36b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687593745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.687593745
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.520822566
Short name T933
Test name
Test status
Simulation time 3058006417 ps
CPU time 9.38 seconds
Started Jun 04 02:20:47 PM PDT 24
Finished Jun 04 02:20:58 PM PDT 24
Peak memory 217004 kb
Host smart-5a1b1779-1353-445c-b639-f2db12b22828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520822566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.520822566
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2995789879
Short name T483
Test name
Test status
Simulation time 1045921313 ps
CPU time 7.16 seconds
Started Jun 04 02:20:53 PM PDT 24
Finished Jun 04 02:21:01 PM PDT 24
Peak memory 232404 kb
Host smart-fca69d06-36b7-45d1-b165-d9caab5cfeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995789879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2995789879
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.295945952
Short name T205
Test name
Test status
Simulation time 18244935703 ps
CPU time 118.63 seconds
Started Jun 04 02:20:47 PM PDT 24
Finished Jun 04 02:22:46 PM PDT 24
Peak memory 235240 kb
Host smart-d1d54468-5fe0-48c5-a861-1c1883c67549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295945952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.295945952
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3921290268
Short name T480
Test name
Test status
Simulation time 5022858785 ps
CPU time 15.34 seconds
Started Jun 04 02:20:40 PM PDT 24
Finished Jun 04 02:20:56 PM PDT 24
Peak memory 233440 kb
Host smart-f3365bf1-c949-4c8a-abac-7c1ebd763f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921290268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3921290268
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3596897573
Short name T373
Test name
Test status
Simulation time 70005374 ps
CPU time 2.57 seconds
Started Jun 04 02:20:42 PM PDT 24
Finished Jun 04 02:20:46 PM PDT 24
Peak memory 232388 kb
Host smart-74320aa4-59cc-47df-a62f-13e29de91b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596897573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3596897573
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3909801410
Short name T880
Test name
Test status
Simulation time 1041311304 ps
CPU time 7.57 seconds
Started Jun 04 02:20:49 PM PDT 24
Finished Jun 04 02:20:58 PM PDT 24
Peak memory 218480 kb
Host smart-6180b2ae-1276-456a-80a1-25f81fa614ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3909801410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3909801410
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3659285289
Short name T262
Test name
Test status
Simulation time 131619799671 ps
CPU time 366.99 seconds
Started Jun 04 02:20:49 PM PDT 24
Finished Jun 04 02:26:57 PM PDT 24
Peak memory 265360 kb
Host smart-f400fb74-0d93-420f-90ef-d167604d687b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659285289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3659285289
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2220219217
Short name T909
Test name
Test status
Simulation time 4422382161 ps
CPU time 35.54 seconds
Started Jun 04 02:20:44 PM PDT 24
Finished Jun 04 02:21:20 PM PDT 24
Peak memory 215896 kb
Host smart-293ead1f-0c47-4f6c-ace1-4741dadfa578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220219217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2220219217
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.609916775
Short name T129
Test name
Test status
Simulation time 583381438 ps
CPU time 2.71 seconds
Started Jun 04 02:20:44 PM PDT 24
Finished Jun 04 02:20:47 PM PDT 24
Peak memory 215808 kb
Host smart-37bdfe48-0fd9-4c87-8040-062dee6acb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609916775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.609916775
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2098828501
Short name T672
Test name
Test status
Simulation time 51326269 ps
CPU time 1.22 seconds
Started Jun 04 02:20:43 PM PDT 24
Finished Jun 04 02:20:46 PM PDT 24
Peak memory 207496 kb
Host smart-869971c5-7271-4c63-ae68-30ffbc4e1159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098828501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2098828501
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3605299379
Short name T736
Test name
Test status
Simulation time 41699358 ps
CPU time 0.79 seconds
Started Jun 04 02:20:40 PM PDT 24
Finished Jun 04 02:20:42 PM PDT 24
Peak memory 205292 kb
Host smart-22040f09-98f6-4d2f-a12b-8d4a35c767af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605299379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3605299379
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.802836354
Short name T919
Test name
Test status
Simulation time 8677405311 ps
CPU time 17.84 seconds
Started Jun 04 02:20:49 PM PDT 24
Finished Jun 04 02:21:08 PM PDT 24
Peak memory 235528 kb
Host smart-1a390474-fa68-4e4b-92d5-41828a436ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802836354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.802836354
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2608072841
Short name T622
Test name
Test status
Simulation time 14578711 ps
CPU time 0.7 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:20:56 PM PDT 24
Peak memory 204288 kb
Host smart-6b2db310-1ecc-4ec4-b79c-55a8662953c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608072841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2608072841
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2472008298
Short name T451
Test name
Test status
Simulation time 230247301 ps
CPU time 2.8 seconds
Started Jun 04 02:20:49 PM PDT 24
Finished Jun 04 02:20:53 PM PDT 24
Peak memory 218360 kb
Host smart-6c4cadfc-9275-4f27-8698-ea40303a86e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472008298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2472008298
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1420467031
Short name T786
Test name
Test status
Simulation time 46555219 ps
CPU time 0.8 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:20:57 PM PDT 24
Peak memory 205948 kb
Host smart-eb6f433d-d916-4f1a-b196-c22f7681648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420467031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1420467031
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3595390784
Short name T260
Test name
Test status
Simulation time 45691169591 ps
CPU time 76.18 seconds
Started Jun 04 02:20:52 PM PDT 24
Finished Jun 04 02:22:09 PM PDT 24
Peak memory 253404 kb
Host smart-8b7b404f-d8c9-4863-933f-520b4187b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595390784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3595390784
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.736100672
Short name T245
Test name
Test status
Simulation time 2153922022 ps
CPU time 55.58 seconds
Started Jun 04 02:20:47 PM PDT 24
Finished Jun 04 02:21:43 PM PDT 24
Peak memory 253732 kb
Host smart-d7666860-9ee7-423b-b680-e1a107c4a2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736100672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.736100672
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.518931302
Short name T663
Test name
Test status
Simulation time 2491202835 ps
CPU time 20.27 seconds
Started Jun 04 02:20:49 PM PDT 24
Finished Jun 04 02:21:10 PM PDT 24
Peak memory 224224 kb
Host smart-a4c303b7-ccb4-4407-88ac-026a57d39500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518931302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.518931302
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3869275770
Short name T889
Test name
Test status
Simulation time 2982731810 ps
CPU time 11.67 seconds
Started Jun 04 02:20:48 PM PDT 24
Finished Jun 04 02:21:00 PM PDT 24
Peak memory 218164 kb
Host smart-bd1b5dc8-4b93-48ab-812e-bdd45ef347e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869275770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3869275770
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1907011612
Short name T209
Test name
Test status
Simulation time 10050869875 ps
CPU time 27.7 seconds
Started Jun 04 02:20:50 PM PDT 24
Finished Jun 04 02:21:19 PM PDT 24
Peak memory 228884 kb
Host smart-701bb3b4-0b18-484d-b6b7-c998cbe3c1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907011612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1907011612
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1483411585
Short name T827
Test name
Test status
Simulation time 31456355282 ps
CPU time 17.8 seconds
Started Jun 04 02:20:49 PM PDT 24
Finished Jun 04 02:21:07 PM PDT 24
Peak memory 233496 kb
Host smart-985f5db8-fd49-4085-86f1-d5a41a71957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483411585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1483411585
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.917090137
Short name T433
Test name
Test status
Simulation time 30432294 ps
CPU time 2.45 seconds
Started Jun 04 02:20:49 PM PDT 24
Finished Jun 04 02:20:52 PM PDT 24
Peak memory 220328 kb
Host smart-1413c9ca-c51b-4bab-84e3-959f199fd3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917090137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.917090137
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2101034823
Short name T149
Test name
Test status
Simulation time 700493394 ps
CPU time 4.74 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:21:01 PM PDT 24
Peak memory 222696 kb
Host smart-a5b5fe4e-da58-441b-9212-e7528805e3fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2101034823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2101034823
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1711374571
Short name T276
Test name
Test status
Simulation time 58313534492 ps
CPU time 117 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:22:54 PM PDT 24
Peak memory 253784 kb
Host smart-6d7c7f3c-34aa-4b6a-a775-17e80550e4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711374571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1711374571
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3064398079
Short name T521
Test name
Test status
Simulation time 27512769 ps
CPU time 0.73 seconds
Started Jun 04 02:20:51 PM PDT 24
Finished Jun 04 02:20:52 PM PDT 24
Peak memory 205060 kb
Host smart-3aa6ba25-dd94-4148-9a9b-182579e7f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064398079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3064398079
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1709006942
Short name T775
Test name
Test status
Simulation time 4692264301 ps
CPU time 15.26 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:21:12 PM PDT 24
Peak memory 215920 kb
Host smart-09bebfc9-d357-4abc-a5b2-5a3122de0601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709006942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1709006942
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2971009155
Short name T78
Test name
Test status
Simulation time 91601469 ps
CPU time 1.47 seconds
Started Jun 04 02:20:49 PM PDT 24
Finished Jun 04 02:20:52 PM PDT 24
Peak memory 215928 kb
Host smart-e1d6d9f4-c0fa-467c-b196-703568045444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971009155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2971009155
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.311143195
Short name T397
Test name
Test status
Simulation time 332743033 ps
CPU time 0.95 seconds
Started Jun 04 02:20:50 PM PDT 24
Finished Jun 04 02:20:51 PM PDT 24
Peak memory 205272 kb
Host smart-d3e5dca5-0323-49c0-b0ca-265a057ac49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311143195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.311143195
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1980267454
Short name T648
Test name
Test status
Simulation time 50906233 ps
CPU time 0.77 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:20:58 PM PDT 24
Peak memory 205264 kb
Host smart-7a6f193f-cbbd-4b13-a3f8-6118e86e006c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980267454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1980267454
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1227234867
Short name T583
Test name
Test status
Simulation time 87098272 ps
CPU time 2.63 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:20:58 PM PDT 24
Peak memory 218328 kb
Host smart-7fc2c00d-ce44-42de-ac20-98b1c5eed35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227234867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1227234867
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.742995571
Short name T730
Test name
Test status
Simulation time 24285789 ps
CPU time 0.76 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:20:57 PM PDT 24
Peak memory 204884 kb
Host smart-11525bfd-d01a-42fa-adc3-c825718b2a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742995571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.742995571
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2855655102
Short name T833
Test name
Test status
Simulation time 2664260873 ps
CPU time 12.82 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:21:09 PM PDT 24
Peak memory 233696 kb
Host smart-4f278e5f-61f5-4606-9f40-aee0acbfe4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855655102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2855655102
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3591506545
Short name T124
Test name
Test status
Simulation time 70325630251 ps
CPU time 85.51 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:22:21 PM PDT 24
Peak memory 254452 kb
Host smart-ad6b8922-8bd3-4736-b3a8-6d0e7fc86e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591506545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3591506545
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.805446610
Short name T733
Test name
Test status
Simulation time 43277135692 ps
CPU time 110.64 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:22:46 PM PDT 24
Peak memory 248820 kb
Host smart-677b7524-65b5-4d37-975a-d25ebb10426c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805446610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.805446610
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2859815045
Short name T765
Test name
Test status
Simulation time 659222632 ps
CPU time 13.77 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:21:09 PM PDT 24
Peak memory 232336 kb
Host smart-950690bb-ab93-4e03-9395-58693355ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859815045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2859815045
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2572264786
Short name T192
Test name
Test status
Simulation time 477691396 ps
CPU time 3.46 seconds
Started Jun 04 02:20:58 PM PDT 24
Finished Jun 04 02:21:02 PM PDT 24
Peak memory 232328 kb
Host smart-12f20953-aab1-4d0b-b2a9-1f728c2c8e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572264786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2572264786
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3351290018
Short name T176
Test name
Test status
Simulation time 3090693313 ps
CPU time 33.66 seconds
Started Jun 04 02:20:57 PM PDT 24
Finished Jun 04 02:21:32 PM PDT 24
Peak memory 229344 kb
Host smart-b184bf08-cf66-4081-83f7-97ef3633b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351290018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3351290018
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.283438132
Short name T885
Test name
Test status
Simulation time 2995668535 ps
CPU time 7.88 seconds
Started Jun 04 02:20:57 PM PDT 24
Finished Jun 04 02:21:06 PM PDT 24
Peak memory 237628 kb
Host smart-c592ba99-769c-4463-8046-ce24a6afab24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283438132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.283438132
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3118322237
Short name T290
Test name
Test status
Simulation time 34743760443 ps
CPU time 24.7 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:21:20 PM PDT 24
Peak memory 248988 kb
Host smart-b23b69ef-0325-4a4a-bcf5-87c64980c7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118322237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3118322237
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2156868624
Short name T843
Test name
Test status
Simulation time 285715675 ps
CPU time 4.52 seconds
Started Jun 04 02:20:58 PM PDT 24
Finished Jun 04 02:21:03 PM PDT 24
Peak memory 219220 kb
Host smart-a99ca9bd-c6ce-48ea-80a9-e175fdd01180
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2156868624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2156868624
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.88111833
Short name T871
Test name
Test status
Simulation time 2694559295 ps
CPU time 15.92 seconds
Started Jun 04 02:20:58 PM PDT 24
Finished Jun 04 02:21:14 PM PDT 24
Peak memory 216000 kb
Host smart-09798e1f-ead4-48a3-9efa-cb6d7ba319c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88111833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.88111833
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3226669028
Short name T916
Test name
Test status
Simulation time 2227541254 ps
CPU time 9.37 seconds
Started Jun 04 02:20:54 PM PDT 24
Finished Jun 04 02:21:04 PM PDT 24
Peak memory 215816 kb
Host smart-9f13e484-7f11-4e2a-8da0-69a02f06ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226669028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3226669028
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.753636369
Short name T759
Test name
Test status
Simulation time 74745303 ps
CPU time 1.26 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:20:59 PM PDT 24
Peak memory 215964 kb
Host smart-84dda2bc-cc61-48cb-84ed-275c162414f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753636369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.753636369
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3165212404
Short name T711
Test name
Test status
Simulation time 190989127 ps
CPU time 0.87 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:20:57 PM PDT 24
Peak memory 206304 kb
Host smart-c9b1d741-f060-4a2f-80ca-461fb83a7f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165212404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3165212404
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3929060470
Short name T664
Test name
Test status
Simulation time 335843476 ps
CPU time 6.37 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:21:03 PM PDT 24
Peak memory 234100 kb
Host smart-217294ff-c449-45f2-b69f-66511b977adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929060470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3929060470
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.991223641
Short name T633
Test name
Test status
Simulation time 14148454 ps
CPU time 0.7 seconds
Started Jun 04 02:21:02 PM PDT 24
Finished Jun 04 02:21:03 PM PDT 24
Peak memory 204916 kb
Host smart-570f43fc-067d-4127-a448-98a3b189db38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991223641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.991223641
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2849705723
Short name T601
Test name
Test status
Simulation time 451812142 ps
CPU time 2.78 seconds
Started Jun 04 02:21:03 PM PDT 24
Finished Jun 04 02:21:06 PM PDT 24
Peak memory 233320 kb
Host smart-e653ff57-bf27-459a-a58e-c1297a11205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849705723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2849705723
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3594434041
Short name T508
Test name
Test status
Simulation time 73639308 ps
CPU time 0.79 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:20:58 PM PDT 24
Peak memory 205884 kb
Host smart-0a583e12-19a8-4b80-9aa5-e10b915b0b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594434041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3594434041
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.667221705
Short name T168
Test name
Test status
Simulation time 16879307004 ps
CPU time 63.19 seconds
Started Jun 04 02:21:02 PM PDT 24
Finished Jun 04 02:22:06 PM PDT 24
Peak memory 240624 kb
Host smart-3a4edd95-4a27-45a2-a31b-47191c6767f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667221705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.667221705
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1832954837
Short name T912
Test name
Test status
Simulation time 3977444150 ps
CPU time 29.37 seconds
Started Jun 04 02:21:03 PM PDT 24
Finished Jun 04 02:21:33 PM PDT 24
Peak memory 223424 kb
Host smart-aa78e31c-0a2f-4196-ac87-5b442cb934c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832954837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1832954837
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3675896311
Short name T255
Test name
Test status
Simulation time 74949351147 ps
CPU time 122.17 seconds
Started Jun 04 02:21:04 PM PDT 24
Finished Jun 04 02:23:07 PM PDT 24
Peak memory 256760 kb
Host smart-2264388a-e880-4058-91b6-16b25219df50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675896311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3675896311
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.856888797
Short name T22
Test name
Test status
Simulation time 257650150 ps
CPU time 3.15 seconds
Started Jun 04 02:21:04 PM PDT 24
Finished Jun 04 02:21:08 PM PDT 24
Peak memory 224164 kb
Host smart-a334cceb-d033-4577-92d3-e517edb5e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856888797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.856888797
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.903731519
Short name T286
Test name
Test status
Simulation time 295555025 ps
CPU time 2.71 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:21:00 PM PDT 24
Peak memory 233900 kb
Host smart-87d1556a-e9f0-43c2-af30-e99c217dd347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903731519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.903731519
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.419768140
Short name T280
Test name
Test status
Simulation time 3576459729 ps
CPU time 38.53 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:21:35 PM PDT 24
Peak memory 218276 kb
Host smart-6e9ffaea-b0c1-40f6-9384-b67a72ba80f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419768140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.419768140
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2298138223
Short name T704
Test name
Test status
Simulation time 8085980956 ps
CPU time 26.73 seconds
Started Jun 04 02:20:57 PM PDT 24
Finished Jun 04 02:21:24 PM PDT 24
Peak memory 239924 kb
Host smart-5f1d1eed-56d8-459a-98ed-5ae36292a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298138223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2298138223
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3418865744
Short name T864
Test name
Test status
Simulation time 1859570958 ps
CPU time 12.97 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:21:10 PM PDT 24
Peak memory 217444 kb
Host smart-f0d1c006-89a5-4f38-8f2d-6d63fdec23ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418865744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3418865744
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1814895773
Short name T147
Test name
Test status
Simulation time 280867459 ps
CPU time 3.36 seconds
Started Jun 04 02:21:02 PM PDT 24
Finished Jun 04 02:21:06 PM PDT 24
Peak memory 222116 kb
Host smart-c0cf33d9-6ca3-4f58-8a38-4f2f849a7594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1814895773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1814895773
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3652076743
Short name T854
Test name
Test status
Simulation time 142478263339 ps
CPU time 267.96 seconds
Started Jun 04 02:21:01 PM PDT 24
Finished Jun 04 02:25:30 PM PDT 24
Peak memory 282372 kb
Host smart-9743d4f5-75c5-457f-8959-951f592ad701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652076743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3652076743
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2653992408
Short name T590
Test name
Test status
Simulation time 1844302079 ps
CPU time 10.47 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:21:07 PM PDT 24
Peak memory 215932 kb
Host smart-7dba5554-80f2-4da7-9c4c-9e741e117f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653992408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2653992408
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1503851720
Short name T575
Test name
Test status
Simulation time 7771990765 ps
CPU time 8.46 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:21:04 PM PDT 24
Peak memory 215860 kb
Host smart-faf833fa-a2b5-48d9-83c9-78e7a3f1d9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503851720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1503851720
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.264599659
Short name T489
Test name
Test status
Simulation time 30986040 ps
CPU time 0.76 seconds
Started Jun 04 02:20:56 PM PDT 24
Finished Jun 04 02:20:58 PM PDT 24
Peak memory 205392 kb
Host smart-7c82676b-4e02-4e06-a8b5-acd4786a7641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264599659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.264599659
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1443022471
Short name T18
Test name
Test status
Simulation time 89694056 ps
CPU time 0.81 seconds
Started Jun 04 02:20:55 PM PDT 24
Finished Jun 04 02:20:57 PM PDT 24
Peak memory 205584 kb
Host smart-75e923e2-6b1a-4336-9913-919d36f9fe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443022471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1443022471
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.461060964
Short name T614
Test name
Test status
Simulation time 4121650911 ps
CPU time 8.24 seconds
Started Jun 04 02:21:02 PM PDT 24
Finished Jun 04 02:21:11 PM PDT 24
Peak memory 238600 kb
Host smart-74bb6f38-dcf9-4600-ba62-6aaa321f1a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461060964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.461060964
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3907504028
Short name T952
Test name
Test status
Simulation time 41491109 ps
CPU time 0.75 seconds
Started Jun 04 02:21:15 PM PDT 24
Finished Jun 04 02:21:16 PM PDT 24
Peak memory 204916 kb
Host smart-b3811043-2698-4a17-82a2-eaedfeb031e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907504028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3907504028
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2571308258
Short name T947
Test name
Test status
Simulation time 201413890 ps
CPU time 2.55 seconds
Started Jun 04 02:21:11 PM PDT 24
Finished Jun 04 02:21:14 PM PDT 24
Peak memory 218096 kb
Host smart-b3a7c7b6-6f7f-4d70-a2d1-a9525fe08a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571308258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2571308258
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.452604371
Short name T515
Test name
Test status
Simulation time 28187038 ps
CPU time 0.78 seconds
Started Jun 04 02:21:02 PM PDT 24
Finished Jun 04 02:21:04 PM PDT 24
Peak memory 205244 kb
Host smart-f485cd2d-9e20-4c49-8819-841808520f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452604371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.452604371
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.486566746
Short name T32
Test name
Test status
Simulation time 2799598426 ps
CPU time 23.91 seconds
Started Jun 04 02:21:11 PM PDT 24
Finished Jun 04 02:21:36 PM PDT 24
Peak memory 235020 kb
Host smart-1f9b214b-42bf-4a59-9f54-9d1f2ccb00d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486566746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.486566746
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.385828455
Short name T48
Test name
Test status
Simulation time 45946191163 ps
CPU time 82.14 seconds
Started Jun 04 02:21:15 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 240688 kb
Host smart-06a26d8a-3278-498e-8d8d-153470598081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385828455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.385828455
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1687553889
Short name T261
Test name
Test status
Simulation time 5077604845 ps
CPU time 39.81 seconds
Started Jun 04 02:21:11 PM PDT 24
Finished Jun 04 02:21:52 PM PDT 24
Peak memory 236160 kb
Host smart-c352b8fe-3d48-47b7-8e9f-5efd15169fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687553889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1687553889
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3102061758
Short name T488
Test name
Test status
Simulation time 628459679 ps
CPU time 12.91 seconds
Started Jun 04 02:21:08 PM PDT 24
Finished Jun 04 02:21:22 PM PDT 24
Peak memory 224204 kb
Host smart-cc29b055-6c07-4d16-b2e1-524c4d2c764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102061758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3102061758
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.777307476
Short name T802
Test name
Test status
Simulation time 119786742 ps
CPU time 2.29 seconds
Started Jun 04 02:21:03 PM PDT 24
Finished Jun 04 02:21:06 PM PDT 24
Peak memory 221040 kb
Host smart-581ddb96-b7cb-4ba4-9bc0-3bbd15b26947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777307476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.777307476
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2516295075
Short name T194
Test name
Test status
Simulation time 188816984 ps
CPU time 4.82 seconds
Started Jun 04 02:21:04 PM PDT 24
Finished Jun 04 02:21:09 PM PDT 24
Peak memory 233344 kb
Host smart-6c241c41-acdf-4521-90c6-ec9d16a250db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516295075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2516295075
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3438564316
Short name T202
Test name
Test status
Simulation time 4585481575 ps
CPU time 3.94 seconds
Started Jun 04 02:21:02 PM PDT 24
Finished Jun 04 02:21:06 PM PDT 24
Peak memory 218432 kb
Host smart-c30ec91d-1580-4bfb-acb8-0547f46c0f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438564316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3438564316
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3278265773
Short name T395
Test name
Test status
Simulation time 33563305 ps
CPU time 2.3 seconds
Started Jun 04 02:21:04 PM PDT 24
Finished Jun 04 02:21:07 PM PDT 24
Peak memory 220840 kb
Host smart-34206469-4a08-4bf5-8701-593c2b4ee6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278265773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3278265773
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3635034351
Short name T680
Test name
Test status
Simulation time 436418002 ps
CPU time 6.09 seconds
Started Jun 04 02:21:09 PM PDT 24
Finished Jun 04 02:21:16 PM PDT 24
Peak memory 222048 kb
Host smart-2aa860a7-9010-4993-9d6b-f30f532ab137
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3635034351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3635034351
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1116752294
Short name T126
Test name
Test status
Simulation time 230539907 ps
CPU time 1.05 seconds
Started Jun 04 02:21:11 PM PDT 24
Finished Jun 04 02:21:13 PM PDT 24
Peak memory 206172 kb
Host smart-10df11cd-09a9-4c97-86ad-8a87ef4f19f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116752294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1116752294
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1606210724
Short name T882
Test name
Test status
Simulation time 9453174075 ps
CPU time 27.76 seconds
Started Jun 04 02:21:05 PM PDT 24
Finished Jun 04 02:21:34 PM PDT 24
Peak memory 215884 kb
Host smart-fe6d70a2-bc23-49b3-8bff-c408e262a7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606210724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1606210724
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4202182223
Short name T649
Test name
Test status
Simulation time 1347293986 ps
CPU time 4.45 seconds
Started Jun 04 02:21:04 PM PDT 24
Finished Jun 04 02:21:09 PM PDT 24
Peak memory 215912 kb
Host smart-2f930f8d-b782-416d-ad0d-28b0ee3a8921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202182223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4202182223
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2715957271
Short name T467
Test name
Test status
Simulation time 12566442 ps
CPU time 0.69 seconds
Started Jun 04 02:21:05 PM PDT 24
Finished Jun 04 02:21:07 PM PDT 24
Peak memory 204912 kb
Host smart-923fcb21-78e0-4a93-a03c-3d7c412fcf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715957271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2715957271
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4020093312
Short name T408
Test name
Test status
Simulation time 38251979 ps
CPU time 0.77 seconds
Started Jun 04 02:21:01 PM PDT 24
Finished Jun 04 02:21:03 PM PDT 24
Peak memory 204920 kb
Host smart-a5a0973c-6dd9-43f7-94e6-06b0ca219883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020093312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4020093312
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3955356738
Short name T691
Test name
Test status
Simulation time 684771180 ps
CPU time 3.41 seconds
Started Jun 04 02:21:03 PM PDT 24
Finished Jun 04 02:21:07 PM PDT 24
Peak memory 217256 kb
Host smart-6649a871-68d6-4513-b25e-6af751543208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955356738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3955356738
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2172800886
Short name T6
Test name
Test status
Simulation time 26438190 ps
CPU time 0.65 seconds
Started Jun 04 02:21:23 PM PDT 24
Finished Jun 04 02:21:24 PM PDT 24
Peak memory 204076 kb
Host smart-11c2ce76-542d-4506-9451-85a67994d8af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172800886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2172800886
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3216920791
Short name T327
Test name
Test status
Simulation time 856672282 ps
CPU time 9.71 seconds
Started Jun 04 02:21:10 PM PDT 24
Finished Jun 04 02:21:21 PM PDT 24
Peak memory 218364 kb
Host smart-16ef7e31-3ceb-4aca-b464-8f1470464edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216920791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3216920791
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.242449841
Short name T370
Test name
Test status
Simulation time 20701278 ps
CPU time 0.84 seconds
Started Jun 04 02:21:11 PM PDT 24
Finished Jun 04 02:21:12 PM PDT 24
Peak memory 205852 kb
Host smart-a6323b68-fd68-4645-b7f1-6fc0c070f5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242449841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.242449841
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4131228943
Short name T31
Test name
Test status
Simulation time 1155019905 ps
CPU time 8.16 seconds
Started Jun 04 02:21:09 PM PDT 24
Finished Jun 04 02:21:18 PM PDT 24
Peak memory 224088 kb
Host smart-f8e37be8-f386-41d3-9e89-e9b0d00ba662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131228943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4131228943
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3472743285
Short name T568
Test name
Test status
Simulation time 10006383866 ps
CPU time 95.54 seconds
Started Jun 04 02:21:10 PM PDT 24
Finished Jun 04 02:22:46 PM PDT 24
Peak memory 251808 kb
Host smart-59252798-5f0d-40ce-ab40-d832f148d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472743285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3472743285
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1313017303
Short name T869
Test name
Test status
Simulation time 4450401049 ps
CPU time 97.11 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:22:56 PM PDT 24
Peak memory 264688 kb
Host smart-5810c911-3221-4b0d-a4ea-eeba10c52fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313017303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1313017303
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1152004198
Short name T795
Test name
Test status
Simulation time 43109577801 ps
CPU time 49.29 seconds
Started Jun 04 02:21:08 PM PDT 24
Finished Jun 04 02:21:58 PM PDT 24
Peak memory 240652 kb
Host smart-6b8d0d3c-5b27-4a56-bdfc-3a6d420cdbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152004198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1152004198
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2745144211
Short name T76
Test name
Test status
Simulation time 166077973 ps
CPU time 4.01 seconds
Started Jun 04 02:21:15 PM PDT 24
Finished Jun 04 02:21:19 PM PDT 24
Peak memory 224104 kb
Host smart-c7f65399-abe2-44a9-ab5d-352ef3747ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745144211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2745144211
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.619052334
Short name T127
Test name
Test status
Simulation time 189290837 ps
CPU time 1.94 seconds
Started Jun 04 02:21:09 PM PDT 24
Finished Jun 04 02:21:12 PM PDT 24
Peak memory 215692 kb
Host smart-7057e722-a203-4e5c-beb8-39b9ce96fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619052334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.619052334
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1731678734
Short name T302
Test name
Test status
Simulation time 5797479416 ps
CPU time 8.78 seconds
Started Jun 04 02:21:09 PM PDT 24
Finished Jun 04 02:21:18 PM PDT 24
Peak memory 238816 kb
Host smart-ed9f7d9b-b026-4c08-89f5-22e1a5345a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731678734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1731678734
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1712184936
Short name T645
Test name
Test status
Simulation time 4077296026 ps
CPU time 12.35 seconds
Started Jun 04 02:21:12 PM PDT 24
Finished Jun 04 02:21:25 PM PDT 24
Peak memory 233264 kb
Host smart-e2170f14-d6ab-43ab-8c4f-a1075d7f1e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712184936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1712184936
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3987741213
Short name T56
Test name
Test status
Simulation time 739221549 ps
CPU time 7.57 seconds
Started Jun 04 02:21:10 PM PDT 24
Finished Jun 04 02:21:18 PM PDT 24
Peak memory 218404 kb
Host smart-b3139941-bcf3-4750-826f-ea6f88ceac89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3987741213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3987741213
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1976647018
Short name T163
Test name
Test status
Simulation time 674783996 ps
CPU time 11.04 seconds
Started Jun 04 02:21:22 PM PDT 24
Finished Jun 04 02:21:34 PM PDT 24
Peak memory 217148 kb
Host smart-f23d4d89-c2ad-4d15-9962-e28aa84321ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976647018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1976647018
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.74037149
Short name T875
Test name
Test status
Simulation time 2034383858 ps
CPU time 21.09 seconds
Started Jun 04 02:21:12 PM PDT 24
Finished Jun 04 02:21:33 PM PDT 24
Peak memory 216260 kb
Host smart-80536449-6b36-4cc8-be50-3728c53d86f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74037149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.74037149
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2550210589
Short name T374
Test name
Test status
Simulation time 5405100445 ps
CPU time 6.44 seconds
Started Jun 04 02:21:11 PM PDT 24
Finished Jun 04 02:21:18 PM PDT 24
Peak memory 215932 kb
Host smart-a1431ecd-9ec9-4aef-a013-7ac1c4b0d605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550210589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2550210589
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3735522064
Short name T812
Test name
Test status
Simulation time 49338904 ps
CPU time 1.1 seconds
Started Jun 04 02:21:10 PM PDT 24
Finished Jun 04 02:21:12 PM PDT 24
Peak memory 206472 kb
Host smart-afd5a4d8-c4a7-4498-a085-e0b572f3f47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735522064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3735522064
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3830601276
Short name T331
Test name
Test status
Simulation time 295712168 ps
CPU time 0.76 seconds
Started Jun 04 02:21:10 PM PDT 24
Finished Jun 04 02:21:12 PM PDT 24
Peak memory 205220 kb
Host smart-3f18323e-8992-4b42-997a-48f75536d9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830601276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3830601276
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3162039311
Short name T616
Test name
Test status
Simulation time 118692114 ps
CPU time 2.24 seconds
Started Jun 04 02:21:12 PM PDT 24
Finished Jun 04 02:21:15 PM PDT 24
Peak memory 215716 kb
Host smart-7da26b84-9da0-43f4-92f1-0824f440cba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162039311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3162039311
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.593699156
Short name T481
Test name
Test status
Simulation time 12399839 ps
CPU time 0.71 seconds
Started Jun 04 02:21:19 PM PDT 24
Finished Jun 04 02:21:21 PM PDT 24
Peak memory 204280 kb
Host smart-4d48c1be-5832-4e23-b88a-cc0b89fea403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593699156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.593699156
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1973212582
Short name T729
Test name
Test status
Simulation time 4623182008 ps
CPU time 4.7 seconds
Started Jun 04 02:21:23 PM PDT 24
Finished Jun 04 02:21:28 PM PDT 24
Peak memory 218212 kb
Host smart-95b79578-c1f1-44e7-a073-58a0dc3f1c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973212582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1973212582
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2060264960
Short name T448
Test name
Test status
Simulation time 18865204 ps
CPU time 0.75 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:21:20 PM PDT 24
Peak memory 204876 kb
Host smart-0570ad37-5a76-4063-8f53-51e0f48fa131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060264960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2060264960
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.935066668
Short name T29
Test name
Test status
Simulation time 6792723668 ps
CPU time 53.69 seconds
Started Jun 04 02:21:23 PM PDT 24
Finished Jun 04 02:22:17 PM PDT 24
Peak memory 248852 kb
Host smart-d5d7750f-3be8-456a-a601-8e8254cfd14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935066668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.935066668
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1007189635
Short name T579
Test name
Test status
Simulation time 10716013614 ps
CPU time 113.01 seconds
Started Jun 04 02:21:21 PM PDT 24
Finished Jun 04 02:23:15 PM PDT 24
Peak memory 256288 kb
Host smart-7ff984a4-55f0-4b0a-b37c-275030909aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007189635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1007189635
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3604897777
Short name T842
Test name
Test status
Simulation time 37015157744 ps
CPU time 375.25 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:27:34 PM PDT 24
Peak memory 260140 kb
Host smart-bd1ef0fc-39b7-4539-b1e5-a4ecbbf9a494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604897777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3604897777
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.373692499
Short name T667
Test name
Test status
Simulation time 601818419 ps
CPU time 12.51 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:21:31 PM PDT 24
Peak memory 218236 kb
Host smart-ca9c9c66-81e6-4301-9d62-66c78c01a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373692499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.373692499
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1869903284
Short name T899
Test name
Test status
Simulation time 8602225018 ps
CPU time 3.55 seconds
Started Jun 04 02:21:23 PM PDT 24
Finished Jun 04 02:21:27 PM PDT 24
Peak memory 224144 kb
Host smart-6de0c68d-4065-43d0-9b80-e037528de04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869903284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1869903284
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.71392333
Short name T109
Test name
Test status
Simulation time 1128282920 ps
CPU time 7.94 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:21:27 PM PDT 24
Peak memory 234128 kb
Host smart-65d801b8-b86b-4edc-8212-87b98a8507b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71392333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.71392333
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3200692049
Short name T287
Test name
Test status
Simulation time 68264569152 ps
CPU time 34.72 seconds
Started Jun 04 02:21:22 PM PDT 24
Finished Jun 04 02:21:57 PM PDT 24
Peak memory 239816 kb
Host smart-04dded89-ba91-4134-b2c4-324cb589ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200692049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3200692049
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.718623883
Short name T299
Test name
Test status
Simulation time 966957047 ps
CPU time 9.64 seconds
Started Jun 04 02:21:17 PM PDT 24
Finished Jun 04 02:21:27 PM PDT 24
Peak memory 237792 kb
Host smart-6f23b377-6998-41e6-a711-88de7da07ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718623883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.718623883
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4222783215
Short name T464
Test name
Test status
Simulation time 1342686898 ps
CPU time 6.77 seconds
Started Jun 04 02:21:19 PM PDT 24
Finished Jun 04 02:21:26 PM PDT 24
Peak memory 222660 kb
Host smart-90971c02-bcf2-462c-bdbd-1363184db7b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4222783215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4222783215
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2492947597
Short name T493
Test name
Test status
Simulation time 243186576 ps
CPU time 1.1 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:21:20 PM PDT 24
Peak memory 206440 kb
Host smart-e0c53965-8f32-48ca-bde8-2e6a80aca2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492947597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2492947597
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1569438827
Short name T752
Test name
Test status
Simulation time 22466443234 ps
CPU time 33.88 seconds
Started Jun 04 02:21:17 PM PDT 24
Finished Jun 04 02:21:52 PM PDT 24
Peak memory 216004 kb
Host smart-71204701-8d64-44a2-b248-2c51c947fa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569438827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1569438827
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2266938004
Short name T673
Test name
Test status
Simulation time 2493447782 ps
CPU time 5.3 seconds
Started Jun 04 02:21:20 PM PDT 24
Finished Jun 04 02:21:26 PM PDT 24
Peak memory 215848 kb
Host smart-1d767c51-4605-4a0d-9455-8a4f711d855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266938004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2266938004
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1769195975
Short name T695
Test name
Test status
Simulation time 13638628 ps
CPU time 0.68 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:21:20 PM PDT 24
Peak memory 204920 kb
Host smart-b0d7fb01-c672-4b30-a725-bb2234efec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769195975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1769195975
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2314145232
Short name T641
Test name
Test status
Simulation time 78518502 ps
CPU time 0.78 seconds
Started Jun 04 02:21:17 PM PDT 24
Finished Jun 04 02:21:18 PM PDT 24
Peak memory 205220 kb
Host smart-6048bd4f-c4bd-409b-8a6a-36eb9ae43580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314145232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2314145232
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3391406895
Short name T431
Test name
Test status
Simulation time 129716985 ps
CPU time 2.57 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:21:21 PM PDT 24
Peak memory 233396 kb
Host smart-9f496e74-b0f0-4955-b136-140c4a5cff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391406895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3391406895
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4044803487
Short name T611
Test name
Test status
Simulation time 10922110 ps
CPU time 0.7 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:21:34 PM PDT 24
Peak memory 204292 kb
Host smart-96c3f538-f266-4522-b934-a3cacde3eb6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044803487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4044803487
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3340292526
Short name T925
Test name
Test status
Simulation time 1610889194 ps
CPU time 13.25 seconds
Started Jun 04 02:21:32 PM PDT 24
Finished Jun 04 02:21:46 PM PDT 24
Peak memory 233760 kb
Host smart-a13bb5e8-6335-4707-b2b6-5b8b2e296d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340292526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3340292526
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2307520745
Short name T657
Test name
Test status
Simulation time 14079585 ps
CPU time 0.76 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:21:20 PM PDT 24
Peak memory 204864 kb
Host smart-2df035f9-e84b-4248-a185-a4a6f8d8d26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307520745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2307520745
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2503540257
Short name T434
Test name
Test status
Simulation time 15790782291 ps
CPU time 108.53 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:23:17 PM PDT 24
Peak memory 249912 kb
Host smart-dd6f3689-629c-4d3d-a1ba-16206ba67ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503540257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2503540257
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3656103444
Short name T628
Test name
Test status
Simulation time 3765613692 ps
CPU time 96.24 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:23:05 PM PDT 24
Peak memory 248892 kb
Host smart-7ffbd5ec-2b68-4ab3-9170-9f10a0764b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656103444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3656103444
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.889488027
Short name T325
Test name
Test status
Simulation time 58046464880 ps
CPU time 303.79 seconds
Started Jun 04 02:21:27 PM PDT 24
Finished Jun 04 02:26:32 PM PDT 24
Peak memory 248800 kb
Host smart-e86cfe63-93d2-4deb-b291-664fe3ede158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889488027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.889488027
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3619767408
Short name T890
Test name
Test status
Simulation time 66007998 ps
CPU time 2.71 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:32 PM PDT 24
Peak memory 232320 kb
Host smart-67c03285-de40-4f5f-84c5-679ddf9c22b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619767408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3619767408
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3019496035
Short name T876
Test name
Test status
Simulation time 1012738580 ps
CPU time 10.1 seconds
Started Jun 04 02:21:29 PM PDT 24
Finished Jun 04 02:21:40 PM PDT 24
Peak memory 232352 kb
Host smart-767820ee-1238-4291-8fb7-07f2161e9284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019496035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3019496035
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.908261711
Short name T204
Test name
Test status
Simulation time 5261370445 ps
CPU time 58.63 seconds
Started Jun 04 02:21:27 PM PDT 24
Finished Jun 04 02:22:26 PM PDT 24
Peak memory 228968 kb
Host smart-13a8438d-6dd1-44be-9b30-d8dd5e046fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908261711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.908261711
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2746578628
Short name T301
Test name
Test status
Simulation time 253784913 ps
CPU time 2.65 seconds
Started Jun 04 02:21:27 PM PDT 24
Finished Jun 04 02:21:31 PM PDT 24
Peak memory 218260 kb
Host smart-35e243d6-ef54-4e85-92eb-1b81adc30b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746578628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2746578628
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4280259074
Short name T801
Test name
Test status
Simulation time 24886297603 ps
CPU time 7.74 seconds
Started Jun 04 02:21:19 PM PDT 24
Finished Jun 04 02:21:27 PM PDT 24
Peak memory 233480 kb
Host smart-2bcffb68-9dd7-44f3-a057-ffb311ddb1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280259074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4280259074
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1327498426
Short name T500
Test name
Test status
Simulation time 726585261 ps
CPU time 3.93 seconds
Started Jun 04 02:21:27 PM PDT 24
Finished Jun 04 02:21:31 PM PDT 24
Peak memory 218956 kb
Host smart-35a647ae-6773-40ef-889c-1de67b4f0ce8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1327498426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1327498426
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3891531835
Short name T850
Test name
Test status
Simulation time 230150724 ps
CPU time 1.16 seconds
Started Jun 04 02:21:26 PM PDT 24
Finished Jun 04 02:21:28 PM PDT 24
Peak memory 206588 kb
Host smart-0b59fe49-896c-4a7c-9b02-45882a472f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891531835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3891531835
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2872553705
Short name T125
Test name
Test status
Simulation time 6957978002 ps
CPU time 13.06 seconds
Started Jun 04 02:21:18 PM PDT 24
Finished Jun 04 02:21:32 PM PDT 24
Peak memory 219204 kb
Host smart-7f523193-0293-422e-b902-aa1932ba1846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872553705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2872553705
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2975063143
Short name T810
Test name
Test status
Simulation time 14748553809 ps
CPU time 21.44 seconds
Started Jun 04 02:21:17 PM PDT 24
Finished Jun 04 02:21:39 PM PDT 24
Peak memory 216208 kb
Host smart-8d81afd2-3a92-4e7a-b0f1-aac981aee4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975063143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2975063143
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4238958381
Short name T362
Test name
Test status
Simulation time 13530240 ps
CPU time 0.86 seconds
Started Jun 04 02:21:17 PM PDT 24
Finished Jun 04 02:21:19 PM PDT 24
Peak memory 205280 kb
Host smart-a075cc33-5c97-4790-b96d-5374dac6f51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238958381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4238958381
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2683871862
Short name T353
Test name
Test status
Simulation time 46759834 ps
CPU time 0.74 seconds
Started Jun 04 02:21:17 PM PDT 24
Finished Jun 04 02:21:19 PM PDT 24
Peak memory 205248 kb
Host smart-2f649d3b-f91e-41e1-9700-e78f6566dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683871862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2683871862
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3252120856
Short name T208
Test name
Test status
Simulation time 397747715 ps
CPU time 3.43 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:32 PM PDT 24
Peak memory 233072 kb
Host smart-c6f14ac3-a1b4-4fe8-97b6-e10f286f8693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252120856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3252120856
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.49806694
Short name T526
Test name
Test status
Simulation time 15052546 ps
CPU time 0.71 seconds
Started Jun 04 02:21:36 PM PDT 24
Finished Jun 04 02:21:37 PM PDT 24
Peak memory 204928 kb
Host smart-0429418e-9ea5-4c3f-9aab-1ea520cd454a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49806694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.49806694
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3055070048
Short name T858
Test name
Test status
Simulation time 122655309 ps
CPU time 3.83 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:21:37 PM PDT 24
Peak memory 233372 kb
Host smart-b07f691c-8370-4296-aeac-ce60a0069a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055070048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3055070048
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3566823588
Short name T908
Test name
Test status
Simulation time 14410903 ps
CPU time 0.75 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:30 PM PDT 24
Peak memory 205220 kb
Host smart-f0286cdb-7ee9-4e71-af01-73995437f229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566823588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3566823588
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2820467997
Short name T559
Test name
Test status
Simulation time 15927692523 ps
CPU time 130.79 seconds
Started Jun 04 02:21:37 PM PDT 24
Finished Jun 04 02:23:48 PM PDT 24
Peak memory 252500 kb
Host smart-ec0b4aac-d439-4e08-a3e7-ddac5b571897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820467997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2820467997
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2641280242
Short name T213
Test name
Test status
Simulation time 28552323440 ps
CPU time 131.03 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:23:46 PM PDT 24
Peak memory 240700 kb
Host smart-dfab9648-edf7-471c-ae28-bda1fddef392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641280242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2641280242
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.156230835
Short name T311
Test name
Test status
Simulation time 2726099009 ps
CPU time 10.37 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:21:45 PM PDT 24
Peak memory 233444 kb
Host smart-a07bee8a-db65-425c-bcb5-5870b254c948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156230835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.156230835
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2204338144
Short name T760
Test name
Test status
Simulation time 189183267 ps
CPU time 3.64 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:32 PM PDT 24
Peak memory 219148 kb
Host smart-98924b4a-1431-4de8-ad8f-157bceb12eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204338144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2204338144
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2539450715
Short name T203
Test name
Test status
Simulation time 4890708161 ps
CPU time 15.05 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:44 PM PDT 24
Peak memory 218392 kb
Host smart-66ea637a-d562-4173-92f6-063deec865d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539450715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2539450715
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3755852868
Short name T677
Test name
Test status
Simulation time 1014438636 ps
CPU time 4.89 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:34 PM PDT 24
Peak memory 233320 kb
Host smart-b5a613b2-86f2-46dd-96c9-db16ecee6af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755852868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3755852868
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1089746057
Short name T848
Test name
Test status
Simulation time 2106564451 ps
CPU time 14.17 seconds
Started Jun 04 02:21:26 PM PDT 24
Finished Jun 04 02:21:40 PM PDT 24
Peak memory 247000 kb
Host smart-7db66316-f811-43ff-8f48-a6b513196755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089746057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1089746057
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3838743102
Short name T747
Test name
Test status
Simulation time 539173073 ps
CPU time 5.7 seconds
Started Jun 04 02:21:35 PM PDT 24
Finished Jun 04 02:21:42 PM PDT 24
Peak memory 221944 kb
Host smart-9ca8cb14-993a-4ade-bffd-92cb14532b37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3838743102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3838743102
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1410315309
Short name T162
Test name
Test status
Simulation time 59509745793 ps
CPU time 295.95 seconds
Started Jun 04 02:21:35 PM PDT 24
Finished Jun 04 02:26:32 PM PDT 24
Peak memory 265072 kb
Host smart-c1d9d50f-c689-4763-aee4-07f2b9d33beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410315309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1410315309
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2147317169
Short name T436
Test name
Test status
Simulation time 4898124869 ps
CPU time 17.01 seconds
Started Jun 04 02:21:27 PM PDT 24
Finished Jun 04 02:21:45 PM PDT 24
Peak memory 215964 kb
Host smart-28488c3f-585d-4b9a-83eb-646932227881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147317169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2147317169
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2735187854
Short name T640
Test name
Test status
Simulation time 142472461 ps
CPU time 0.96 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:29 PM PDT 24
Peak memory 205416 kb
Host smart-d3db9e1b-1ffc-4dbf-8a47-785adf3543dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735187854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2735187854
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.869666205
Short name T340
Test name
Test status
Simulation time 80820810 ps
CPU time 1.21 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:30 PM PDT 24
Peak memory 207500 kb
Host smart-cf9062ec-fbeb-4869-91b2-cfd9192f8911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869666205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.869666205
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.4167282544
Short name T46
Test name
Test status
Simulation time 123074483 ps
CPU time 0.89 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:30 PM PDT 24
Peak memory 205272 kb
Host smart-fadc1416-5bbd-4b0a-8745-15030598ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167282544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.4167282544
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1109438509
Short name T881
Test name
Test status
Simulation time 5158117479 ps
CPU time 12.6 seconds
Started Jun 04 02:21:28 PM PDT 24
Finished Jun 04 02:21:42 PM PDT 24
Peak memory 236580 kb
Host smart-a6a0e0e9-2efd-45e7-b47c-7764cddacb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109438509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1109438509
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2744412982
Short name T604
Test name
Test status
Simulation time 12028830 ps
CPU time 0.74 seconds
Started Jun 04 02:19:06 PM PDT 24
Finished Jun 04 02:19:08 PM PDT 24
Peak memory 204288 kb
Host smart-49b0169e-0601-498a-ad6a-254443d2d0a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744412982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
744412982
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3758717544
Short name T298
Test name
Test status
Simulation time 7737879446 ps
CPU time 7.43 seconds
Started Jun 04 02:19:06 PM PDT 24
Finished Jun 04 02:19:14 PM PDT 24
Peak memory 238412 kb
Host smart-c61511c1-0751-4c1f-b2a7-4d7955b5353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758717544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3758717544
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.286603548
Short name T400
Test name
Test status
Simulation time 111374565 ps
CPU time 0.75 seconds
Started Jun 04 02:19:01 PM PDT 24
Finished Jun 04 02:19:03 PM PDT 24
Peak memory 206252 kb
Host smart-e7c098cc-50f6-47cf-bef5-bb48b2167c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286603548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.286603548
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3482797387
Short name T216
Test name
Test status
Simulation time 18285060550 ps
CPU time 119.78 seconds
Started Jun 04 02:19:10 PM PDT 24
Finished Jun 04 02:21:11 PM PDT 24
Peak memory 248812 kb
Host smart-13350bcd-73c9-4aff-9d22-c98dcce7d1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482797387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3482797387
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2497360086
Short name T482
Test name
Test status
Simulation time 34955139664 ps
CPU time 66.28 seconds
Started Jun 04 02:19:07 PM PDT 24
Finished Jun 04 02:20:15 PM PDT 24
Peak memory 224312 kb
Host smart-4c15886a-8d55-469b-a844-50025aba2cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497360086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2497360086
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3074062723
Short name T175
Test name
Test status
Simulation time 3482619259 ps
CPU time 93.29 seconds
Started Jun 04 02:19:05 PM PDT 24
Finished Jun 04 02:20:39 PM PDT 24
Peak memory 252540 kb
Host smart-c0fcdc52-849d-4c7b-a648-da1409def406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074062723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3074062723
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2728335291
Short name T531
Test name
Test status
Simulation time 3032365967 ps
CPU time 10.13 seconds
Started Jun 04 02:19:07 PM PDT 24
Finished Jun 04 02:19:18 PM PDT 24
Peak memory 228096 kb
Host smart-0ee447a1-a31e-4a25-88ab-d66a8ba4d997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728335291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2728335291
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.441230303
Short name T218
Test name
Test status
Simulation time 35313569 ps
CPU time 2.41 seconds
Started Jun 04 02:18:57 PM PDT 24
Finished Jun 04 02:19:00 PM PDT 24
Peak memory 218084 kb
Host smart-bd2c5973-5b84-4c77-bcaa-e9391cc26c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441230303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.441230303
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1747755655
Short name T441
Test name
Test status
Simulation time 135580376 ps
CPU time 2.62 seconds
Started Jun 04 02:19:12 PM PDT 24
Finished Jun 04 02:19:15 PM PDT 24
Peak memory 233724 kb
Host smart-ce8887c2-cf15-46c7-bed8-175e5ac049c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747755655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1747755655
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1591283145
Short name T26
Test name
Test status
Simulation time 58383334 ps
CPU time 1.13 seconds
Started Jun 04 02:18:58 PM PDT 24
Finished Jun 04 02:19:00 PM PDT 24
Peak memory 216196 kb
Host smart-44c65d73-5db9-4c31-b5ff-5b8c94958f00
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591283145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1591283145
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1844050921
Short name T728
Test name
Test status
Simulation time 1993643418 ps
CPU time 5.63 seconds
Started Jun 04 02:18:58 PM PDT 24
Finished Jun 04 02:19:04 PM PDT 24
Peak memory 233216 kb
Host smart-dc3af62d-b165-4d80-a92e-dd5f1df2df0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844050921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1844050921
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4234452832
Short name T385
Test name
Test status
Simulation time 1476273915 ps
CPU time 4.98 seconds
Started Jun 04 02:19:02 PM PDT 24
Finished Jun 04 02:19:07 PM PDT 24
Peak memory 233208 kb
Host smart-101b489f-d374-409e-8270-69e653f10bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234452832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4234452832
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3262306208
Short name T381
Test name
Test status
Simulation time 497467684 ps
CPU time 4.23 seconds
Started Jun 04 02:19:05 PM PDT 24
Finished Jun 04 02:19:10 PM PDT 24
Peak memory 222568 kb
Host smart-2611cae2-64c0-45f1-ae40-3d71e1848a39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3262306208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3262306208
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.850047683
Short name T68
Test name
Test status
Simulation time 64750424 ps
CPU time 1.17 seconds
Started Jun 04 02:19:08 PM PDT 24
Finished Jun 04 02:19:10 PM PDT 24
Peak memory 234812 kb
Host smart-91dad43f-e0f4-4a4c-ae09-e26af3f22019
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850047683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.850047683
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2824552925
Short name T782
Test name
Test status
Simulation time 42246401 ps
CPU time 0.91 seconds
Started Jun 04 02:19:06 PM PDT 24
Finished Jun 04 02:19:08 PM PDT 24
Peak memory 205944 kb
Host smart-34702716-6f47-4882-879f-039122664686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824552925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2824552925
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1204517913
Short name T594
Test name
Test status
Simulation time 9425203875 ps
CPU time 26.19 seconds
Started Jun 04 02:19:01 PM PDT 24
Finished Jun 04 02:19:28 PM PDT 24
Peak memory 216040 kb
Host smart-aa60ccbe-9246-45d2-9b38-ea4842496d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204517913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1204517913
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3879046417
Short name T346
Test name
Test status
Simulation time 2789714184 ps
CPU time 13.44 seconds
Started Jun 04 02:19:04 PM PDT 24
Finished Jun 04 02:19:18 PM PDT 24
Peak memory 215916 kb
Host smart-4bbd585c-5e50-4715-9c68-7f8b27aede30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879046417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3879046417
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.505856743
Short name T50
Test name
Test status
Simulation time 411718365 ps
CPU time 2.49 seconds
Started Jun 04 02:18:59 PM PDT 24
Finished Jun 04 02:19:02 PM PDT 24
Peak memory 215884 kb
Host smart-420e5f90-b6a7-47bb-8354-1d6f73a27b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505856743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.505856743
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.93358357
Short name T8
Test name
Test status
Simulation time 119075127 ps
CPU time 1 seconds
Started Jun 04 02:18:58 PM PDT 24
Finished Jun 04 02:19:00 PM PDT 24
Peak memory 205320 kb
Host smart-1dbf0506-a715-47a2-a7ff-425ed350b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93358357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.93358357
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.286732141
Short name T211
Test name
Test status
Simulation time 6548244432 ps
CPU time 9.05 seconds
Started Jun 04 02:19:12 PM PDT 24
Finished Jun 04 02:19:22 PM PDT 24
Peak memory 226204 kb
Host smart-72d5046b-ce0a-4c9d-be46-2dc763378538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286732141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.286732141
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3654106843
Short name T62
Test name
Test status
Simulation time 32265051 ps
CPU time 0.69 seconds
Started Jun 04 02:21:32 PM PDT 24
Finished Jun 04 02:21:33 PM PDT 24
Peak memory 204876 kb
Host smart-414db582-781d-41c4-b842-07bd211f14ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654106843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3654106843
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1848280565
Short name T430
Test name
Test status
Simulation time 213553757 ps
CPU time 2.46 seconds
Started Jun 04 02:21:35 PM PDT 24
Finished Jun 04 02:21:39 PM PDT 24
Peak memory 218248 kb
Host smart-927b22cb-2ee0-4ce4-bf65-1b6b47477012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848280565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1848280565
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2910435221
Short name T789
Test name
Test status
Simulation time 35364409 ps
CPU time 0.77 seconds
Started Jun 04 02:21:42 PM PDT 24
Finished Jun 04 02:21:43 PM PDT 24
Peak memory 206248 kb
Host smart-55bd57f9-ca6f-47d4-b81a-104ead824c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910435221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2910435221
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3495944181
Short name T258
Test name
Test status
Simulation time 41691926706 ps
CPU time 55.59 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:22:30 PM PDT 24
Peak memory 248888 kb
Host smart-207d85b3-e21a-4551-be7f-94cee395d502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495944181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3495944181
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1373367181
Short name T277
Test name
Test status
Simulation time 104837768212 ps
CPU time 231.46 seconds
Started Jun 04 02:21:32 PM PDT 24
Finished Jun 04 02:25:25 PM PDT 24
Peak memory 249068 kb
Host smart-1afe7fd4-8084-4871-b67b-68899c04a368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373367181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1373367181
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3385906462
Short name T406
Test name
Test status
Simulation time 17481258035 ps
CPU time 154.93 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:24:10 PM PDT 24
Peak memory 248900 kb
Host smart-44d41d5a-ec6f-4d03-9847-a04a86e8005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385906462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3385906462
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2694283188
Short name T389
Test name
Test status
Simulation time 233209610 ps
CPU time 3.86 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:21:37 PM PDT 24
Peak memory 224188 kb
Host smart-0bbe6935-615b-42cd-89f7-387646d02563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694283188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2694283188
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.150849652
Short name T278
Test name
Test status
Simulation time 6613441173 ps
CPU time 35.16 seconds
Started Jun 04 02:21:38 PM PDT 24
Finished Jun 04 02:22:14 PM PDT 24
Peak memory 234016 kb
Host smart-f852712e-2213-4542-b65e-7d0cc438006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150849652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.150849652
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1902237025
Short name T964
Test name
Test status
Simulation time 1322215909 ps
CPU time 23.64 seconds
Started Jun 04 02:21:38 PM PDT 24
Finished Jun 04 02:22:02 PM PDT 24
Peak memory 230288 kb
Host smart-88e88a67-a8d0-4e12-9d73-151ade8dc20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902237025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1902237025
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.704897991
Short name T42
Test name
Test status
Simulation time 12595028694 ps
CPU time 14 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:21:49 PM PDT 24
Peak memory 232444 kb
Host smart-684fe405-2bb7-437a-a503-15a941742e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704897991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.704897991
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3227752238
Short name T2
Test name
Test status
Simulation time 9463351805 ps
CPU time 26.7 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:22:00 PM PDT 24
Peak memory 223712 kb
Host smart-b127af15-aa8f-430f-8909-918b41931efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227752238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3227752238
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4183619575
Short name T44
Test name
Test status
Simulation time 1485251572 ps
CPU time 4.75 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:47 PM PDT 24
Peak memory 220380 kb
Host smart-3891f6da-1b69-47e1-a0eb-df2f286e9026
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4183619575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4183619575
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.877560259
Short name T894
Test name
Test status
Simulation time 42299460 ps
CPU time 0.98 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:43 PM PDT 24
Peak memory 206508 kb
Host smart-c466e21e-7b1e-4ed4-bae7-c403f896820f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877560259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.877560259
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.773285876
Short name T710
Test name
Test status
Simulation time 1104552909 ps
CPU time 6.98 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:49 PM PDT 24
Peak memory 215888 kb
Host smart-fa264c6f-212d-4425-a5bd-de37b080a688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773285876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.773285876
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.745251150
Short name T5
Test name
Test status
Simulation time 5427110813 ps
CPU time 9.72 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:21:43 PM PDT 24
Peak memory 215884 kb
Host smart-22032d39-ad0a-4e52-b021-7498c019ed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745251150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.745251150
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4162966221
Short name T643
Test name
Test status
Simulation time 141026171 ps
CPU time 1.62 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:21:35 PM PDT 24
Peak memory 215908 kb
Host smart-2f471e91-d1e4-4d8a-818c-cbc05c334b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162966221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4162966221
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.774294246
Short name T865
Test name
Test status
Simulation time 96254845 ps
CPU time 0.99 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:21:36 PM PDT 24
Peak memory 206316 kb
Host smart-380f2d45-6374-4d49-bcee-b06f813d34f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774294246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.774294246
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1090155517
Short name T369
Test name
Test status
Simulation time 12848949380 ps
CPU time 13 seconds
Started Jun 04 02:21:35 PM PDT 24
Finished Jun 04 02:21:49 PM PDT 24
Peak memory 235764 kb
Host smart-25769ec2-7e35-405d-b7e7-0d99bd60bf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090155517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1090155517
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2244293616
Short name T380
Test name
Test status
Simulation time 13018350 ps
CPU time 0.74 seconds
Started Jun 04 02:21:39 PM PDT 24
Finished Jun 04 02:21:40 PM PDT 24
Peak memory 204256 kb
Host smart-a38266ce-4325-46af-8334-54577c87a3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244293616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2244293616
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1799002470
Short name T61
Test name
Test status
Simulation time 458855381 ps
CPU time 4.38 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:21:40 PM PDT 24
Peak memory 233432 kb
Host smart-19141f11-c026-4cdb-b31d-9f5dada0f807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799002470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1799002470
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1150508776
Short name T533
Test name
Test status
Simulation time 14431443 ps
CPU time 0.75 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:21:36 PM PDT 24
Peak memory 205936 kb
Host smart-01fdafb9-3f96-4558-9aac-8d87be0092d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150508776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1150508776
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3084598735
Short name T173
Test name
Test status
Simulation time 47459405622 ps
CPU time 85.64 seconds
Started Jun 04 02:21:39 PM PDT 24
Finished Jun 04 02:23:05 PM PDT 24
Peak memory 233764 kb
Host smart-3a0f6b69-1244-4c9a-a1e6-ea4bcceedeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084598735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3084598735
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2415734113
Short name T427
Test name
Test status
Simulation time 34229698636 ps
CPU time 37.5 seconds
Started Jun 04 02:21:42 PM PDT 24
Finished Jun 04 02:22:21 PM PDT 24
Peak memory 240492 kb
Host smart-60f2dd17-6cdf-4049-bfc8-690b03c6ab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415734113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2415734113
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3044534799
Short name T186
Test name
Test status
Simulation time 54282928834 ps
CPU time 183.77 seconds
Started Jun 04 02:21:40 PM PDT 24
Finished Jun 04 02:24:45 PM PDT 24
Peak memory 265872 kb
Host smart-9e8a3dcd-5b82-4638-8dfa-298b5c26fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044534799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3044534799
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2842214983
Short name T826
Test name
Test status
Simulation time 1076517580 ps
CPU time 15.96 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:58 PM PDT 24
Peak memory 232352 kb
Host smart-9c96deb0-6e18-4435-b857-625d57aa2569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842214983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2842214983
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1273304311
Short name T851
Test name
Test status
Simulation time 155630141 ps
CPU time 3.47 seconds
Started Jun 04 02:21:35 PM PDT 24
Finished Jun 04 02:21:40 PM PDT 24
Peak memory 224128 kb
Host smart-770380d9-0950-4613-bc08-6a7321770541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273304311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1273304311
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2695022803
Short name T300
Test name
Test status
Simulation time 96335499470 ps
CPU time 62.69 seconds
Started Jun 04 02:21:34 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 240240 kb
Host smart-63037019-d0c3-4ffb-8229-668aba888bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695022803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2695022803
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3157971444
Short name T507
Test name
Test status
Simulation time 35770381933 ps
CPU time 23.19 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:21:57 PM PDT 24
Peak memory 233136 kb
Host smart-dc4a3134-0545-44be-8f3d-766bd3bf206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157971444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3157971444
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3535611784
Short name T536
Test name
Test status
Simulation time 1061580251 ps
CPU time 9.18 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:21:43 PM PDT 24
Peak memory 240036 kb
Host smart-39cf1f21-8e4a-4881-9ee6-aac902c2708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535611784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3535611784
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1860897801
Short name T686
Test name
Test status
Simulation time 543118032 ps
CPU time 8.45 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:50 PM PDT 24
Peak memory 222552 kb
Host smart-f7e5561c-6d7f-4406-843d-fb0236891012
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1860897801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1860897801
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2180817543
Short name T164
Test name
Test status
Simulation time 263355608 ps
CPU time 1.01 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:43 PM PDT 24
Peak memory 206100 kb
Host smart-6b45d435-11b3-4e66-a7b0-fe8db2fb1ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180817543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2180817543
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2859559243
Short name T418
Test name
Test status
Simulation time 1980912789 ps
CPU time 29.03 seconds
Started Jun 04 02:21:33 PM PDT 24
Finished Jun 04 02:22:03 PM PDT 24
Peak memory 219368 kb
Host smart-36b9248e-16c4-46df-a863-2cb6708c5315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859559243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2859559243
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.594191826
Short name T849
Test name
Test status
Simulation time 5440535862 ps
CPU time 6.49 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:49 PM PDT 24
Peak memory 215924 kb
Host smart-06f3dda6-334d-4dda-af17-057ca605fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594191826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.594191826
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1012186223
Short name T941
Test name
Test status
Simulation time 168671889 ps
CPU time 1.25 seconds
Started Jun 04 02:21:32 PM PDT 24
Finished Jun 04 02:21:34 PM PDT 24
Peak memory 215976 kb
Host smart-4dc59d47-6770-472e-9538-953d68e060f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012186223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1012186223
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4141753274
Short name T635
Test name
Test status
Simulation time 122848794 ps
CPU time 0.75 seconds
Started Jun 04 02:21:35 PM PDT 24
Finished Jun 04 02:21:37 PM PDT 24
Peak memory 205224 kb
Host smart-c78af929-7770-4f1c-92e5-13021042eefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141753274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4141753274
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1870686184
Short name T401
Test name
Test status
Simulation time 3985734034 ps
CPU time 10.72 seconds
Started Jun 04 02:21:37 PM PDT 24
Finished Jun 04 02:21:48 PM PDT 24
Peak memory 233472 kb
Host smart-11798429-ddff-4e81-88cf-9cdcb1209dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870686184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1870686184
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3463930538
Short name T660
Test name
Test status
Simulation time 30676891 ps
CPU time 0.7 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:21:49 PM PDT 24
Peak memory 204912 kb
Host smart-1b220c13-ad12-4976-afd2-2e1d60a79e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463930538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3463930538
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3276548214
Short name T485
Test name
Test status
Simulation time 4570333831 ps
CPU time 28.79 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:22:10 PM PDT 24
Peak memory 221340 kb
Host smart-d5379e9f-e98d-4e9b-9e35-fa6a00fd5d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276548214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3276548214
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1329603049
Short name T335
Test name
Test status
Simulation time 19114679 ps
CPU time 0.77 seconds
Started Jun 04 02:21:40 PM PDT 24
Finished Jun 04 02:21:41 PM PDT 24
Peak memory 205928 kb
Host smart-53a3f574-c14a-4d70-9bca-4d36feeee6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329603049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1329603049
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1735203413
Short name T197
Test name
Test status
Simulation time 96624071601 ps
CPU time 208.7 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:25:11 PM PDT 24
Peak memory 240600 kb
Host smart-e5da1dae-cbf1-406e-bc80-d8ffd71b646c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735203413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1735203413
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1145784109
Short name T938
Test name
Test status
Simulation time 153484847777 ps
CPU time 367.86 seconds
Started Jun 04 02:21:49 PM PDT 24
Finished Jun 04 02:27:57 PM PDT 24
Peak memory 255160 kb
Host smart-109e65b7-2bfd-461b-a70e-0fadc39e0a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145784109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1145784109
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1126901117
Short name T936
Test name
Test status
Simulation time 467173743 ps
CPU time 2.25 seconds
Started Jun 04 02:21:40 PM PDT 24
Finished Jun 04 02:21:44 PM PDT 24
Peak memory 215724 kb
Host smart-c7b2b46d-86ca-40a7-80e3-04c839f048ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126901117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1126901117
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.150375217
Short name T675
Test name
Test status
Simulation time 1899831033 ps
CPU time 9.97 seconds
Started Jun 04 02:21:40 PM PDT 24
Finished Jun 04 02:21:50 PM PDT 24
Peak memory 234944 kb
Host smart-f9e43227-6963-407c-b42c-31441eaf6378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150375217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.150375217
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2695211301
Short name T239
Test name
Test status
Simulation time 495464307 ps
CPU time 6.44 seconds
Started Jun 04 02:21:42 PM PDT 24
Finished Jun 04 02:21:49 PM PDT 24
Peak memory 219460 kb
Host smart-b8be7571-ed97-4dfc-9859-f559c9da9aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695211301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2695211301
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2374338270
Short name T600
Test name
Test status
Simulation time 767590412 ps
CPU time 4.68 seconds
Started Jun 04 02:21:40 PM PDT 24
Finished Jun 04 02:21:45 PM PDT 24
Peak memory 233792 kb
Host smart-313f16de-e00b-4ea4-b468-1df4853f5011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374338270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2374338270
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3186022014
Short name T438
Test name
Test status
Simulation time 244503084 ps
CPU time 4.28 seconds
Started Jun 04 02:21:42 PM PDT 24
Finished Jun 04 02:21:47 PM PDT 24
Peak memory 219880 kb
Host smart-a7e37af9-c0ff-4069-b7f2-98d0aa6d4fcc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3186022014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3186022014
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1031056096
Short name T813
Test name
Test status
Simulation time 9993954966 ps
CPU time 29.08 seconds
Started Jun 04 02:21:45 PM PDT 24
Finished Jun 04 02:22:15 PM PDT 24
Peak memory 224208 kb
Host smart-895bf682-e09d-401f-a37b-44e5edecda02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031056096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1031056096
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.262632393
Short name T608
Test name
Test status
Simulation time 2301549826 ps
CPU time 5.54 seconds
Started Jun 04 02:21:42 PM PDT 24
Finished Jun 04 02:21:49 PM PDT 24
Peak memory 215964 kb
Host smart-e393de4d-4fcd-4d3b-b8af-2867d1a4191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262632393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.262632393
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3287593584
Short name T510
Test name
Test status
Simulation time 2045688379 ps
CPU time 4.43 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:46 PM PDT 24
Peak memory 215840 kb
Host smart-0b7edea2-c3ab-461c-9ae0-861ad3737421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287593584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3287593584
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2227114819
Short name T966
Test name
Test status
Simulation time 181441339 ps
CPU time 2.04 seconds
Started Jun 04 02:21:40 PM PDT 24
Finished Jun 04 02:21:43 PM PDT 24
Peak memory 215908 kb
Host smart-ee090ab5-5d27-4aeb-b9e5-0a12ddfdd2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227114819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2227114819
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1596188320
Short name T701
Test name
Test status
Simulation time 135490987 ps
CPU time 0.8 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:42 PM PDT 24
Peak memory 205288 kb
Host smart-907db5cf-b31d-47fd-a5b7-fa0c82cc8f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596188320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1596188320
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2752697533
Short name T602
Test name
Test status
Simulation time 21328985703 ps
CPU time 10.49 seconds
Started Jun 04 02:21:41 PM PDT 24
Finished Jun 04 02:21:53 PM PDT 24
Peak memory 218720 kb
Host smart-59ecc014-6230-4ee0-9a68-29df1765309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752697533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2752697533
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2954312831
Short name T804
Test name
Test status
Simulation time 43970414 ps
CPU time 0.72 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:21:49 PM PDT 24
Peak memory 204920 kb
Host smart-41d1b40e-92cf-4fb2-8f26-c404918eff8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954312831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2954312831
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1112907368
Short name T921
Test name
Test status
Simulation time 416440396 ps
CPU time 7.01 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:21:55 PM PDT 24
Peak memory 232404 kb
Host smart-ef46cf4e-07f4-4861-84bf-2776715a4461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112907368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1112907368
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2095587547
Short name T650
Test name
Test status
Simulation time 35630660 ps
CPU time 0.75 seconds
Started Jun 04 02:21:48 PM PDT 24
Finished Jun 04 02:21:50 PM PDT 24
Peak memory 205856 kb
Host smart-87522412-1326-45cd-9ea7-048bebf18bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095587547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2095587547
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3296645525
Short name T171
Test name
Test status
Simulation time 11574544702 ps
CPU time 59.88 seconds
Started Jun 04 02:21:48 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 252840 kb
Host smart-6e21b7e9-9467-45d3-9ffa-be9b20e37c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296645525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3296645525
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.467547465
Short name T918
Test name
Test status
Simulation time 4099167138 ps
CPU time 24.57 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:22:12 PM PDT 24
Peak memory 217060 kb
Host smart-08e9de73-fdb3-432d-adae-07d9c1568e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467547465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.467547465
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.881307167
Short name T522
Test name
Test status
Simulation time 484291260 ps
CPU time 5.92 seconds
Started Jun 04 02:21:46 PM PDT 24
Finished Jun 04 02:21:52 PM PDT 24
Peak memory 232284 kb
Host smart-c22490d6-8969-4bfb-970b-73f84e10a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881307167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.881307167
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2640183343
Short name T757
Test name
Test status
Simulation time 787375390 ps
CPU time 9.79 seconds
Started Jun 04 02:21:48 PM PDT 24
Finished Jun 04 02:21:58 PM PDT 24
Peak memory 233000 kb
Host smart-f06db110-7cd5-48f6-b36d-01ac37815039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640183343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2640183343
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1882058393
Short name T188
Test name
Test status
Simulation time 34526747768 ps
CPU time 59.8 seconds
Started Jun 04 02:21:50 PM PDT 24
Finished Jun 04 02:22:50 PM PDT 24
Peak memory 233188 kb
Host smart-59ee2f9e-d0a2-4ecb-8dde-8c72e00ed41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882058393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1882058393
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1696032802
Short name T718
Test name
Test status
Simulation time 50500292 ps
CPU time 2.06 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:21:50 PM PDT 24
Peak memory 220892 kb
Host smart-394f67ac-9b17-413d-9441-ff0940afd079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696032802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1696032802
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.94345637
Short name T955
Test name
Test status
Simulation time 107030003 ps
CPU time 2.79 seconds
Started Jun 04 02:21:50 PM PDT 24
Finished Jun 04 02:21:53 PM PDT 24
Peak memory 233164 kb
Host smart-1717858d-1ea5-46ed-b65a-8df82235530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94345637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.94345637
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.259914789
Short name T597
Test name
Test status
Simulation time 1623778582 ps
CPU time 15.3 seconds
Started Jun 04 02:21:48 PM PDT 24
Finished Jun 04 02:22:04 PM PDT 24
Peak memory 220032 kb
Host smart-94fbf448-4676-49ef-b9c7-ba6a7c61802d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=259914789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.259914789
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1845430098
Short name T651
Test name
Test status
Simulation time 9719907928 ps
CPU time 150.09 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:24:17 PM PDT 24
Peak memory 255496 kb
Host smart-bec2b8bf-4d04-4a93-a4ca-3e10a9310ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845430098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1845430098
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4280310958
Short name T745
Test name
Test status
Simulation time 20552847868 ps
CPU time 24.7 seconds
Started Jun 04 02:21:49 PM PDT 24
Finished Jun 04 02:22:14 PM PDT 24
Peak memory 216020 kb
Host smart-b2be4bd9-ce2f-4187-803e-285a2d26e736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280310958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4280310958
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.58441259
Short name T805
Test name
Test status
Simulation time 1165032500 ps
CPU time 3.13 seconds
Started Jun 04 02:21:49 PM PDT 24
Finished Jun 04 02:21:53 PM PDT 24
Peak memory 215812 kb
Host smart-c60ffa8c-62cf-42f7-b102-be00dfc4b901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58441259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.58441259
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3942477160
Short name T661
Test name
Test status
Simulation time 119132253 ps
CPU time 1.9 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:21:50 PM PDT 24
Peak memory 215948 kb
Host smart-b33b269c-d370-4fd8-a0e3-8ebdd3b9ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942477160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3942477160
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.89228408
Short name T545
Test name
Test status
Simulation time 202779430 ps
CPU time 1.05 seconds
Started Jun 04 02:21:48 PM PDT 24
Finished Jun 04 02:21:50 PM PDT 24
Peak memory 205580 kb
Host smart-1cceecbe-026d-4267-a881-da4cdaf1708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89228408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.89228408
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3638916602
Short name T922
Test name
Test status
Simulation time 5765572315 ps
CPU time 12.3 seconds
Started Jun 04 02:21:50 PM PDT 24
Finished Jun 04 02:22:03 PM PDT 24
Peak memory 248828 kb
Host smart-645a9723-1b0d-4c89-8d4e-5d05e2a775c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638916602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3638916602
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3569157220
Short name T681
Test name
Test status
Simulation time 13370610 ps
CPU time 0.74 seconds
Started Jun 04 02:21:57 PM PDT 24
Finished Jun 04 02:21:58 PM PDT 24
Peak memory 204956 kb
Host smart-423cedbe-25da-4186-9a10-e0e6a0ec7618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569157220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3569157220
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3181370246
Short name T791
Test name
Test status
Simulation time 982814148 ps
CPU time 6.33 seconds
Started Jun 04 02:21:56 PM PDT 24
Finished Jun 04 02:22:03 PM PDT 24
Peak memory 218312 kb
Host smart-46d11fe6-c566-4dab-8f16-3e084441e9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181370246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3181370246
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3486295137
Short name T334
Test name
Test status
Simulation time 23369164 ps
CPU time 0.81 seconds
Started Jun 04 02:21:51 PM PDT 24
Finished Jun 04 02:21:52 PM PDT 24
Peak memory 205920 kb
Host smart-c8159ef8-d5e3-4930-bb8b-098d1e433974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486295137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3486295137
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3216805670
Short name T683
Test name
Test status
Simulation time 12121176 ps
CPU time 0.77 seconds
Started Jun 04 02:21:55 PM PDT 24
Finished Jun 04 02:21:57 PM PDT 24
Peak memory 215436 kb
Host smart-9dd07d5d-129a-4ce9-baef-172ab2e87ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216805670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3216805670
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3130954890
Short name T249
Test name
Test status
Simulation time 50748017904 ps
CPU time 76.53 seconds
Started Jun 04 02:21:56 PM PDT 24
Finished Jun 04 02:23:13 PM PDT 24
Peak memory 256692 kb
Host smart-5da72b50-9e6a-4639-8dea-71216873cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130954890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3130954890
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2927199677
Short name T366
Test name
Test status
Simulation time 301351860 ps
CPU time 2.56 seconds
Started Jun 04 02:21:58 PM PDT 24
Finished Jun 04 02:22:01 PM PDT 24
Peak memory 217228 kb
Host smart-b1b3349e-0c5b-4b51-bb56-35f2c49a82e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927199677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2927199677
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.934536308
Short name T577
Test name
Test status
Simulation time 5379917345 ps
CPU time 38.05 seconds
Started Jun 04 02:21:56 PM PDT 24
Finished Jun 04 02:22:35 PM PDT 24
Peak memory 232352 kb
Host smart-71485a76-a64d-47ef-b6a2-b1ce5dd066b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934536308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.934536308
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2804419275
Short name T720
Test name
Test status
Simulation time 11832971599 ps
CPU time 8.31 seconds
Started Jun 04 02:21:57 PM PDT 24
Finished Jun 04 02:22:05 PM PDT 24
Peak memory 218260 kb
Host smart-cda76594-c219-4367-babc-47c7b7c39951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804419275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2804419275
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.783251328
Short name T506
Test name
Test status
Simulation time 332412184 ps
CPU time 4.8 seconds
Started Jun 04 02:21:55 PM PDT 24
Finished Jun 04 02:22:01 PM PDT 24
Peak memory 218476 kb
Host smart-779ee2cb-f064-4e3a-9501-502c219fd429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783251328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.783251328
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2086408861
Short name T420
Test name
Test status
Simulation time 87322746 ps
CPU time 3.2 seconds
Started Jun 04 02:21:57 PM PDT 24
Finished Jun 04 02:22:01 PM PDT 24
Peak memory 233016 kb
Host smart-6d0ffddb-2b70-4554-ab8a-028794aa2baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086408861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2086408861
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2916550062
Short name T498
Test name
Test status
Simulation time 32750201 ps
CPU time 2.45 seconds
Started Jun 04 02:21:56 PM PDT 24
Finished Jun 04 02:21:59 PM PDT 24
Peak memory 220300 kb
Host smart-fa99603e-8927-4dbd-8e02-29313f1e9ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916550062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2916550062
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.508695028
Short name T953
Test name
Test status
Simulation time 2918973610 ps
CPU time 5.54 seconds
Started Jun 04 02:21:57 PM PDT 24
Finished Jun 04 02:22:03 PM PDT 24
Peak memory 219556 kb
Host smart-8f150c1a-b966-4739-be0c-94ef83cd336e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=508695028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.508695028
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.116508639
Short name T751
Test name
Test status
Simulation time 16725010406 ps
CPU time 44.75 seconds
Started Jun 04 02:21:49 PM PDT 24
Finished Jun 04 02:22:34 PM PDT 24
Peak memory 215972 kb
Host smart-332319f7-3bbc-4225-a7ff-4b5d96e779a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116508639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.116508639
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2079907834
Short name T393
Test name
Test status
Simulation time 2032361213 ps
CPU time 8.54 seconds
Started Jun 04 02:21:47 PM PDT 24
Finished Jun 04 02:21:56 PM PDT 24
Peak memory 215796 kb
Host smart-0e45c1cb-48f5-4a5f-9f83-c96705ed90fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079907834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2079907834
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.451551405
Short name T323
Test name
Test status
Simulation time 13845774 ps
CPU time 0.82 seconds
Started Jun 04 02:21:57 PM PDT 24
Finished Jun 04 02:21:58 PM PDT 24
Peak memory 206064 kb
Host smart-ea85e852-d1bd-411f-8cb7-22e6a3c51e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451551405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.451551405
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.468388388
Short name T354
Test name
Test status
Simulation time 226575406 ps
CPU time 0.77 seconds
Started Jun 04 02:21:48 PM PDT 24
Finished Jun 04 02:21:50 PM PDT 24
Peak memory 205296 kb
Host smart-bbca205b-5cb6-4eb7-ac1a-2f9d8fe502bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468388388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.468388388
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1257416132
Short name T177
Test name
Test status
Simulation time 5543835596 ps
CPU time 8.6 seconds
Started Jun 04 02:22:00 PM PDT 24
Finished Jun 04 02:22:09 PM PDT 24
Peak memory 227544 kb
Host smart-c8b9367b-4c60-4abe-b92f-158a9e9d337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257416132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1257416132
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3309602171
Short name T971
Test name
Test status
Simulation time 38159026 ps
CPU time 0.78 seconds
Started Jun 04 02:22:09 PM PDT 24
Finished Jun 04 02:22:10 PM PDT 24
Peak memory 204888 kb
Host smart-bf022a1a-9284-4a6f-8776-89cd35acddaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309602171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3309602171
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.350825429
Short name T748
Test name
Test status
Simulation time 67397729 ps
CPU time 2.29 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:22:07 PM PDT 24
Peak memory 218480 kb
Host smart-5020391b-dd56-435b-8e59-c80af597bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350825429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.350825429
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2005013931
Short name T758
Test name
Test status
Simulation time 15043183 ps
CPU time 0.76 seconds
Started Jun 04 02:21:57 PM PDT 24
Finished Jun 04 02:21:59 PM PDT 24
Peak memory 204884 kb
Host smart-f45734ae-b918-4b5d-878c-c2db179e2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005013931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2005013931
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2655801725
Short name T59
Test name
Test status
Simulation time 28692081387 ps
CPU time 47.52 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:22:53 PM PDT 24
Peak memory 224216 kb
Host smart-5fec2fce-6dcb-4f1d-818d-5a1fbc2a38db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655801725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2655801725
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1977312203
Short name T111
Test name
Test status
Simulation time 186847057179 ps
CPU time 457.11 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:29:42 PM PDT 24
Peak memory 249696 kb
Host smart-431eeecc-8f3a-4548-80bf-656f0889ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977312203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1977312203
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.550754183
Short name T426
Test name
Test status
Simulation time 1403661089 ps
CPU time 6.17 seconds
Started Jun 04 02:22:05 PM PDT 24
Finished Jun 04 02:22:13 PM PDT 24
Peak memory 224172 kb
Host smart-397ad6d1-1374-4b38-9bb0-a68aac7f24ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550754183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.550754183
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2151035707
Short name T217
Test name
Test status
Simulation time 2880793850 ps
CPU time 15.91 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:22:21 PM PDT 24
Peak memory 233472 kb
Host smart-9407f473-998e-447f-9c2c-f7cf513e9756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151035707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2151035707
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.672737777
Short name T494
Test name
Test status
Simulation time 2373187726 ps
CPU time 12.25 seconds
Started Jun 04 02:22:07 PM PDT 24
Finished Jun 04 02:22:20 PM PDT 24
Peak memory 218296 kb
Host smart-d42d5706-a90d-4a65-9b59-9b8804402f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672737777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.672737777
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4243038034
Short name T390
Test name
Test status
Simulation time 52150311 ps
CPU time 2.04 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:22:07 PM PDT 24
Peak memory 215744 kb
Host smart-527e8eb3-06c0-4237-91ad-83e973f34130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243038034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4243038034
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.748861601
Short name T696
Test name
Test status
Simulation time 3287144573 ps
CPU time 7.15 seconds
Started Jun 04 02:21:57 PM PDT 24
Finished Jun 04 02:22:05 PM PDT 24
Peak memory 233168 kb
Host smart-251489f0-96ac-4495-898a-bea7c1377a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748861601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.748861601
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3104411800
Short name T409
Test name
Test status
Simulation time 546669494 ps
CPU time 5.45 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:22:10 PM PDT 24
Peak memory 221676 kb
Host smart-2bb0fae0-4e0a-4fbe-aa59-c8a22bcdaeb3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3104411800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3104411800
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.674991443
Short name T766
Test name
Test status
Simulation time 1295123480 ps
CPU time 29.51 seconds
Started Jun 04 02:22:06 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 248872 kb
Host smart-4f3ce946-23d6-4178-a206-9f1b0c5e6452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674991443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.674991443
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2828980915
Short name T518
Test name
Test status
Simulation time 1546916373 ps
CPU time 12.32 seconds
Started Jun 04 02:21:56 PM PDT 24
Finished Jun 04 02:22:09 PM PDT 24
Peak memory 216168 kb
Host smart-13b561b7-3ae8-4f4e-ab34-31986d85c147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828980915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2828980915
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.785912936
Short name T55
Test name
Test status
Simulation time 5212658541 ps
CPU time 8.27 seconds
Started Jun 04 02:21:58 PM PDT 24
Finished Jun 04 02:22:07 PM PDT 24
Peak memory 215964 kb
Host smart-62ab0a7c-9293-419d-812b-3b88c8e41284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785912936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.785912936
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2621864677
Short name T557
Test name
Test status
Simulation time 66378311 ps
CPU time 1.31 seconds
Started Jun 04 02:21:57 PM PDT 24
Finished Jun 04 02:21:59 PM PDT 24
Peak memory 207468 kb
Host smart-3086e771-5223-4d02-ab75-35cefb8be8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621864677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2621864677
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3682415390
Short name T128
Test name
Test status
Simulation time 107522139 ps
CPU time 0.79 seconds
Started Jun 04 02:21:58 PM PDT 24
Finished Jun 04 02:21:59 PM PDT 24
Peak memory 205292 kb
Host smart-d876dd83-99b1-47cf-b532-4783824d0f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682415390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3682415390
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.832357391
Short name T182
Test name
Test status
Simulation time 3204782457 ps
CPU time 7.86 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:22:12 PM PDT 24
Peak memory 237728 kb
Host smart-bdd0e16c-e56a-4386-90ca-ee71d76711e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832357391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.832357391
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.651017849
Short name T972
Test name
Test status
Simulation time 12703489 ps
CPU time 0.7 seconds
Started Jun 04 02:22:07 PM PDT 24
Finished Jun 04 02:22:08 PM PDT 24
Peak memory 204264 kb
Host smart-41098063-b4c5-4c54-8168-e995d72bd04d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651017849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.651017849
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1294907672
Short name T965
Test name
Test status
Simulation time 872103975 ps
CPU time 3.64 seconds
Started Jun 04 02:22:07 PM PDT 24
Finished Jun 04 02:22:11 PM PDT 24
Peak memory 218104 kb
Host smart-3a71e5aa-fed6-421d-bc01-e8b9202e8b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294907672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1294907672
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1107093218
Short name T475
Test name
Test status
Simulation time 31177196 ps
CPU time 0.75 seconds
Started Jun 04 02:22:06 PM PDT 24
Finished Jun 04 02:22:07 PM PDT 24
Peak memory 205936 kb
Host smart-510e96aa-aefc-4c40-913e-672d61db6b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107093218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1107093218
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.691726953
Short name T776
Test name
Test status
Simulation time 24734104247 ps
CPU time 283.24 seconds
Started Jun 04 02:22:06 PM PDT 24
Finished Jun 04 02:26:50 PM PDT 24
Peak memory 254672 kb
Host smart-93fc1578-ace1-4778-983d-6667a82dec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691726953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.691726953
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1063726313
Short name T174
Test name
Test status
Simulation time 10481949664 ps
CPU time 35.25 seconds
Started Jun 04 02:22:05 PM PDT 24
Finished Jun 04 02:22:41 PM PDT 24
Peak memory 236724 kb
Host smart-79a0b4a1-746b-42de-ab2b-e05b7988a30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063726313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1063726313
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.205944957
Short name T309
Test name
Test status
Simulation time 876366312 ps
CPU time 10.13 seconds
Started Jun 04 02:22:05 PM PDT 24
Finished Jun 04 02:22:16 PM PDT 24
Peak memory 248776 kb
Host smart-e3eb4927-2dd2-493a-a203-332cc6624126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205944957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.205944957
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1343468447
Short name T453
Test name
Test status
Simulation time 108940856 ps
CPU time 2.62 seconds
Started Jun 04 02:22:05 PM PDT 24
Finished Jun 04 02:22:08 PM PDT 24
Peak memory 220704 kb
Host smart-bf9d7f64-14a9-4c96-b08c-cc9989199311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343468447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1343468447
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.66406549
Short name T945
Test name
Test status
Simulation time 301078923 ps
CPU time 2.95 seconds
Started Jun 04 02:22:05 PM PDT 24
Finished Jun 04 02:22:09 PM PDT 24
Peak memory 218056 kb
Host smart-2b526ddd-d978-4b2d-b82d-b0ad7a4427f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66406549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.66406549
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3799058372
Short name T647
Test name
Test status
Simulation time 258460539 ps
CPU time 2.93 seconds
Started Jun 04 02:22:02 PM PDT 24
Finished Jun 04 02:22:05 PM PDT 24
Peak memory 233388 kb
Host smart-2157a4eb-6044-4ace-bb29-1371f8403192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799058372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3799058372
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4194653883
Short name T692
Test name
Test status
Simulation time 151239301 ps
CPU time 3.73 seconds
Started Jun 04 02:22:05 PM PDT 24
Finished Jun 04 02:22:09 PM PDT 24
Peak memory 222496 kb
Host smart-1ed2cf53-3c4a-4129-962a-eecb5136ef09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4194653883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4194653883
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.682156371
Short name T240
Test name
Test status
Simulation time 11892380512 ps
CPU time 133.53 seconds
Started Jun 04 02:22:03 PM PDT 24
Finished Jun 04 02:24:17 PM PDT 24
Peak memory 250308 kb
Host smart-31bba99a-2068-463f-a1b7-8cde50e5ef1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682156371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.682156371
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3945458657
Short name T654
Test name
Test status
Simulation time 3357873525 ps
CPU time 7.55 seconds
Started Jun 04 02:22:04 PM PDT 24
Finished Jun 04 02:22:12 PM PDT 24
Peak memory 217516 kb
Host smart-a6cb0c6b-2666-47ae-9736-7fac38051203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945458657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3945458657
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3581063712
Short name T19
Test name
Test status
Simulation time 16690868765 ps
CPU time 13.9 seconds
Started Jun 04 02:22:05 PM PDT 24
Finished Jun 04 02:22:20 PM PDT 24
Peak memory 215940 kb
Host smart-a4c67c05-e0d4-41be-a279-91d0bf88348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581063712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3581063712
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1695748021
Short name T74
Test name
Test status
Simulation time 731194675 ps
CPU time 2.18 seconds
Started Jun 04 02:22:06 PM PDT 24
Finished Jun 04 02:22:09 PM PDT 24
Peak memory 215940 kb
Host smart-957cc59d-9d47-4f37-afdb-f6f2711eacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695748021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1695748021
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.268039167
Short name T749
Test name
Test status
Simulation time 37216027 ps
CPU time 0.67 seconds
Started Jun 04 02:22:07 PM PDT 24
Finished Jun 04 02:22:08 PM PDT 24
Peak memory 204932 kb
Host smart-8fbed5a6-33d7-416e-858e-15de56e0a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268039167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.268039167
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2682028516
Short name T206
Test name
Test status
Simulation time 14976515658 ps
CPU time 16.06 seconds
Started Jun 04 02:22:06 PM PDT 24
Finished Jun 04 02:22:23 PM PDT 24
Peak memory 233384 kb
Host smart-d1af5531-c6d2-4ec2-bf80-6412182a9541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682028516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2682028516
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3245179025
Short name T837
Test name
Test status
Simulation time 70270880 ps
CPU time 0.75 seconds
Started Jun 04 02:22:15 PM PDT 24
Finished Jun 04 02:22:17 PM PDT 24
Peak memory 204908 kb
Host smart-911e9f05-6030-44d7-bd0d-0d6d1b869bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245179025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3245179025
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1506760206
Short name T845
Test name
Test status
Simulation time 8145043025 ps
CPU time 22.45 seconds
Started Jun 04 02:22:11 PM PDT 24
Finished Jun 04 02:22:35 PM PDT 24
Peak memory 234272 kb
Host smart-962f589b-55bc-4d87-a6ac-c538b2f2c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506760206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1506760206
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1649476770
Short name T961
Test name
Test status
Simulation time 14893258 ps
CPU time 0.75 seconds
Started Jun 04 02:22:12 PM PDT 24
Finished Jun 04 02:22:14 PM PDT 24
Peak memory 205844 kb
Host smart-595907fb-c2a2-46d6-bb45-3ef2ea4631a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649476770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1649476770
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.242176302
Short name T555
Test name
Test status
Simulation time 64233245338 ps
CPU time 148.61 seconds
Started Jun 04 02:22:10 PM PDT 24
Finished Jun 04 02:24:40 PM PDT 24
Peak memory 254112 kb
Host smart-9a960048-0c2d-462e-bb62-f2191c1b838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242176302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.242176302
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3596115259
Short name T698
Test name
Test status
Simulation time 2160983042 ps
CPU time 20.07 seconds
Started Jun 04 02:22:13 PM PDT 24
Finished Jun 04 02:22:34 PM PDT 24
Peak memory 232444 kb
Host smart-5647213a-f37c-49d5-8e88-133f6a17a068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596115259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3596115259
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1976275608
Short name T866
Test name
Test status
Simulation time 2927771905 ps
CPU time 26.74 seconds
Started Jun 04 02:22:11 PM PDT 24
Finished Jun 04 02:22:39 PM PDT 24
Peak memory 233452 kb
Host smart-6aabf8c7-6b9b-4217-a6d4-0e88f7a4ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976275608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1976275608
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4042003326
Short name T57
Test name
Test status
Simulation time 1093230858 ps
CPU time 9.69 seconds
Started Jun 04 02:22:14 PM PDT 24
Finished Jun 04 02:22:24 PM PDT 24
Peak memory 224148 kb
Host smart-53327502-04bb-4b9e-8636-3bea60298d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042003326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4042003326
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3256021524
Short name T110
Test name
Test status
Simulation time 838621292 ps
CPU time 4.38 seconds
Started Jun 04 02:22:09 PM PDT 24
Finished Jun 04 02:22:14 PM PDT 24
Peak memory 233324 kb
Host smart-e15dc315-2a4f-45f2-9ae5-04790e6ada36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256021524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3256021524
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.965416329
Short name T642
Test name
Test status
Simulation time 1695747238 ps
CPU time 10.67 seconds
Started Jun 04 02:22:10 PM PDT 24
Finished Jun 04 02:22:21 PM PDT 24
Peak memory 233384 kb
Host smart-6149b207-3ec0-4172-b990-c4c3f8a61a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965416329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.965416329
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3506332004
Short name T21
Test name
Test status
Simulation time 415035554 ps
CPU time 4.7 seconds
Started Jun 04 02:22:15 PM PDT 24
Finished Jun 04 02:22:20 PM PDT 24
Peak memory 220064 kb
Host smart-a6726b26-e9f8-431d-957d-31947cf05aa9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3506332004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3506332004
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2554666298
Short name T161
Test name
Test status
Simulation time 9804334699 ps
CPU time 66.96 seconds
Started Jun 04 02:22:09 PM PDT 24
Finished Jun 04 02:23:17 PM PDT 24
Peak memory 256256 kb
Host smart-0da55a40-a961-48bf-b168-89c27b28d3ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554666298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2554666298
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2903312566
Short name T449
Test name
Test status
Simulation time 11813065824 ps
CPU time 28.65 seconds
Started Jun 04 02:22:12 PM PDT 24
Finished Jun 04 02:22:42 PM PDT 24
Peak memory 215996 kb
Host smart-786e329c-1ea6-4ba8-b9d7-b9a8b87a25fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903312566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2903312566
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4166598786
Short name T386
Test name
Test status
Simulation time 4466388105 ps
CPU time 6.65 seconds
Started Jun 04 02:22:13 PM PDT 24
Finished Jun 04 02:22:20 PM PDT 24
Peak memory 215868 kb
Host smart-9e921b08-5dfe-4bfc-8688-1f87c7f77635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166598786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4166598786
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1650308495
Short name T151
Test name
Test status
Simulation time 41517669 ps
CPU time 0.69 seconds
Started Jun 04 02:22:11 PM PDT 24
Finished Jun 04 02:22:13 PM PDT 24
Peak memory 204928 kb
Host smart-2bf24124-eafa-474c-af7e-1a8a9c41e2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650308495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1650308495
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2475667581
Short name T910
Test name
Test status
Simulation time 181268896 ps
CPU time 0.87 seconds
Started Jun 04 02:22:09 PM PDT 24
Finished Jun 04 02:22:10 PM PDT 24
Peak memory 205292 kb
Host smart-57567b0c-1ca1-4b9c-b998-af198786c532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475667581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2475667581
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3975216760
Short name T761
Test name
Test status
Simulation time 9452350190 ps
CPU time 15.11 seconds
Started Jun 04 02:22:09 PM PDT 24
Finished Jun 04 02:22:25 PM PDT 24
Peak memory 217420 kb
Host smart-466ccb7d-6e0d-4366-a8e0-c86f6fbbc363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975216760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3975216760
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3399805551
Short name T326
Test name
Test status
Simulation time 19777921 ps
CPU time 0.75 seconds
Started Jun 04 02:22:18 PM PDT 24
Finished Jun 04 02:22:19 PM PDT 24
Peak memory 204908 kb
Host smart-07237280-9332-41f5-a34f-9254fbb767af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399805551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3399805551
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3024734554
Short name T396
Test name
Test status
Simulation time 113983255 ps
CPU time 2.18 seconds
Started Jun 04 02:22:17 PM PDT 24
Finished Jun 04 02:22:20 PM PDT 24
Peak memory 220848 kb
Host smart-be4751d6-4d04-471c-b68b-ed452390e921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024734554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3024734554
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2441655498
Short name T474
Test name
Test status
Simulation time 15520093 ps
CPU time 0.78 seconds
Started Jun 04 02:22:12 PM PDT 24
Finished Jun 04 02:22:14 PM PDT 24
Peak memory 205892 kb
Host smart-360cb3fa-8a25-4708-a0bd-31eeb057a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441655498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2441655498
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.887979058
Short name T962
Test name
Test status
Simulation time 4293087154 ps
CPU time 57.46 seconds
Started Jun 04 02:22:18 PM PDT 24
Finished Jun 04 02:23:16 PM PDT 24
Peak memory 248824 kb
Host smart-3ec3d92c-1ef9-4f26-b577-6287469797c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887979058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.887979058
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3139627173
Short name T957
Test name
Test status
Simulation time 14259975876 ps
CPU time 36.79 seconds
Started Jun 04 02:22:23 PM PDT 24
Finished Jun 04 02:23:01 PM PDT 24
Peak memory 219216 kb
Host smart-9f001d01-8d50-4b01-8bff-b79d2cc53fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139627173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3139627173
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3440466749
Short name T234
Test name
Test status
Simulation time 12567946257 ps
CPU time 78.19 seconds
Started Jun 04 02:22:17 PM PDT 24
Finished Jun 04 02:23:36 PM PDT 24
Peak memory 248832 kb
Host smart-cfe1700e-40f0-4985-98bd-796e5888e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440466749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3440466749
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2582054631
Short name T336
Test name
Test status
Simulation time 1264515822 ps
CPU time 13.47 seconds
Started Jun 04 02:22:18 PM PDT 24
Finished Jun 04 02:22:32 PM PDT 24
Peak memory 239796 kb
Host smart-614eaead-3b98-494b-8eeb-ca745f11ef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582054631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2582054631
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.96856531
Short name T832
Test name
Test status
Simulation time 98227023 ps
CPU time 3.49 seconds
Started Jun 04 02:22:11 PM PDT 24
Finished Jun 04 02:22:16 PM PDT 24
Peak memory 232928 kb
Host smart-d5461a5d-e68b-4ced-8bd1-0f7907072b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96856531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.96856531
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3214394585
Short name T505
Test name
Test status
Simulation time 17374005732 ps
CPU time 44.41 seconds
Started Jun 04 02:22:17 PM PDT 24
Finished Jun 04 02:23:02 PM PDT 24
Peak memory 247112 kb
Host smart-ea763f88-ea58-4dd9-b81f-3fcd7b5e6b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214394585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3214394585
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1874461708
Short name T43
Test name
Test status
Simulation time 3880755807 ps
CPU time 13.83 seconds
Started Jun 04 02:22:12 PM PDT 24
Finished Jun 04 02:22:27 PM PDT 24
Peak memory 233368 kb
Host smart-22ee0bb2-719c-40f5-8445-908dcfd11d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874461708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1874461708
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2616896452
Short name T570
Test name
Test status
Simulation time 363423223 ps
CPU time 3.54 seconds
Started Jun 04 02:22:13 PM PDT 24
Finished Jun 04 02:22:17 PM PDT 24
Peak memory 218400 kb
Host smart-c8f4bae2-7b67-46bb-b6e1-b70634e271c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616896452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2616896452
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3884905184
Short name T937
Test name
Test status
Simulation time 8138506650 ps
CPU time 10.19 seconds
Started Jun 04 02:22:16 PM PDT 24
Finished Jun 04 02:22:27 PM PDT 24
Peak memory 222612 kb
Host smart-5e12db0b-9d98-48c8-8e33-250339e8d334
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3884905184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3884905184
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3557292041
Short name T34
Test name
Test status
Simulation time 33781827291 ps
CPU time 167.17 seconds
Started Jun 04 02:22:21 PM PDT 24
Finished Jun 04 02:25:09 PM PDT 24
Peak memory 249920 kb
Host smart-12254f9f-3ef2-46b6-99f7-803810628c26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557292041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3557292041
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2528031718
Short name T440
Test name
Test status
Simulation time 1547110284 ps
CPU time 23.3 seconds
Started Jun 04 02:22:13 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 215908 kb
Host smart-29fd18df-e390-4ddb-aafd-c527b0392248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528031718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2528031718
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.44179075
Short name T553
Test name
Test status
Simulation time 77063696828 ps
CPU time 19.14 seconds
Started Jun 04 02:22:09 PM PDT 24
Finished Jun 04 02:22:29 PM PDT 24
Peak memory 215824 kb
Host smart-f081cfd8-c5f7-4235-9cf3-7e663eca8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44179075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.44179075
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4000460383
Short name T779
Test name
Test status
Simulation time 72194954 ps
CPU time 1.04 seconds
Started Jun 04 02:22:10 PM PDT 24
Finished Jun 04 02:22:11 PM PDT 24
Peak memory 207436 kb
Host smart-10c5154b-d61e-4fde-a4cc-09c0867f29ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000460383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4000460383
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.474511532
Short name T543
Test name
Test status
Simulation time 48228632 ps
CPU time 0.87 seconds
Started Jun 04 02:22:11 PM PDT 24
Finished Jun 04 02:22:13 PM PDT 24
Peak memory 205288 kb
Host smart-61c74d1e-51f1-426c-9701-d7b4253dcec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474511532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.474511532
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4063417636
Short name T631
Test name
Test status
Simulation time 11133182044 ps
CPU time 24.71 seconds
Started Jun 04 02:22:23 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 238508 kb
Host smart-42e28998-87b0-4da7-a5f8-cf1215cdccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063417636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4063417636
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4207324107
Short name T523
Test name
Test status
Simulation time 22066381 ps
CPU time 0.7 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:22:27 PM PDT 24
Peak memory 204288 kb
Host smart-de3c9da6-d46c-4700-9c23-88042c178e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207324107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4207324107
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.779634478
Short name T587
Test name
Test status
Simulation time 275432659 ps
CPU time 2.58 seconds
Started Jun 04 02:22:19 PM PDT 24
Finished Jun 04 02:22:22 PM PDT 24
Peak memory 218424 kb
Host smart-63524a1c-3d17-47a2-a1df-dc988801a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779634478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.779634478
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3585276557
Short name T700
Test name
Test status
Simulation time 18810668 ps
CPU time 0.85 seconds
Started Jun 04 02:22:19 PM PDT 24
Finished Jun 04 02:22:20 PM PDT 24
Peak memory 205896 kb
Host smart-4acdbc4f-46a6-48fe-b5e0-db680297bb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585276557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3585276557
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2419579334
Short name T581
Test name
Test status
Simulation time 7999789222 ps
CPU time 58.97 seconds
Started Jun 04 02:22:29 PM PDT 24
Finished Jun 04 02:23:29 PM PDT 24
Peak memory 239404 kb
Host smart-10d7cf66-f5a8-4205-a46b-fea204effca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419579334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2419579334
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.728540849
Short name T973
Test name
Test status
Simulation time 3794988990 ps
CPU time 93.19 seconds
Started Jun 04 02:22:24 PM PDT 24
Finished Jun 04 02:23:59 PM PDT 24
Peak memory 256096 kb
Host smart-3fe1efc3-54fe-49d0-b62d-aedc83792e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728540849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.728540849
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3799159095
Short name T746
Test name
Test status
Simulation time 2221481571 ps
CPU time 27.43 seconds
Started Jun 04 02:22:28 PM PDT 24
Finished Jun 04 02:22:56 PM PDT 24
Peak memory 224248 kb
Host smart-edb50688-5fea-4d15-a30a-ac999ff431c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799159095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3799159095
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1970720115
Short name T364
Test name
Test status
Simulation time 2954280710 ps
CPU time 22.64 seconds
Started Jun 04 02:22:18 PM PDT 24
Finished Jun 04 02:22:42 PM PDT 24
Peak memory 232464 kb
Host smart-a4351916-ff7e-4f3a-889b-5e6ffc88047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970720115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1970720115
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3982300094
Short name T605
Test name
Test status
Simulation time 9792023549 ps
CPU time 14.57 seconds
Started Jun 04 02:22:19 PM PDT 24
Finished Jun 04 02:22:34 PM PDT 24
Peak memory 219192 kb
Host smart-9314e63d-0f95-4c0f-8724-a06c4e578b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982300094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3982300094
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.478583200
Short name T879
Test name
Test status
Simulation time 6469499788 ps
CPU time 44.15 seconds
Started Jun 04 02:22:21 PM PDT 24
Finished Jun 04 02:23:06 PM PDT 24
Peak memory 240652 kb
Host smart-2d31e291-d3b1-46e2-bde2-73ee79ceca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478583200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.478583200
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.46939680
Short name T807
Test name
Test status
Simulation time 17108205940 ps
CPU time 15.51 seconds
Started Jun 04 02:22:17 PM PDT 24
Finished Jun 04 02:22:33 PM PDT 24
Peak memory 237748 kb
Host smart-049e7a82-0cb0-42d5-8bb0-2202f78d5755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46939680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.46939680
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1289053674
Short name T607
Test name
Test status
Simulation time 129353368 ps
CPU time 2.67 seconds
Started Jun 04 02:22:17 PM PDT 24
Finished Jun 04 02:22:20 PM PDT 24
Peak memory 232384 kb
Host smart-01ca0598-0435-46e1-9516-80a4a9993b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289053674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1289053674
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1825475817
Short name T694
Test name
Test status
Simulation time 2665881751 ps
CPU time 4.89 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:22:31 PM PDT 24
Peak memory 219736 kb
Host smart-af4b1f92-3803-439a-95cf-cc1cf65a375f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1825475817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1825475817
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1068728768
Short name T419
Test name
Test status
Simulation time 6968459996 ps
CPU time 18.78 seconds
Started Jun 04 02:22:17 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 219244 kb
Host smart-d56f8ece-f1cd-4b6a-ac97-9b2d434ba9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068728768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1068728768
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3470875168
Short name T532
Test name
Test status
Simulation time 2580375416 ps
CPU time 3.53 seconds
Started Jun 04 02:22:24 PM PDT 24
Finished Jun 04 02:22:28 PM PDT 24
Peak memory 215852 kb
Host smart-51cdb585-ff45-4822-a31c-adb809cf104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470875168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3470875168
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1192347546
Short name T934
Test name
Test status
Simulation time 38130102 ps
CPU time 1.13 seconds
Started Jun 04 02:22:17 PM PDT 24
Finished Jun 04 02:22:19 PM PDT 24
Peak memory 207024 kb
Host smart-69393596-9852-496a-8a03-a6adec035d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192347546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1192347546
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1203664882
Short name T330
Test name
Test status
Simulation time 88254606 ps
CPU time 0.91 seconds
Started Jun 04 02:22:18 PM PDT 24
Finished Jun 04 02:22:20 PM PDT 24
Peak memory 205296 kb
Host smart-b29811eb-77fa-4caf-a9ce-43679646ec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203664882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1203664882
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3424423797
Short name T565
Test name
Test status
Simulation time 13794362600 ps
CPU time 11.45 seconds
Started Jun 04 02:22:22 PM PDT 24
Finished Jun 04 02:22:34 PM PDT 24
Peak memory 229404 kb
Host smart-2eabee89-45a6-46fb-a586-1607be161397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424423797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3424423797
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3697979259
Short name T821
Test name
Test status
Simulation time 13485988 ps
CPU time 0.71 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:17 PM PDT 24
Peak memory 205268 kb
Host smart-2c23ad55-dde1-4578-8dd6-721e7b786241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697979259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
697979259
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1573955185
Short name T191
Test name
Test status
Simulation time 770746473 ps
CPU time 2.82 seconds
Started Jun 04 02:19:07 PM PDT 24
Finished Jun 04 02:19:11 PM PDT 24
Peak memory 235840 kb
Host smart-12a0f883-89e2-485f-a313-58a276d8eb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573955185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1573955185
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3329676364
Short name T14
Test name
Test status
Simulation time 49123951 ps
CPU time 0.77 seconds
Started Jun 04 02:19:05 PM PDT 24
Finished Jun 04 02:19:07 PM PDT 24
Peak memory 204848 kb
Host smart-56de8a7d-d0ec-4387-ae6f-d668c5102a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329676364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3329676364
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3819554401
Short name T404
Test name
Test status
Simulation time 2385700093 ps
CPU time 14.67 seconds
Started Jun 04 02:19:11 PM PDT 24
Finished Jun 04 02:19:26 PM PDT 24
Peak memory 238056 kb
Host smart-8ec2e6c1-8828-48f1-8937-447a1377100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819554401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3819554401
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2970778494
Short name T888
Test name
Test status
Simulation time 12067376287 ps
CPU time 82.72 seconds
Started Jun 04 02:19:06 PM PDT 24
Finished Jun 04 02:20:30 PM PDT 24
Peak memory 250448 kb
Host smart-d014a749-ec5c-4000-8466-59df9d8863eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970778494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2970778494
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.291272472
Short name T264
Test name
Test status
Simulation time 39311964887 ps
CPU time 133.07 seconds
Started Jun 04 02:19:07 PM PDT 24
Finished Jun 04 02:21:21 PM PDT 24
Peak memory 248888 kb
Host smart-baeb28f5-9ad6-4681-8143-211dfc9189b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291272472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
291272472
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4228425574
Short name T339
Test name
Test status
Simulation time 322894487 ps
CPU time 4.65 seconds
Started Jun 04 02:19:10 PM PDT 24
Finished Jun 04 02:19:15 PM PDT 24
Peak memory 234836 kb
Host smart-cea80e7d-7f1e-4d76-9eac-14e2108750f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228425574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4228425574
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1586767295
Short name T939
Test name
Test status
Simulation time 2221565786 ps
CPU time 8.04 seconds
Started Jun 04 02:19:10 PM PDT 24
Finished Jun 04 02:19:19 PM PDT 24
Peak memory 233444 kb
Host smart-c1a8ddd6-8882-4d06-808f-96bf544aa5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586767295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1586767295
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2607623970
Short name T929
Test name
Test status
Simulation time 6697229008 ps
CPU time 15.01 seconds
Started Jun 04 02:19:07 PM PDT 24
Finished Jun 04 02:19:23 PM PDT 24
Peak memory 224192 kb
Host smart-11f5fc7b-53f6-4d1e-82b8-ccd271e5948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607623970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2607623970
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1004206703
Short name T469
Test name
Test status
Simulation time 31393202 ps
CPU time 1.02 seconds
Started Jun 04 02:19:08 PM PDT 24
Finished Jun 04 02:19:10 PM PDT 24
Peak memory 217452 kb
Host smart-147db26f-ef5c-4049-a21e-a6213b21a82e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004206703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1004206703
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1083273584
Short name T517
Test name
Test status
Simulation time 13655384605 ps
CPU time 16.32 seconds
Started Jun 04 02:19:09 PM PDT 24
Finished Jun 04 02:19:26 PM PDT 24
Peak memory 240516 kb
Host smart-01646318-8f35-471d-88a0-0a8a8c0dc7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083273584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1083273584
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1282673127
Short name T784
Test name
Test status
Simulation time 125189634 ps
CPU time 2.67 seconds
Started Jun 04 02:19:07 PM PDT 24
Finished Jun 04 02:19:11 PM PDT 24
Peak memory 233144 kb
Host smart-273dd2d6-ced0-448f-bcad-57e23274f17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282673127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1282673127
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.647252931
Short name T516
Test name
Test status
Simulation time 622121187 ps
CPU time 7.83 seconds
Started Jun 04 02:19:06 PM PDT 24
Finished Jun 04 02:19:15 PM PDT 24
Peak memory 222044 kb
Host smart-d9db59d8-e3b8-4dc0-9ff6-b55bc6aea3a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=647252931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.647252931
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2484201607
Short name T66
Test name
Test status
Simulation time 214299749 ps
CPU time 1.06 seconds
Started Jun 04 02:19:14 PM PDT 24
Finished Jun 04 02:19:16 PM PDT 24
Peak memory 234676 kb
Host smart-5a02c63f-7b35-4948-97b1-64f5c9d5297b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484201607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2484201607
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.4001755890
Short name T160
Test name
Test status
Simulation time 36630795256 ps
CPU time 122.13 seconds
Started Jun 04 02:19:08 PM PDT 24
Finished Jun 04 02:21:11 PM PDT 24
Peak memory 264184 kb
Host smart-c292f9be-8fda-4cc6-a2db-a6d54a545092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001755890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.4001755890
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2991337998
Short name T670
Test name
Test status
Simulation time 16089953451 ps
CPU time 18.35 seconds
Started Jun 04 02:19:09 PM PDT 24
Finished Jun 04 02:19:28 PM PDT 24
Peak memory 215996 kb
Host smart-679f0494-f201-471b-82bc-4d98ad520314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991337998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2991337998
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3128727302
Short name T538
Test name
Test status
Simulation time 15508450040 ps
CPU time 10.75 seconds
Started Jun 04 02:19:07 PM PDT 24
Finished Jun 04 02:19:19 PM PDT 24
Peak memory 215892 kb
Host smart-96deabc6-3f30-44b0-8b62-f3f4b30ac405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128727302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3128727302
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3785028273
Short name T387
Test name
Test status
Simulation time 18727250 ps
CPU time 0.75 seconds
Started Jun 04 02:19:07 PM PDT 24
Finished Jun 04 02:19:09 PM PDT 24
Peak memory 205312 kb
Host smart-a36739b3-e291-49f0-8cdd-baf4ef903dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785028273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3785028273
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3690286211
Short name T841
Test name
Test status
Simulation time 70785617 ps
CPU time 0.85 seconds
Started Jun 04 02:19:05 PM PDT 24
Finished Jun 04 02:19:06 PM PDT 24
Peak memory 205292 kb
Host smart-f5991afb-eca9-4dcc-8017-45f12d5fae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690286211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3690286211
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.117788858
Short name T296
Test name
Test status
Simulation time 405569367 ps
CPU time 6.67 seconds
Started Jun 04 02:19:12 PM PDT 24
Finished Jun 04 02:19:19 PM PDT 24
Peak memory 223880 kb
Host smart-c9e22690-7cbc-4f63-8851-3248b11a57b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117788858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.117788858
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3403842667
Short name T540
Test name
Test status
Simulation time 31522597 ps
CPU time 0.71 seconds
Started Jun 04 02:22:24 PM PDT 24
Finished Jun 04 02:22:26 PM PDT 24
Peak memory 204896 kb
Host smart-5cf1b71d-8180-43c3-9128-b8e45114e004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403842667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3403842667
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.805012239
Short name T714
Test name
Test status
Simulation time 151785820 ps
CPU time 2.56 seconds
Started Jun 04 02:22:29 PM PDT 24
Finished Jun 04 02:22:32 PM PDT 24
Peak memory 233372 kb
Host smart-d0040718-9f7e-4859-962f-a6c440d9e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805012239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.805012239
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.897865824
Short name T793
Test name
Test status
Simulation time 14683715 ps
CPU time 0.73 seconds
Started Jun 04 02:22:23 PM PDT 24
Finished Jun 04 02:22:25 PM PDT 24
Peak memory 205936 kb
Host smart-4c51b3c2-ca34-401f-8ac1-8a22d68ca5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897865824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.897865824
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1511307991
Short name T715
Test name
Test status
Simulation time 29811858 ps
CPU time 0.77 seconds
Started Jun 04 02:22:29 PM PDT 24
Finished Jun 04 02:22:31 PM PDT 24
Peak memory 215568 kb
Host smart-1740b6a3-ac99-42db-9ba8-0aae28879859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511307991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1511307991
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1475551548
Short name T236
Test name
Test status
Simulation time 50869898447 ps
CPU time 522.95 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:31:09 PM PDT 24
Peak memory 265020 kb
Host smart-c58c19fd-0524-43ab-afb6-89f3fe3464a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475551548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1475551548
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2098570791
Short name T721
Test name
Test status
Simulation time 20292263822 ps
CPU time 38.32 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:23:04 PM PDT 24
Peak memory 221832 kb
Host smart-cee4a773-a03b-442b-a720-6fb66036647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098570791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2098570791
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2116009620
Short name T825
Test name
Test status
Simulation time 7431547886 ps
CPU time 26.8 seconds
Started Jun 04 02:22:29 PM PDT 24
Finished Jun 04 02:22:56 PM PDT 24
Peak memory 240624 kb
Host smart-110c7cfa-7986-4f85-921c-c628286be80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116009620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2116009620
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.688720426
Short name T514
Test name
Test status
Simulation time 325064867 ps
CPU time 6.69 seconds
Started Jun 04 02:22:26 PM PDT 24
Finished Jun 04 02:22:34 PM PDT 24
Peak memory 218208 kb
Host smart-62f4659e-60f4-4d6e-9065-9fafc5972e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688720426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.688720426
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3870262276
Short name T435
Test name
Test status
Simulation time 7236187838 ps
CPU time 54.49 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:23:20 PM PDT 24
Peak memory 233604 kb
Host smart-65537863-0eeb-4bd8-82c4-16f6b1c4419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870262276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3870262276
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2714621224
Short name T256
Test name
Test status
Simulation time 589909720 ps
CPU time 7.28 seconds
Started Jun 04 02:22:24 PM PDT 24
Finished Jun 04 02:22:32 PM PDT 24
Peak memory 222428 kb
Host smart-2b87c7e3-c79c-4b4e-9139-239cd30de3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714621224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2714621224
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2690331651
Short name T207
Test name
Test status
Simulation time 5717271172 ps
CPU time 19.72 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:22:46 PM PDT 24
Peak memory 222364 kb
Host smart-2d844b66-24d9-46aa-adc6-a45a0a9acf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690331651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2690331651
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2590557826
Short name T479
Test name
Test status
Simulation time 819855035 ps
CPU time 12.27 seconds
Started Jun 04 02:22:24 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 222452 kb
Host smart-7e554cb8-8c8f-4a1f-aec4-3dcc3f77d634
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590557826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2590557826
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.256766215
Short name T509
Test name
Test status
Simulation time 21936670885 ps
CPU time 260.53 seconds
Started Jun 04 02:22:29 PM PDT 24
Finished Jun 04 02:26:50 PM PDT 24
Peak memory 251756 kb
Host smart-b4664cce-28ff-4810-b9d8-d78de2aa7d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256766215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.256766215
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2791929258
Short name T671
Test name
Test status
Simulation time 2884733130 ps
CPU time 25.45 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:22:52 PM PDT 24
Peak memory 215968 kb
Host smart-b2759c0d-c561-4dbd-9e20-7f5832c6fdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791929258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2791929258
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1077301060
Short name T150
Test name
Test status
Simulation time 38545804 ps
CPU time 0.71 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:22:27 PM PDT 24
Peak memory 205008 kb
Host smart-3cd9367d-2201-4475-a078-23c399661758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077301060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1077301060
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1615908421
Short name T392
Test name
Test status
Simulation time 49190993 ps
CPU time 0.86 seconds
Started Jun 04 02:22:24 PM PDT 24
Finished Jun 04 02:22:26 PM PDT 24
Peak memory 207452 kb
Host smart-bfbeebef-e99c-451a-b383-c7ba18f2c0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615908421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1615908421
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2420822170
Short name T623
Test name
Test status
Simulation time 64484332 ps
CPU time 0.98 seconds
Started Jun 04 02:22:24 PM PDT 24
Finished Jun 04 02:22:26 PM PDT 24
Peak memory 205268 kb
Host smart-fc520a65-e329-4d44-97c8-d9ab54372b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420822170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2420822170
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.632540095
Short name T868
Test name
Test status
Simulation time 306202107 ps
CPU time 2.95 seconds
Started Jun 04 02:22:26 PM PDT 24
Finished Jun 04 02:22:30 PM PDT 24
Peak memory 233196 kb
Host smart-831ba060-5f08-4cc8-82e6-507d6e22c84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632540095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.632540095
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3764138658
Short name T777
Test name
Test status
Simulation time 19454141 ps
CPU time 0.77 seconds
Started Jun 04 02:22:36 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 204916 kb
Host smart-2a81ecd6-0514-45fc-8e17-c9ae7c0fe899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764138658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3764138658
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4074171637
Short name T606
Test name
Test status
Simulation time 2479833555 ps
CPU time 6.09 seconds
Started Jun 04 02:22:32 PM PDT 24
Finished Jun 04 02:22:39 PM PDT 24
Peak memory 218656 kb
Host smart-d230fd53-34b5-4743-9038-87d10b7017bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074171637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4074171637
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1868537649
Short name T360
Test name
Test status
Simulation time 43158486 ps
CPU time 0.76 seconds
Started Jun 04 02:22:25 PM PDT 24
Finished Jun 04 02:22:27 PM PDT 24
Peak memory 205924 kb
Host smart-77273a62-066f-4d52-a9ba-1f0309610625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868537649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1868537649
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1047458652
Short name T960
Test name
Test status
Simulation time 2461910593 ps
CPU time 28.66 seconds
Started Jun 04 02:22:33 PM PDT 24
Finished Jun 04 02:23:02 PM PDT 24
Peak memory 248824 kb
Host smart-7e2932f6-68c0-425c-a48e-6485ebb18b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047458652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1047458652
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1301863943
Short name T275
Test name
Test status
Simulation time 39215878187 ps
CPU time 94.13 seconds
Started Jun 04 02:22:33 PM PDT 24
Finished Jun 04 02:24:08 PM PDT 24
Peak memory 251116 kb
Host smart-6afd87f1-af9f-48e0-8514-67807816182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301863943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1301863943
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1129375944
Short name T788
Test name
Test status
Simulation time 2965622424 ps
CPU time 27.82 seconds
Started Jun 04 02:22:31 PM PDT 24
Finished Jun 04 02:23:00 PM PDT 24
Peak memory 221608 kb
Host smart-78ccd8b7-8ac9-4f5a-ac17-fd0eaccbfb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129375944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1129375944
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3204705056
Short name T824
Test name
Test status
Simulation time 23101604038 ps
CPU time 70 seconds
Started Jun 04 02:22:32 PM PDT 24
Finished Jun 04 02:23:43 PM PDT 24
Peak memory 235432 kb
Host smart-adc962c7-0db9-46b2-a219-8a1ebe90d655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204705056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3204705056
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4099018532
Short name T288
Test name
Test status
Simulation time 37145005520 ps
CPU time 18.43 seconds
Started Jun 04 02:22:33 PM PDT 24
Finished Jun 04 02:22:52 PM PDT 24
Peak memory 233164 kb
Host smart-bcccbc23-ef99-444d-b189-cec6db00c914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099018532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4099018532
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2137655239
Short name T284
Test name
Test status
Simulation time 6654444842 ps
CPU time 6.69 seconds
Started Jun 04 02:22:34 PM PDT 24
Finished Jun 04 02:22:41 PM PDT 24
Peak memory 218536 kb
Host smart-fbc778a0-26e7-487f-9cf8-91f6452ec57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137655239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2137655239
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3395942666
Short name T902
Test name
Test status
Simulation time 1094448597 ps
CPU time 11.49 seconds
Started Jun 04 02:22:36 PM PDT 24
Finished Jun 04 02:22:48 PM PDT 24
Peak memory 220372 kb
Host smart-c3c85098-cdf7-435e-9269-1652bfaeefb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3395942666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3395942666
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1388468721
Short name T792
Test name
Test status
Simulation time 6842869925 ps
CPU time 42.75 seconds
Started Jun 04 02:22:28 PM PDT 24
Finished Jun 04 02:23:11 PM PDT 24
Peak memory 215960 kb
Host smart-aea95011-6718-44fd-815c-72fe8c89a256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388468721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1388468721
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1597714733
Short name T873
Test name
Test status
Simulation time 1035088320 ps
CPU time 3.51 seconds
Started Jun 04 02:22:26 PM PDT 24
Finished Jun 04 02:22:31 PM PDT 24
Peak memory 215900 kb
Host smart-c6d1884b-7c3e-4bce-9be6-93f80c9e2c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597714733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1597714733
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1496715576
Short name T630
Test name
Test status
Simulation time 13222997 ps
CPU time 0.72 seconds
Started Jun 04 02:22:32 PM PDT 24
Finished Jun 04 02:22:34 PM PDT 24
Peak memory 204952 kb
Host smart-9e70ea18-a783-41d2-bca9-0f667dca56bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496715576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1496715576
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2802975189
Short name T337
Test name
Test status
Simulation time 111101954 ps
CPU time 0.83 seconds
Started Jun 04 02:22:32 PM PDT 24
Finished Jun 04 02:22:34 PM PDT 24
Peak memory 206256 kb
Host smart-3b025c62-2c2d-462d-b2be-678bb639405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802975189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2802975189
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2482422933
Short name T180
Test name
Test status
Simulation time 221723879 ps
CPU time 3.37 seconds
Started Jun 04 02:22:30 PM PDT 24
Finished Jun 04 02:22:34 PM PDT 24
Peak memory 233068 kb
Host smart-87758967-bc5a-45d3-873b-9f7c277a1ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482422933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2482422933
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1112263414
Short name T544
Test name
Test status
Simulation time 15987154 ps
CPU time 0.74 seconds
Started Jun 04 02:22:41 PM PDT 24
Finished Jun 04 02:22:44 PM PDT 24
Peak memory 204892 kb
Host smart-f4cd94ba-ae5d-445b-adab-9c5a99719647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112263414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1112263414
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3252660435
Short name T731
Test name
Test status
Simulation time 605001360 ps
CPU time 3.07 seconds
Started Jun 04 02:22:32 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 218144 kb
Host smart-30e84067-0f1c-4384-badb-8684ad0b474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252660435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3252660435
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2082915205
Short name T853
Test name
Test status
Simulation time 62334624 ps
CPU time 0.78 seconds
Started Jun 04 02:22:36 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 205028 kb
Host smart-25e24077-9cbd-4d38-872d-b75283d5c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082915205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2082915205
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1136028659
Short name T238
Test name
Test status
Simulation time 26123146467 ps
CPU time 241.22 seconds
Started Jun 04 02:22:40 PM PDT 24
Finished Jun 04 02:26:42 PM PDT 24
Peak memory 250344 kb
Host smart-b2cea9ce-298d-4e96-b3c9-f25728f1a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136028659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1136028659
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1438767263
Short name T13
Test name
Test status
Simulation time 14389150799 ps
CPU time 115.1 seconds
Started Jun 04 02:22:40 PM PDT 24
Finished Jun 04 02:24:36 PM PDT 24
Peak memory 248856 kb
Host smart-34f1abbb-2cfc-4a4d-8f8e-98d8e92c0249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438767263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1438767263
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1789289063
Short name T229
Test name
Test status
Simulation time 81374378043 ps
CPU time 226.59 seconds
Started Jun 04 02:22:49 PM PDT 24
Finished Jun 04 02:26:36 PM PDT 24
Peak memory 249248 kb
Host smart-9a5224af-fcf2-46e6-9c2f-dec3f7a7fcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789289063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1789289063
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2579267932
Short name T596
Test name
Test status
Simulation time 439969362 ps
CPU time 9.61 seconds
Started Jun 04 02:22:40 PM PDT 24
Finished Jun 04 02:22:51 PM PDT 24
Peak memory 232384 kb
Host smart-500bde10-331d-42b2-81ec-b87e6a9e277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579267932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2579267932
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3052244
Short name T750
Test name
Test status
Simulation time 72980254 ps
CPU time 2.08 seconds
Started Jun 04 02:22:33 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 215712 kb
Host smart-39008c24-1db6-42db-bc39-aceb446764eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3052244
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2615712691
Short name T424
Test name
Test status
Simulation time 269093434 ps
CPU time 5.64 seconds
Started Jun 04 02:22:34 PM PDT 24
Finished Jun 04 02:22:40 PM PDT 24
Peak memory 218116 kb
Host smart-baccc7ac-1e1c-4428-8967-291fbe7f3e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615712691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2615712691
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.933821184
Short name T193
Test name
Test status
Simulation time 6347700742 ps
CPU time 5.49 seconds
Started Jun 04 02:22:32 PM PDT 24
Finished Jun 04 02:22:38 PM PDT 24
Peak memory 218448 kb
Host smart-723dfdbb-f804-4118-bbc4-33baedb9383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933821184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.933821184
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2924661957
Short name T610
Test name
Test status
Simulation time 1146569884 ps
CPU time 5.28 seconds
Started Jun 04 02:22:31 PM PDT 24
Finished Jun 04 02:22:37 PM PDT 24
Peak memory 233356 kb
Host smart-bc8dc27b-5d7d-486b-b730-7e8b4797a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924661957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2924661957
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3085327690
Short name T639
Test name
Test status
Simulation time 1711171020 ps
CPU time 6.86 seconds
Started Jun 04 02:22:38 PM PDT 24
Finished Jun 04 02:22:46 PM PDT 24
Peak memory 219772 kb
Host smart-3b2cc97a-ae6a-4bcc-8ee5-50419a86032c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3085327690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3085327690
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4189783967
Short name T931
Test name
Test status
Simulation time 17641416422 ps
CPU time 64.08 seconds
Started Jun 04 02:22:41 PM PDT 24
Finished Jun 04 02:23:46 PM PDT 24
Peak memory 235444 kb
Host smart-bd2e78cf-17f8-444c-9f07-d92cf98d02ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189783967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4189783967
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2493370091
Short name T815
Test name
Test status
Simulation time 1802989039 ps
CPU time 1.92 seconds
Started Jun 04 02:22:33 PM PDT 24
Finished Jun 04 02:22:36 PM PDT 24
Peak memory 216112 kb
Host smart-19ad3554-a950-4e7e-a1e2-99ad169b8262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493370091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2493370091
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1778560460
Short name T723
Test name
Test status
Simulation time 753175365 ps
CPU time 3.7 seconds
Started Jun 04 02:22:36 PM PDT 24
Finished Jun 04 02:22:40 PM PDT 24
Peak memory 215936 kb
Host smart-8fd0753c-ca8b-48d0-8f77-117a13971946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778560460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1778560460
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.202302
Short name T625
Test name
Test status
Simulation time 267553408 ps
CPU time 5.76 seconds
Started Jun 04 02:22:33 PM PDT 24
Finished Jun 04 02:22:40 PM PDT 24
Peak memory 215784 kb
Host smart-c85b941a-0f6b-44ec-9390-451da3209b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.202302
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.782681684
Short name T413
Test name
Test status
Simulation time 19441501 ps
CPU time 0.68 seconds
Started Jun 04 02:22:33 PM PDT 24
Finished Jun 04 02:22:35 PM PDT 24
Peak memory 204900 kb
Host smart-9dc2e68c-bac2-420e-9b2f-b95f09d37392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782681684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.782681684
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1542389408
Short name T530
Test name
Test status
Simulation time 3349700295 ps
CPU time 5.4 seconds
Started Jun 04 02:22:34 PM PDT 24
Finished Jun 04 02:22:40 PM PDT 24
Peak memory 219072 kb
Host smart-7123632d-f897-4723-94f7-6be5288678a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542389408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1542389408
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.602039274
Short name T547
Test name
Test status
Simulation time 89036870 ps
CPU time 0.69 seconds
Started Jun 04 02:22:48 PM PDT 24
Finished Jun 04 02:22:50 PM PDT 24
Peak memory 204288 kb
Host smart-e076fa61-c052-411a-a44c-ffe92e17c2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602039274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.602039274
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.180605246
Short name T343
Test name
Test status
Simulation time 223398671 ps
CPU time 5.31 seconds
Started Jun 04 02:22:39 PM PDT 24
Finished Jun 04 02:22:45 PM PDT 24
Peak memory 232984 kb
Host smart-0eb93c23-6015-4d61-8bcc-824caf9fa8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180605246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.180605246
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.753638509
Short name T384
Test name
Test status
Simulation time 17800674 ps
CPU time 0.81 seconds
Started Jun 04 02:22:40 PM PDT 24
Finished Jun 04 02:22:42 PM PDT 24
Peak memory 205952 kb
Host smart-a0ac68cd-e4f9-4d14-b1b0-16e0fe8eb0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753638509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.753638509
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2910700972
Short name T33
Test name
Test status
Simulation time 14568369666 ps
CPU time 75.26 seconds
Started Jun 04 02:22:39 PM PDT 24
Finished Jun 04 02:23:55 PM PDT 24
Peak memory 256384 kb
Host smart-61fc9f83-78ef-4f26-8cf7-ba3aee3ad442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910700972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2910700972
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1391995145
Short name T49
Test name
Test status
Simulation time 264214489965 ps
CPU time 348.64 seconds
Started Jun 04 02:22:39 PM PDT 24
Finished Jun 04 02:28:31 PM PDT 24
Peak memory 253736 kb
Host smart-4d13f134-ce14-4df2-8d72-5cdc3bf07a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391995145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1391995145
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.444304525
Short name T817
Test name
Test status
Simulation time 36725207386 ps
CPU time 67.08 seconds
Started Jun 04 02:22:40 PM PDT 24
Finished Jun 04 02:23:48 PM PDT 24
Peak memory 239944 kb
Host smart-161589ae-2141-4258-ada0-7872f346ce1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444304525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.444304525
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1554462054
Short name T289
Test name
Test status
Simulation time 1044281871 ps
CPU time 6.07 seconds
Started Jun 04 02:22:40 PM PDT 24
Finished Jun 04 02:22:47 PM PDT 24
Peak memory 233516 kb
Host smart-b731e45a-74ed-435c-b022-fb1dc5dec569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554462054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1554462054
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.352106018
Short name T816
Test name
Test status
Simulation time 791032429 ps
CPU time 4.16 seconds
Started Jun 04 02:22:47 PM PDT 24
Finished Jun 04 02:22:52 PM PDT 24
Peak memory 218120 kb
Host smart-fb1e93d4-ac4d-4905-b64f-d30b5db8c7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352106018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.352106018
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2065690526
Short name T210
Test name
Test status
Simulation time 320453546 ps
CPU time 10.13 seconds
Started Jun 04 02:22:39 PM PDT 24
Finished Jun 04 02:22:50 PM PDT 24
Peak memory 218232 kb
Host smart-ac894b20-e44e-4527-a7d5-85cad08f6a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065690526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2065690526
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2263058603
Short name T593
Test name
Test status
Simulation time 53920854 ps
CPU time 2 seconds
Started Jun 04 02:22:49 PM PDT 24
Finished Jun 04 02:22:51 PM PDT 24
Peak memory 215592 kb
Host smart-5feeca28-1381-4814-b4f9-6df52fa131b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263058603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2263058603
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1143820846
Short name T455
Test name
Test status
Simulation time 1671086098 ps
CPU time 7.81 seconds
Started Jun 04 02:22:39 PM PDT 24
Finished Jun 04 02:22:48 PM PDT 24
Peak memory 222428 kb
Host smart-5b90fcd3-41d7-42ea-9078-38b2c7800499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143820846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1143820846
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4290530731
Short name T443
Test name
Test status
Simulation time 181854853 ps
CPU time 4.04 seconds
Started Jun 04 02:22:49 PM PDT 24
Finished Jun 04 02:22:54 PM PDT 24
Peak memory 222480 kb
Host smart-497ac2b1-8841-4a62-a101-208d7ec06443
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4290530731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4290530731
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.884180118
Short name T706
Test name
Test status
Simulation time 57216229 ps
CPU time 1.21 seconds
Started Jun 04 02:22:47 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 206288 kb
Host smart-882f6b1a-c4ea-40fd-a5cd-9f15bec452c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884180118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.884180118
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2136280162
Short name T423
Test name
Test status
Simulation time 4813886452 ps
CPU time 8.34 seconds
Started Jun 04 02:22:49 PM PDT 24
Finished Jun 04 02:22:58 PM PDT 24
Peak memory 217076 kb
Host smart-ce411b6e-8cd7-46d5-8ef6-65b0571dcfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136280162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2136280162
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1761992137
Short name T969
Test name
Test status
Simulation time 198368753 ps
CPU time 1.35 seconds
Started Jun 04 02:22:38 PM PDT 24
Finished Jun 04 02:22:40 PM PDT 24
Peak memory 207392 kb
Host smart-77bee0c8-84d8-4816-9634-4d6f2cc761b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761992137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1761992137
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4012131936
Short name T655
Test name
Test status
Simulation time 38630539 ps
CPU time 0.85 seconds
Started Jun 04 02:22:39 PM PDT 24
Finished Jun 04 02:22:40 PM PDT 24
Peak memory 206328 kb
Host smart-fc6be40b-9fa8-4ef2-8e6f-c02c2c1222af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012131936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4012131936
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.420805656
Short name T524
Test name
Test status
Simulation time 319985845 ps
CPU time 0.97 seconds
Started Jun 04 02:22:39 PM PDT 24
Finished Jun 04 02:22:41 PM PDT 24
Peak memory 205292 kb
Host smart-313ceaa8-9e9d-46cb-a1ad-b84123d4551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420805656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.420805656
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.972579200
Short name T53
Test name
Test status
Simulation time 1933709722 ps
CPU time 10 seconds
Started Jun 04 02:22:39 PM PDT 24
Finished Jun 04 02:22:50 PM PDT 24
Peak memory 229672 kb
Host smart-592f008b-d343-4985-9a1d-efedc9850559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972579200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.972579200
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1673023406
Short name T569
Test name
Test status
Simulation time 35281088 ps
CPU time 0.69 seconds
Started Jun 04 02:22:48 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 204884 kb
Host smart-d8266784-9e6d-45f4-ad50-aedb8412415e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673023406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1673023406
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3619907067
Short name T665
Test name
Test status
Simulation time 942448716 ps
CPU time 8.03 seconds
Started Jun 04 02:22:46 PM PDT 24
Finished Jun 04 02:22:55 PM PDT 24
Peak memory 232504 kb
Host smart-f7c0ee87-2f2c-4843-bcb0-b5beb73b00b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619907067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3619907067
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3764914626
Short name T768
Test name
Test status
Simulation time 38367206 ps
CPU time 0.75 seconds
Started Jun 04 02:22:47 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 204872 kb
Host smart-6e6dc15d-941e-49e7-9b9a-5e2af1bec9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764914626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3764914626
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2235139098
Short name T243
Test name
Test status
Simulation time 41572227847 ps
CPU time 285.31 seconds
Started Jun 04 02:22:46 PM PDT 24
Finished Jun 04 02:27:32 PM PDT 24
Peak memory 251804 kb
Host smart-8543a926-dfa5-4973-b459-d1e62cd9fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235139098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2235139098
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.722674241
Short name T136
Test name
Test status
Simulation time 48181265809 ps
CPU time 99.37 seconds
Started Jun 04 02:22:48 PM PDT 24
Finished Jun 04 02:24:28 PM PDT 24
Peak memory 248884 kb
Host smart-a7fbfa66-643b-44a9-974f-2408a1ed8cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722674241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.722674241
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3924488205
Short name T230
Test name
Test status
Simulation time 41367892668 ps
CPU time 295.9 seconds
Started Jun 04 02:22:48 PM PDT 24
Finished Jun 04 02:27:44 PM PDT 24
Peak memory 251148 kb
Host smart-72e8e300-ba31-49a1-bf1b-cf5ad41028a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924488205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3924488205
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1592246537
Short name T314
Test name
Test status
Simulation time 4495528386 ps
CPU time 27.17 seconds
Started Jun 04 02:22:46 PM PDT 24
Finished Jun 04 02:23:14 PM PDT 24
Peak memory 232420 kb
Host smart-9869f82e-ada2-4008-8b6c-4fac2ff07e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592246537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1592246537
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.960003470
Short name T388
Test name
Test status
Simulation time 1174385495 ps
CPU time 4.95 seconds
Started Jun 04 02:22:52 PM PDT 24
Finished Jun 04 02:22:58 PM PDT 24
Peak memory 224156 kb
Host smart-90b4e4f9-ae66-4491-aaeb-1b09faafe534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960003470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.960003470
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.791729286
Short name T87
Test name
Test status
Simulation time 5598839183 ps
CPU time 35.31 seconds
Started Jun 04 02:22:52 PM PDT 24
Finished Jun 04 02:23:28 PM PDT 24
Peak memory 239584 kb
Host smart-594b992f-59f6-4adc-8790-74d8f4b5911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791729286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.791729286
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3758336807
Short name T708
Test name
Test status
Simulation time 1068514045 ps
CPU time 6.61 seconds
Started Jun 04 02:22:45 PM PDT 24
Finished Jun 04 02:22:52 PM PDT 24
Peak memory 233160 kb
Host smart-80ffd5c3-b8c9-479f-ba47-c6120addf084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758336807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3758336807
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3353630046
Short name T678
Test name
Test status
Simulation time 511109098 ps
CPU time 2.73 seconds
Started Jun 04 02:22:48 PM PDT 24
Finished Jun 04 02:22:52 PM PDT 24
Peak memory 218088 kb
Host smart-7157b2a2-bd9e-4ea9-b594-9f23ed6cee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353630046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3353630046
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.291843003
Short name T377
Test name
Test status
Simulation time 859398745 ps
CPU time 4.68 seconds
Started Jun 04 02:22:50 PM PDT 24
Finished Jun 04 02:22:55 PM PDT 24
Peak memory 218512 kb
Host smart-96f40832-3e0a-49b5-a46a-f59da244054f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=291843003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.291843003
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2817771855
Short name T914
Test name
Test status
Simulation time 24754530779 ps
CPU time 25.96 seconds
Started Jun 04 02:22:48 PM PDT 24
Finished Jun 04 02:23:15 PM PDT 24
Peak memory 215932 kb
Host smart-ceefef91-8c45-4637-adb5-444aa3811de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817771855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2817771855
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1177341737
Short name T476
Test name
Test status
Simulation time 4071251171 ps
CPU time 9.76 seconds
Started Jun 04 02:22:45 PM PDT 24
Finished Jun 04 02:22:56 PM PDT 24
Peak memory 215916 kb
Host smart-01e4debd-89c7-456c-8e47-03efa9296682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177341737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1177341737
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2327516343
Short name T37
Test name
Test status
Simulation time 38351412 ps
CPU time 0.69 seconds
Started Jun 04 02:22:45 PM PDT 24
Finished Jun 04 02:22:46 PM PDT 24
Peak memory 204964 kb
Host smart-04c79a2c-018c-4cc0-a405-926b2b6dd24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327516343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2327516343
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1157695101
Short name T497
Test name
Test status
Simulation time 89996383 ps
CPU time 0.93 seconds
Started Jun 04 02:22:46 PM PDT 24
Finished Jun 04 02:22:48 PM PDT 24
Peak memory 205296 kb
Host smart-5a49564e-8a21-4743-b3d8-2c382c7fb112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157695101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1157695101
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3371897551
Short name T539
Test name
Test status
Simulation time 62642636 ps
CPU time 2.81 seconds
Started Jun 04 02:22:46 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 224212 kb
Host smart-56755465-f131-4347-8a5e-2be091bbb08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371897551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3371897551
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1652242232
Short name T662
Test name
Test status
Simulation time 15495885 ps
CPU time 0.73 seconds
Started Jun 04 02:22:58 PM PDT 24
Finished Jun 04 02:23:00 PM PDT 24
Peak memory 204896 kb
Host smart-b69f637d-442c-4191-97f7-139cb109d090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652242232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1652242232
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3633218321
Short name T811
Test name
Test status
Simulation time 245169388 ps
CPU time 2.4 seconds
Started Jun 04 02:22:53 PM PDT 24
Finished Jun 04 02:22:56 PM PDT 24
Peak memory 218316 kb
Host smart-a36d8d94-0e85-429f-9721-f5f1d212066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633218321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3633218321
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2534786551
Short name T357
Test name
Test status
Simulation time 48069690 ps
CPU time 0.74 seconds
Started Jun 04 02:22:47 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 204900 kb
Host smart-09faf3d4-deb5-4317-8d1e-807f81cc2be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534786551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2534786551
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3116871823
Short name T367
Test name
Test status
Simulation time 11419986 ps
CPU time 0.81 seconds
Started Jun 04 02:22:59 PM PDT 24
Finished Jun 04 02:23:02 PM PDT 24
Peak memory 215424 kb
Host smart-3f914374-8dd2-45bb-9ac0-db995f51c5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116871823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3116871823
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1585555250
Short name T172
Test name
Test status
Simulation time 7426423482 ps
CPU time 88.48 seconds
Started Jun 04 02:22:55 PM PDT 24
Finished Jun 04 02:24:25 PM PDT 24
Peak memory 252720 kb
Host smart-7b241ed7-87bd-4085-afe6-b60a20b4f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585555250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1585555250
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3770569953
Short name T884
Test name
Test status
Simulation time 392805918205 ps
CPU time 287.17 seconds
Started Jun 04 02:22:56 PM PDT 24
Finished Jun 04 02:27:45 PM PDT 24
Peak memory 252240 kb
Host smart-3c47bd0c-9187-46cd-a440-78b20a399f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770569953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3770569953
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1976553044
Short name T585
Test name
Test status
Simulation time 110461605 ps
CPU time 2.4 seconds
Started Jun 04 02:22:47 PM PDT 24
Finished Jun 04 02:22:50 PM PDT 24
Peak memory 220996 kb
Host smart-3f709d4a-96ad-4e42-b4a3-32b8beef4742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976553044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1976553044
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.724502403
Short name T484
Test name
Test status
Simulation time 997002139 ps
CPU time 6.56 seconds
Started Jun 04 02:22:54 PM PDT 24
Finished Jun 04 02:23:02 PM PDT 24
Peak memory 218464 kb
Host smart-bcb02b83-32fd-4fad-944b-4347f35578c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724502403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.724502403
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3687861357
Short name T735
Test name
Test status
Simulation time 509625131 ps
CPU time 6.74 seconds
Started Jun 04 02:22:47 PM PDT 24
Finished Jun 04 02:22:54 PM PDT 24
Peak memory 216416 kb
Host smart-5d114ba3-36ed-4e69-9f06-cbad392f2c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687861357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3687861357
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2152442890
Short name T394
Test name
Test status
Simulation time 39954759 ps
CPU time 2.56 seconds
Started Jun 04 02:22:48 PM PDT 24
Finished Jun 04 02:22:52 PM PDT 24
Peak memory 232324 kb
Host smart-1eea5249-ab95-4e3d-9a68-7aeca79e31d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152442890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2152442890
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1609829879
Short name T818
Test name
Test status
Simulation time 1459887945 ps
CPU time 5.46 seconds
Started Jun 04 02:23:01 PM PDT 24
Finished Jun 04 02:23:07 PM PDT 24
Peak memory 218872 kb
Host smart-dbc932f5-590a-46f9-b11c-f1df35475b88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1609829879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1609829879
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.988191190
Short name T246
Test name
Test status
Simulation time 30046936342 ps
CPU time 307.47 seconds
Started Jun 04 02:23:01 PM PDT 24
Finished Jun 04 02:28:10 PM PDT 24
Peak memory 248888 kb
Host smart-de01c00b-c4dd-4d8b-a321-c13e275b17b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988191190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.988191190
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.307743839
Short name T316
Test name
Test status
Simulation time 19454583992 ps
CPU time 30.42 seconds
Started Jun 04 02:22:50 PM PDT 24
Finished Jun 04 02:23:21 PM PDT 24
Peak memory 215872 kb
Host smart-87c85812-5a52-4d10-bb2c-eecada7b83a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307743839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.307743839
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2438862494
Short name T341
Test name
Test status
Simulation time 7475668679 ps
CPU time 12.45 seconds
Started Jun 04 02:22:50 PM PDT 24
Finished Jun 04 02:23:03 PM PDT 24
Peak memory 215872 kb
Host smart-94419c85-a3cd-4a46-b521-93b59bfb87b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438862494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2438862494
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4022466113
Short name T690
Test name
Test status
Simulation time 104447076 ps
CPU time 0.97 seconds
Started Jun 04 02:22:47 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 206476 kb
Host smart-fec76546-ebf0-4e25-aa22-df36bc6b923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022466113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4022466113
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.903195532
Short name T764
Test name
Test status
Simulation time 70791590 ps
CPU time 0.95 seconds
Started Jun 04 02:22:47 PM PDT 24
Finished Jun 04 02:22:49 PM PDT 24
Peak memory 205296 kb
Host smart-72719d8b-bf98-49e9-87eb-ade23179ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903195532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.903195532
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1535479081
Short name T220
Test name
Test status
Simulation time 5347813004 ps
CPU time 11.12 seconds
Started Jun 04 02:22:56 PM PDT 24
Finished Jun 04 02:23:08 PM PDT 24
Peak memory 239036 kb
Host smart-f4d50699-df3a-499a-a1ec-3fcfd5e10c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535479081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1535479081
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1921765424
Short name T520
Test name
Test status
Simulation time 42742261 ps
CPU time 0.7 seconds
Started Jun 04 02:23:05 PM PDT 24
Finished Jun 04 02:23:07 PM PDT 24
Peak memory 204916 kb
Host smart-9e861561-6e3d-41b1-b952-1af49547c020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921765424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1921765424
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1129586097
Short name T86
Test name
Test status
Simulation time 47226606 ps
CPU time 2.6 seconds
Started Jun 04 02:22:53 PM PDT 24
Finished Jun 04 02:22:57 PM PDT 24
Peak memory 234284 kb
Host smart-c3d52411-60ad-4129-ab13-b1ac3fc011c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129586097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1129586097
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1306746677
Short name T425
Test name
Test status
Simulation time 19261937 ps
CPU time 0.76 seconds
Started Jun 04 02:22:53 PM PDT 24
Finished Jun 04 02:22:54 PM PDT 24
Peak memory 204904 kb
Host smart-6bc1c49a-872a-46b3-8090-c1deb0b78cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306746677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1306746677
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1561228685
Short name T223
Test name
Test status
Simulation time 6511428671 ps
CPU time 38.13 seconds
Started Jun 04 02:23:02 PM PDT 24
Finished Jun 04 02:23:42 PM PDT 24
Peak memory 232448 kb
Host smart-6d0ff790-fe5b-4798-bf12-36473ad71327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561228685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1561228685
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2193019535
Short name T250
Test name
Test status
Simulation time 26455442001 ps
CPU time 150.25 seconds
Started Jun 04 02:22:57 PM PDT 24
Finished Jun 04 02:25:28 PM PDT 24
Peak memory 253532 kb
Host smart-30126437-e9ba-4c60-b5d5-ad9323d13962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193019535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2193019535
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1748166415
Short name T588
Test name
Test status
Simulation time 5326329167 ps
CPU time 35.39 seconds
Started Jun 04 02:22:59 PM PDT 24
Finished Jun 04 02:23:36 PM PDT 24
Peak memory 224308 kb
Host smart-e5b5746d-d067-4ce1-9eed-388679779afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748166415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1748166415
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.227148257
Short name T285
Test name
Test status
Simulation time 835326921 ps
CPU time 4.09 seconds
Started Jun 04 02:23:00 PM PDT 24
Finished Jun 04 02:23:05 PM PDT 24
Peak memory 232508 kb
Host smart-00fba7f1-16a0-4f9c-a193-d464acb0ae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227148257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.227148257
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3382093729
Short name T282
Test name
Test status
Simulation time 5066526814 ps
CPU time 16.89 seconds
Started Jun 04 02:22:56 PM PDT 24
Finished Jun 04 02:23:14 PM PDT 24
Peak memory 217552 kb
Host smart-1dda7c9d-8dd0-4bbd-83d7-bc31dbb7c16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382093729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3382093729
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4044081815
Short name T685
Test name
Test status
Simulation time 4909510797 ps
CPU time 44.47 seconds
Started Jun 04 02:22:53 PM PDT 24
Finished Jun 04 02:23:39 PM PDT 24
Peak memory 223172 kb
Host smart-b0d34799-9715-421a-bebf-bfbd5e79109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044081815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4044081815
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3463361656
Short name T753
Test name
Test status
Simulation time 862888791 ps
CPU time 4.05 seconds
Started Jun 04 02:22:52 PM PDT 24
Finished Jun 04 02:22:57 PM PDT 24
Peak memory 222120 kb
Host smart-a2281b70-bc00-40ea-a7b8-1dd71dc8d450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463361656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3463361656
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.185408062
Short name T582
Test name
Test status
Simulation time 2217019879 ps
CPU time 5.61 seconds
Started Jun 04 02:23:02 PM PDT 24
Finished Jun 04 02:23:09 PM PDT 24
Peak memory 232760 kb
Host smart-6dcd6846-ae07-4f7b-ba87-8df7cd7ed363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185408062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.185408062
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.240074534
Short name T551
Test name
Test status
Simulation time 812678478 ps
CPU time 13.19 seconds
Started Jun 04 02:22:59 PM PDT 24
Finished Jun 04 02:23:14 PM PDT 24
Peak memory 222552 kb
Host smart-323c9ca1-17ca-4171-9e16-2afad6b3a4de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=240074534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.240074534
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1187853461
Short name T257
Test name
Test status
Simulation time 63656893920 ps
CPU time 633.96 seconds
Started Jun 04 02:22:59 PM PDT 24
Finished Jun 04 02:33:35 PM PDT 24
Peak memory 265880 kb
Host smart-5db67d34-5682-4eda-bb2b-b6995f516a89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187853461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1187853461
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3694570768
Short name T487
Test name
Test status
Simulation time 24814358442 ps
CPU time 24.25 seconds
Started Jun 04 02:22:57 PM PDT 24
Finished Jun 04 02:23:23 PM PDT 24
Peak memory 215948 kb
Host smart-5b6586a0-3a82-4b00-8b80-7931582a4f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694570768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3694570768
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3154878609
Short name T717
Test name
Test status
Simulation time 86005090603 ps
CPU time 15.64 seconds
Started Jun 04 02:22:53 PM PDT 24
Finished Jun 04 02:23:11 PM PDT 24
Peak memory 215656 kb
Host smart-df286e68-e25d-4319-9233-2b95ae89bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154878609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3154878609
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.73298455
Short name T371
Test name
Test status
Simulation time 86664460 ps
CPU time 0.96 seconds
Started Jun 04 02:22:54 PM PDT 24
Finished Jun 04 02:22:57 PM PDT 24
Peak memory 206600 kb
Host smart-5f18d001-410a-4894-be55-8241244d4303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73298455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.73298455
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1723354416
Short name T615
Test name
Test status
Simulation time 473220042 ps
CPU time 1.07 seconds
Started Jun 04 02:22:54 PM PDT 24
Finished Jun 04 02:22:57 PM PDT 24
Peak memory 206312 kb
Host smart-cb58845d-ed03-4eec-aed7-2e3561539a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723354416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1723354416
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4230389782
Short name T901
Test name
Test status
Simulation time 3790306153 ps
CPU time 6.37 seconds
Started Jun 04 02:22:56 PM PDT 24
Finished Jun 04 02:23:04 PM PDT 24
Peak memory 224280 kb
Host smart-6a12c4f4-7358-4b21-8e71-44529f074c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230389782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4230389782
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4140439338
Short name T930
Test name
Test status
Simulation time 14247757 ps
CPU time 0.72 seconds
Started Jun 04 02:23:19 PM PDT 24
Finished Jun 04 02:23:21 PM PDT 24
Peak memory 204896 kb
Host smart-94403b53-1caf-4e6d-acde-4d344102e0eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140439338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4140439338
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1405825815
Short name T770
Test name
Test status
Simulation time 1042383814 ps
CPU time 4.51 seconds
Started Jun 04 02:23:04 PM PDT 24
Finished Jun 04 02:23:10 PM PDT 24
Peak memory 218444 kb
Host smart-b08f4b79-07c2-4ed5-98eb-f1eef3ab18cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405825815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1405825815
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3435580247
Short name T659
Test name
Test status
Simulation time 25399520 ps
CPU time 0.79 seconds
Started Jun 04 02:23:08 PM PDT 24
Finished Jun 04 02:23:10 PM PDT 24
Peak memory 205912 kb
Host smart-02e50771-2556-4841-8087-8033c5df2581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435580247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3435580247
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2311136933
Short name T713
Test name
Test status
Simulation time 2030613697 ps
CPU time 9.97 seconds
Started Jun 04 02:23:04 PM PDT 24
Finished Jun 04 02:23:16 PM PDT 24
Peak memory 224200 kb
Host smart-508fe1ac-bf10-4837-98de-5c205a69caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311136933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2311136933
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4087350388
Short name T534
Test name
Test status
Simulation time 5395228894 ps
CPU time 35.33 seconds
Started Jun 04 02:23:10 PM PDT 24
Finished Jun 04 02:23:46 PM PDT 24
Peak memory 233528 kb
Host smart-3d9c5f90-239c-427f-a214-6448d9c5082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087350388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4087350388
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.338771384
Short name T743
Test name
Test status
Simulation time 62056315270 ps
CPU time 115.26 seconds
Started Jun 04 02:22:58 PM PDT 24
Finished Jun 04 02:24:55 PM PDT 24
Peak memory 248896 kb
Host smart-6e64934a-ec84-4c32-8714-ceaa6f5ebcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338771384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.338771384
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3143390851
Short name T803
Test name
Test status
Simulation time 3262273655 ps
CPU time 57.28 seconds
Started Jun 04 02:23:08 PM PDT 24
Finished Jun 04 02:24:06 PM PDT 24
Peak memory 240524 kb
Host smart-18783b26-d327-4143-9d2d-ef2f3d900f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143390851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3143390851
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1167814738
Short name T740
Test name
Test status
Simulation time 874328562 ps
CPU time 6.5 seconds
Started Jun 04 02:23:10 PM PDT 24
Finished Jun 04 02:23:17 PM PDT 24
Peak memory 221076 kb
Host smart-c858039d-2afc-49a0-a770-b209764c7a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167814738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1167814738
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2811590502
Short name T756
Test name
Test status
Simulation time 111145059 ps
CPU time 2.34 seconds
Started Jun 04 02:23:13 PM PDT 24
Finished Jun 04 02:23:16 PM PDT 24
Peak memory 215716 kb
Host smart-05a13c0b-820e-4c4d-9c88-fda86e1155bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811590502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2811590502
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3458463486
Short name T573
Test name
Test status
Simulation time 21905840135 ps
CPU time 13.33 seconds
Started Jun 04 02:22:59 PM PDT 24
Finished Jun 04 02:23:14 PM PDT 24
Peak memory 234744 kb
Host smart-233be20e-7618-43e6-9cdb-8f9f71f97212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458463486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3458463486
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.865491563
Short name T618
Test name
Test status
Simulation time 17728322696 ps
CPU time 23.83 seconds
Started Jun 04 02:23:08 PM PDT 24
Finished Jun 04 02:23:33 PM PDT 24
Peak memory 218604 kb
Host smart-7a167368-1c23-4844-9b5b-f0b5968a195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865491563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.865491563
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4252486275
Short name T548
Test name
Test status
Simulation time 1378164928 ps
CPU time 6.6 seconds
Started Jun 04 02:23:00 PM PDT 24
Finished Jun 04 02:23:08 PM PDT 24
Peak memory 219696 kb
Host smart-b0408195-bb18-4a86-ad99-a6df148cb7c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252486275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4252486275
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1695454846
Short name T754
Test name
Test status
Simulation time 20496239148 ps
CPU time 89.94 seconds
Started Jun 04 02:23:09 PM PDT 24
Finished Jun 04 02:24:39 PM PDT 24
Peak memory 252548 kb
Host smart-82b99a57-3361-48fd-9fc4-d580cf1fb5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695454846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1695454846
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3484045761
Short name T967
Test name
Test status
Simulation time 13053857 ps
CPU time 0.75 seconds
Started Jun 04 02:23:00 PM PDT 24
Finished Jun 04 02:23:02 PM PDT 24
Peak memory 205044 kb
Host smart-d3a9b13f-c498-428d-bc69-bf52720c90f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484045761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3484045761
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3981261884
Short name T519
Test name
Test status
Simulation time 1996521417 ps
CPU time 10.8 seconds
Started Jun 04 02:23:04 PM PDT 24
Finished Jun 04 02:23:17 PM PDT 24
Peak memory 215796 kb
Host smart-eb99cd16-342d-4ded-9996-734b1474e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981261884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3981261884
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.532401238
Short name T416
Test name
Test status
Simulation time 12210369 ps
CPU time 0.77 seconds
Started Jun 04 02:23:12 PM PDT 24
Finished Jun 04 02:23:13 PM PDT 24
Peak memory 205396 kb
Host smart-459d281c-f0ca-4580-88a1-77d68733c121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532401238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.532401238
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1820526462
Short name T808
Test name
Test status
Simulation time 48597911 ps
CPU time 0.7 seconds
Started Jun 04 02:23:14 PM PDT 24
Finished Jun 04 02:23:16 PM PDT 24
Peak memory 204952 kb
Host smart-ad78a17b-ad44-4879-a3ed-3a2beffe2b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820526462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1820526462
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2706987663
Short name T283
Test name
Test status
Simulation time 4324428842 ps
CPU time 15.74 seconds
Started Jun 04 02:23:09 PM PDT 24
Finished Jun 04 02:23:26 PM PDT 24
Peak memory 229104 kb
Host smart-1e469653-9b3a-4143-a4d1-53778fbb5a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706987663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2706987663
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3518395883
Short name T332
Test name
Test status
Simulation time 44064277 ps
CPU time 0.71 seconds
Started Jun 04 02:23:14 PM PDT 24
Finished Jun 04 02:23:16 PM PDT 24
Peak memory 204912 kb
Host smart-7fa29347-f678-42d4-b0cb-16b442c12f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518395883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3518395883
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3937194641
Short name T846
Test name
Test status
Simulation time 531175918 ps
CPU time 7.24 seconds
Started Jun 04 02:23:06 PM PDT 24
Finished Jun 04 02:23:14 PM PDT 24
Peak memory 219272 kb
Host smart-abd160c1-1d1e-400b-b217-74f9a5dda275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937194641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3937194641
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2647646507
Short name T382
Test name
Test status
Simulation time 78182061 ps
CPU time 0.79 seconds
Started Jun 04 02:23:13 PM PDT 24
Finished Jun 04 02:23:15 PM PDT 24
Peak memory 205856 kb
Host smart-e6b3e111-705e-42e2-ae1d-8efb4d7386d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647646507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2647646507
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2618802106
Short name T595
Test name
Test status
Simulation time 4611362430 ps
CPU time 12.71 seconds
Started Jun 04 02:23:11 PM PDT 24
Finished Jun 04 02:23:24 PM PDT 24
Peak memory 233444 kb
Host smart-2d515e28-55e2-40b2-8983-7769ee870ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618802106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2618802106
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1243629766
Short name T52
Test name
Test status
Simulation time 3153422792 ps
CPU time 61.22 seconds
Started Jun 04 02:23:13 PM PDT 24
Finished Jun 04 02:24:15 PM PDT 24
Peak memory 248900 kb
Host smart-e9bc5781-dda2-4188-abc4-17296315074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243629766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1243629766
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3324065115
Short name T552
Test name
Test status
Simulation time 12931680050 ps
CPU time 133.86 seconds
Started Jun 04 02:23:15 PM PDT 24
Finished Jun 04 02:25:30 PM PDT 24
Peak memory 250240 kb
Host smart-653ab42e-5fd5-49c1-89ba-7763e4193dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324065115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3324065115
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1872359347
Short name T755
Test name
Test status
Simulation time 1055377292 ps
CPU time 13.4 seconds
Started Jun 04 02:23:09 PM PDT 24
Finished Jun 04 02:23:23 PM PDT 24
Peak memory 224096 kb
Host smart-4ebbd269-10c4-4107-ba2b-dd09644a8669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872359347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1872359347
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3011295591
Short name T944
Test name
Test status
Simulation time 1307265880 ps
CPU time 12.54 seconds
Started Jun 04 02:23:19 PM PDT 24
Finished Jun 04 02:23:32 PM PDT 24
Peak memory 233228 kb
Host smart-8bcdc45c-021c-4ae6-9f22-f6fa42f35ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011295591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3011295591
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3660113981
Short name T819
Test name
Test status
Simulation time 157454336 ps
CPU time 4.71 seconds
Started Jun 04 02:23:17 PM PDT 24
Finished Jun 04 02:23:22 PM PDT 24
Peak memory 233616 kb
Host smart-7522bb80-4bde-464b-b087-5a950ce6c2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660113981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3660113981
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3450189474
Short name T525
Test name
Test status
Simulation time 2499437043 ps
CPU time 10.9 seconds
Started Jun 04 02:23:15 PM PDT 24
Finished Jun 04 02:23:26 PM PDT 24
Peak memory 227784 kb
Host smart-e0ccc0be-be6d-41f0-95e3-cbd7d60a1d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450189474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3450189474
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1799913121
Short name T727
Test name
Test status
Simulation time 157888656 ps
CPU time 3.7 seconds
Started Jun 04 02:23:08 PM PDT 24
Finished Jun 04 02:23:12 PM PDT 24
Peak memory 224164 kb
Host smart-0ef6402f-44c9-450a-911d-a840618be08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799913121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1799913121
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3514171743
Short name T490
Test name
Test status
Simulation time 385753372 ps
CPU time 5.27 seconds
Started Jun 04 02:23:06 PM PDT 24
Finished Jun 04 02:23:12 PM PDT 24
Peak memory 221908 kb
Host smart-c90bcecf-20c1-44c0-8bb1-e1834676c59f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3514171743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3514171743
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1734613755
Short name T241
Test name
Test status
Simulation time 9066537999 ps
CPU time 85.04 seconds
Started Jun 04 02:23:08 PM PDT 24
Finished Jun 04 02:24:34 PM PDT 24
Peak memory 253732 kb
Host smart-f0080107-80c9-488d-8354-5fda7babb287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734613755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1734613755
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2698878955
Short name T338
Test name
Test status
Simulation time 19426590 ps
CPU time 0.72 seconds
Started Jun 04 02:23:11 PM PDT 24
Finished Jun 04 02:23:12 PM PDT 24
Peak memory 205048 kb
Host smart-4840a3b2-c6bb-4bca-be9b-ef3d2f728e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698878955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2698878955
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3937598306
Short name T855
Test name
Test status
Simulation time 8314932883 ps
CPU time 24.63 seconds
Started Jun 04 02:23:14 PM PDT 24
Finished Jun 04 02:23:40 PM PDT 24
Peak memory 215872 kb
Host smart-f95229b1-eb5f-461a-94c6-8c6bb7245c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937598306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3937598306
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1658878764
Short name T495
Test name
Test status
Simulation time 454375546 ps
CPU time 11.75 seconds
Started Jun 04 02:23:07 PM PDT 24
Finished Jun 04 02:23:20 PM PDT 24
Peak memory 215904 kb
Host smart-330861b2-12e7-42cc-97b1-fcca600321ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658878764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1658878764
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.954532112
Short name T895
Test name
Test status
Simulation time 39228225 ps
CPU time 0.76 seconds
Started Jun 04 02:23:08 PM PDT 24
Finished Jun 04 02:23:09 PM PDT 24
Peak memory 205288 kb
Host smart-6b4c6f31-e9f1-418a-af50-fe67b5b9251a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954532112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.954532112
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3253374034
Short name T948
Test name
Test status
Simulation time 24638075085 ps
CPU time 22.61 seconds
Started Jun 04 02:23:07 PM PDT 24
Finished Jun 04 02:23:31 PM PDT 24
Peak memory 235248 kb
Host smart-b85f3c7c-a75c-4269-8b49-b32eb0b8d5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253374034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3253374034
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2996022248
Short name T741
Test name
Test status
Simulation time 11781812 ps
CPU time 0.71 seconds
Started Jun 04 02:23:19 PM PDT 24
Finished Jun 04 02:23:20 PM PDT 24
Peak memory 204296 kb
Host smart-04fe1e32-7ed0-45f6-83a3-4c23dcb2e272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996022248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2996022248
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.789750695
Short name T959
Test name
Test status
Simulation time 312868532 ps
CPU time 3.89 seconds
Started Jun 04 02:23:15 PM PDT 24
Finished Jun 04 02:23:20 PM PDT 24
Peak memory 232896 kb
Host smart-b6ad746a-5734-40e8-b5f9-48434bd9a088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789750695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.789750695
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2575623124
Short name T725
Test name
Test status
Simulation time 150162777 ps
CPU time 0.74 seconds
Started Jun 04 02:23:07 PM PDT 24
Finished Jun 04 02:23:08 PM PDT 24
Peak memory 204892 kb
Host smart-70386a99-7d22-49cf-a8b0-8b84130e2511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575623124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2575623124
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4129620162
Short name T458
Test name
Test status
Simulation time 95326309595 ps
CPU time 191.19 seconds
Started Jun 04 02:23:23 PM PDT 24
Finished Jun 04 02:26:35 PM PDT 24
Peak memory 253308 kb
Host smart-4c442420-56ac-41d7-97e5-bee44e483c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129620162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4129620162
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1210537255
Short name T861
Test name
Test status
Simulation time 103459329209 ps
CPU time 229.57 seconds
Started Jun 04 02:23:14 PM PDT 24
Finished Jun 04 02:27:05 PM PDT 24
Peak memory 248896 kb
Host smart-6dacfea7-fe96-4dba-a873-eced4f4f15bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210537255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1210537255
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1715154260
Short name T183
Test name
Test status
Simulation time 2485571744 ps
CPU time 39.32 seconds
Started Jun 04 02:23:13 PM PDT 24
Finished Jun 04 02:23:53 PM PDT 24
Peak memory 251532 kb
Host smart-e712963b-0dd9-4fa4-94e2-72e0bbf96e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715154260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1715154260
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4128875739
Short name T368
Test name
Test status
Simulation time 411459093 ps
CPU time 7.86 seconds
Started Jun 04 02:23:20 PM PDT 24
Finished Jun 04 02:23:29 PM PDT 24
Peak memory 232408 kb
Host smart-6b94a826-ef01-4c27-81a4-4f45a81dee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128875739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4128875739
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3755189775
Short name T9
Test name
Test status
Simulation time 861475420 ps
CPU time 9.34 seconds
Started Jun 04 02:23:21 PM PDT 24
Finished Jun 04 02:23:31 PM PDT 24
Peak memory 233704 kb
Host smart-335d4ba6-5ce4-4388-886e-1968ff14a84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755189775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3755189775
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2278635152
Short name T376
Test name
Test status
Simulation time 3125375543 ps
CPU time 14.08 seconds
Started Jun 04 02:23:19 PM PDT 24
Finished Jun 04 02:23:34 PM PDT 24
Peak memory 226844 kb
Host smart-916558da-dd3c-4be0-8b41-878da4a888ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278635152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2278635152
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1439829250
Short name T251
Test name
Test status
Simulation time 841107159 ps
CPU time 9.65 seconds
Started Jun 04 02:23:14 PM PDT 24
Finished Jun 04 02:23:24 PM PDT 24
Peak memory 252784 kb
Host smart-9e596b70-36f3-436a-8cdd-17c2788bf4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439829250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1439829250
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3806706627
Short name T98
Test name
Test status
Simulation time 1336210369 ps
CPU time 3.78 seconds
Started Jun 04 02:23:16 PM PDT 24
Finished Jun 04 02:23:20 PM PDT 24
Peak memory 234508 kb
Host smart-bd9b779c-65e5-4600-bfde-08820f3fa6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806706627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3806706627
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1094170720
Short name T428
Test name
Test status
Simulation time 818134189 ps
CPU time 7.82 seconds
Started Jun 04 02:23:20 PM PDT 24
Finished Jun 04 02:23:29 PM PDT 24
Peak memory 220156 kb
Host smart-be624c70-65b3-4ec0-a929-bc2d9b6085a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1094170720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1094170720
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2663917010
Short name T63
Test name
Test status
Simulation time 68760803542 ps
CPU time 209 seconds
Started Jun 04 02:23:22 PM PDT 24
Finished Jun 04 02:26:52 PM PDT 24
Peak memory 249924 kb
Host smart-12f05805-ff18-4a22-b7d9-b70f642c7f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663917010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2663917010
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2444495261
Short name T315
Test name
Test status
Simulation time 2559018920 ps
CPU time 23.89 seconds
Started Jun 04 02:23:14 PM PDT 24
Finished Jun 04 02:23:39 PM PDT 24
Peak memory 215988 kb
Host smart-82590429-a48e-4ddf-b444-15e0ae2c0a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444495261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2444495261
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2641282197
Short name T501
Test name
Test status
Simulation time 4538106031 ps
CPU time 14.49 seconds
Started Jun 04 02:23:13 PM PDT 24
Finished Jun 04 02:23:28 PM PDT 24
Peak memory 215880 kb
Host smart-8e19e723-2e48-4f1e-8b2f-1a3a56433e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641282197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2641282197
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.973112622
Short name T549
Test name
Test status
Simulation time 171446969 ps
CPU time 1.99 seconds
Started Jun 04 02:23:25 PM PDT 24
Finished Jun 04 02:23:28 PM PDT 24
Peak memory 216004 kb
Host smart-f2b43091-6f2d-458e-818b-3e539c5ba473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973112622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.973112622
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.160304815
Short name T780
Test name
Test status
Simulation time 46601865 ps
CPU time 0.71 seconds
Started Jun 04 02:23:19 PM PDT 24
Finished Jun 04 02:23:20 PM PDT 24
Peak memory 205312 kb
Host smart-fd930952-6ef9-4297-88b7-fea7b157a7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160304815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.160304815
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2226389352
Short name T806
Test name
Test status
Simulation time 1757753474 ps
CPU time 8.73 seconds
Started Jun 04 02:23:16 PM PDT 24
Finished Jun 04 02:23:26 PM PDT 24
Peak memory 240496 kb
Host smart-833d2722-8f38-483a-a6d1-2c4f610a6228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226389352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2226389352
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.205369402
Short name T724
Test name
Test status
Simulation time 14564968 ps
CPU time 0.71 seconds
Started Jun 04 02:19:17 PM PDT 24
Finished Jun 04 02:19:18 PM PDT 24
Peak memory 204904 kb
Host smart-3797d583-2e40-4c3e-aafa-5bb676f50e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205369402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.205369402
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3976543006
Short name T132
Test name
Test status
Simulation time 668350751 ps
CPU time 4.63 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:21 PM PDT 24
Peak memory 219392 kb
Host smart-bb5711d0-5b52-4df9-96c2-3993ac205c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976543006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3976543006
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.448569501
Short name T470
Test name
Test status
Simulation time 19576136 ps
CPU time 0.8 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:17 PM PDT 24
Peak memory 206264 kb
Host smart-3326e9fe-4f14-4876-8854-df05ba0a5cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448569501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.448569501
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1906385803
Short name T226
Test name
Test status
Simulation time 58449472091 ps
CPU time 81.27 seconds
Started Jun 04 02:19:14 PM PDT 24
Finished Jun 04 02:20:36 PM PDT 24
Peak memory 249740 kb
Host smart-af511da9-d6e2-4b10-a79b-4b6c63f7794c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906385803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1906385803
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1032690775
Short name T305
Test name
Test status
Simulation time 22077964309 ps
CPU time 76.66 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:20:32 PM PDT 24
Peak memory 224300 kb
Host smart-431303f8-7629-43f6-880d-b4880bc5088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032690775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1032690775
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.71957998
Short name T862
Test name
Test status
Simulation time 12092036518 ps
CPU time 80.44 seconds
Started Jun 04 02:19:13 PM PDT 24
Finished Jun 04 02:20:35 PM PDT 24
Peak memory 248868 kb
Host smart-5143cd04-4ee6-4524-80cb-12be4cac26b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71957998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.71957998
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.645856841
Short name T554
Test name
Test status
Simulation time 726133638 ps
CPU time 12.13 seconds
Started Jun 04 02:19:14 PM PDT 24
Finished Jun 04 02:19:27 PM PDT 24
Peak memory 240548 kb
Host smart-d507cd25-deec-427e-8d40-f70456f0a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645856841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.645856841
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1229472230
Short name T679
Test name
Test status
Simulation time 226882254 ps
CPU time 4.76 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:21 PM PDT 24
Peak memory 234672 kb
Host smart-113b3025-0285-4657-8c45-3329f70638e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229472230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1229472230
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4235698578
Short name T572
Test name
Test status
Simulation time 804666617 ps
CPU time 5.31 seconds
Started Jun 04 02:19:12 PM PDT 24
Finished Jun 04 02:19:18 PM PDT 24
Peak memory 224144 kb
Host smart-a624a442-0f1e-4980-9512-19862438f44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235698578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4235698578
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1347992923
Short name T77
Test name
Test status
Simulation time 23931457 ps
CPU time 1.01 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:17 PM PDT 24
Peak memory 216192 kb
Host smart-bc6d0e55-8ec1-47f2-a134-375fb011a168
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347992923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1347992923
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.178832725
Short name T221
Test name
Test status
Simulation time 618956001 ps
CPU time 6.72 seconds
Started Jun 04 02:19:14 PM PDT 24
Finished Jun 04 02:19:22 PM PDT 24
Peak memory 238116 kb
Host smart-18e79819-a4db-4609-86b1-278ca42556a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178832725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
178832725
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4053150772
Short name T637
Test name
Test status
Simulation time 71838980 ps
CPU time 2.19 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:18 PM PDT 24
Peak memory 215528 kb
Host smart-09d80901-a4b5-4a6d-9f03-55bfb93b9a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053150772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4053150772
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.440140734
Short name T632
Test name
Test status
Simulation time 566946116 ps
CPU time 6.13 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:23 PM PDT 24
Peak memory 222204 kb
Host smart-945a8d8c-23e2-46a6-b547-b51d6e1ef99f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=440140734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.440140734
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3251901450
Short name T546
Test name
Test status
Simulation time 629844984 ps
CPU time 1.85 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:18 PM PDT 24
Peak memory 217360 kb
Host smart-889af105-9d5e-4f5d-80dd-cbb2c5de5683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251901450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3251901450
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2350510847
Short name T684
Test name
Test status
Simulation time 11830492732 ps
CPU time 23.7 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:40 PM PDT 24
Peak memory 215880 kb
Host smart-b88fe19b-9358-4baf-9dfe-37a163b9e08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350510847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2350510847
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2733671055
Short name T347
Test name
Test status
Simulation time 3274562571 ps
CPU time 12.65 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:28 PM PDT 24
Peak memory 215872 kb
Host smart-18a734b2-cf46-45df-8e88-f80131e15ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733671055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2733671055
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2733637280
Short name T350
Test name
Test status
Simulation time 81306139 ps
CPU time 3.55 seconds
Started Jun 04 02:19:14 PM PDT 24
Finished Jun 04 02:19:18 PM PDT 24
Peak memory 216096 kb
Host smart-b0e3b71f-49c6-458f-b8e5-f3e4b5be46ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733637280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2733637280
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3758934032
Short name T560
Test name
Test status
Simulation time 172326054 ps
CPU time 0.89 seconds
Started Jun 04 02:19:16 PM PDT 24
Finished Jun 04 02:19:18 PM PDT 24
Peak memory 205296 kb
Host smart-921ee00c-df4f-413f-a88b-d490b267e43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758934032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3758934032
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.270634945
Short name T783
Test name
Test status
Simulation time 1435086262 ps
CPU time 8.44 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:24 PM PDT 24
Peak memory 226392 kb
Host smart-054fc183-a61a-4c97-8f71-4ace742acfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270634945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.270634945
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1130702485
Short name T617
Test name
Test status
Simulation time 39665256 ps
CPU time 0.69 seconds
Started Jun 04 02:19:21 PM PDT 24
Finished Jun 04 02:19:23 PM PDT 24
Peak memory 204920 kb
Host smart-62707b08-b472-4607-a070-fbc8329d9e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130702485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
130702485
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1074721592
Short name T828
Test name
Test status
Simulation time 200302613 ps
CPU time 2.24 seconds
Started Jun 04 02:19:21 PM PDT 24
Finished Jun 04 02:19:24 PM PDT 24
Peak memory 215748 kb
Host smart-3bb6f54b-ebdb-454f-ade6-fa0b96a891b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074721592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1074721592
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.36294746
Short name T564
Test name
Test status
Simulation time 31153369 ps
CPU time 0.8 seconds
Started Jun 04 02:19:15 PM PDT 24
Finished Jun 04 02:19:17 PM PDT 24
Peak memory 205944 kb
Host smart-1fd211bc-7358-4195-aabd-2f4148f5bb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36294746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.36294746
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1025248603
Short name T712
Test name
Test status
Simulation time 1437385755 ps
CPU time 8.22 seconds
Started Jun 04 02:19:23 PM PDT 24
Finished Jun 04 02:19:32 PM PDT 24
Peak memory 233276 kb
Host smart-ba1a1dc6-1b6c-4e00-9d20-41f6cf788d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025248603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1025248603
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.815903336
Short name T232
Test name
Test status
Simulation time 24814432594 ps
CPU time 87.23 seconds
Started Jun 04 02:19:21 PM PDT 24
Finished Jun 04 02:20:50 PM PDT 24
Peak memory 254316 kb
Host smart-07d12417-3102-4d1b-94cb-f591dbb2ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815903336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.815903336
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2448838997
Short name T896
Test name
Test status
Simulation time 19086772449 ps
CPU time 79.07 seconds
Started Jun 04 02:19:20 PM PDT 24
Finished Jun 04 02:20:39 PM PDT 24
Peak memory 256840 kb
Host smart-daa6446c-9dca-4831-ac80-ef5607eaae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448838997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2448838997
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3312017899
Short name T411
Test name
Test status
Simulation time 8470702354 ps
CPU time 23.33 seconds
Started Jun 04 02:19:21 PM PDT 24
Finished Jun 04 02:19:45 PM PDT 24
Peak memory 232372 kb
Host smart-bfae4c5e-dbc7-4682-9fa8-12df5475b56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312017899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3312017899
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3524998612
Short name T603
Test name
Test status
Simulation time 634678484 ps
CPU time 4.16 seconds
Started Jun 04 02:19:23 PM PDT 24
Finished Jun 04 02:19:28 PM PDT 24
Peak memory 232364 kb
Host smart-76108711-3c8d-4823-a28d-149222f9d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524998612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3524998612
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.95134900
Short name T414
Test name
Test status
Simulation time 10706283845 ps
CPU time 66.82 seconds
Started Jun 04 02:19:22 PM PDT 24
Finished Jun 04 02:20:30 PM PDT 24
Peak memory 232456 kb
Host smart-fa1660f3-40a8-419f-99b3-77975eda17e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95134900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.95134900
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3456449273
Short name T950
Test name
Test status
Simulation time 41582367 ps
CPU time 0.98 seconds
Started Jun 04 02:19:13 PM PDT 24
Finished Jun 04 02:19:15 PM PDT 24
Peak memory 217444 kb
Host smart-76f5ce6a-4595-49b5-b1e7-33cd1a31a371
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456449273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3456449273
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1359737113
Short name T10
Test name
Test status
Simulation time 36811256 ps
CPU time 2.03 seconds
Started Jun 04 02:19:24 PM PDT 24
Finished Jun 04 02:19:26 PM PDT 24
Peak memory 218376 kb
Host smart-be024e83-db80-4c5e-b67f-73e4dc4a9426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359737113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1359737113
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3225434350
Short name T212
Test name
Test status
Simulation time 1789538269 ps
CPU time 3.1 seconds
Started Jun 04 02:19:22 PM PDT 24
Finished Jun 04 02:19:26 PM PDT 24
Peak memory 218344 kb
Host smart-d13bcd3b-82bb-47ce-92f2-660477d7cf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225434350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3225434350
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3725636513
Short name T456
Test name
Test status
Simulation time 2939585841 ps
CPU time 9.33 seconds
Started Jun 04 02:19:21 PM PDT 24
Finished Jun 04 02:19:32 PM PDT 24
Peak memory 220108 kb
Host smart-3fa4ca2b-f8f6-414a-ae41-d8fa6a7edd7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3725636513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3725636513
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3836806983
Short name T324
Test name
Test status
Simulation time 3228971958 ps
CPU time 25.88 seconds
Started Jun 04 02:19:20 PM PDT 24
Finished Jun 04 02:19:47 PM PDT 24
Peak memory 216016 kb
Host smart-280c218e-e145-4a4f-8370-a4a38966e1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836806983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3836806983
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3142932769
Short name T496
Test name
Test status
Simulation time 306178094 ps
CPU time 1.92 seconds
Started Jun 04 02:19:22 PM PDT 24
Finished Jun 04 02:19:25 PM PDT 24
Peak memory 207344 kb
Host smart-7787639a-dd07-4e56-a866-ae6473f988a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142932769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3142932769
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.747244724
Short name T322
Test name
Test status
Simulation time 57444875 ps
CPU time 0.93 seconds
Started Jun 04 02:19:22 PM PDT 24
Finished Jun 04 02:19:24 PM PDT 24
Peak memory 206204 kb
Host smart-7e95fdd9-d95b-429a-9ae0-f7f8c10a4554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747244724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.747244724
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3745568437
Short name T621
Test name
Test status
Simulation time 91272350 ps
CPU time 0.82 seconds
Started Jun 04 02:19:21 PM PDT 24
Finished Jun 04 02:19:23 PM PDT 24
Peak memory 205292 kb
Host smart-32b328c2-08ac-4082-825e-c0ea3cfd73dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745568437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3745568437
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1207479422
Short name T17
Test name
Test status
Simulation time 399244353 ps
CPU time 4.91 seconds
Started Jun 04 02:19:23 PM PDT 24
Finished Jun 04 02:19:29 PM PDT 24
Peak memory 226724 kb
Host smart-0fca0f20-f045-4679-88a4-ca3f0f949d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207479422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1207479422
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3796733868
Short name T36
Test name
Test status
Simulation time 13294501 ps
CPU time 0.73 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:30 PM PDT 24
Peak memory 204892 kb
Host smart-0527cd40-4f1a-4d6b-82b1-60a073f9ccfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796733868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
796733868
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.338894919
Short name T460
Test name
Test status
Simulation time 296221974 ps
CPU time 5.05 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:35 PM PDT 24
Peak memory 232420 kb
Host smart-c1c4700c-8346-48db-b4e6-7aadb18a213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338894919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.338894919
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3323185400
Short name T927
Test name
Test status
Simulation time 20015171 ps
CPU time 0.77 seconds
Started Jun 04 02:19:23 PM PDT 24
Finished Jun 04 02:19:25 PM PDT 24
Peak memory 204912 kb
Host smart-f1ccb036-5f79-4933-8233-899b50b1c847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323185400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3323185400
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3444172802
Short name T769
Test name
Test status
Simulation time 36281141997 ps
CPU time 254.18 seconds
Started Jun 04 02:19:30 PM PDT 24
Finished Jun 04 02:23:45 PM PDT 24
Peak memory 250864 kb
Host smart-baafb564-eee6-48ae-856f-db059088c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444172802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3444172802
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2087228040
Short name T693
Test name
Test status
Simulation time 33456420 ps
CPU time 0.8 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:30 PM PDT 24
Peak memory 216464 kb
Host smart-b96c2acb-fd34-4ffa-9222-b8f1c583e927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087228040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2087228040
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.78683658
Short name T580
Test name
Test status
Simulation time 16725017295 ps
CPU time 153.97 seconds
Started Jun 04 02:19:32 PM PDT 24
Finished Jun 04 02:22:07 PM PDT 24
Peak memory 248884 kb
Host smart-771729a5-fb1a-4fc8-9f6a-5cf4e056b527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78683658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.78683658
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2513675407
Short name T620
Test name
Test status
Simulation time 327926979 ps
CPU time 4.38 seconds
Started Jun 04 02:19:32 PM PDT 24
Finished Jun 04 02:19:37 PM PDT 24
Peak memory 224120 kb
Host smart-f9316755-0645-44b2-8ec4-fc54d5ab0fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513675407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2513675407
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2014509712
Short name T599
Test name
Test status
Simulation time 1134595985 ps
CPU time 7.44 seconds
Started Jun 04 02:19:28 PM PDT 24
Finished Jun 04 02:19:36 PM PDT 24
Peak memory 233800 kb
Host smart-905fd0c2-3d30-4c9f-adfb-7f1edd2285c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014509712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2014509712
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1538563047
Short name T926
Test name
Test status
Simulation time 8032808299 ps
CPU time 55.71 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:20:26 PM PDT 24
Peak memory 219796 kb
Host smart-bc931eb8-044a-46e0-ab19-cd2a909150bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538563047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1538563047
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.488984761
Short name T73
Test name
Test status
Simulation time 32465021 ps
CPU time 1.09 seconds
Started Jun 04 02:19:23 PM PDT 24
Finished Jun 04 02:19:24 PM PDT 24
Peak memory 216216 kb
Host smart-9373ef46-72f9-4b13-b20b-1bd375d967f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488984761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.488984761
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2478931767
Short name T958
Test name
Test status
Simulation time 55889025 ps
CPU time 2.12 seconds
Started Jun 04 02:19:22 PM PDT 24
Finished Jun 04 02:19:25 PM PDT 24
Peak memory 218084 kb
Host smart-c7576103-02ca-4f66-b18f-2a1e82fff3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478931767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2478931767
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1416499028
Short name T668
Test name
Test status
Simulation time 1630233031 ps
CPU time 3.5 seconds
Started Jun 04 02:19:23 PM PDT 24
Finished Jun 04 02:19:27 PM PDT 24
Peak memory 216316 kb
Host smart-93f0325d-512d-41e2-9893-66b0e1645cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416499028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1416499028
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2925346741
Short name T429
Test name
Test status
Simulation time 319600828 ps
CPU time 5.73 seconds
Started Jun 04 02:19:27 PM PDT 24
Finished Jun 04 02:19:34 PM PDT 24
Peak memory 222036 kb
Host smart-f8a44043-96f3-4f9e-89b1-1730b86653a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2925346741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2925346741
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4173142346
Short name T859
Test name
Test status
Simulation time 13954087037 ps
CPU time 24.75 seconds
Started Jun 04 02:19:24 PM PDT 24
Finished Jun 04 02:19:49 PM PDT 24
Peak memory 216024 kb
Host smart-7eb95661-b78a-41b2-9752-96ec92ee2c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173142346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4173142346
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.278476511
Short name T707
Test name
Test status
Simulation time 272179305 ps
CPU time 2.13 seconds
Started Jun 04 02:19:23 PM PDT 24
Finished Jun 04 02:19:26 PM PDT 24
Peak memory 215608 kb
Host smart-24cfe86d-8796-49d3-bc81-f8d5cac118c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278476511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.278476511
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1874677619
Short name T732
Test name
Test status
Simulation time 162428873 ps
CPU time 0.93 seconds
Started Jun 04 02:19:20 PM PDT 24
Finished Jun 04 02:19:22 PM PDT 24
Peak memory 205920 kb
Host smart-61194ff4-58c1-409e-93f7-ff1d8d4f9651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874677619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1874677619
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.48157326
Short name T913
Test name
Test status
Simulation time 112314905 ps
CPU time 0.87 seconds
Started Jun 04 02:19:21 PM PDT 24
Finished Jun 04 02:19:23 PM PDT 24
Peak memory 205324 kb
Host smart-5467ab0f-7d35-4f15-949e-6e9cd398da9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48157326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.48157326
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2006999980
Short name T586
Test name
Test status
Simulation time 286413046 ps
CPU time 3.76 seconds
Started Jun 04 02:19:27 PM PDT 24
Finished Jun 04 02:19:32 PM PDT 24
Peak memory 224172 kb
Host smart-e454080a-2dc1-4f1f-9541-38beaf9062b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006999980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2006999980
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3165806789
Short name T375
Test name
Test status
Simulation time 38818058 ps
CPU time 0.72 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:31 PM PDT 24
Peak memory 204912 kb
Host smart-baea805c-8a11-46f7-9713-1701ae4b1500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165806789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
165806789
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.833485997
Short name T7
Test name
Test status
Simulation time 34410796 ps
CPU time 2.4 seconds
Started Jun 04 02:19:33 PM PDT 24
Finished Jun 04 02:19:36 PM PDT 24
Peak memory 220664 kb
Host smart-26751d74-2bab-4616-95b4-7ddf629c9172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833485997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.833485997
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2520692393
Short name T512
Test name
Test status
Simulation time 81868524 ps
CPU time 0.76 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:31 PM PDT 24
Peak memory 204912 kb
Host smart-1a4965ad-8a54-49f4-a014-9f7ddfc56a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520692393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2520692393
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3245817545
Short name T974
Test name
Test status
Simulation time 53047470 ps
CPU time 0.74 seconds
Started Jun 04 02:19:35 PM PDT 24
Finished Jun 04 02:19:36 PM PDT 24
Peak memory 215436 kb
Host smart-34393170-a7af-44c5-8b30-d8bdd716c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245817545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3245817545
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1527057394
Short name T134
Test name
Test status
Simulation time 52876545545 ps
CPU time 115.87 seconds
Started Jun 04 02:19:30 PM PDT 24
Finished Jun 04 02:21:27 PM PDT 24
Peak memory 255920 kb
Host smart-1d064e8b-17b4-439a-a52d-94ec1abc4187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527057394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1527057394
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3691636996
Short name T923
Test name
Test status
Simulation time 9351121637 ps
CPU time 16.95 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:48 PM PDT 24
Peak memory 231828 kb
Host smart-8fba373b-b60a-4c95-91a1-e0237c08157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691636996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3691636996
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.863500900
Short name T146
Test name
Test status
Simulation time 3911392207 ps
CPU time 53.29 seconds
Started Jun 04 02:19:31 PM PDT 24
Finished Jun 04 02:20:25 PM PDT 24
Peak memory 240572 kb
Host smart-5b5f3462-137e-4122-ad8d-6849f3c0101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863500900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.863500900
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.223105012
Short name T903
Test name
Test status
Simulation time 715787111 ps
CPU time 5.53 seconds
Started Jun 04 02:19:32 PM PDT 24
Finished Jun 04 02:19:38 PM PDT 24
Peak memory 218256 kb
Host smart-25658958-18ed-4618-80ac-bbe43a861db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223105012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.223105012
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3817547458
Short name T576
Test name
Test status
Simulation time 28764779928 ps
CPU time 24.09 seconds
Started Jun 04 02:19:30 PM PDT 24
Finished Jun 04 02:19:55 PM PDT 24
Peak memory 219296 kb
Host smart-34f9bb97-c924-41d6-bf63-b672250da5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817547458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3817547458
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3741243483
Short name T591
Test name
Test status
Simulation time 24848696 ps
CPU time 1.04 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:31 PM PDT 24
Peak memory 216172 kb
Host smart-e6372363-7cfc-45bb-bf00-795f1597c07e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741243483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3741243483
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2855975046
Short name T767
Test name
Test status
Simulation time 11454436259 ps
CPU time 10.37 seconds
Started Jun 04 02:19:37 PM PDT 24
Finished Jun 04 02:19:48 PM PDT 24
Peak memory 233204 kb
Host smart-247adfde-bc3c-4156-b6bd-94fab77634b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855975046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2855975046
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3491136909
Short name T951
Test name
Test status
Simulation time 49988731804 ps
CPU time 18.56 seconds
Started Jun 04 02:19:30 PM PDT 24
Finished Jun 04 02:19:49 PM PDT 24
Peak memory 217468 kb
Host smart-6c4e8634-569e-400e-8a66-0b4c94dfe3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491136909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3491136909
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3758621881
Short name T822
Test name
Test status
Simulation time 103784120 ps
CPU time 3.71 seconds
Started Jun 04 02:19:28 PM PDT 24
Finished Jun 04 02:19:33 PM PDT 24
Peak memory 222636 kb
Host smart-687b4f6d-55c9-425e-b38a-0818be1ec233
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3758621881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3758621881
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3810365172
Short name T157
Test name
Test status
Simulation time 17517176433 ps
CPU time 55.63 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:20:26 PM PDT 24
Peak memory 231100 kb
Host smart-d28bcc46-a1fd-461b-8c9e-e6e6c87c6015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810365172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3810365172
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2873774582
Short name T318
Test name
Test status
Simulation time 2484270812 ps
CPU time 7.59 seconds
Started Jun 04 02:19:32 PM PDT 24
Finished Jun 04 02:19:40 PM PDT 24
Peak memory 216228 kb
Host smart-d8a2fc39-4e5b-452a-8477-6308b61b0ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873774582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2873774582
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3160373862
Short name T503
Test name
Test status
Simulation time 2831795246 ps
CPU time 7.95 seconds
Started Jun 04 02:19:37 PM PDT 24
Finished Jun 04 02:19:45 PM PDT 24
Peak memory 215876 kb
Host smart-41bd5739-f331-4daf-9ec0-0fd43cbad76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160373862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3160373862
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.532403934
Short name T609
Test name
Test status
Simulation time 18943393 ps
CPU time 0.9 seconds
Started Jun 04 02:19:32 PM PDT 24
Finished Jun 04 02:19:34 PM PDT 24
Peak memory 205328 kb
Host smart-3a60fcd1-91ab-459f-b096-5231f5ca2924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532403934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.532403934
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1262459843
Short name T872
Test name
Test status
Simulation time 34916043 ps
CPU time 0.84 seconds
Started Jun 04 02:19:32 PM PDT 24
Finished Jun 04 02:19:33 PM PDT 24
Peak memory 205272 kb
Host smart-e86c1f06-ba01-421c-934a-0a7e8ceed849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262459843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1262459843
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4103885223
Short name T863
Test name
Test status
Simulation time 3118436459 ps
CPU time 6.37 seconds
Started Jun 04 02:19:30 PM PDT 24
Finished Jun 04 02:19:37 PM PDT 24
Peak memory 233880 kb
Host smart-0cb249bb-73b5-47ee-9318-f912ed752dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103885223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4103885223
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4273521045
Short name T3
Test name
Test status
Simulation time 31760288 ps
CPU time 0.72 seconds
Started Jun 04 02:19:38 PM PDT 24
Finished Jun 04 02:19:40 PM PDT 24
Peak memory 204288 kb
Host smart-cfd5b959-c31a-487d-ba45-1902809a6d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273521045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
273521045
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1035265453
Short name T737
Test name
Test status
Simulation time 347301857 ps
CPU time 5.13 seconds
Started Jun 04 02:19:39 PM PDT 24
Finished Jun 04 02:19:45 PM PDT 24
Peak memory 220644 kb
Host smart-70711004-fff9-45da-8f6f-cc6896cdaa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035265453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1035265453
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.846320535
Short name T329
Test name
Test status
Simulation time 119435353 ps
CPU time 0.8 seconds
Started Jun 04 02:19:28 PM PDT 24
Finished Jun 04 02:19:30 PM PDT 24
Peak memory 206192 kb
Host smart-8c1cafba-4fc1-4b34-9cb7-14d9d0a24d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846320535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.846320535
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3501054817
Short name T656
Test name
Test status
Simulation time 21757774778 ps
CPU time 167.91 seconds
Started Jun 04 02:19:36 PM PDT 24
Finished Jun 04 02:22:25 PM PDT 24
Peak memory 248812 kb
Host smart-e6c1ba26-07c9-4583-94e1-bedcfbc837dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501054817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3501054817
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1073348768
Short name T185
Test name
Test status
Simulation time 60132393125 ps
CPU time 362.84 seconds
Started Jun 04 02:19:40 PM PDT 24
Finished Jun 04 02:25:44 PM PDT 24
Peak memory 248848 kb
Host smart-5f375095-5651-4c85-be4e-3231b4044724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073348768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1073348768
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1875861573
Short name T35
Test name
Test status
Simulation time 620489003 ps
CPU time 16.5 seconds
Started Jun 04 02:19:38 PM PDT 24
Finished Jun 04 02:19:56 PM PDT 24
Peak memory 248796 kb
Host smart-7dc04145-39fe-49f8-8323-df750242e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875861573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1875861573
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4077205808
Short name T629
Test name
Test status
Simulation time 7982901985 ps
CPU time 36.56 seconds
Started Jun 04 02:19:37 PM PDT 24
Finished Jun 04 02:20:15 PM PDT 24
Peak memory 224244 kb
Host smart-19b6fc70-e6b6-407a-91eb-71e07fe13a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077205808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4077205808
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.289183523
Short name T85
Test name
Test status
Simulation time 571046293 ps
CPU time 2.42 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:32 PM PDT 24
Peak memory 218416 kb
Host smart-24e71503-2e73-4b44-acab-6bf70bf334db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289183523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.289183523
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1002234945
Short name T472
Test name
Test status
Simulation time 2872292541 ps
CPU time 13.55 seconds
Started Jun 04 02:19:37 PM PDT 24
Finished Jun 04 02:19:52 PM PDT 24
Peak memory 237504 kb
Host smart-dce8e95a-62e8-4c38-afbc-bf6607a96c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002234945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1002234945
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.859891116
Short name T739
Test name
Test status
Simulation time 24980168 ps
CPU time 1.03 seconds
Started Jun 04 02:19:36 PM PDT 24
Finished Jun 04 02:19:37 PM PDT 24
Peak memory 217448 kb
Host smart-a5ff63b0-9eb3-4f45-8bfb-9378bf943f91
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859891116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.859891116
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4067842474
Short name T303
Test name
Test status
Simulation time 682166476 ps
CPU time 4.12 seconds
Started Jun 04 02:19:30 PM PDT 24
Finished Jun 04 02:19:35 PM PDT 24
Peak memory 233248 kb
Host smart-34111e97-ce80-46e1-9914-59ee6772ca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067842474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4067842474
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1597619981
Short name T219
Test name
Test status
Simulation time 182534054 ps
CPU time 3.25 seconds
Started Jun 04 02:19:31 PM PDT 24
Finished Jun 04 02:19:35 PM PDT 24
Peak memory 232892 kb
Host smart-69b2af46-584e-4d7d-bedc-4e7142de9a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597619981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1597619981
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1022800777
Short name T477
Test name
Test status
Simulation time 10193957098 ps
CPU time 9.53 seconds
Started Jun 04 02:19:40 PM PDT 24
Finished Jun 04 02:19:50 PM PDT 24
Peak memory 220116 kb
Host smart-80026cda-cbaa-4e65-b94b-439ba2edfe35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1022800777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1022800777
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1266225919
Short name T492
Test name
Test status
Simulation time 1280742277 ps
CPU time 18.92 seconds
Started Jun 04 02:19:36 PM PDT 24
Finished Jun 04 02:19:55 PM PDT 24
Peak memory 219692 kb
Host smart-0f290340-848e-47f1-b798-93e73e394781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266225919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1266225919
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2741940593
Short name T935
Test name
Test status
Simulation time 5230756267 ps
CPU time 17.87 seconds
Started Jun 04 02:19:30 PM PDT 24
Finished Jun 04 02:19:49 PM PDT 24
Peak memory 215884 kb
Host smart-6772bcd1-153a-4fee-a024-6011c17cd213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741940593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2741940593
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1191596403
Short name T932
Test name
Test status
Simulation time 447426694 ps
CPU time 1.45 seconds
Started Jun 04 02:19:30 PM PDT 24
Finished Jun 04 02:19:33 PM PDT 24
Peak memory 215904 kb
Host smart-93360faa-df70-4344-bc06-1e9f275bcd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191596403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1191596403
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.587029809
Short name T358
Test name
Test status
Simulation time 179483467 ps
CPU time 0.8 seconds
Started Jun 04 02:19:29 PM PDT 24
Finished Jun 04 02:19:30 PM PDT 24
Peak memory 205316 kb
Host smart-aaf86c2a-7749-4b87-88c8-66fd277c4132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587029809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.587029809
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1612835189
Short name T292
Test name
Test status
Simulation time 47248260076 ps
CPU time 19.71 seconds
Started Jun 04 02:19:40 PM PDT 24
Finished Jun 04 02:20:01 PM PDT 24
Peak memory 233836 kb
Host smart-356c3690-9b4d-472b-88fe-d0d588feeaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612835189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1612835189
Directory /workspace/9.spi_device_upload/latest
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