Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3825797	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4090005

1

T1

894

T2

878

T3

995

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4487911	1			T1	5		T2	2		T3	225
values[0x0]	1714637	1			T1	449		T2	437		T3	453
values[0x1]	1713254	1			T1	446		T2	443		T3	434

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2706122	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5209680

1

T1

896

T2

878

T3

1023

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28597	1			T1	3		T3	1		T4	19
valid_sources[0x01]	28621	1			T1	3		T3	1		T4	19
valid_sources[0x02]	28805	1			T1	1		T4	23		T7	29
valid_sources[0x03]	28881	1			T1	3		T2	3		T3	12
valid_sources[0x04]	32217	1			T1	3		T2	17		T3	12
valid_sources[0x05]	30470	1			T1	3		T3	18		T4	22
valid_sources[0x06]	67720	1			T1	2		T2	7		T3	14
valid_sources[0x07]	28863	1			T1	3		T3	2		T4	12
valid_sources[0x08]	28905	1			T4	19		T7	41		T10	22
valid_sources[0x09]	29493	1			T1	2		T3	5		T4	21
valid_sources[0x0a]	30543	1			T1	2		T3	4		T4	15
valid_sources[0x0b]	28452	1			T1	2		T2	13		T3	2
valid_sources[0x0c]	34455	1			T1	1		T3	2		T4	21
valid_sources[0x0d]	27322	1			T1	3		T3	6		T4	14
valid_sources[0x0e]	29184	1			T1	4		T3	4		T4	19
valid_sources[0x0f]	32384	1			T1	7		T3	2		T4	20
valid_sources[0x10]	30556	1			T1	4		T3	7		T4	15
valid_sources[0x11]	28067	1			T1	2		T4	21		T7	28
valid_sources[0x12]	30538	1			T1	5		T2	7		T3	5
valid_sources[0x13]	30951	1			T1	7		T3	3		T4	22
valid_sources[0x14]	30601	1			T1	8		T2	5		T3	4
valid_sources[0x15]	29777	1			T1	1		T4	24		T7	37
valid_sources[0x16]	32005	1			T1	2		T3	2		T4	26
valid_sources[0x17]	26217	1			T1	2		T3	2		T4	27
valid_sources[0x18]	29537	1			T1	2		T3	3		T4	22
valid_sources[0x19]	28743	1			T1	3		T4	24		T7	23
valid_sources[0x1a]	28985	1			T1	4		T2	12		T3	4
valid_sources[0x1b]	31385	1			T1	7		T3	7		T4	24
valid_sources[0x1c]	29927	1			T1	4		T3	7		T4	21
valid_sources[0x1d]	29892	1			T1	5		T4	24		T7	23
valid_sources[0x1e]	31545	1			T1	9		T2	6		T3	9
valid_sources[0x1f]	27578	1			T3	4		T4	19		T7	37
valid_sources[0x20]	30096	1			T1	2		T2	5		T3	3
valid_sources[0x21]	29286	1			T1	2		T3	1		T4	20
valid_sources[0x22]	29320	1			T1	5		T3	7		T4	33
valid_sources[0x23]	30698	1			T1	3		T3	2		T4	23
valid_sources[0x24]	27365	1			T1	5		T4	27		T7	36
valid_sources[0x25]	28626	1			T1	2		T4	21		T7	26
valid_sources[0x26]	32591	1			T1	2		T2	6		T3	1
valid_sources[0x27]	30643	1			T1	4		T2	4		T3	1
valid_sources[0x28]	27455	1			T1	2		T2	15		T3	1
valid_sources[0x29]	27653	1			T2	14		T3	4		T4	30
valid_sources[0x2a]	30959	1			T1	2		T2	9		T3	4
valid_sources[0x2b]	30726	1			T1	2		T2	36		T3	8
valid_sources[0x2c]	28812	1			T1	5		T2	1		T3	12
valid_sources[0x2d]	27550	1			T1	4		T3	16		T4	19
valid_sources[0x2e]	30308	1			T1	2		T3	8		T4	17
valid_sources[0x2f]	35310	1			T1	5		T3	7		T4	20
valid_sources[0x30]	29800	1			T1	8		T3	2		T4	22
valid_sources[0x31]	30256	1			T1	5		T2	1		T3	10
valid_sources[0x32]	28094	1			T1	5		T4	22		T7	28
valid_sources[0x33]	29569	1			T1	6		T2	1		T4	19
valid_sources[0x34]	32641	1			T1	7		T4	18		T7	37
valid_sources[0x35]	31029	1			T1	5		T2	34		T4	17
valid_sources[0x36]	27809	1			T1	5		T3	10		T4	13
valid_sources[0x37]	49520	1			T1	3		T3	5		T4	16
valid_sources[0x38]	31000	1			T1	3		T2	11		T3	6
valid_sources[0x39]	28692	1			T1	2		T3	1		T4	22
valid_sources[0x3a]	27614	1			T1	2		T2	29		T3	14
valid_sources[0x3b]	31108	1			T1	3		T3	3		T4	21
valid_sources[0x3c]	32782	1			T3	13		T4	14		T7	24
valid_sources[0x3d]	31994	1			T1	1		T3	17		T4	22
valid_sources[0x3e]	31380	1			T1	1		T3	7		T4	19
valid_sources[0x3f]	43146	1			T1	4		T2	4		T3	7
valid_sources[0x40]	30347	1			T1	5		T3	8		T4	20
valid_sources[0x41]	28167	1			T1	4		T3	9		T4	23
valid_sources[0x42]	29167	1			T1	3		T2	12		T3	8
valid_sources[0x43]	28100	1			T1	5		T3	4		T4	20
valid_sources[0x44]	28809	1			T1	4		T4	24		T7	39
valid_sources[0x45]	31219	1			T1	1		T2	5		T3	2
valid_sources[0x46]	29062	1			T2	7		T3	3		T4	24
valid_sources[0x47]	29081	1			T2	8		T4	22		T7	50
valid_sources[0x48]	29415	1			T1	2		T3	1		T4	20
valid_sources[0x49]	31381	1			T2	8		T3	1		T4	24
valid_sources[0x4a]	29149	1			T1	4		T3	20		T4	18
valid_sources[0x4b]	28275	1			T1	1		T3	9		T4	23
valid_sources[0x4c]	30594	1			T1	3		T3	6		T4	17
valid_sources[0x4d]	30964	1			T1	7		T2	12		T3	12
valid_sources[0x4e]	30682	1			T1	2		T3	11		T4	20
valid_sources[0x4f]	30395	1			T1	4		T2	28		T3	3
valid_sources[0x50]	30413	1			T1	6		T3	2		T4	18
valid_sources[0x51]	35328	1			T1	5		T4	19		T7	29
valid_sources[0x52]	27435	1			T1	1		T4	17		T7	28
valid_sources[0x53]	29478	1			T1	3		T2	5		T3	6
valid_sources[0x54]	33832	1			T1	1		T2	5		T3	4
valid_sources[0x55]	32411	1			T1	3		T3	3		T4	18
valid_sources[0x56]	35505	1			T1	3		T2	35		T3	5
valid_sources[0x57]	30100	1			T1	6		T2	10		T3	3
valid_sources[0x58]	29152	1			T1	3		T2	6		T3	12
valid_sources[0x59]	28232	1			T1	3		T3	2		T4	26
valid_sources[0x5a]	29706	1			T1	2		T3	13		T4	22
valid_sources[0x5b]	34448	1			T1	4		T2	8		T4	14
valid_sources[0x5c]	29642	1			T1	5		T3	2		T4	17
valid_sources[0x5d]	30323	1			T1	3		T4	21		T7	28
valid_sources[0x5e]	29861	1			T1	9		T3	3		T4	22
valid_sources[0x5f]	31531	1			T1	3		T2	6		T4	31
valid_sources[0x60]	30672	1			T1	3		T4	22		T7	22
valid_sources[0x61]	28674	1			T1	1		T3	5		T4	24
valid_sources[0x62]	29071	1			T1	5		T2	12		T4	23
valid_sources[0x63]	34074	1			T1	3		T3	6		T4	34
valid_sources[0x64]	28993	1			T1	6		T4	22		T7	27
valid_sources[0x65]	33032	1			T1	3		T4	11		T7	28
valid_sources[0x66]	31198	1			T1	3		T2	1		T3	9
valid_sources[0x67]	28442	1			T1	5		T2	10		T3	5
valid_sources[0x68]	29205	1			T1	1		T2	11		T3	6
valid_sources[0x69]	28876	1			T1	1		T3	3		T4	22
valid_sources[0x6a]	34273	1			T1	3		T3	4		T4	20
valid_sources[0x6b]	32303	1			T1	4		T2	5		T3	2
valid_sources[0x6c]	32731	1			T1	8		T3	2		T4	21
valid_sources[0x6d]	33997	1			T1	1		T3	16		T4	16
valid_sources[0x6e]	27651	1			T1	6		T2	29		T4	18
valid_sources[0x6f]	28846	1			T1	2		T4	22		T7	30
valid_sources[0x70]	30111	1			T1	2		T3	4		T4	23
valid_sources[0x71]	28715	1			T1	9		T2	8		T3	7
valid_sources[0x72]	32546	1			T1	4		T3	6		T4	17
valid_sources[0x73]	34756	1			T1	2		T4	25		T7	27
valid_sources[0x74]	29402	1			T1	3		T4	19		T7	28
valid_sources[0x75]	29769	1			T1	5		T3	4		T4	15
valid_sources[0x76]	30452	1			T1	4		T3	1		T4	15
valid_sources[0x77]	42035	1			T1	3		T3	2		T4	19
valid_sources[0x78]	27564	1			T1	3		T3	6		T4	15
valid_sources[0x79]	27030	1			T1	4		T3	1		T4	20
valid_sources[0x7a]	27501	1			T1	1		T3	1		T4	29
valid_sources[0x7b]	30639	1			T1	9		T3	1		T4	18
valid_sources[0x7c]	29459	1			T1	4		T2	2		T3	3
valid_sources[0x7d]	29860	1			T1	5		T2	26		T3	9
valid_sources[0x7e]	31529	1			T1	3		T3	4		T4	15
valid_sources[0x7f]	28561	1			T1	2		T3	4		T4	15
valid_sources[0x80]	29187	1			T1	4		T3	6		T4	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1016464

1

T1

2

T2

1

T3

112

values[0x0]

all_enables

biggest_size

1550077

1

T1

447

T2

435

T3

451

values[0x1]

all_enables

biggest_size

1523464

1

T1

445

T2

442

T3

432