Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3843546

1

T1

6

T2

4

T3

117

full_word

4088984

1

T1

894

T2

878

T3

995

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7932130	1			T1	900		T2	882		T3	1112
auto[TlIntgErrCmd]	121	1			T89	11		T92	9		T94	12
auto[TlIntgErrData]	133	1			T89	13		T92	11		T94	9
auto[TlIntgErrBoth]	146	1			T89	6		T92	10		T94	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4489147

1

T1

5

T2

2

T3

225

auto[1]

3443383

1

T1

895

T2

880

T3

887

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3472451	1			T1	3		T2	1		T3	113
auto[TlIntgErrNone]	partial	auto[1]	370731	1			T1	3		T2	3		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	1016524	1			T1	2		T2	1		T3	112
auto[TlIntgErrNone]	full_word	auto[1]	3072424	1			T1	892		T2	877		T3	883
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T89	2		T92	1		T94	3
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T89	8		T92	7		T94	8
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T94	1		T143	1		T239	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T89	1		T92	1		T143	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T89	5		T92	5		T94	4
auto[TlIntgErrData]	partial	auto[1]	67	1			T89	6		T92	6		T94	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T89	1		T141	1		T239	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T89	1		T242	1		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T89	3		T92	4		T94	4
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T89	3		T92	4		T94	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T92	1		T242	1		T243	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T92	1		T94	2		T110	2