SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_scanmode_sync | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.62 | 93.89 | 84.31 | 96.94 | 87.50 | 95.45 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 926 | 926 | 0 | 0 |
OutputsKnown_A | 417457136 | 417375191 | 0 | 0 |
gen_no_flops.OutputDelay_A | 417457136 | 417375191 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 926 | 926 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 417457136 | 417375191 | 0 | 0 |
T1 | 55485 | 55413 | 0 | 0 |
T2 | 10199 | 10149 | 0 | 0 |
T3 | 7369 | 7293 | 0 | 0 |
T4 | 103110 | 103046 | 0 | 0 |
T5 | 18036 | 17943 | 0 | 0 |
T6 | 3259 | 3167 | 0 | 0 |
T7 | 145217 | 145147 | 0 | 0 |
T8 | 664 | 567 | 0 | 0 |
T9 | 46800 | 46726 | 0 | 0 |
T10 | 713749 | 713697 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 417457136 | 417375191 | 0 | 0 |
T1 | 55485 | 55413 | 0 | 0 |
T2 | 10199 | 10149 | 0 | 0 |
T3 | 7369 | 7293 | 0 | 0 |
T4 | 103110 | 103046 | 0 | 0 |
T5 | 18036 | 17943 | 0 | 0 |
T6 | 3259 | 3167 | 0 | 0 |
T7 | 145217 | 145147 | 0 | 0 |
T8 | 664 | 567 | 0 | 0 |
T9 | 46800 | 46726 | 0 | 0 |
T10 | 713749 | 713697 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |