Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T4,T10,T12
1	0	Covered	T4,T10,T12
1	1	Covered	T10,T12,T13

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T12
1	0	Covered	T10,T12,T13
1	1	Covered	T4,T10,T12

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1252371408	2192	0	0
SrcPulseCheck_M	401200557	2192	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1252371408	2192	0	0
T4	103110	1	0	0
T5	18036	0	0	0
T6	3259	0	0	0
T7	145217	0	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	1427498	10	0	0
T11	418024	0	0	0
T12	291142	10	0	0
T13	317549	4	0	0
T15	0	6	0	0
T16	0	7	0	0
T17	0	9	0	0
T18	0	19	0	0
T24	61271	0	0	0
T25	172237	9	0	0
T26	228890	6	0	0
T27	111517	14	0	0
T28	2858	0	0	0
T35	28512	7	0	0
T36	15316	0	0	0
T37	0	22	0	0
T38	0	1	0	0
T39	0	3	0	0
T54	1246	0	0	0
T65	0	4	0	0
T87	45485	0	0	0
T97	10009	0	0	0
T125	14848	0	0	0
T133	0	2	0	0
T134	0	7	0	0
T135	0	7	0	0
T136	0	7	0	0
T137	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401200557	2192	0	0
T4	16876	1	0	0
T5	2946	0	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	266896	10	0	0
T11	82122	0	0	0
T12	1301068	10	0	0
T13	291492	4	0	0
T14	1152	0	0	0
T15	489102	6	0	0
T16	460916	7	0	0
T17	0	9	0	0
T18	432548	19	0	0
T24	339878	0	0	0
T25	566617	9	0	0
T26	185061	6	0	0
T27	180374	14	0	0
T35	38706	7	0	0
T36	2088	0	0	0
T37	0	22	0	0
T38	0	1	0	0
T39	0	3	0	0
T65	0	4	0	0
T87	35439	0	0	0
T97	3809	0	0	0
T125	2064	0	0	0
T133	0	2	0	0
T134	0	7	0	0
T135	0	7	0	0
T136	0	7	0	0
T137	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T35,T37,T38
1	0	Covered	T35,T37,T38
1	1	Covered	T35,T37,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T35,T37,T38
1	0	Covered	T35,T37,T39
1	1	Covered	T35,T37,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	417457136	174	0	0
SrcPulseCheck_M	133733519	174	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	174	0	0
T24	61271	0	0	0
T25	172237	0	0	0
T26	228890	0	0	0
T27	111517	0	0	0
T35	28512	2	0	0
T36	15316	0	0	0
T37	0	11	0	0
T38	0	1	0	0
T39	0	2	0	0
T54	1246	0	0	0
T65	0	2	0	0
T87	45485	0	0	0
T97	10009	0	0	0
T125	14848	0	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	174	0	0
T18	432548	0	0	0
T24	169939	0	0	0
T25	566617	0	0	0
T26	185061	0	0	0
T27	180374	0	0	0
T35	19353	2	0	0
T36	2088	0	0	0
T37	0	11	0	0
T38	0	1	0	0
T39	0	2	0	0
T65	0	2	0	0
T87	35439	0	0	0
T97	3809	0	0	0
T125	2064	0	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T4,T35,T37
1	0	Covered	T4,T35,T37
1	1	Covered	T35,T37,T134

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T35,T37
1	0	Covered	T35,T37,T134
1	1	Covered	T4,T35,T37

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	417457136	316	0	0
SrcPulseCheck_M	133733519	316	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	316	0	0
T4	103110	1	0	0
T5	18036	0	0	0
T6	3259	0	0	0
T7	145217	0	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	0	0	0
T11	209012	0	0	0
T12	145571	0	0	0
T28	1429	0	0	0
T35	0	5	0	0
T37	0	11	0	0
T39	0	1	0	0
T65	0	2	0	0
T133	0	1	0	0
T134	0	5	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	316	0	0
T4	16876	1	0	0
T5	2946	0	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	133448	0	0	0
T11	41061	0	0	0
T12	650534	0	0	0
T13	145746	0	0	0
T14	576	0	0	0
T15	244551	0	0	0
T35	0	5	0	0
T37	0	11	0	0
T39	0	1	0	0
T65	0	2	0	0
T133	0	1	0	0
T134	0	5	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13
1	1	Covered	T10,T12,T13

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13
1	1	Covered	T10,T12,T13

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	417457136	1702	0	0
SrcPulseCheck_M	133733519	1702	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	1702	0	0
T10	713749	10	0	0
T11	209012	0	0	0
T12	145571	10	0	0
T13	317549	4	0	0
T14	6073	0	0	0
T15	173021	6	0	0
T16	550675	7	0	0
T17	437582	9	0	0
T18	0	19	0	0
T25	0	9	0	0
T26	0	6	0	0
T27	0	14	0	0
T28	1429	0	0	0
T53	1745	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	1702	0	0
T10	133448	10	0	0
T11	41061	0	0	0
T12	650534	10	0	0
T13	145746	4	0	0
T14	576	0	0	0
T15	244551	6	0	0
T16	460916	7	0	0
T17	718838	9	0	0
T18	0	19	0	0
T24	169939	0	0	0
T25	0	9	0	0
T26	0	6	0	0
T27	0	14	0	0
T35	19353	0	0	0