Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420108857	2587242	0	0
DepthKnown_A	420108857	419981793	0	0
RvalidKnown_A	420108857	419981793	0	0
WreadyKnown_A	420108857	419981793	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	2587242	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	1670	0	0
T4	103110	2174	0	0
T5	18036	0	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	19142	0	0
T12	0	15834	0	0
T13	0	4990	0	0
T15	0	12493	0	0
T16	0	8317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420108857	2847416	0	0
DepthKnown_A	420108857	419981793	0	0
RvalidKnown_A	420108857	419981793	0	0
WreadyKnown_A	420108857	419981793	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	2847416	0	0
T1	55485	3754	0	0
T2	10199	3651	0	0
T3	7369	840	0	0
T4	103110	1088	0	0
T5	18036	0	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	27042	0	0
T12	0	18479	0	0
T13	0	3328	0	0
T15	0	9553	0	0
T16	0	5824	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420108857	160972	0	0
DepthKnown_A	420108857	419981793	0	0
RvalidKnown_A	420108857	419981793	0	0
WreadyKnown_A	420108857	419981793	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	160972	0	0
T5	18036	33	0	0
T6	3259	0	0	0
T7	145217	0	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	1323	0	0
T11	209012	0	0	0
T12	145571	1029	0	0
T13	317549	0	0	0
T15	0	235	0	0
T16	0	921	0	0
T17	0	535	0	0
T24	0	309	0	0
T25	0	485	0	0
T26	0	65	0	0
T27	0	448	0	0
T28	1429	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420108857	383273	0	0
DepthKnown_A	420108857	419981793	0	0
RvalidKnown_A	420108857	419981793	0	0
WreadyKnown_A	420108857	419981793	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	383273	0	0
T5	18036	33	0	0
T6	3259	0	0	0
T7	145217	0	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	6156	0	0
T11	209012	0	0	0
T12	145571	4690	0	0
T13	317549	0	0	0
T15	0	1087	0	0
T16	0	921	0	0
T17	0	2567	0	0
T24	0	1005	0	0
T25	0	2197	0	0
T26	0	176	0	0
T27	0	1342	0	0
T28	1429	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420108857	6562355	0	0
DepthKnown_A	420108857	419981793	0	0
RvalidKnown_A	420108857	419981793	0	0
WreadyKnown_A	420108857	419981793	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	6562355	0	0
T1	55485	68	0	0
T2	10199	50	0	0
T3	7369	280	0	0
T4	103110	4022	0	0
T5	18036	4353	0	0
T6	3259	148	0	0
T7	145217	7192	0	0
T8	664	2	0	0
T9	46800	228	0	0
T10	713749	19610	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420108857	14471458	0	0
DepthKnown_A	420108857	419981793	0	0
RvalidKnown_A	420108857	419981793	0	0
WreadyKnown_A	420108857	419981793	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	14471458	0	0
T1	55485	314	0	0
T2	10199	197	0	0
T3	7369	1126	0	0
T4	103110	4022	0	0
T5	18036	4353	0	0
T6	3259	148	0	0
T7	145217	7192	0	0
T8	664	2	0	0
T9	46800	228	0	0
T10	713749	77233	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420108857	419981793	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0