Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Unreachable
1	1	Covered	T5,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T10,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	684924174	549803268	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	684924174	3145825	0	0
GntImpliesValid_A	684924174	3145825	0	0
GrantKnown_A	684924174	549803268	0	0
IdxKnown_A	684924174	549803268	0	0
IndexIsCorrect_A	684924174	3145825	0	0
LockArbDecision_A	684924174	0	0	0
NoReadyValidNoGrant_A	684924174	0	0	0
ReadyAndValidImplyGrant_A	684924174	3145825	0	0
ReqAndReadyImplyGrant_A	684924174	3145825	0	0
ReqImpliesValid_A	684924174	3145825	0	0
ReqStaysHighUntilGranted0_M	684924174	0	0	0
RoundRobin_A	684924174	4	0	926
ValidKnown_A	684924174	549803268	0	0
gen_data_port_assertion.DataFlow_A	684924174	3145825	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	549803268	0	0
T1	144000	143499	0	0
T2	10199	10149	0	0
T3	15865	15789	0	0
T4	119986	119528	0	0
T5	23928	20407	0	0
T6	3259	3167	0	0
T7	237089	191083	0	0
T8	664	567	0	0
T9	125282	83766	0	0
T10	980645	2039908	0	0
T11	82122	38448	0	0
T12	1301068	645160	0	0
T13	291492	145364	0	0
T14	576	576	0	0
T15	244551	241981	0	0
T16	460916	452274	0	0
T17	0	716158	0	0
T24	0	168432	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	3145825	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	20982	227	0	0
T6	3259	0	0	0
T7	191153	832	0	0
T8	664	0	0	0
T9	86041	0	0	0
T10	980645	23171	0	0
T11	82122	0	0	0
T12	1301068	17808	0	0
T13	291492	3342	0	0
T14	1152	0	0	0
T15	489102	9945	0	0
T16	921832	5335	0	0
T17	718838	9091	0	0
T18	0	7728	0	0
T24	169939	1841	0	0
T25	0	2452	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0
T40	0	1576	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	3145825	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	20982	227	0	0
T6	3259	0	0	0
T7	191153	832	0	0
T8	664	0	0	0
T9	86041	0	0	0
T10	980645	23171	0	0
T11	82122	0	0	0
T12	1301068	17808	0	0
T13	291492	3342	0	0
T14	1152	0	0	0
T15	489102	9945	0	0
T16	921832	5335	0	0
T17	718838	9091	0	0
T18	0	7728	0	0
T24	169939	1841	0	0
T25	0	2452	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0
T40	0	1576	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	549803268	0	0
T1	144000	143499	0	0
T2	10199	10149	0	0
T3	15865	15789	0	0
T4	119986	119528	0	0
T5	23928	20407	0	0
T6	3259	3167	0	0
T7	237089	191083	0	0
T8	664	567	0	0
T9	125282	83766	0	0
T10	980645	2039908	0	0
T11	82122	38448	0	0
T12	1301068	645160	0	0
T13	291492	145364	0	0
T14	576	576	0	0
T15	244551	241981	0	0
T16	460916	452274	0	0
T17	0	716158	0	0
T24	0	168432	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	549803268	0	0
T1	144000	143499	0	0
T2	10199	10149	0	0
T3	15865	15789	0	0
T4	119986	119528	0	0
T5	23928	20407	0	0
T6	3259	3167	0	0
T7	237089	191083	0	0
T8	664	567	0	0
T9	125282	83766	0	0
T10	980645	2039908	0	0
T11	82122	38448	0	0
T12	1301068	645160	0	0
T13	291492	145364	0	0
T14	576	576	0	0
T15	244551	241981	0	0
T16	460916	452274	0	0
T17	0	716158	0	0
T24	0	168432	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	3145825	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	20982	227	0	0
T6	3259	0	0	0
T7	191153	832	0	0
T8	664	0	0	0
T9	86041	0	0	0
T10	980645	23171	0	0
T11	82122	0	0	0
T12	1301068	17808	0	0
T13	291492	3342	0	0
T14	1152	0	0	0
T15	489102	9945	0	0
T16	921832	5335	0	0
T17	718838	9091	0	0
T18	0	7728	0	0
T24	169939	1841	0	0
T25	0	2452	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0
T40	0	1576	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	3145825	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	20982	227	0	0
T6	3259	0	0	0
T7	191153	832	0	0
T8	664	0	0	0
T9	86041	0	0	0
T10	980645	23171	0	0
T11	82122	0	0	0
T12	1301068	17808	0	0
T13	291492	3342	0	0
T14	1152	0	0	0
T15	489102	9945	0	0
T16	921832	5335	0	0
T17	718838	9091	0	0
T18	0	7728	0	0
T24	169939	1841	0	0
T25	0	2452	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0
T40	0	1576	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	3145825	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	20982	227	0	0
T6	3259	0	0	0
T7	191153	832	0	0
T8	664	0	0	0
T9	86041	0	0	0
T10	980645	23171	0	0
T11	82122	0	0	0
T12	1301068	17808	0	0
T13	291492	3342	0	0
T14	1152	0	0	0
T15	489102	9945	0	0
T16	921832	5335	0	0
T17	718838	9091	0	0
T18	0	7728	0	0
T24	169939	1841	0	0
T25	0	2452	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0
T40	0	1576	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	3145825	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	20982	227	0	0
T6	3259	0	0	0
T7	191153	832	0	0
T8	664	0	0	0
T9	86041	0	0	0
T10	980645	23171	0	0
T11	82122	0	0	0
T12	1301068	17808	0	0
T13	291492	3342	0	0
T14	1152	0	0	0
T15	489102	9945	0	0
T16	921832	5335	0	0
T17	718838	9091	0	0
T18	0	7728	0	0
T24	169939	1841	0	0
T25	0	2452	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0
T40	0	1576	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	4	0	926
T19	248454	0	0	1
T41	204136	1	0	1
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	327247	0	0	1
T46	120383	0	0	1
T47	980	0	0	1
T48	66295	0	0	1
T49	346505	0	0	1
T50	631102	0	0	1
T51	102327	0	0	1
T52	418453	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	549803268	0	0
T1	144000	143499	0	0
T2	10199	10149	0	0
T3	15865	15789	0	0
T4	119986	119528	0	0
T5	23928	20407	0	0
T6	3259	3167	0	0
T7	237089	191083	0	0
T8	664	567	0	0
T9	125282	83766	0	0
T10	980645	2039908	0	0
T11	82122	38448	0	0
T12	1301068	645160	0	0
T13	291492	145364	0	0
T14	576	576	0	0
T15	244551	241981	0	0
T16	460916	452274	0	0
T17	0	716158	0	0
T24	0	168432	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	684924174	3145825	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	20982	227	0	0
T6	3259	0	0	0
T7	191153	832	0	0
T8	664	0	0	0
T9	86041	0	0	0
T10	980645	23171	0	0
T11	82122	0	0	0
T12	1301068	17808	0	0
T13	291492	3342	0	0
T14	1152	0	0	0
T15	489102	9945	0	0
T16	921832	5335	0	0
T17	718838	9091	0	0
T18	0	7728	0	0
T24	169939	1841	0	0
T25	0	2452	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0
T40	0	1576	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Unreachable
1	1	Covered	T5,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T10,T12
0	0	1	Unreachable
0	0	0	Covered	T5,T9,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	133733519	26852136	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	133733519	645973	0	0
GntImpliesValid_A	133733519	645973	0	0
GrantKnown_A	133733519	26852136	0	0
IdxKnown_A	133733519	26852136	0	0
IndexIsCorrect_A	133733519	645973	0	0
LockArbDecision_A	133733519	0	0	0
NoReadyValidNoGrant_A	133733519	0	0	0
ReadyAndValidImplyGrant_A	133733519	645973	0	0
ReqAndReadyImplyGrant_A	133733519	645973	0	0
ReqImpliesValid_A	133733519	645973	0	0
ReqStaysHighUntilGranted0_M	133733519	0	0	0
RoundRobin_A	133733519	0	0	0
ValidKnown_A	133733519	26852136	0	0
gen_data_port_assertion.DataFlow_A	133733519	645973	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	26852136	0	0
T5	2946	2464	0	0
T7	45936	0	0	0
T9	39241	37040	0	0
T10	133448	389680	0	0
T11	41061	38448	0	0
T12	650534	210312	0	0
T13	145746	0	0	0
T14	576	576	0	0
T15	244551	19224	0	0
T16	460916	197360	0	0
T17	0	14400	0	0
T24	0	168432	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	645973	0	0
T5	2946	163	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	133448	6659	0	0
T11	41061	0	0	0
T12	650534	5845	0	0
T13	145746	0	0	0
T14	576	0	0	0
T15	244551	929	0	0
T16	460916	5322	0	0
T17	0	763	0	0
T18	0	4328	0	0
T24	0	1841	0	0
T25	0	1615	0	0
T40	0	1576	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	645973	0	0
T5	2946	163	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	133448	6659	0	0
T11	41061	0	0	0
T12	650534	5845	0	0
T13	145746	0	0	0
T14	576	0	0	0
T15	244551	929	0	0
T16	460916	5322	0	0
T17	0	763	0	0
T18	0	4328	0	0
T24	0	1841	0	0
T25	0	1615	0	0
T40	0	1576	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	26852136	0	0
T5	2946	2464	0	0
T7	45936	0	0	0
T9	39241	37040	0	0
T10	133448	389680	0	0
T11	41061	38448	0	0
T12	650534	210312	0	0
T13	145746	0	0	0
T14	576	576	0	0
T15	244551	19224	0	0
T16	460916	197360	0	0
T17	0	14400	0	0
T24	0	168432	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	26852136	0	0
T5	2946	2464	0	0
T7	45936	0	0	0
T9	39241	37040	0	0
T10	133448	389680	0	0
T11	41061	38448	0	0
T12	650534	210312	0	0
T13	145746	0	0	0
T14	576	576	0	0
T15	244551	19224	0	0
T16	460916	197360	0	0
T17	0	14400	0	0
T24	0	168432	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	645973	0	0
T5	2946	163	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	133448	6659	0	0
T11	41061	0	0	0
T12	650534	5845	0	0
T13	145746	0	0	0
T14	576	0	0	0
T15	244551	929	0	0
T16	460916	5322	0	0
T17	0	763	0	0
T18	0	4328	0	0
T24	0	1841	0	0
T25	0	1615	0	0
T40	0	1576	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	645973	0	0
T5	2946	163	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	133448	6659	0	0
T11	41061	0	0	0
T12	650534	5845	0	0
T13	145746	0	0	0
T14	576	0	0	0
T15	244551	929	0	0
T16	460916	5322	0	0
T17	0	763	0	0
T18	0	4328	0	0
T24	0	1841	0	0
T25	0	1615	0	0
T40	0	1576	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	645973	0	0
T5	2946	163	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	133448	6659	0	0
T11	41061	0	0	0
T12	650534	5845	0	0
T13	145746	0	0	0
T14	576	0	0	0
T15	244551	929	0	0
T16	460916	5322	0	0
T17	0	763	0	0
T18	0	4328	0	0
T24	0	1841	0	0
T25	0	1615	0	0
T40	0	1576	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	645973	0	0
T5	2946	163	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	133448	6659	0	0
T11	41061	0	0	0
T12	650534	5845	0	0
T13	145746	0	0	0
T14	576	0	0	0
T15	244551	929	0	0
T16	460916	5322	0	0
T17	0	763	0	0
T18	0	4328	0	0
T24	0	1841	0	0
T25	0	1615	0	0
T40	0	1576	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	26852136	0	0
T5	2946	2464	0	0
T7	45936	0	0	0
T9	39241	37040	0	0
T10	133448	389680	0	0
T11	41061	38448	0	0
T12	650534	210312	0	0
T13	145746	0	0	0
T14	576	576	0	0
T15	244551	19224	0	0
T16	460916	197360	0	0
T17	0	14400	0	0
T24	0	168432	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	645973	0	0
T5	2946	163	0	0
T7	45936	0	0	0
T9	39241	0	0	0
T10	133448	6659	0	0
T11	41061	0	0	0
T12	650534	5845	0	0
T13	145746	0	0	0
T14	576	0	0	0
T15	244551	929	0	0
T16	460916	5322	0	0
T17	0	763	0	0
T18	0	4328	0	0
T24	0	1841	0	0
T25	0	1615	0	0
T40	0	1576	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T10,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T12,T13
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	133733519	105575941	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	133733519	464645	0	0
GntImpliesValid_A	133733519	464645	0	0
GrantKnown_A	133733519	105575941	0	0
IdxKnown_A	133733519	105575941	0	0
IndexIsCorrect_A	133733519	464645	0	0
LockArbDecision_A	133733519	0	0	0
NoReadyValidNoGrant_A	133733519	0	0	0
ReadyAndValidImplyGrant_A	133733519	464645	0	0
ReqAndReadyImplyGrant_A	133733519	464645	0	0
ReqImpliesValid_A	133733519	464645	0	0
ReqStaysHighUntilGranted0_M	133733519	0	0	0
RoundRobin_A	133733519	0	0	0
ValidKnown_A	133733519	105575941	0	0
gen_data_port_assertion.DataFlow_A	133733519	464645	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	105575941	0	0
T1	88515	88086	0	0
T3	8496	8496	0	0
T4	16876	16482	0	0
T5	2946	0	0	0
T7	45936	45936	0	0
T9	39241	0	0	0
T10	133448	936531	0	0
T11	41061	0	0	0
T12	650534	434848	0	0
T13	145746	145364	0	0
T15	0	222757	0	0
T16	0	254914	0	0
T17	0	701758	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	464645	0	0
T10	133448	1664	0	0
T11	41061	0	0	0
T12	650534	20	0	0
T13	145746	7	0	0
T14	576	0	0	0
T15	244551	1839	0	0
T16	460916	13	0	0
T17	718838	8328	0	0
T18	0	3400	0	0
T24	169939	0	0	0
T25	0	837	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	464645	0	0
T10	133448	1664	0	0
T11	41061	0	0	0
T12	650534	20	0	0
T13	145746	7	0	0
T14	576	0	0	0
T15	244551	1839	0	0
T16	460916	13	0	0
T17	718838	8328	0	0
T18	0	3400	0	0
T24	169939	0	0	0
T25	0	837	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	105575941	0	0
T1	88515	88086	0	0
T3	8496	8496	0	0
T4	16876	16482	0	0
T5	2946	0	0	0
T7	45936	45936	0	0
T9	39241	0	0	0
T10	133448	936531	0	0
T11	41061	0	0	0
T12	650534	434848	0	0
T13	145746	145364	0	0
T15	0	222757	0	0
T16	0	254914	0	0
T17	0	701758	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	105575941	0	0
T1	88515	88086	0	0
T3	8496	8496	0	0
T4	16876	16482	0	0
T5	2946	0	0	0
T7	45936	45936	0	0
T9	39241	0	0	0
T10	133448	936531	0	0
T11	41061	0	0	0
T12	650534	434848	0	0
T13	145746	145364	0	0
T15	0	222757	0	0
T16	0	254914	0	0
T17	0	701758	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	464645	0	0
T10	133448	1664	0	0
T11	41061	0	0	0
T12	650534	20	0	0
T13	145746	7	0	0
T14	576	0	0	0
T15	244551	1839	0	0
T16	460916	13	0	0
T17	718838	8328	0	0
T18	0	3400	0	0
T24	169939	0	0	0
T25	0	837	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	464645	0	0
T10	133448	1664	0	0
T11	41061	0	0	0
T12	650534	20	0	0
T13	145746	7	0	0
T14	576	0	0	0
T15	244551	1839	0	0
T16	460916	13	0	0
T17	718838	8328	0	0
T18	0	3400	0	0
T24	169939	0	0	0
T25	0	837	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	464645	0	0
T10	133448	1664	0	0
T11	41061	0	0	0
T12	650534	20	0	0
T13	145746	7	0	0
T14	576	0	0	0
T15	244551	1839	0	0
T16	460916	13	0	0
T17	718838	8328	0	0
T18	0	3400	0	0
T24	169939	0	0	0
T25	0	837	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	464645	0	0
T10	133448	1664	0	0
T11	41061	0	0	0
T12	650534	20	0	0
T13	145746	7	0	0
T14	576	0	0	0
T15	244551	1839	0	0
T16	460916	13	0	0
T17	718838	8328	0	0
T18	0	3400	0	0
T24	169939	0	0	0
T25	0	837	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	105575941	0	0
T1	88515	88086	0	0
T3	8496	8496	0	0
T4	16876	16482	0	0
T5	2946	0	0	0
T7	45936	45936	0	0
T9	39241	0	0	0
T10	133448	936531	0	0
T11	41061	0	0	0
T12	650534	434848	0	0
T13	145746	145364	0	0
T15	0	222757	0	0
T16	0	254914	0	0
T17	0	701758	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133733519	464645	0	0
T10	133448	1664	0	0
T11	41061	0	0	0
T12	650534	20	0	0
T13	145746	7	0	0
T14	576	0	0	0
T15	244551	1839	0	0
T16	460916	13	0	0
T17	718838	8328	0	0
T18	0	3400	0	0
T24	169939	0	0	0
T25	0	837	0	0
T26	0	274	0	0
T27	0	3705	0	0
T35	19353	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417457136	417375191	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	417457136	2035207	0	0
GntImpliesValid_A	417457136	2035207	0	0
GrantKnown_A	417457136	417375191	0	0
IdxKnown_A	417457136	417375191	0	0
IndexIsCorrect_A	417457136	2035207	0	0
LockArbDecision_A	417457136	0	0	0
NoReadyValidNoGrant_A	417457136	0	0	0
ReadyAndValidImplyGrant_A	417457136	2035207	0	0
ReqAndReadyImplyGrant_A	417457136	2035207	0	0
ReqImpliesValid_A	417457136	2035207	0	0
ReqStaysHighUntilGranted0_M	417457136	0	0	0
RoundRobin_A	417457136	4	0	926
ValidKnown_A	417457136	417375191	0	0
gen_data_port_assertion.DataFlow_A	417457136	2035207	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	417375191	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	2035207	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	18036	64	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	14848	0	0
T12	0	11943	0	0
T13	0	3335	0	0
T15	0	7177	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	2035207	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	18036	64	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	14848	0	0
T12	0	11943	0	0
T13	0	3335	0	0
T15	0	7177	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	417375191	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	417375191	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	2035207	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	18036	64	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	14848	0	0
T12	0	11943	0	0
T13	0	3335	0	0
T15	0	7177	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	2035207	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	18036	64	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	14848	0	0
T12	0	11943	0	0
T13	0	3335	0	0
T15	0	7177	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	2035207	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	18036	64	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	14848	0	0
T12	0	11943	0	0
T13	0	3335	0	0
T15	0	7177	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	2035207	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	18036	64	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	14848	0	0
T12	0	11943	0	0
T13	0	3335	0	0
T15	0	7177	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	4	0	926
T19	248454	0	0	1
T41	204136	1	0	1
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	327247	0	0	1
T46	120383	0	0	1
T47	980	0	0	1
T48	66295	0	0	1
T49	346505	0	0	1
T50	631102	0	0	1
T51	102327	0	0	1
T52	418453	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	417375191	0	0
T1	55485	55413	0	0
T2	10199	10149	0	0
T3	7369	7293	0	0
T4	103110	103046	0	0
T5	18036	17943	0	0
T6	3259	3167	0	0
T7	145217	145147	0	0
T8	664	567	0	0
T9	46800	46726	0	0
T10	713749	713697	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417457136	2035207	0	0
T1	55485	832	0	0
T2	10199	832	0	0
T3	7369	832	0	0
T4	103110	1088	0	0
T5	18036	64	0	0
T6	3259	0	0	0
T7	145217	832	0	0
T8	664	0	0	0
T9	46800	0	0	0
T10	713749	14848	0	0
T12	0	11943	0	0
T13	0	3335	0	0
T15	0	7177	0	0