Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3752 |
0 |
0 |
T88 |
11602 |
12 |
0 |
0 |
T89 |
81774 |
3 |
0 |
0 |
T90 |
6682 |
121 |
0 |
0 |
T92 |
91086 |
3 |
0 |
0 |
T93 |
6898 |
100 |
0 |
0 |
T94 |
101263 |
2 |
0 |
0 |
T95 |
4788 |
15 |
0 |
0 |
T96 |
9739 |
228 |
0 |
0 |
T99 |
5772 |
215 |
0 |
0 |
T109 |
5587 |
17 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3046 |
0 |
0 |
T88 |
11602 |
8 |
0 |
0 |
T92 |
91086 |
76 |
0 |
0 |
T94 |
101263 |
107 |
0 |
0 |
T110 |
33177 |
20 |
0 |
0 |
T118 |
74476 |
478 |
0 |
0 |
T138 |
8043 |
5 |
0 |
0 |
T139 |
14742 |
17 |
0 |
0 |
T140 |
2438 |
3 |
0 |
0 |
T141 |
105597 |
101 |
0 |
0 |
T142 |
15122 |
16 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2819 |
0 |
0 |
T88 |
11602 |
13 |
0 |
0 |
T92 |
91086 |
75 |
0 |
0 |
T94 |
101263 |
121 |
0 |
0 |
T110 |
33177 |
14 |
0 |
0 |
T118 |
74476 |
488 |
0 |
0 |
T138 |
8043 |
5 |
0 |
0 |
T139 |
14742 |
10 |
0 |
0 |
T140 |
2438 |
6 |
0 |
0 |
T141 |
105597 |
114 |
0 |
0 |
T142 |
15122 |
23 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3617 |
0 |
0 |
T88 |
11602 |
17 |
0 |
0 |
T92 |
91086 |
139 |
0 |
0 |
T94 |
101263 |
234 |
0 |
0 |
T110 |
33177 |
21 |
0 |
0 |
T118 |
74476 |
450 |
0 |
0 |
T138 |
8043 |
13 |
0 |
0 |
T139 |
14742 |
11 |
0 |
0 |
T140 |
2438 |
4 |
0 |
0 |
T141 |
105597 |
269 |
0 |
0 |
T142 |
15122 |
26 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
13681 |
0 |
0 |
T88 |
11602 |
5 |
0 |
0 |
T92 |
91086 |
986 |
0 |
0 |
T94 |
101263 |
2188 |
0 |
0 |
T110 |
33177 |
294 |
0 |
0 |
T118 |
74476 |
547 |
0 |
0 |
T138 |
8043 |
130 |
0 |
0 |
T139 |
14742 |
225 |
0 |
0 |
T140 |
2438 |
6 |
0 |
0 |
T141 |
105597 |
1606 |
0 |
0 |
T142 |
15122 |
123 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
14094 |
0 |
0 |
T88 |
11602 |
26 |
0 |
0 |
T92 |
91086 |
1383 |
0 |
0 |
T94 |
101263 |
1862 |
0 |
0 |
T110 |
33177 |
334 |
0 |
0 |
T118 |
74476 |
490 |
0 |
0 |
T138 |
8043 |
15 |
0 |
0 |
T139 |
14742 |
171 |
0 |
0 |
T141 |
105597 |
2276 |
0 |
0 |
T142 |
15122 |
269 |
0 |
0 |
T143 |
62857 |
691 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
14069 |
0 |
0 |
T88 |
11602 |
4 |
0 |
0 |
T92 |
91086 |
804 |
0 |
0 |
T94 |
101263 |
1667 |
0 |
0 |
T110 |
33177 |
377 |
0 |
0 |
T118 |
74476 |
532 |
0 |
0 |
T138 |
8043 |
125 |
0 |
0 |
T139 |
14742 |
62 |
0 |
0 |
T140 |
2438 |
6 |
0 |
0 |
T141 |
105597 |
2741 |
0 |
0 |
T142 |
15122 |
259 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
13721 |
0 |
0 |
T88 |
11602 |
71 |
0 |
0 |
T92 |
91086 |
944 |
0 |
0 |
T94 |
101263 |
1986 |
0 |
0 |
T110 |
33177 |
368 |
0 |
0 |
T118 |
74476 |
499 |
0 |
0 |
T138 |
8043 |
243 |
0 |
0 |
T139 |
14742 |
154 |
0 |
0 |
T141 |
105597 |
1991 |
0 |
0 |
T142 |
15122 |
135 |
0 |
0 |
T143 |
62857 |
902 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
14113 |
0 |
0 |
T88 |
11602 |
61 |
0 |
0 |
T92 |
91086 |
1216 |
0 |
0 |
T94 |
101263 |
2507 |
0 |
0 |
T110 |
33177 |
265 |
0 |
0 |
T118 |
74476 |
522 |
0 |
0 |
T138 |
8043 |
230 |
0 |
0 |
T139 |
14742 |
91 |
0 |
0 |
T140 |
2438 |
7 |
0 |
0 |
T141 |
105597 |
1802 |
0 |
0 |
T142 |
15122 |
21 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
14212 |
0 |
0 |
T88 |
11602 |
12 |
0 |
0 |
T92 |
91086 |
1276 |
0 |
0 |
T94 |
101263 |
1447 |
0 |
0 |
T110 |
33177 |
546 |
0 |
0 |
T118 |
74476 |
486 |
0 |
0 |
T138 |
8043 |
6 |
0 |
0 |
T139 |
14742 |
93 |
0 |
0 |
T140 |
2438 |
1 |
0 |
0 |
T141 |
105597 |
2189 |
0 |
0 |
T142 |
15122 |
264 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
12857 |
0 |
0 |
T88 |
11602 |
116 |
0 |
0 |
T92 |
91086 |
881 |
0 |
0 |
T94 |
101263 |
2012 |
0 |
0 |
T110 |
33177 |
442 |
0 |
0 |
T118 |
74476 |
510 |
0 |
0 |
T138 |
8043 |
135 |
0 |
0 |
T139 |
14742 |
55 |
0 |
0 |
T141 |
105597 |
1503 |
0 |
0 |
T142 |
15122 |
264 |
0 |
0 |
T143 |
62857 |
1624 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
12944 |
0 |
0 |
T88 |
11602 |
77 |
0 |
0 |
T92 |
91086 |
1052 |
0 |
0 |
T94 |
101263 |
2247 |
0 |
0 |
T110 |
33177 |
340 |
0 |
0 |
T118 |
74476 |
521 |
0 |
0 |
T138 |
8043 |
127 |
0 |
0 |
T139 |
14742 |
146 |
0 |
0 |
T140 |
2438 |
9 |
0 |
0 |
T141 |
105597 |
1513 |
0 |
0 |
T142 |
15122 |
271 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6442 |
0 |
0 |
T88 |
11602 |
28 |
0 |
0 |
T92 |
91086 |
333 |
0 |
0 |
T94 |
101263 |
721 |
0 |
0 |
T110 |
33177 |
144 |
0 |
0 |
T118 |
74476 |
480 |
0 |
0 |
T138 |
8043 |
10 |
0 |
0 |
T139 |
14742 |
9 |
0 |
0 |
T140 |
2438 |
2 |
0 |
0 |
T141 |
105597 |
673 |
0 |
0 |
T142 |
15122 |
68 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6681 |
0 |
0 |
T88 |
11602 |
32 |
0 |
0 |
T92 |
91086 |
523 |
0 |
0 |
T94 |
101263 |
939 |
0 |
0 |
T110 |
33177 |
113 |
0 |
0 |
T118 |
74476 |
501 |
0 |
0 |
T138 |
8043 |
50 |
0 |
0 |
T139 |
14742 |
69 |
0 |
0 |
T140 |
2438 |
9 |
0 |
0 |
T141 |
105597 |
729 |
0 |
0 |
T142 |
15122 |
75 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6548 |
0 |
0 |
T88 |
11602 |
30 |
0 |
0 |
T92 |
91086 |
413 |
0 |
0 |
T94 |
101263 |
692 |
0 |
0 |
T110 |
33177 |
80 |
0 |
0 |
T118 |
74476 |
503 |
0 |
0 |
T138 |
8043 |
46 |
0 |
0 |
T139 |
14742 |
8 |
0 |
0 |
T140 |
2438 |
2 |
0 |
0 |
T141 |
105597 |
754 |
0 |
0 |
T142 |
15122 |
187 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
7246 |
0 |
0 |
T88 |
11602 |
40 |
0 |
0 |
T92 |
91086 |
490 |
0 |
0 |
T94 |
101263 |
675 |
0 |
0 |
T110 |
33177 |
107 |
0 |
0 |
T118 |
74476 |
495 |
0 |
0 |
T138 |
8043 |
98 |
0 |
0 |
T139 |
14742 |
52 |
0 |
0 |
T140 |
2438 |
7 |
0 |
0 |
T141 |
105597 |
1014 |
0 |
0 |
T142 |
15122 |
94 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6929 |
0 |
0 |
T88 |
11602 |
31 |
0 |
0 |
T92 |
91086 |
337 |
0 |
0 |
T94 |
101263 |
882 |
0 |
0 |
T110 |
33177 |
199 |
0 |
0 |
T118 |
74476 |
566 |
0 |
0 |
T138 |
8043 |
83 |
0 |
0 |
T139 |
14742 |
57 |
0 |
0 |
T140 |
2438 |
9 |
0 |
0 |
T141 |
105597 |
686 |
0 |
0 |
T142 |
15122 |
11 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
7009 |
0 |
0 |
T88 |
11602 |
40 |
0 |
0 |
T92 |
91086 |
341 |
0 |
0 |
T94 |
101263 |
828 |
0 |
0 |
T110 |
33177 |
142 |
0 |
0 |
T118 |
74476 |
504 |
0 |
0 |
T138 |
8043 |
54 |
0 |
0 |
T139 |
14742 |
59 |
0 |
0 |
T140 |
2438 |
3 |
0 |
0 |
T141 |
105597 |
817 |
0 |
0 |
T142 |
15122 |
86 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
7205 |
0 |
0 |
T88 |
11602 |
64 |
0 |
0 |
T92 |
91086 |
560 |
0 |
0 |
T94 |
101263 |
799 |
0 |
0 |
T110 |
33177 |
161 |
0 |
0 |
T118 |
74476 |
496 |
0 |
0 |
T138 |
8043 |
47 |
0 |
0 |
T139 |
14742 |
96 |
0 |
0 |
T140 |
2438 |
5 |
0 |
0 |
T141 |
105597 |
791 |
0 |
0 |
T142 |
15122 |
102 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6716 |
0 |
0 |
T88 |
11602 |
17 |
0 |
0 |
T92 |
91086 |
351 |
0 |
0 |
T94 |
101263 |
737 |
0 |
0 |
T110 |
33177 |
165 |
0 |
0 |
T118 |
74476 |
460 |
0 |
0 |
T138 |
8043 |
47 |
0 |
0 |
T139 |
14742 |
25 |
0 |
0 |
T140 |
2438 |
7 |
0 |
0 |
T141 |
105597 |
757 |
0 |
0 |
T142 |
15122 |
102 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6523 |
0 |
0 |
T88 |
11602 |
13 |
0 |
0 |
T92 |
91086 |
394 |
0 |
0 |
T94 |
101263 |
684 |
0 |
0 |
T110 |
33177 |
140 |
0 |
0 |
T118 |
74476 |
489 |
0 |
0 |
T138 |
8043 |
12 |
0 |
0 |
T139 |
14742 |
43 |
0 |
0 |
T140 |
2438 |
8 |
0 |
0 |
T141 |
105597 |
742 |
0 |
0 |
T142 |
15122 |
138 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
7316 |
0 |
0 |
T88 |
11602 |
38 |
0 |
0 |
T92 |
91086 |
482 |
0 |
0 |
T94 |
101263 |
1063 |
0 |
0 |
T110 |
33177 |
108 |
0 |
0 |
T118 |
74476 |
511 |
0 |
0 |
T138 |
8043 |
115 |
0 |
0 |
T139 |
14742 |
73 |
0 |
0 |
T140 |
2438 |
9 |
0 |
0 |
T141 |
105597 |
834 |
0 |
0 |
T142 |
15122 |
166 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
7602 |
0 |
0 |
T88 |
11602 |
61 |
0 |
0 |
T92 |
91086 |
610 |
0 |
0 |
T94 |
101263 |
1029 |
0 |
0 |
T110 |
33177 |
179 |
0 |
0 |
T118 |
74476 |
522 |
0 |
0 |
T138 |
8043 |
12 |
0 |
0 |
T139 |
14742 |
45 |
0 |
0 |
T140 |
2438 |
6 |
0 |
0 |
T141 |
105597 |
827 |
0 |
0 |
T142 |
15122 |
104 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
7026 |
0 |
0 |
T92 |
91086 |
428 |
0 |
0 |
T94 |
101263 |
981 |
0 |
0 |
T110 |
33177 |
160 |
0 |
0 |
T118 |
74476 |
506 |
0 |
0 |
T138 |
8043 |
45 |
0 |
0 |
T139 |
14742 |
39 |
0 |
0 |
T140 |
2438 |
8 |
0 |
0 |
T141 |
105597 |
832 |
0 |
0 |
T142 |
15122 |
114 |
0 |
0 |
T143 |
62857 |
623 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6406 |
0 |
0 |
T88 |
11602 |
47 |
0 |
0 |
T92 |
91086 |
462 |
0 |
0 |
T94 |
101263 |
593 |
0 |
0 |
T110 |
33177 |
156 |
0 |
0 |
T118 |
74476 |
500 |
0 |
0 |
T138 |
8043 |
63 |
0 |
0 |
T139 |
14742 |
52 |
0 |
0 |
T140 |
2438 |
1 |
0 |
0 |
T141 |
105597 |
740 |
0 |
0 |
T142 |
15122 |
110 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
7219 |
0 |
0 |
T88 |
11602 |
54 |
0 |
0 |
T92 |
91086 |
628 |
0 |
0 |
T94 |
101263 |
728 |
0 |
0 |
T110 |
33177 |
150 |
0 |
0 |
T118 |
74476 |
534 |
0 |
0 |
T138 |
8043 |
12 |
0 |
0 |
T139 |
14742 |
54 |
0 |
0 |
T140 |
2438 |
8 |
0 |
0 |
T141 |
105597 |
869 |
0 |
0 |
T142 |
15122 |
107 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6652 |
0 |
0 |
T88 |
11602 |
63 |
0 |
0 |
T92 |
91086 |
387 |
0 |
0 |
T94 |
101263 |
719 |
0 |
0 |
T110 |
33177 |
180 |
0 |
0 |
T118 |
74476 |
518 |
0 |
0 |
T138 |
8043 |
47 |
0 |
0 |
T139 |
14742 |
61 |
0 |
0 |
T140 |
2438 |
3 |
0 |
0 |
T141 |
105597 |
826 |
0 |
0 |
T142 |
15122 |
126 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6590 |
0 |
0 |
T88 |
11602 |
46 |
0 |
0 |
T92 |
91086 |
594 |
0 |
0 |
T94 |
101263 |
695 |
0 |
0 |
T110 |
33177 |
64 |
0 |
0 |
T118 |
74476 |
467 |
0 |
0 |
T138 |
8043 |
28 |
0 |
0 |
T139 |
14742 |
51 |
0 |
0 |
T141 |
105597 |
743 |
0 |
0 |
T142 |
15122 |
18 |
0 |
0 |
T143 |
62857 |
493 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
7092 |
0 |
0 |
T88 |
11602 |
24 |
0 |
0 |
T92 |
91086 |
601 |
0 |
0 |
T94 |
101263 |
1000 |
0 |
0 |
T110 |
33177 |
227 |
0 |
0 |
T118 |
74476 |
453 |
0 |
0 |
T138 |
8043 |
111 |
0 |
0 |
T139 |
14742 |
85 |
0 |
0 |
T140 |
2438 |
5 |
0 |
0 |
T141 |
105597 |
743 |
0 |
0 |
T142 |
15122 |
90 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6720 |
0 |
0 |
T88 |
11602 |
24 |
0 |
0 |
T92 |
91086 |
489 |
0 |
0 |
T94 |
101263 |
672 |
0 |
0 |
T110 |
33177 |
137 |
0 |
0 |
T118 |
74476 |
444 |
0 |
0 |
T138 |
8043 |
5 |
0 |
0 |
T139 |
14742 |
86 |
0 |
0 |
T140 |
2438 |
5 |
0 |
0 |
T141 |
105597 |
717 |
0 |
0 |
T142 |
15122 |
106 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6687 |
0 |
0 |
T88 |
11602 |
59 |
0 |
0 |
T92 |
91086 |
486 |
0 |
0 |
T94 |
101263 |
735 |
0 |
0 |
T110 |
33177 |
81 |
0 |
0 |
T118 |
74476 |
513 |
0 |
0 |
T138 |
8043 |
101 |
0 |
0 |
T139 |
14742 |
39 |
0 |
0 |
T140 |
2438 |
3 |
0 |
0 |
T141 |
105597 |
619 |
0 |
0 |
T142 |
15122 |
87 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6923 |
0 |
0 |
T88 |
11602 |
75 |
0 |
0 |
T92 |
91086 |
305 |
0 |
0 |
T94 |
101263 |
840 |
0 |
0 |
T110 |
33177 |
104 |
0 |
0 |
T118 |
74476 |
461 |
0 |
0 |
T138 |
8043 |
51 |
0 |
0 |
T139 |
14742 |
57 |
0 |
0 |
T140 |
2438 |
4 |
0 |
0 |
T141 |
105597 |
807 |
0 |
0 |
T142 |
15122 |
79 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6855 |
0 |
0 |
T88 |
11602 |
36 |
0 |
0 |
T92 |
91086 |
332 |
0 |
0 |
T94 |
101263 |
958 |
0 |
0 |
T110 |
33177 |
188 |
0 |
0 |
T118 |
74476 |
518 |
0 |
0 |
T138 |
8043 |
99 |
0 |
0 |
T139 |
14742 |
66 |
0 |
0 |
T140 |
2438 |
6 |
0 |
0 |
T141 |
105597 |
696 |
0 |
0 |
T142 |
15122 |
111 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6430 |
0 |
0 |
T88 |
11602 |
14 |
0 |
0 |
T92 |
91086 |
495 |
0 |
0 |
T94 |
101263 |
786 |
0 |
0 |
T110 |
33177 |
67 |
0 |
0 |
T118 |
74476 |
468 |
0 |
0 |
T138 |
8043 |
42 |
0 |
0 |
T139 |
14742 |
56 |
0 |
0 |
T140 |
2438 |
2 |
0 |
0 |
T141 |
105597 |
616 |
0 |
0 |
T142 |
15122 |
69 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6782 |
0 |
0 |
T88 |
11602 |
31 |
0 |
0 |
T92 |
91086 |
380 |
0 |
0 |
T94 |
101263 |
815 |
0 |
0 |
T110 |
33177 |
109 |
0 |
0 |
T118 |
74476 |
520 |
0 |
0 |
T138 |
8043 |
5 |
0 |
0 |
T139 |
14742 |
73 |
0 |
0 |
T140 |
2438 |
6 |
0 |
0 |
T141 |
105597 |
1007 |
0 |
0 |
T142 |
15122 |
78 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
6724 |
0 |
0 |
T88 |
11602 |
40 |
0 |
0 |
T92 |
91086 |
465 |
0 |
0 |
T94 |
101263 |
807 |
0 |
0 |
T110 |
33177 |
131 |
0 |
0 |
T118 |
74476 |
547 |
0 |
0 |
T138 |
8043 |
77 |
0 |
0 |
T139 |
14742 |
71 |
0 |
0 |
T140 |
2438 |
2 |
0 |
0 |
T141 |
105597 |
621 |
0 |
0 |
T142 |
15122 |
117 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3229 |
0 |
0 |
T88 |
11602 |
24 |
0 |
0 |
T92 |
91086 |
68 |
0 |
0 |
T94 |
101263 |
142 |
0 |
0 |
T110 |
33177 |
23 |
0 |
0 |
T118 |
74476 |
555 |
0 |
0 |
T138 |
8043 |
8 |
0 |
0 |
T139 |
14742 |
20 |
0 |
0 |
T140 |
2438 |
7 |
0 |
0 |
T141 |
105597 |
179 |
0 |
0 |
T142 |
15122 |
21 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3237 |
0 |
0 |
T88 |
11602 |
22 |
0 |
0 |
T92 |
91086 |
95 |
0 |
0 |
T94 |
101263 |
156 |
0 |
0 |
T110 |
33177 |
38 |
0 |
0 |
T118 |
74476 |
483 |
0 |
0 |
T138 |
8043 |
6 |
0 |
0 |
T139 |
14742 |
13 |
0 |
0 |
T140 |
2438 |
4 |
0 |
0 |
T141 |
105597 |
180 |
0 |
0 |
T142 |
15122 |
19 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3132 |
0 |
0 |
T88 |
11602 |
13 |
0 |
0 |
T92 |
91086 |
109 |
0 |
0 |
T94 |
101263 |
167 |
0 |
0 |
T110 |
33177 |
45 |
0 |
0 |
T118 |
74476 |
509 |
0 |
0 |
T138 |
8043 |
11 |
0 |
0 |
T139 |
14742 |
20 |
0 |
0 |
T140 |
2438 |
2 |
0 |
0 |
T141 |
105597 |
177 |
0 |
0 |
T142 |
15122 |
21 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3162 |
0 |
0 |
T88 |
11602 |
16 |
0 |
0 |
T92 |
91086 |
157 |
0 |
0 |
T94 |
101263 |
164 |
0 |
0 |
T110 |
33177 |
13 |
0 |
0 |
T118 |
74476 |
437 |
0 |
0 |
T138 |
8043 |
7 |
0 |
0 |
T139 |
14742 |
9 |
0 |
0 |
T140 |
2438 |
1 |
0 |
0 |
T141 |
105597 |
150 |
0 |
0 |
T142 |
15122 |
36 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3895 |
0 |
0 |
T88 |
11602 |
30 |
0 |
0 |
T92 |
91086 |
137 |
0 |
0 |
T94 |
101263 |
283 |
0 |
0 |
T110 |
33177 |
77 |
0 |
0 |
T118 |
74476 |
425 |
0 |
0 |
T138 |
8043 |
33 |
0 |
0 |
T139 |
14742 |
4 |
0 |
0 |
T140 |
2438 |
7 |
0 |
0 |
T141 |
105597 |
259 |
0 |
0 |
T142 |
15122 |
53 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
5863 |
0 |
0 |
T12 |
145571 |
37 |
0 |
0 |
T13 |
317549 |
0 |
0 |
0 |
T14 |
6073 |
0 |
0 |
0 |
T15 |
173021 |
0 |
0 |
0 |
T16 |
550675 |
0 |
0 |
0 |
T17 |
437582 |
0 |
0 |
0 |
T24 |
61271 |
0 |
0 |
0 |
T28 |
1429 |
0 |
0 |
0 |
T35 |
28512 |
0 |
0 |
0 |
T44 |
0 |
12 |
0 |
0 |
T53 |
1745 |
0 |
0 |
0 |
T57 |
0 |
34 |
0 |
0 |
T144 |
0 |
53 |
0 |
0 |
T145 |
0 |
46 |
0 |
0 |
T146 |
0 |
7 |
0 |
0 |
T147 |
0 |
19 |
0 |
0 |
T148 |
0 |
68 |
0 |
0 |
T149 |
0 |
63 |
0 |
0 |
T150 |
0 |
33 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3229 |
0 |
0 |
T88 |
11602 |
25 |
0 |
0 |
T92 |
91086 |
94 |
0 |
0 |
T94 |
101263 |
197 |
0 |
0 |
T110 |
33177 |
55 |
0 |
0 |
T118 |
74476 |
486 |
0 |
0 |
T138 |
8043 |
16 |
0 |
0 |
T139 |
14742 |
12 |
0 |
0 |
T140 |
2438 |
9 |
0 |
0 |
T141 |
105597 |
193 |
0 |
0 |
T142 |
15122 |
34 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3206 |
0 |
0 |
T88 |
11602 |
27 |
0 |
0 |
T92 |
91086 |
88 |
0 |
0 |
T94 |
101263 |
142 |
0 |
0 |
T110 |
33177 |
31 |
0 |
0 |
T118 |
74476 |
466 |
0 |
0 |
T138 |
8043 |
9 |
0 |
0 |
T139 |
14742 |
7 |
0 |
0 |
T141 |
105597 |
179 |
0 |
0 |
T142 |
15122 |
32 |
0 |
0 |
T143 |
62857 |
91 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2749 |
0 |
0 |
T88 |
11602 |
6 |
0 |
0 |
T92 |
91086 |
72 |
0 |
0 |
T94 |
101263 |
116 |
0 |
0 |
T110 |
33177 |
35 |
0 |
0 |
T118 |
74476 |
487 |
0 |
0 |
T138 |
8043 |
11 |
0 |
0 |
T139 |
14742 |
15 |
0 |
0 |
T140 |
2438 |
1 |
0 |
0 |
T141 |
105597 |
103 |
0 |
0 |
T142 |
15122 |
25 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3030 |
0 |
0 |
T88 |
11602 |
5 |
0 |
0 |
T92 |
91086 |
72 |
0 |
0 |
T94 |
101263 |
131 |
0 |
0 |
T110 |
33177 |
21 |
0 |
0 |
T118 |
74476 |
526 |
0 |
0 |
T138 |
8043 |
5 |
0 |
0 |
T139 |
14742 |
14 |
0 |
0 |
T140 |
2438 |
3 |
0 |
0 |
T141 |
105597 |
123 |
0 |
0 |
T142 |
15122 |
17 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2911 |
0 |
0 |
T88 |
11602 |
27 |
0 |
0 |
T92 |
91086 |
68 |
0 |
0 |
T94 |
101263 |
126 |
0 |
0 |
T110 |
33177 |
3 |
0 |
0 |
T118 |
74476 |
489 |
0 |
0 |
T138 |
8043 |
11 |
0 |
0 |
T139 |
14742 |
23 |
0 |
0 |
T141 |
105597 |
124 |
0 |
0 |
T142 |
15122 |
29 |
0 |
0 |
T143 |
62857 |
99 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2981 |
0 |
0 |
T88 |
11602 |
15 |
0 |
0 |
T92 |
91086 |
76 |
0 |
0 |
T94 |
101263 |
106 |
0 |
0 |
T110 |
33177 |
10 |
0 |
0 |
T118 |
74476 |
521 |
0 |
0 |
T138 |
8043 |
11 |
0 |
0 |
T139 |
14742 |
20 |
0 |
0 |
T140 |
2438 |
6 |
0 |
0 |
T141 |
105597 |
104 |
0 |
0 |
T142 |
15122 |
19 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3743 |
0 |
0 |
T88 |
11602 |
10 |
0 |
0 |
T92 |
91086 |
133 |
0 |
0 |
T94 |
101263 |
200 |
0 |
0 |
T110 |
33177 |
39 |
0 |
0 |
T118 |
74476 |
490 |
0 |
0 |
T138 |
8043 |
44 |
0 |
0 |
T139 |
14742 |
39 |
0 |
0 |
T140 |
2438 |
5 |
0 |
0 |
T141 |
105597 |
299 |
0 |
0 |
T142 |
15122 |
25 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2816 |
0 |
0 |
T88 |
11602 |
11 |
0 |
0 |
T92 |
91086 |
51 |
0 |
0 |
T94 |
101263 |
102 |
0 |
0 |
T110 |
33177 |
29 |
0 |
0 |
T118 |
74476 |
457 |
0 |
0 |
T138 |
8043 |
6 |
0 |
0 |
T139 |
14742 |
6 |
0 |
0 |
T140 |
2438 |
9 |
0 |
0 |
T141 |
105597 |
97 |
0 |
0 |
T142 |
15122 |
13 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
4199 |
0 |
0 |
T88 |
11602 |
23 |
0 |
0 |
T92 |
91086 |
105 |
0 |
0 |
T94 |
101263 |
382 |
0 |
0 |
T110 |
33177 |
50 |
0 |
0 |
T118 |
74476 |
465 |
0 |
0 |
T138 |
8043 |
40 |
0 |
0 |
T139 |
14742 |
17 |
0 |
0 |
T140 |
2438 |
7 |
0 |
0 |
T141 |
105597 |
279 |
0 |
0 |
T142 |
15122 |
69 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3203 |
0 |
0 |
T88 |
11602 |
6 |
0 |
0 |
T92 |
91086 |
82 |
0 |
0 |
T94 |
101263 |
180 |
0 |
0 |
T110 |
33177 |
35 |
0 |
0 |
T118 |
74476 |
509 |
0 |
0 |
T138 |
8043 |
24 |
0 |
0 |
T139 |
14742 |
36 |
0 |
0 |
T141 |
105597 |
162 |
0 |
0 |
T142 |
15122 |
29 |
0 |
0 |
T143 |
62857 |
108 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2819 |
0 |
0 |
T88 |
11602 |
10 |
0 |
0 |
T92 |
91086 |
45 |
0 |
0 |
T94 |
101263 |
108 |
0 |
0 |
T110 |
33177 |
15 |
0 |
0 |
T118 |
74476 |
477 |
0 |
0 |
T138 |
8043 |
7 |
0 |
0 |
T139 |
14742 |
4 |
0 |
0 |
T140 |
2438 |
1 |
0 |
0 |
T141 |
105597 |
131 |
0 |
0 |
T142 |
15122 |
23 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2735 |
0 |
0 |
T88 |
11602 |
8 |
0 |
0 |
T92 |
91086 |
92 |
0 |
0 |
T94 |
101263 |
101 |
0 |
0 |
T110 |
33177 |
17 |
0 |
0 |
T118 |
74476 |
454 |
0 |
0 |
T138 |
8043 |
9 |
0 |
0 |
T139 |
14742 |
8 |
0 |
0 |
T140 |
2438 |
3 |
0 |
0 |
T141 |
105597 |
109 |
0 |
0 |
T142 |
15122 |
27 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2975 |
0 |
0 |
T88 |
11602 |
4 |
0 |
0 |
T92 |
91086 |
58 |
0 |
0 |
T94 |
101263 |
137 |
0 |
0 |
T110 |
33177 |
11 |
0 |
0 |
T118 |
74476 |
535 |
0 |
0 |
T138 |
8043 |
6 |
0 |
0 |
T139 |
14742 |
7 |
0 |
0 |
T140 |
2438 |
8 |
0 |
0 |
T141 |
105597 |
96 |
0 |
0 |
T142 |
15122 |
22 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2742 |
0 |
0 |
T88 |
11602 |
5 |
0 |
0 |
T92 |
91086 |
36 |
0 |
0 |
T94 |
101263 |
116 |
0 |
0 |
T110 |
33177 |
22 |
0 |
0 |
T118 |
74476 |
484 |
0 |
0 |
T138 |
8043 |
6 |
0 |
0 |
T139 |
14742 |
7 |
0 |
0 |
T140 |
2438 |
5 |
0 |
0 |
T141 |
105597 |
116 |
0 |
0 |
T142 |
15122 |
23 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
3012 |
0 |
0 |
T88 |
11602 |
8 |
0 |
0 |
T92 |
91086 |
87 |
0 |
0 |
T94 |
101263 |
133 |
0 |
0 |
T110 |
33177 |
39 |
0 |
0 |
T118 |
74476 |
516 |
0 |
0 |
T138 |
8043 |
11 |
0 |
0 |
T139 |
14742 |
5 |
0 |
0 |
T140 |
2438 |
2 |
0 |
0 |
T141 |
105597 |
91 |
0 |
0 |
T142 |
15122 |
16 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
420108857 |
2759 |
0 |
0 |
T88 |
11602 |
18 |
0 |
0 |
T92 |
91086 |
53 |
0 |
0 |
T94 |
101263 |
76 |
0 |
0 |
T110 |
33177 |
6 |
0 |
0 |
T118 |
74476 |
467 |
0 |
0 |
T138 |
8043 |
12 |
0 |
0 |
T139 |
14742 |
9 |
0 |
0 |
T140 |
2438 |
2 |
0 |
0 |
T141 |
105597 |
131 |
0 |
0 |
T142 |
15122 |
8 |
0 |
0 |