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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 98.35 94.20 98.61 89.36 97.23 95.82 99.15


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1014 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1740925665 Jun 05 04:34:09 PM PDT 24 Jun 05 04:34:11 PM PDT 24 12075693 ps
T1015 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3776790022 Jun 05 04:34:12 PM PDT 24 Jun 05 04:34:17 PM PDT 24 796493497 ps
T1016 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1982240075 Jun 05 04:34:25 PM PDT 24 Jun 05 04:34:27 PM PDT 24 168775799 ps
T1017 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1181940430 Jun 05 04:34:36 PM PDT 24 Jun 05 04:34:40 PM PDT 24 14886282 ps
T119 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3214911391 Jun 05 04:34:20 PM PDT 24 Jun 05 04:34:23 PM PDT 24 30470991 ps
T1018 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3445156249 Jun 05 04:34:13 PM PDT 24 Jun 05 04:34:14 PM PDT 24 17525419 ps
T1019 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1720614935 Jun 05 04:34:11 PM PDT 24 Jun 05 04:34:12 PM PDT 24 18780031 ps
T1020 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.595078336 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:06 PM PDT 24 48825206 ps
T1021 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3613740187 Jun 05 04:34:00 PM PDT 24 Jun 05 04:34:03 PM PDT 24 169092259 ps
T1022 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2655233895 Jun 05 04:34:34 PM PDT 24 Jun 05 04:34:38 PM PDT 24 11805937 ps
T1023 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1738579500 Jun 05 04:34:25 PM PDT 24 Jun 05 04:34:28 PM PDT 24 464224016 ps
T1024 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2708939791 Jun 05 04:34:29 PM PDT 24 Jun 05 04:34:31 PM PDT 24 13107314 ps
T1025 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3645484182 Jun 05 04:34:12 PM PDT 24 Jun 05 04:34:15 PM PDT 24 57585231 ps
T107 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3860051475 Jun 05 04:34:26 PM PDT 24 Jun 05 04:34:30 PM PDT 24 70809703 ps
T120 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.530518043 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:07 PM PDT 24 33144531 ps
T1026 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2144188582 Jun 05 04:34:32 PM PDT 24 Jun 05 04:34:35 PM PDT 24 17000191 ps
T122 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2155292055 Jun 05 04:34:32 PM PDT 24 Jun 05 04:34:36 PM PDT 24 91547151 ps
T1027 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.368838517 Jun 05 04:34:13 PM PDT 24 Jun 05 04:34:15 PM PDT 24 60204730 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.177727794 Jun 05 04:34:24 PM PDT 24 Jun 05 04:35:02 PM PDT 24 25882624315 ps
T239 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1713895041 Jun 05 04:34:22 PM PDT 24 Jun 05 04:34:41 PM PDT 24 1119522872 ps
T1028 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3718004921 Jun 05 04:34:28 PM PDT 24 Jun 05 04:34:30 PM PDT 24 16914684 ps
T1029 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2564274412 Jun 05 04:34:24 PM PDT 24 Jun 05 04:34:29 PM PDT 24 171768523 ps
T104 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3454174592 Jun 05 04:34:13 PM PDT 24 Jun 05 04:34:18 PM PDT 24 153591948 ps
T105 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2555223528 Jun 05 04:34:17 PM PDT 24 Jun 05 04:34:21 PM PDT 24 272107975 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1594933538 Jun 05 04:34:23 PM PDT 24 Jun 05 04:35:01 PM PDT 24 1893572557 ps
T1031 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1653608204 Jun 05 04:34:24 PM PDT 24 Jun 05 04:34:26 PM PDT 24 25913543 ps
T1032 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2231889533 Jun 05 04:34:12 PM PDT 24 Jun 05 04:34:35 PM PDT 24 4353506138 ps
T1033 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3307907994 Jun 05 04:34:11 PM PDT 24 Jun 05 04:34:14 PM PDT 24 56696695 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.569375215 Jun 05 04:34:06 PM PDT 24 Jun 05 04:34:08 PM PDT 24 104451244 ps
T1035 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3038091960 Jun 05 04:34:08 PM PDT 24 Jun 05 04:34:10 PM PDT 24 11825513 ps
T1036 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.791223977 Jun 05 04:34:16 PM PDT 24 Jun 05 04:34:18 PM PDT 24 287394445 ps
T1037 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3822451988 Jun 05 04:34:10 PM PDT 24 Jun 05 04:34:16 PM PDT 24 4253167120 ps
T1038 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3292168681 Jun 05 04:34:07 PM PDT 24 Jun 05 04:34:11 PM PDT 24 45907858 ps
T124 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.427143084 Jun 05 04:34:26 PM PDT 24 Jun 05 04:34:29 PM PDT 24 127428350 ps
T1039 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.925270508 Jun 05 04:34:12 PM PDT 24 Jun 05 04:34:15 PM PDT 24 62084218 ps
T1040 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1517313857 Jun 05 04:34:24 PM PDT 24 Jun 05 04:34:25 PM PDT 24 114978176 ps
T1041 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2672998125 Jun 05 04:34:07 PM PDT 24 Jun 05 04:34:08 PM PDT 24 29249542 ps
T1042 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1397941845 Jun 05 04:34:28 PM PDT 24 Jun 05 04:34:32 PM PDT 24 321545353 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.848521923 Jun 05 04:34:23 PM PDT 24 Jun 05 04:34:27 PM PDT 24 577359067 ps
T1044 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.917339993 Jun 05 04:34:40 PM PDT 24 Jun 05 04:34:43 PM PDT 24 321531256 ps
T1045 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3968420574 Jun 05 04:34:31 PM PDT 24 Jun 05 04:34:45 PM PDT 24 1096633450 ps
T78 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2553920115 Jun 05 04:34:03 PM PDT 24 Jun 05 04:34:06 PM PDT 24 76969288 ps
T1046 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3040493663 Jun 05 04:34:24 PM PDT 24 Jun 05 04:34:27 PM PDT 24 94424192 ps
T1047 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1381044543 Jun 05 04:34:10 PM PDT 24 Jun 05 04:34:14 PM PDT 24 270665753 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4062038459 Jun 05 04:34:13 PM PDT 24 Jun 05 04:34:18 PM PDT 24 638685352 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2221861092 Jun 05 04:34:21 PM PDT 24 Jun 05 04:34:25 PM PDT 24 54716899 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4149360641 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:06 PM PDT 24 11141963 ps
T1051 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2200393991 Jun 05 04:34:16 PM PDT 24 Jun 05 04:34:20 PM PDT 24 112849092 ps
T1052 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3642802035 Jun 05 04:34:01 PM PDT 24 Jun 05 04:34:03 PM PDT 24 34078400 ps
T1053 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2459077056 Jun 05 04:34:23 PM PDT 24 Jun 05 04:34:31 PM PDT 24 409531797 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2756888366 Jun 05 04:34:11 PM PDT 24 Jun 05 04:34:15 PM PDT 24 118256720 ps
T1055 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.524142435 Jun 05 04:34:12 PM PDT 24 Jun 05 04:34:15 PM PDT 24 93693902 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2870391124 Jun 05 04:34:24 PM PDT 24 Jun 05 04:34:34 PM PDT 24 591174811 ps
T240 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3024270062 Jun 05 04:34:09 PM PDT 24 Jun 05 04:34:30 PM PDT 24 1210666033 ps
T108 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2725742449 Jun 05 04:34:39 PM PDT 24 Jun 05 04:34:44 PM PDT 24 380390452 ps
T1057 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1578210262 Jun 05 04:34:02 PM PDT 24 Jun 05 04:34:09 PM PDT 24 221246501 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2583880328 Jun 05 04:34:02 PM PDT 24 Jun 05 04:34:24 PM PDT 24 4984697463 ps
T1059 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3944707720 Jun 05 04:34:24 PM PDT 24 Jun 05 04:34:26 PM PDT 24 28255936 ps
T1060 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3233041027 Jun 05 04:34:23 PM PDT 24 Jun 05 04:34:24 PM PDT 24 15576320 ps
T1061 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1907425187 Jun 05 04:34:31 PM PDT 24 Jun 05 04:34:33 PM PDT 24 16186213 ps
T1062 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2802433608 Jun 05 04:34:30 PM PDT 24 Jun 05 04:34:32 PM PDT 24 68967596 ps
T1063 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1763180593 Jun 05 04:34:34 PM PDT 24 Jun 05 04:34:36 PM PDT 24 42185704 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4264572449 Jun 05 04:34:09 PM PDT 24 Jun 05 04:34:19 PM PDT 24 1605577980 ps
T1065 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.727887444 Jun 05 04:34:29 PM PDT 24 Jun 05 04:34:31 PM PDT 24 24438475 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4111753412 Jun 05 04:33:58 PM PDT 24 Jun 05 04:34:00 PM PDT 24 18363171 ps
T1067 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1165921767 Jun 05 04:34:23 PM PDT 24 Jun 05 04:34:25 PM PDT 24 48623922 ps
T1068 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1902378399 Jun 05 04:34:10 PM PDT 24 Jun 05 04:34:13 PM PDT 24 364148424 ps
T1069 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2400363924 Jun 05 04:34:34 PM PDT 24 Jun 05 04:34:37 PM PDT 24 139481094 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.385329286 Jun 05 04:34:21 PM PDT 24 Jun 05 04:34:26 PM PDT 24 161627353 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2564109899 Jun 05 04:34:18 PM PDT 24 Jun 05 04:34:43 PM PDT 24 5201080151 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1448410349 Jun 05 04:34:17 PM PDT 24 Jun 05 04:34:20 PM PDT 24 111002977 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3294835770 Jun 05 04:34:07 PM PDT 24 Jun 05 04:34:10 PM PDT 24 62740352 ps
T1074 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2681202829 Jun 05 04:34:32 PM PDT 24 Jun 05 04:34:37 PM PDT 24 132334870 ps
T1075 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1372334590 Jun 05 04:34:29 PM PDT 24 Jun 05 04:34:31 PM PDT 24 38586587 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.649741950 Jun 05 04:34:09 PM PDT 24 Jun 05 04:34:11 PM PDT 24 122740433 ps
T1077 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.838265260 Jun 05 04:34:14 PM PDT 24 Jun 05 04:34:18 PM PDT 24 74143626 ps
T1078 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.628910029 Jun 05 04:34:14 PM PDT 24 Jun 05 04:34:17 PM PDT 24 423376913 ps
T1079 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2852617266 Jun 05 04:34:24 PM PDT 24 Jun 05 04:34:25 PM PDT 24 169789751 ps
T1080 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2412903769 Jun 05 04:34:14 PM PDT 24 Jun 05 04:34:19 PM PDT 24 557333494 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1954152078 Jun 05 04:34:02 PM PDT 24 Jun 05 04:34:06 PM PDT 24 44484196 ps
T1082 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3540404155 Jun 05 04:34:25 PM PDT 24 Jun 05 04:34:28 PM PDT 24 159137088 ps
T1083 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3622677542 Jun 05 04:34:01 PM PDT 24 Jun 05 04:34:03 PM PDT 24 14359987 ps
T1084 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1001277385 Jun 05 04:34:16 PM PDT 24 Jun 05 04:34:20 PM PDT 24 199215893 ps
T1085 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.931500150 Jun 05 04:34:37 PM PDT 24 Jun 05 04:34:41 PM PDT 24 368811402 ps
T1086 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2318140020 Jun 05 04:34:20 PM PDT 24 Jun 05 04:34:23 PM PDT 24 179784843 ps
T1087 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2298029523 Jun 05 04:34:08 PM PDT 24 Jun 05 04:34:11 PM PDT 24 1008355860 ps
T1088 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.118908648 Jun 05 04:34:14 PM PDT 24 Jun 05 04:34:20 PM PDT 24 165223886 ps
T1089 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4094338474 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:07 PM PDT 24 162434308 ps
T1090 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.283207911 Jun 05 04:34:28 PM PDT 24 Jun 05 04:34:30 PM PDT 24 27614702 ps
T1091 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.992415644 Jun 05 04:34:29 PM PDT 24 Jun 05 04:34:38 PM PDT 24 437725115 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2639914935 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:07 PM PDT 24 194088223 ps
T1093 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.8022546 Jun 05 04:34:14 PM PDT 24 Jun 05 04:34:17 PM PDT 24 71689136 ps
T1094 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.254752148 Jun 05 04:34:13 PM PDT 24 Jun 05 04:34:16 PM PDT 24 51970367 ps
T1095 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.564842307 Jun 05 04:34:27 PM PDT 24 Jun 05 04:34:28 PM PDT 24 13031361 ps
T1096 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4220707321 Jun 05 04:34:33 PM PDT 24 Jun 05 04:34:36 PM PDT 24 16658913 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1323561483 Jun 05 04:34:07 PM PDT 24 Jun 05 04:34:10 PM PDT 24 59440942 ps
T1098 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3070102895 Jun 05 04:34:09 PM PDT 24 Jun 05 04:34:24 PM PDT 24 745928426 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1402385724 Jun 05 04:34:09 PM PDT 24 Jun 05 04:34:14 PM PDT 24 467690319 ps
T1100 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2782059249 Jun 05 04:34:25 PM PDT 24 Jun 05 04:34:26 PM PDT 24 16650386 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4027121425 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:07 PM PDT 24 66313154 ps
T79 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.140759807 Jun 05 04:34:21 PM PDT 24 Jun 05 04:34:23 PM PDT 24 25133444 ps

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.197322187
Short name T10
Test name
Test status
Simulation time 14869547183 ps
CPU time 153.41 seconds
Started Jun 05 05:42:17 PM PDT 24
Finished Jun 05 05:44:51 PM PDT 24
Peak memory 249952 kb
Host smart-5856e9cb-e74a-4599-aff3-b7b3d6cbee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197322187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.197322187
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1580183080
Short name T29
Test name
Test status
Simulation time 139520480773 ps
CPU time 446.97 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:50:37 PM PDT 24
Peak memory 283576 kb
Host smart-a1f9ae52-75e0-438e-8416-a4ed2d36f50f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580183080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1580183080
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2141724135
Short name T16
Test name
Test status
Simulation time 5506776336 ps
CPU time 77.59 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:42:25 PM PDT 24
Peak memory 249052 kb
Host smart-9e9d4223-d898-4381-a039-02af07a0c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141724135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2141724135
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3105900769
Short name T92
Test name
Test status
Simulation time 3795374757 ps
CPU time 20.42 seconds
Started Jun 05 04:34:37 PM PDT 24
Finished Jun 05 04:34:59 PM PDT 24
Peak memory 215620 kb
Host smart-70f4193c-150e-4bd3-89b6-f6a17d8abe97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105900769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3105900769
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.513140503
Short name T154
Test name
Test status
Simulation time 113482371481 ps
CPU time 1008.01 seconds
Started Jun 05 05:41:23 PM PDT 24
Finished Jun 05 05:58:12 PM PDT 24
Peak memory 273192 kb
Host smart-c5cf15a5-4200-42cd-9985-11140e8c08d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513140503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.513140503
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.119885455
Short name T58
Test name
Test status
Simulation time 36584729 ps
CPU time 0.72 seconds
Started Jun 05 05:40:45 PM PDT 24
Finished Jun 05 05:40:47 PM PDT 24
Peak memory 216644 kb
Host smart-ea2f0857-b918-40aa-9a41-ff8726ead009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119885455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.119885455
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2763321938
Short name T166
Test name
Test status
Simulation time 504201023881 ps
CPU time 760.94 seconds
Started Jun 05 05:43:12 PM PDT 24
Finished Jun 05 05:55:54 PM PDT 24
Peak memory 289804 kb
Host smart-76fc626f-b04c-4cf5-af97-2e492a5d8f84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763321938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2763321938
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3101539799
Short name T126
Test name
Test status
Simulation time 68108654970 ps
CPU time 469.59 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:49:20 PM PDT 24
Peak memory 269900 kb
Host smart-6beba5bc-7d7c-47c0-92b5-e623dcf84342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101539799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3101539799
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2133108408
Short name T12
Test name
Test status
Simulation time 21726559429 ps
CPU time 171.5 seconds
Started Jun 05 05:41:33 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 256432 kb
Host smart-4e86d663-a49e-4350-8b97-14f295af8478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133108408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2133108408
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1571856674
Short name T99
Test name
Test status
Simulation time 230928594 ps
CPU time 4.02 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:14 PM PDT 24
Peak memory 215876 kb
Host smart-1ec89fa1-8212-4e2d-ad53-49e020c4e327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571856674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
571856674
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3373085883
Short name T37
Test name
Test status
Simulation time 3475152092 ps
CPU time 23.59 seconds
Started Jun 05 05:42:42 PM PDT 24
Finished Jun 05 05:43:07 PM PDT 24
Peak memory 233244 kb
Host smart-9c0b8e83-c09b-41c7-a080-a6cff61e48ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373085883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3373085883
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3426351712
Short name T296
Test name
Test status
Simulation time 38589138 ps
CPU time 0.75 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 206108 kb
Host smart-c8e61216-f444-4dfc-993b-69d91b5e74cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426351712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3426351712
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1882857400
Short name T33
Test name
Test status
Simulation time 14134412748 ps
CPU time 141.76 seconds
Started Jun 05 05:42:11 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 254736 kb
Host smart-7387fbd7-1542-4fbf-9649-a57f3e9c9b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882857400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1882857400
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2610804567
Short name T147
Test name
Test status
Simulation time 56220302382 ps
CPU time 652.04 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:52:59 PM PDT 24
Peak memory 285436 kb
Host smart-16c78a17-7f88-4bfe-a0ec-777b3eaecfb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610804567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2610804567
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3037707894
Short name T160
Test name
Test status
Simulation time 17476578067 ps
CPU time 166.57 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:45:39 PM PDT 24
Peak memory 233336 kb
Host smart-009c6789-69fe-47c5-a4e6-ec71cad9a9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037707894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3037707894
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4061705136
Short name T77
Test name
Test status
Simulation time 47438848 ps
CPU time 0.97 seconds
Started Jun 05 04:34:02 PM PDT 24
Finished Jun 05 04:34:05 PM PDT 24
Peak memory 207136 kb
Host smart-a81422d7-73ee-4006-9336-359604aa6c34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061705136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.4061705136
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4164421355
Short name T203
Test name
Test status
Simulation time 63451556283 ps
CPU time 679.14 seconds
Started Jun 05 05:40:53 PM PDT 24
Finished Jun 05 05:52:13 PM PDT 24
Peak memory 282136 kb
Host smart-de4f39bb-2b02-45fa-8fc2-20c12db48605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164421355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4164421355
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3823629806
Short name T41
Test name
Test status
Simulation time 72905258548 ps
CPU time 218.45 seconds
Started Jun 05 05:42:23 PM PDT 24
Finished Jun 05 05:46:02 PM PDT 24
Peak memory 255240 kb
Host smart-503c2f02-87e2-4d43-a004-222a4f9afb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823629806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3823629806
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3631099512
Short name T400
Test name
Test status
Simulation time 23824005 ps
CPU time 1.04 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:30 PM PDT 24
Peak memory 217024 kb
Host smart-dc228efd-7f37-4baa-ba2b-93595eeb38b5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631099512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3631099512
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2315413163
Short name T179
Test name
Test status
Simulation time 9553799212 ps
CPU time 96.82 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:43:37 PM PDT 24
Peak memory 254452 kb
Host smart-e8d0d80c-972c-4b19-a304-3fb4132c2ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315413163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2315413163
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.198755154
Short name T62
Test name
Test status
Simulation time 61920772 ps
CPU time 1.1 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:40:53 PM PDT 24
Peak memory 235292 kb
Host smart-90120deb-528c-42a2-8804-a559e5903072
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198755154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.198755154
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1104509603
Short name T169
Test name
Test status
Simulation time 71109239987 ps
CPU time 202.04 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:45:49 PM PDT 24
Peak memory 249728 kb
Host smart-6f0a4fa3-6de0-4b5c-b3d9-e03bcb6d6872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104509603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1104509603
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3866462387
Short name T42
Test name
Test status
Simulation time 33801297048 ps
CPU time 100.41 seconds
Started Jun 05 05:41:53 PM PDT 24
Finished Jun 05 05:43:34 PM PDT 24
Peak memory 252064 kb
Host smart-496db982-3ea2-4ccd-b554-7edea2bd27ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866462387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3866462387
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2452752377
Short name T254
Test name
Test status
Simulation time 34384617978 ps
CPU time 337.32 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:47:06 PM PDT 24
Peak memory 250060 kb
Host smart-d7cde80b-6eb7-4f4a-a650-7d2f3f8e4bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452752377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2452752377
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3666949811
Short name T32
Test name
Test status
Simulation time 41177206034 ps
CPU time 292.3 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:47:49 PM PDT 24
Peak memory 249620 kb
Host smart-51c3842a-e37a-43e8-97a4-398851c0a8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666949811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3666949811
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3832459269
Short name T198
Test name
Test status
Simulation time 4277236810 ps
CPU time 61.45 seconds
Started Jun 05 05:43:08 PM PDT 24
Finished Jun 05 05:44:10 PM PDT 24
Peak memory 255464 kb
Host smart-4485b874-bcdf-41a5-a8a6-995c68b4fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832459269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3832459269
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1713895041
Short name T239
Test name
Test status
Simulation time 1119522872 ps
CPU time 18.2 seconds
Started Jun 05 04:34:22 PM PDT 24
Finished Jun 05 04:34:41 PM PDT 24
Peak memory 216196 kb
Host smart-4541b839-1bc4-4a06-a689-5be17d34a667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713895041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1713895041
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.606282778
Short name T362
Test name
Test status
Simulation time 14391128583 ps
CPU time 109.63 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:43:55 PM PDT 24
Peak memory 252400 kb
Host smart-aef84581-7afe-4e7e-bdc9-1b0ea0c2c539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606282778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.606282778
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2323053607
Short name T211
Test name
Test status
Simulation time 293867446863 ps
CPU time 289.14 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:46:24 PM PDT 24
Peak memory 267560 kb
Host smart-6367d98a-0c1b-421b-b1fd-70f99eb31d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323053607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2323053607
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3263880162
Short name T157
Test name
Test status
Simulation time 116981530831 ps
CPU time 203.79 seconds
Started Jun 05 05:41:41 PM PDT 24
Finished Jun 05 05:45:05 PM PDT 24
Peak memory 249616 kb
Host smart-32251339-f66a-4640-a65f-1d5ddb65bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263880162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3263880162
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1671983508
Short name T168
Test name
Test status
Simulation time 77538576376 ps
CPU time 517.21 seconds
Started Jun 05 05:41:00 PM PDT 24
Finished Jun 05 05:49:39 PM PDT 24
Peak memory 266016 kb
Host smart-fc5fa29b-3b43-40aa-8ebf-125a34f1a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671983508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1671983508
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3220935045
Short name T25
Test name
Test status
Simulation time 246053545084 ps
CPU time 199.64 seconds
Started Jun 05 05:42:34 PM PDT 24
Finished Jun 05 05:45:54 PM PDT 24
Peak memory 257904 kb
Host smart-fae6ce53-00e9-4308-bf92-348fca1a7c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220935045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3220935045
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.391452086
Short name T65
Test name
Test status
Simulation time 2598429647 ps
CPU time 11.46 seconds
Started Jun 05 05:43:25 PM PDT 24
Finished Jun 05 05:43:38 PM PDT 24
Peak memory 233168 kb
Host smart-1a328d58-a876-4566-b7f8-c54429cf96ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391452086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.391452086
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3852093743
Short name T87
Test name
Test status
Simulation time 1895303425 ps
CPU time 6.67 seconds
Started Jun 05 05:41:43 PM PDT 24
Finished Jun 05 05:41:50 PM PDT 24
Peak memory 224904 kb
Host smart-f0de4a32-7fec-4e27-bb50-674e17898808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852093743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3852093743
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3454174592
Short name T104
Test name
Test status
Simulation time 153591948 ps
CPU time 4.17 seconds
Started Jun 05 04:34:13 PM PDT 24
Finished Jun 05 04:34:18 PM PDT 24
Peak memory 216724 kb
Host smart-42d44b97-4725-4921-ae89-81f73e15d71d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454174592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
454174592
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1836071224
Short name T153
Test name
Test status
Simulation time 118841616232 ps
CPU time 285.72 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 249716 kb
Host smart-2204ed0a-037e-4170-a353-1cf8752b99c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836071224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1836071224
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1371501764
Short name T931
Test name
Test status
Simulation time 4715063026 ps
CPU time 56.09 seconds
Started Jun 05 05:42:21 PM PDT 24
Finished Jun 05 05:43:18 PM PDT 24
Peak memory 241532 kb
Host smart-e192368e-fb22-4a0b-820f-9674ec6e2591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371501764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1371501764
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1536632154
Short name T174
Test name
Test status
Simulation time 86489970967 ps
CPU time 591.03 seconds
Started Jun 05 05:43:05 PM PDT 24
Finished Jun 05 05:52:56 PM PDT 24
Peak memory 257772 kb
Host smart-a14596a7-6bcc-4a46-8044-44d8f0990dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536632154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1536632154
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2896259578
Short name T223
Test name
Test status
Simulation time 7848335039 ps
CPU time 112.47 seconds
Started Jun 05 05:43:20 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 254116 kb
Host smart-20edebf4-9f32-497d-9759-97dbb90fecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896259578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2896259578
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1040484498
Short name T89
Test name
Test status
Simulation time 1703624714 ps
CPU time 22.36 seconds
Started Jun 05 04:34:02 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 216004 kb
Host smart-5d114dfd-50e4-404c-a5ca-4ea1f647f4aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040484498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1040484498
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1017416294
Short name T233
Test name
Test status
Simulation time 1521375739 ps
CPU time 26.32 seconds
Started Jun 05 05:40:52 PM PDT 24
Finished Jun 05 05:41:19 PM PDT 24
Peak memory 249496 kb
Host smart-0ee478ab-0d75-4074-b368-997d3dbc4d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017416294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1017416294
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3302874245
Short name T228
Test name
Test status
Simulation time 12545156880 ps
CPU time 129.03 seconds
Started Jun 05 05:40:52 PM PDT 24
Finished Jun 05 05:43:02 PM PDT 24
Peak memory 249732 kb
Host smart-4040d75f-d999-47cf-9af7-7ab36a7f42c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302874245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3302874245
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2965853236
Short name T916
Test name
Test status
Simulation time 13420382496 ps
CPU time 16.26 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:41:46 PM PDT 24
Peak memory 241400 kb
Host smart-371d3fd2-51dd-47d5-bebd-12f263e95941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965853236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2965853236
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2403058674
Short name T279
Test name
Test status
Simulation time 227972242 ps
CPU time 4.83 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 233328 kb
Host smart-6fc8812f-956d-48b0-90b5-8b95c31a3aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403058674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2403058674
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2076265983
Short name T572
Test name
Test status
Simulation time 133362421 ps
CPU time 5.81 seconds
Started Jun 05 05:41:42 PM PDT 24
Finished Jun 05 05:41:48 PM PDT 24
Peak memory 224936 kb
Host smart-014a36b2-044b-449d-8dae-d3dd3aa096a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076265983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2076265983
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2644962585
Short name T216
Test name
Test status
Simulation time 225358204977 ps
CPU time 359.25 seconds
Started Jun 05 05:41:52 PM PDT 24
Finished Jun 05 05:47:52 PM PDT 24
Peak memory 253540 kb
Host smart-a2068657-9c33-4870-aea1-c9a7ee880eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644962585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2644962585
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3944709046
Short name T215
Test name
Test status
Simulation time 10583534993 ps
CPU time 91.73 seconds
Started Jun 05 05:40:58 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 250704 kb
Host smart-8a0d1487-09ca-4725-8064-1570f120b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944709046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3944709046
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3197721873
Short name T182
Test name
Test status
Simulation time 104908272215 ps
CPU time 474.48 seconds
Started Jun 05 05:41:21 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 249712 kb
Host smart-666f60e8-6710-4c97-9227-c7b901c2083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197721873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3197721873
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1577720450
Short name T135
Test name
Test status
Simulation time 7685492288 ps
CPU time 7.7 seconds
Started Jun 05 05:41:42 PM PDT 24
Finished Jun 05 05:41:50 PM PDT 24
Peak memory 222936 kb
Host smart-444f7e51-86e2-45bb-9349-b2177511252e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577720450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1577720450
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3999844559
Short name T218
Test name
Test status
Simulation time 52815053928 ps
CPU time 361.28 seconds
Started Jun 05 05:42:41 PM PDT 24
Finished Jun 05 05:48:43 PM PDT 24
Peak memory 249756 kb
Host smart-45705282-8bb8-4a2e-8f12-cabf934a0308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999844559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3999844559
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1276309629
Short name T118
Test name
Test status
Simulation time 744794725 ps
CPU time 16.43 seconds
Started Jun 05 04:34:02 PM PDT 24
Finished Jun 05 04:34:20 PM PDT 24
Peak memory 207400 kb
Host smart-022c4033-3da6-411d-8891-70f14a998728
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276309629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1276309629
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3742064743
Short name T999
Test name
Test status
Simulation time 9351040743 ps
CPU time 26.46 seconds
Started Jun 05 04:34:01 PM PDT 24
Finished Jun 05 04:34:29 PM PDT 24
Peak memory 207488 kb
Host smart-a2362139-d19a-4828-8788-1082ea174b5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742064743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3742064743
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2553920115
Short name T78
Test name
Test status
Simulation time 76969288 ps
CPU time 1.47 seconds
Started Jun 05 04:34:03 PM PDT 24
Finished Jun 05 04:34:06 PM PDT 24
Peak memory 207344 kb
Host smart-356019ec-202d-4d12-bc84-7788480d9709
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553920115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2553920115
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2932345393
Short name T1011
Test name
Test status
Simulation time 50747129 ps
CPU time 1.73 seconds
Started Jun 05 04:34:05 PM PDT 24
Finished Jun 05 04:34:07 PM PDT 24
Peak memory 215568 kb
Host smart-0778d8e4-5d46-4092-a863-9a5345822b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932345393 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2932345393
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3294835770
Short name T1073
Test name
Test status
Simulation time 62740352 ps
CPU time 1.94 seconds
Started Jun 05 04:34:07 PM PDT 24
Finished Jun 05 04:34:10 PM PDT 24
Peak memory 215624 kb
Host smart-fe771e48-9a4d-4e34-b1f9-062653ca13a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294835770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
294835770
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.569375215
Short name T1034
Test name
Test status
Simulation time 104451244 ps
CPU time 0.74 seconds
Started Jun 05 04:34:06 PM PDT 24
Finished Jun 05 04:34:08 PM PDT 24
Peak memory 204260 kb
Host smart-a56dcb68-a10e-4191-bc5f-0b954c8dc075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569375215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.569375215
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3642802035
Short name T1052
Test name
Test status
Simulation time 34078400 ps
CPU time 1.38 seconds
Started Jun 05 04:34:01 PM PDT 24
Finished Jun 05 04:34:03 PM PDT 24
Peak memory 215556 kb
Host smart-647a48b2-097d-43c9-914f-89b91ec85bef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642802035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3642802035
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3203293186
Short name T996
Test name
Test status
Simulation time 16884246 ps
CPU time 0.65 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:06 PM PDT 24
Peak memory 204176 kb
Host smart-8162b90b-c3b9-4125-963a-69b56a9bc646
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203293186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3203293186
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1402385724
Short name T1099
Test name
Test status
Simulation time 467690319 ps
CPU time 4.05 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:14 PM PDT 24
Peak memory 215600 kb
Host smart-82d22ade-108d-4665-be3e-2cda20d12f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402385724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1402385724
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.822518239
Short name T101
Test name
Test status
Simulation time 75014019 ps
CPU time 4.77 seconds
Started Jun 05 04:34:00 PM PDT 24
Finished Jun 05 04:34:06 PM PDT 24
Peak memory 215776 kb
Host smart-0c07e12d-2b19-40fb-9380-e82927d33459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822518239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.822518239
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4264572449
Short name T1064
Test name
Test status
Simulation time 1605577980 ps
CPU time 8.78 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:19 PM PDT 24
Peak memory 207348 kb
Host smart-c09369d3-755e-43d1-b000-fa7d30082135
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264572449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4264572449
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1041894308
Short name T984
Test name
Test status
Simulation time 1256487947 ps
CPU time 24.17 seconds
Started Jun 05 04:34:01 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 207400 kb
Host smart-7e94836d-b671-43ad-9430-7065f6ca55b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041894308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1041894308
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2105021124
Short name T76
Test name
Test status
Simulation time 39824578 ps
CPU time 1.4 seconds
Started Jun 05 04:34:06 PM PDT 24
Finished Jun 05 04:34:08 PM PDT 24
Peak memory 207328 kb
Host smart-25ab12ff-fac1-4562-97aa-e70e43373328
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105021124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2105021124
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2571067370
Short name T88
Test name
Test status
Simulation time 464178491 ps
CPU time 3.16 seconds
Started Jun 05 04:34:03 PM PDT 24
Finished Jun 05 04:34:07 PM PDT 24
Peak memory 217892 kb
Host smart-6b3247b9-61fc-4584-b2a3-910f7f3a2073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571067370 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2571067370
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.265133367
Short name T115
Test name
Test status
Simulation time 41956759 ps
CPU time 2.64 seconds
Started Jun 05 04:34:07 PM PDT 24
Finished Jun 05 04:34:10 PM PDT 24
Peak memory 207412 kb
Host smart-42ca50d6-47f3-4f42-97dc-8046c2b9bc3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265133367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.265133367
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.595078336
Short name T1020
Test name
Test status
Simulation time 48825206 ps
CPU time 0.75 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:06 PM PDT 24
Peak memory 203980 kb
Host smart-353f61e6-c7c0-4f1a-be09-3b105700c3da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595078336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.595078336
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3776460327
Short name T113
Test name
Test status
Simulation time 147982522 ps
CPU time 1.33 seconds
Started Jun 05 04:34:03 PM PDT 24
Finished Jun 05 04:34:06 PM PDT 24
Peak memory 215648 kb
Host smart-07926692-ecd5-4465-8c5d-20fb40903b75
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776460327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3776460327
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3347533961
Short name T1009
Test name
Test status
Simulation time 89836970 ps
CPU time 0.65 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:16 PM PDT 24
Peak memory 204108 kb
Host smart-b90ed8da-6574-4f76-95b8-ae5c80b261b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347533961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3347533961
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2290249674
Short name T1010
Test name
Test status
Simulation time 128493584 ps
CPU time 2.52 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:16 PM PDT 24
Peak memory 215576 kb
Host smart-aa13d94b-11fd-4975-8896-c9d07db15659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290249674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2290249674
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3024270062
Short name T240
Test name
Test status
Simulation time 1210666033 ps
CPU time 19.66 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:30 PM PDT 24
Peak memory 215620 kb
Host smart-a1461654-7b84-4ace-b932-e12bd1427bed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024270062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3024270062
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3860051475
Short name T107
Test name
Test status
Simulation time 70809703 ps
CPU time 3.21 seconds
Started Jun 05 04:34:26 PM PDT 24
Finished Jun 05 04:34:30 PM PDT 24
Peak memory 218848 kb
Host smart-066e1103-8296-44c6-b68e-455929bc63d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860051475 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3860051475
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.649741950
Short name T1076
Test name
Test status
Simulation time 122740433 ps
CPU time 1.24 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:11 PM PDT 24
Peak memory 215484 kb
Host smart-b823c83f-f73b-4a07-8dc0-7ef2d74a3fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649741950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.649741950
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2547685933
Short name T992
Test name
Test status
Simulation time 15089190 ps
CPU time 0.75 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:16 PM PDT 24
Peak memory 204324 kb
Host smart-de83653e-f552-49a3-8774-b18c530a2b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547685933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2547685933
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2564274412
Short name T1029
Test name
Test status
Simulation time 171768523 ps
CPU time 4.02 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:34:29 PM PDT 24
Peak memory 215448 kb
Host smart-e29c9e9f-06c1-4922-8cd3-70b4823f6f0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564274412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2564274412
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3341805486
Short name T1012
Test name
Test status
Simulation time 55611551 ps
CPU time 1.83 seconds
Started Jun 05 04:34:11 PM PDT 24
Finished Jun 05 04:34:13 PM PDT 24
Peak memory 215788 kb
Host smart-4cac1034-c5d7-4958-81b4-c3e4ba6e381b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341805486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3341805486
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1721982518
Short name T143
Test name
Test status
Simulation time 2619149077 ps
CPU time 15.87 seconds
Started Jun 05 04:34:30 PM PDT 24
Finished Jun 05 04:34:47 PM PDT 24
Peak memory 215616 kb
Host smart-96aca288-63df-4d76-8c34-7597495fe397
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721982518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1721982518
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.791223977
Short name T1036
Test name
Test status
Simulation time 287394445 ps
CPU time 1.78 seconds
Started Jun 05 04:34:16 PM PDT 24
Finished Jun 05 04:34:18 PM PDT 24
Peak memory 216624 kb
Host smart-6f1cdf3b-c715-4c21-b5ed-a54000b934bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791223977 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.791223977
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.348325713
Short name T993
Test name
Test status
Simulation time 29430172 ps
CPU time 1.94 seconds
Started Jun 05 04:34:13 PM PDT 24
Finished Jun 05 04:34:16 PM PDT 24
Peak memory 219896 kb
Host smart-85cc7776-c5f6-4764-a559-196e1d69333a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348325713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.348325713
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.482991579
Short name T990
Test name
Test status
Simulation time 20574286 ps
CPU time 0.78 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:31 PM PDT 24
Peak memory 203936 kb
Host smart-aae87508-8a4b-49ac-b8f0-d5c33f137f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482991579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.482991579
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2200393991
Short name T1051
Test name
Test status
Simulation time 112849092 ps
CPU time 3.06 seconds
Started Jun 05 04:34:16 PM PDT 24
Finished Jun 05 04:34:20 PM PDT 24
Peak memory 215600 kb
Host smart-ac17fe40-a411-46bb-876b-c8b35fb23bc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200393991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2200393991
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.420825801
Short name T96
Test name
Test status
Simulation time 405906824 ps
CPU time 3.08 seconds
Started Jun 05 04:34:22 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 215748 kb
Host smart-7cfb3119-6bb8-4a22-9b26-06506e174657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420825801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.420825801
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3822712350
Short name T139
Test name
Test status
Simulation time 223407239 ps
CPU time 3.85 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:19 PM PDT 24
Peak memory 217780 kb
Host smart-c3699a8a-7337-4da6-b81c-ac8ef103c89c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822712350 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3822712350
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3040493663
Short name T1046
Test name
Test status
Simulation time 94424192 ps
CPU time 2.29 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:34:27 PM PDT 24
Peak memory 215584 kb
Host smart-da4616a0-727d-422c-8af9-72ca54d98059
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040493663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3040493663
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1517313857
Short name T1040
Test name
Test status
Simulation time 114978176 ps
CPU time 0.66 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:34:25 PM PDT 24
Peak memory 204040 kb
Host smart-dfe0715f-775f-4c64-a9aa-7b06602e72bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517313857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1517313857
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.611593680
Short name T131
Test name
Test status
Simulation time 92816991 ps
CPU time 1.71 seconds
Started Jun 05 04:34:19 PM PDT 24
Finished Jun 05 04:34:22 PM PDT 24
Peak memory 215456 kb
Host smart-825a03b7-7e4e-41ec-b46c-7d7ff1efcad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611593680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.611593680
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1676033252
Short name T103
Test name
Test status
Simulation time 85584169 ps
CPU time 1.71 seconds
Started Jun 05 04:34:16 PM PDT 24
Finished Jun 05 04:34:18 PM PDT 24
Peak memory 215796 kb
Host smart-f8e7dc0a-4bfd-4c7b-90cf-9d4f59233b89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676033252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1676033252
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2870391124
Short name T1056
Test name
Test status
Simulation time 591174811 ps
CPU time 8.84 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:34:34 PM PDT 24
Peak memory 223468 kb
Host smart-43420df3-aa9a-4729-a411-f475b3e6db74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870391124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2870391124
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1502351392
Short name T109
Test name
Test status
Simulation time 93160314 ps
CPU time 4.45 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:34:29 PM PDT 24
Peak memory 218260 kb
Host smart-f0e43737-6593-428e-9e7c-9f0b6ed3f73e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502351392 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1502351392
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2155292055
Short name T122
Test name
Test status
Simulation time 91547151 ps
CPU time 2.42 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:36 PM PDT 24
Peak memory 215560 kb
Host smart-6e0c906e-f8a8-4d19-8bbb-5d002b6c631e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155292055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2155292055
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.861099581
Short name T987
Test name
Test status
Simulation time 13160042 ps
CPU time 0.7 seconds
Started Jun 05 04:34:52 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 204340 kb
Host smart-2a7740f8-6a47-4988-9340-7110b5a176d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861099581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.861099581
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3645484182
Short name T1025
Test name
Test status
Simulation time 57585231 ps
CPU time 1.96 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:15 PM PDT 24
Peak memory 207336 kb
Host smart-86b36423-6308-4931-a5ab-36d8661f9193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645484182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3645484182
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.691450779
Short name T100
Test name
Test status
Simulation time 208887548 ps
CPU time 3.58 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:34 PM PDT 24
Peak memory 215668 kb
Host smart-588c2442-1dd8-4690-a70c-ad08f78c0444
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691450779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.691450779
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2559439033
Short name T141
Test name
Test status
Simulation time 5557827754 ps
CPU time 24.38 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:34:53 PM PDT 24
Peak memory 215816 kb
Host smart-e16ee9cd-5bf0-4cc3-b057-6fe8840cf036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559439033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2559439033
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3776790022
Short name T1015
Test name
Test status
Simulation time 796493497 ps
CPU time 3.85 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:17 PM PDT 24
Peak memory 217124 kb
Host smart-18346f2b-214b-4bc4-973c-3b746e5b8ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776790022 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3776790022
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.427143084
Short name T124
Test name
Test status
Simulation time 127428350 ps
CPU time 2.88 seconds
Started Jun 05 04:34:26 PM PDT 24
Finished Jun 05 04:34:29 PM PDT 24
Peak memory 207452 kb
Host smart-da58d6da-ce5b-4a30-9b95-d4ab975380dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427143084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.427143084
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4220707321
Short name T1096
Test name
Test status
Simulation time 16658913 ps
CPU time 0.78 seconds
Started Jun 05 04:34:33 PM PDT 24
Finished Jun 05 04:34:36 PM PDT 24
Peak memory 204308 kb
Host smart-265fc476-6243-4e63-995c-e8fab6d85123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220707321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
4220707321
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.917339993
Short name T1044
Test name
Test status
Simulation time 321531256 ps
CPU time 1.91 seconds
Started Jun 05 04:34:40 PM PDT 24
Finished Jun 05 04:34:43 PM PDT 24
Peak memory 207392 kb
Host smart-fa47dab9-5a85-467c-8801-c8add99651c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917339993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.917339993
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2725742449
Short name T108
Test name
Test status
Simulation time 380390452 ps
CPU time 2.85 seconds
Started Jun 05 04:34:39 PM PDT 24
Finished Jun 05 04:34:44 PM PDT 24
Peak memory 215808 kb
Host smart-114e4344-f254-410d-acec-d4d14ca0beea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725742449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2725742449
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1389059485
Short name T243
Test name
Test status
Simulation time 1846792595 ps
CPU time 15.21 seconds
Started Jun 05 04:34:30 PM PDT 24
Finished Jun 05 04:34:46 PM PDT 24
Peak memory 215776 kb
Host smart-de7447c2-f164-4bd8-81e2-83557c5733fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389059485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1389059485
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1738579500
Short name T1023
Test name
Test status
Simulation time 464224016 ps
CPU time 1.68 seconds
Started Jun 05 04:34:25 PM PDT 24
Finished Jun 05 04:34:28 PM PDT 24
Peak memory 215668 kb
Host smart-176f7ee5-05cb-4390-94da-f30f0794c755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738579500 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1738579500
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3480562970
Short name T116
Test name
Test status
Simulation time 124170148 ps
CPU time 2.54 seconds
Started Jun 05 04:34:22 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 207408 kb
Host smart-5379695b-aafc-4966-937f-a717cfbb21ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480562970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3480562970
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3087134531
Short name T1005
Test name
Test status
Simulation time 27276590 ps
CPU time 0.73 seconds
Started Jun 05 04:34:23 PM PDT 24
Finished Jun 05 04:34:25 PM PDT 24
Peak memory 204320 kb
Host smart-56ce5599-284e-4ce0-8bca-1bdd00bd769d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087134531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3087134531
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3378057146
Short name T1000
Test name
Test status
Simulation time 41371213 ps
CPU time 1.75 seconds
Started Jun 05 04:34:16 PM PDT 24
Finished Jun 05 04:34:19 PM PDT 24
Peak memory 207312 kb
Host smart-ea08daa1-7f98-485a-afe2-a94b6a7484bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378057146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3378057146
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3580245644
Short name T106
Test name
Test status
Simulation time 97460792 ps
CPU time 1.67 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:34:39 PM PDT 24
Peak memory 216808 kb
Host smart-d345c68d-268e-4faf-9e03-30a374329f54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580245644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3580245644
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1628538309
Short name T110
Test name
Test status
Simulation time 1442472504 ps
CPU time 7.78 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:23 PM PDT 24
Peak memory 215592 kb
Host smart-f56578eb-831a-4da8-a1bd-41a83f2e5deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628538309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1628538309
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.385329286
Short name T1070
Test name
Test status
Simulation time 161627353 ps
CPU time 3.87 seconds
Started Jun 05 04:34:21 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 217504 kb
Host smart-7e90447e-a3b8-45e5-b02d-3abb82182eca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385329286 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.385329286
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.925270508
Short name T1039
Test name
Test status
Simulation time 62084218 ps
CPU time 2 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:15 PM PDT 24
Peak memory 215616 kb
Host smart-ddc18381-7b98-4c58-826a-9cbac0490716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925270508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.925270508
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1165921767
Short name T1067
Test name
Test status
Simulation time 48623922 ps
CPU time 0.75 seconds
Started Jun 05 04:34:23 PM PDT 24
Finished Jun 05 04:34:25 PM PDT 24
Peak memory 204036 kb
Host smart-b71bc8f9-e11c-4cc7-bcae-7f7afd58ca1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165921767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1165921767
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1653608204
Short name T1031
Test name
Test status
Simulation time 25913543 ps
CPU time 1.79 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 215456 kb
Host smart-145b6b3a-85f0-4c14-9715-fcb9b5300cf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653608204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1653608204
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2856006929
Short name T90
Test name
Test status
Simulation time 351767521 ps
CPU time 2.3 seconds
Started Jun 05 04:34:36 PM PDT 24
Finished Jun 05 04:34:41 PM PDT 24
Peak memory 215780 kb
Host smart-0e421f0b-24ed-41c1-a56e-afdb765a1e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856006929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2856006929
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.992415644
Short name T1091
Test name
Test status
Simulation time 437725115 ps
CPU time 6.74 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:38 PM PDT 24
Peak memory 215524 kb
Host smart-73eb3783-332b-4986-9fd8-25fee05e9cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992415644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.992415644
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2318140020
Short name T1086
Test name
Test status
Simulation time 179784843 ps
CPU time 2.87 seconds
Started Jun 05 04:34:20 PM PDT 24
Finished Jun 05 04:34:23 PM PDT 24
Peak memory 218184 kb
Host smart-b0200f58-e266-43b3-a35b-f9d900fdff86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318140020 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2318140020
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.628910029
Short name T1078
Test name
Test status
Simulation time 423376913 ps
CPU time 1.92 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:17 PM PDT 24
Peak memory 207408 kb
Host smart-efc33a17-1075-478f-af18-b91f56609895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628910029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.628910029
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2852617266
Short name T1079
Test name
Test status
Simulation time 169789751 ps
CPU time 0.74 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:34:25 PM PDT 24
Peak memory 204000 kb
Host smart-51a1dd7f-25d6-456d-8a5b-34bdd34298b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852617266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2852617266
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3540404155
Short name T1082
Test name
Test status
Simulation time 159137088 ps
CPU time 2.59 seconds
Started Jun 05 04:34:25 PM PDT 24
Finished Jun 05 04:34:28 PM PDT 24
Peak memory 215560 kb
Host smart-00826ba9-dcdf-40f4-a6eb-fc737d1483b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540404155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3540404155
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2555223528
Short name T105
Test name
Test status
Simulation time 272107975 ps
CPU time 3.66 seconds
Started Jun 05 04:34:17 PM PDT 24
Finished Jun 05 04:34:21 PM PDT 24
Peak memory 215800 kb
Host smart-479e6907-0231-4fd9-b2d8-c62cd756a710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555223528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2555223528
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3968420574
Short name T1045
Test name
Test status
Simulation time 1096633450 ps
CPU time 6.65 seconds
Started Jun 05 04:34:31 PM PDT 24
Finished Jun 05 04:34:45 PM PDT 24
Peak memory 215492 kb
Host smart-49ce824c-3909-425a-bf18-c0805b995ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968420574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3968420574
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1397941845
Short name T1042
Test name
Test status
Simulation time 321545353 ps
CPU time 3.76 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:34:32 PM PDT 24
Peak memory 217028 kb
Host smart-645ff53e-9e76-48f7-9fdd-850809cb8129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397941845 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1397941845
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3662832956
Short name T114
Test name
Test status
Simulation time 26405180 ps
CPU time 1.23 seconds
Started Jun 05 04:34:26 PM PDT 24
Finished Jun 05 04:34:28 PM PDT 24
Peak memory 207404 kb
Host smart-6ac1e96d-da5c-48a8-9277-2fb3da2ee23c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662832956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3662832956
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1181940430
Short name T1017
Test name
Test status
Simulation time 14886282 ps
CPU time 0.72 seconds
Started Jun 05 04:34:36 PM PDT 24
Finished Jun 05 04:34:40 PM PDT 24
Peak memory 204024 kb
Host smart-46339c47-59be-451a-805e-2c247ba32ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181940430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1181940430
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3183251530
Short name T1001
Test name
Test status
Simulation time 57830666 ps
CPU time 3.7 seconds
Started Jun 05 04:34:16 PM PDT 24
Finished Jun 05 04:34:20 PM PDT 24
Peak memory 215596 kb
Host smart-73657cc0-5173-46d2-b4c7-5940e5183ed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183251530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3183251530
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3890164857
Short name T102
Test name
Test status
Simulation time 156303463 ps
CPU time 3.93 seconds
Started Jun 05 04:34:11 PM PDT 24
Finished Jun 05 04:34:16 PM PDT 24
Peak memory 215808 kb
Host smart-3a0e7ffd-755d-460f-88a8-ee20e1b5f66c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890164857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3890164857
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1438336859
Short name T242
Test name
Test status
Simulation time 1217086416 ps
CPU time 19.79 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:33 PM PDT 24
Peak memory 215484 kb
Host smart-1a86c627-18b8-4ce1-9064-e10ac50f3fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438336859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1438336859
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2681202829
Short name T1074
Test name
Test status
Simulation time 132334870 ps
CPU time 3.96 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:37 PM PDT 24
Peak memory 217684 kb
Host smart-ad874223-ee8f-4d28-aad8-e1c89470f5b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681202829 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2681202829
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4230309910
Short name T132
Test name
Test status
Simulation time 265875551 ps
CPU time 2.17 seconds
Started Jun 05 04:34:21 PM PDT 24
Finished Jun 05 04:34:24 PM PDT 24
Peak memory 215440 kb
Host smart-4066b777-ff17-4d4a-9379-919e64859c9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230309910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4230309910
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.317663305
Short name T1008
Test name
Test status
Simulation time 17527546 ps
CPU time 0.73 seconds
Started Jun 05 04:34:15 PM PDT 24
Finished Jun 05 04:34:17 PM PDT 24
Peak memory 204028 kb
Host smart-9205810b-0a1d-44f4-891b-be575843639d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317663305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.317663305
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3307907994
Short name T1033
Test name
Test status
Simulation time 56696695 ps
CPU time 1.82 seconds
Started Jun 05 04:34:11 PM PDT 24
Finished Jun 05 04:34:14 PM PDT 24
Peak memory 215608 kb
Host smart-76567597-4f4e-4f9f-bcec-276f24d1c3dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307907994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3307907994
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.254752148
Short name T1094
Test name
Test status
Simulation time 51970367 ps
CPU time 1.87 seconds
Started Jun 05 04:34:13 PM PDT 24
Finished Jun 05 04:34:16 PM PDT 24
Peak memory 216896 kb
Host smart-810c5a55-b5bb-4d40-a7df-7176b2deddb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254752148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.254752148
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.291289285
Short name T997
Test name
Test status
Simulation time 132801726 ps
CPU time 6.85 seconds
Started Jun 05 04:34:20 PM PDT 24
Finished Jun 05 04:34:28 PM PDT 24
Peak memory 215432 kb
Host smart-4f657069-0084-41e1-9613-016bf4278a64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291289285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.291289285
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2583880328
Short name T1058
Test name
Test status
Simulation time 4984697463 ps
CPU time 20.99 seconds
Started Jun 05 04:34:02 PM PDT 24
Finished Jun 05 04:34:24 PM PDT 24
Peak memory 207344 kb
Host smart-8c79c49c-2c2b-4bf7-99e1-d96f8fff603a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583880328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2583880328
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2545165535
Short name T121
Test name
Test status
Simulation time 2538312320 ps
CPU time 12.73 seconds
Started Jun 05 04:34:07 PM PDT 24
Finished Jun 05 04:34:21 PM PDT 24
Peak memory 207440 kb
Host smart-301348c8-2c75-45ac-9f2a-b51033eaff5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545165535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2545165535
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1381044543
Short name T1047
Test name
Test status
Simulation time 270665753 ps
CPU time 2.73 seconds
Started Jun 05 04:34:10 PM PDT 24
Finished Jun 05 04:34:14 PM PDT 24
Peak memory 216564 kb
Host smart-2ce0877b-0c6d-4113-a369-e77091804a17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381044543 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1381044543
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3613740187
Short name T1021
Test name
Test status
Simulation time 169092259 ps
CPU time 2.27 seconds
Started Jun 05 04:34:00 PM PDT 24
Finished Jun 05 04:34:03 PM PDT 24
Peak memory 215612 kb
Host smart-96c65e1a-7af0-42b3-8d92-fa51ac367d7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613740187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
613740187
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2877550884
Short name T1003
Test name
Test status
Simulation time 49608249 ps
CPU time 0.73 seconds
Started Jun 05 04:34:03 PM PDT 24
Finished Jun 05 04:34:05 PM PDT 24
Peak memory 204024 kb
Host smart-88778bff-da17-4f74-a761-ba92863c6f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877550884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
877550884
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.545631842
Short name T112
Test name
Test status
Simulation time 23141768 ps
CPU time 1.54 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:07 PM PDT 24
Peak memory 215592 kb
Host smart-48f78741-658d-4831-bf8e-490f7f6d7402
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545631842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.545631842
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2672998125
Short name T1041
Test name
Test status
Simulation time 29249542 ps
CPU time 0.72 seconds
Started Jun 05 04:34:07 PM PDT 24
Finished Jun 05 04:34:08 PM PDT 24
Peak memory 204172 kb
Host smart-5a42b46f-0812-42f5-b6f2-bba498edff4d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672998125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2672998125
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1954152078
Short name T1081
Test name
Test status
Simulation time 44484196 ps
CPU time 2.76 seconds
Started Jun 05 04:34:02 PM PDT 24
Finished Jun 05 04:34:06 PM PDT 24
Peak memory 215544 kb
Host smart-d11cc1e9-a28f-461d-9ef7-385d9b3d7988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954152078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1954152078
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4062038459
Short name T1048
Test name
Test status
Simulation time 638685352 ps
CPU time 3.92 seconds
Started Jun 05 04:34:13 PM PDT 24
Finished Jun 05 04:34:18 PM PDT 24
Peak memory 215712 kb
Host smart-2c806560-b737-4b19-81ed-384717fb1a23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062038459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
062038459
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2515049797
Short name T241
Test name
Test status
Simulation time 107928043 ps
CPU time 6.67 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:12 PM PDT 24
Peak memory 215604 kb
Host smart-69eff137-e2d9-4e66-91fe-0189a15cebee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515049797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2515049797
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1372334590
Short name T1075
Test name
Test status
Simulation time 38586587 ps
CPU time 0.7 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:31 PM PDT 24
Peak memory 204016 kb
Host smart-cd47ae54-43d9-4a61-afbc-7c1d1ac5a2e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372334590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1372334590
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3438536571
Short name T982
Test name
Test status
Simulation time 12534896 ps
CPU time 0.69 seconds
Started Jun 05 04:34:20 PM PDT 24
Finished Jun 05 04:34:22 PM PDT 24
Peak memory 204040 kb
Host smart-60a4e04f-abe5-47a2-834a-3bc1959b34b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438536571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3438536571
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3233041027
Short name T1060
Test name
Test status
Simulation time 15576320 ps
CPU time 0.74 seconds
Started Jun 05 04:34:23 PM PDT 24
Finished Jun 05 04:34:24 PM PDT 24
Peak memory 203940 kb
Host smart-d54ab61e-9484-4c94-a21a-6797233072c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233041027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3233041027
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.368838517
Short name T1027
Test name
Test status
Simulation time 60204730 ps
CPU time 0.76 seconds
Started Jun 05 04:34:13 PM PDT 24
Finished Jun 05 04:34:15 PM PDT 24
Peak memory 204024 kb
Host smart-29c4e967-5df8-4b90-b674-c6a14bf76f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368838517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.368838517
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.283207911
Short name T1090
Test name
Test status
Simulation time 27614702 ps
CPU time 0.74 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:34:30 PM PDT 24
Peak memory 204024 kb
Host smart-7b062208-d505-4218-953f-7a770cbf06df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283207911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.283207911
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1907425187
Short name T1061
Test name
Test status
Simulation time 16186213 ps
CPU time 0.79 seconds
Started Jun 05 04:34:31 PM PDT 24
Finished Jun 05 04:34:33 PM PDT 24
Peak memory 204040 kb
Host smart-615bf9da-f3f1-47ef-aa03-ed12daf8667a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907425187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1907425187
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2882132047
Short name T988
Test name
Test status
Simulation time 20445028 ps
CPU time 0.77 seconds
Started Jun 05 04:34:30 PM PDT 24
Finished Jun 05 04:34:32 PM PDT 24
Peak memory 204084 kb
Host smart-9e08df4f-bc1f-4181-9956-088354a5ce2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882132047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2882132047
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.727887444
Short name T1065
Test name
Test status
Simulation time 24438475 ps
CPU time 0.67 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:31 PM PDT 24
Peak memory 204328 kb
Host smart-8b312b01-2a70-4fb5-ab99-7a8c3c6bb334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727887444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.727887444
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.440868403
Short name T978
Test name
Test status
Simulation time 11427170 ps
CPU time 0.79 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:37 PM PDT 24
Peak memory 204028 kb
Host smart-a24f9b04-3273-4f28-89c3-a3f244e8d690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440868403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.440868403
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4073230396
Short name T980
Test name
Test status
Simulation time 17448584 ps
CPU time 0.75 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:34 PM PDT 24
Peak memory 204480 kb
Host smart-15effee9-1376-4a4a-bb3a-d6d563a87548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073230396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4073230396
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2564109899
Short name T1071
Test name
Test status
Simulation time 5201080151 ps
CPU time 24.43 seconds
Started Jun 05 04:34:18 PM PDT 24
Finished Jun 05 04:34:43 PM PDT 24
Peak memory 215656 kb
Host smart-b4a5b9a9-ad29-40f1-860a-13fa657e8a04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564109899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2564109899
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1594933538
Short name T1030
Test name
Test status
Simulation time 1893572557 ps
CPU time 37.08 seconds
Started Jun 05 04:34:23 PM PDT 24
Finished Jun 05 04:35:01 PM PDT 24
Peak memory 207380 kb
Host smart-4913c2ee-5197-47d1-8afe-06ab255016be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594933538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1594933538
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4130106950
Short name T140
Test name
Test status
Simulation time 24412513 ps
CPU time 1 seconds
Started Jun 05 04:34:16 PM PDT 24
Finished Jun 05 04:34:18 PM PDT 24
Peak memory 207128 kb
Host smart-ab80a6a6-be47-497a-9e66-1278859cc49e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130106950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4130106950
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2221861092
Short name T1049
Test name
Test status
Simulation time 54716899 ps
CPU time 3.43 seconds
Started Jun 05 04:34:21 PM PDT 24
Finished Jun 05 04:34:25 PM PDT 24
Peak memory 218612 kb
Host smart-b1b7fec2-53b3-44f3-955e-abd4a9c872bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221861092 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2221861092
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1323561483
Short name T1097
Test name
Test status
Simulation time 59440942 ps
CPU time 1.86 seconds
Started Jun 05 04:34:07 PM PDT 24
Finished Jun 05 04:34:10 PM PDT 24
Peak memory 215608 kb
Host smart-2420a6ff-689c-4cf4-aaa5-38fce6914d5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323561483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
323561483
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4149360641
Short name T1050
Test name
Test status
Simulation time 11141963 ps
CPU time 0.73 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:06 PM PDT 24
Peak memory 204016 kb
Host smart-78745519-3bce-4a54-a276-b716bdf4e3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149360641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
149360641
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3456785784
Short name T117
Test name
Test status
Simulation time 124552914 ps
CPU time 2.21 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:07 PM PDT 24
Peak memory 215568 kb
Host smart-6fc6b4b6-e59a-40fb-8d37-f8f61928aee1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456785784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3456785784
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4111753412
Short name T1066
Test name
Test status
Simulation time 18363171 ps
CPU time 0.73 seconds
Started Jun 05 04:33:58 PM PDT 24
Finished Jun 05 04:34:00 PM PDT 24
Peak memory 203836 kb
Host smart-cabc7ed2-84f0-496f-b201-6d636416337a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111753412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4111753412
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.848521923
Short name T1043
Test name
Test status
Simulation time 577359067 ps
CPU time 2.68 seconds
Started Jun 05 04:34:23 PM PDT 24
Finished Jun 05 04:34:27 PM PDT 24
Peak memory 215616 kb
Host smart-7e2e4d95-7fab-4057-9149-0afca5552212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848521923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.848521923
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2639914935
Short name T1092
Test name
Test status
Simulation time 194088223 ps
CPU time 1.62 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:07 PM PDT 24
Peak memory 215844 kb
Host smart-57183516-9833-4991-996c-69cbf2cb105e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639914935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
639914935
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3070102895
Short name T1098
Test name
Test status
Simulation time 745928426 ps
CPU time 14.41 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:24 PM PDT 24
Peak memory 215764 kb
Host smart-d45bf818-f189-4435-a04a-ecb168ae006f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070102895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3070102895
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2743576688
Short name T994
Test name
Test status
Simulation time 75134109 ps
CPU time 0.69 seconds
Started Jun 05 04:34:30 PM PDT 24
Finished Jun 05 04:34:32 PM PDT 24
Peak memory 204024 kb
Host smart-890b0c33-8a8b-4c79-a7be-a366027ed37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743576688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2743576688
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.564842307
Short name T1095
Test name
Test status
Simulation time 13031361 ps
CPU time 0.66 seconds
Started Jun 05 04:34:27 PM PDT 24
Finished Jun 05 04:34:28 PM PDT 24
Peak memory 204032 kb
Host smart-3ffa8b9a-d425-4500-b36e-eace519e6ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564842307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.564842307
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.319256450
Short name T991
Test name
Test status
Simulation time 58239267 ps
CPU time 0.79 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:34:30 PM PDT 24
Peak memory 204004 kb
Host smart-2704e49e-8de7-4d13-9e14-1abf0be7afca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319256450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.319256450
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2311299597
Short name T995
Test name
Test status
Simulation time 12477851 ps
CPU time 0.71 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:34:30 PM PDT 24
Peak memory 203976 kb
Host smart-aaa57fab-7a14-4727-a8b9-2575d89129fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311299597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2311299597
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3944707720
Short name T1059
Test name
Test status
Simulation time 28255936 ps
CPU time 0.78 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 204328 kb
Host smart-68f870bd-a255-4966-bdce-a53a4e794c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944707720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3944707720
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2674141132
Short name T1013
Test name
Test status
Simulation time 49413140 ps
CPU time 0.73 seconds
Started Jun 05 04:34:30 PM PDT 24
Finished Jun 05 04:34:32 PM PDT 24
Peak memory 204012 kb
Host smart-5bf80cf0-e1e2-47d4-b7de-68ddf81646df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674141132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2674141132
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2144188582
Short name T1026
Test name
Test status
Simulation time 17000191 ps
CPU time 0.75 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:35 PM PDT 24
Peak memory 204016 kb
Host smart-b4fd661b-e330-4728-81d4-2e2796e50197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144188582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2144188582
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1982240075
Short name T1016
Test name
Test status
Simulation time 168775799 ps
CPU time 0.74 seconds
Started Jun 05 04:34:25 PM PDT 24
Finished Jun 05 04:34:27 PM PDT 24
Peak memory 204012 kb
Host smart-f8006c15-a71a-4f68-91e7-039ba58164be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982240075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1982240075
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2708939791
Short name T1024
Test name
Test status
Simulation time 13107314 ps
CPU time 0.7 seconds
Started Jun 05 04:34:29 PM PDT 24
Finished Jun 05 04:34:31 PM PDT 24
Peak memory 204028 kb
Host smart-40ac7d72-5280-4747-9dee-272e2470633e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708939791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2708939791
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3953314230
Short name T1004
Test name
Test status
Simulation time 31861967 ps
CPU time 0.71 seconds
Started Jun 05 04:34:41 PM PDT 24
Finished Jun 05 04:34:43 PM PDT 24
Peak memory 204040 kb
Host smart-c3fdd4fe-c26a-42d7-8645-66dff7145671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953314230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3953314230
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.197968023
Short name T1007
Test name
Test status
Simulation time 2454550093 ps
CPU time 16.8 seconds
Started Jun 05 04:34:07 PM PDT 24
Finished Jun 05 04:34:25 PM PDT 24
Peak memory 215560 kb
Host smart-28551a0a-4808-4b98-bc48-a79d13e0a936
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197968023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.197968023
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.177727794
Short name T123
Test name
Test status
Simulation time 25882624315 ps
CPU time 37.09 seconds
Started Jun 05 04:34:24 PM PDT 24
Finished Jun 05 04:35:02 PM PDT 24
Peak memory 207304 kb
Host smart-20216db4-2338-4f1f-a74e-0717a848ac73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177727794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.177727794
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.140759807
Short name T79
Test name
Test status
Simulation time 25133444 ps
CPU time 1.33 seconds
Started Jun 05 04:34:21 PM PDT 24
Finished Jun 05 04:34:23 PM PDT 24
Peak memory 207308 kb
Host smart-4d3b5d2a-e51a-437c-b113-737f1a26d204
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140759807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.140759807
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1448410349
Short name T1072
Test name
Test status
Simulation time 111002977 ps
CPU time 1.91 seconds
Started Jun 05 04:34:17 PM PDT 24
Finished Jun 05 04:34:20 PM PDT 24
Peak memory 216692 kb
Host smart-08b5fd3f-e2eb-4138-85e7-114e8364e0f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448410349 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1448410349
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4094338474
Short name T1089
Test name
Test status
Simulation time 162434308 ps
CPU time 1.42 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:07 PM PDT 24
Peak memory 207408 kb
Host smart-d34e9e33-1eb4-4b22-b335-a72a0d0ebb99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094338474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
094338474
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1740925665
Short name T1014
Test name
Test status
Simulation time 12075693 ps
CPU time 0.76 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:11 PM PDT 24
Peak memory 204212 kb
Host smart-103e25a7-e8d4-47c1-b92c-d4ea9fd0e9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740925665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
740925665
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4027121425
Short name T1101
Test name
Test status
Simulation time 66313154 ps
CPU time 1.28 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:07 PM PDT 24
Peak memory 215684 kb
Host smart-9766de77-2fe5-4ac3-814a-3806347ed5a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027121425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4027121425
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3464492691
Short name T998
Test name
Test status
Simulation time 31061947 ps
CPU time 0.67 seconds
Started Jun 05 04:34:09 PM PDT 24
Finished Jun 05 04:34:11 PM PDT 24
Peak memory 204172 kb
Host smart-a58665c1-a960-492e-a7b4-5a95146dc6f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464492691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3464492691
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.934592825
Short name T989
Test name
Test status
Simulation time 178300241 ps
CPU time 2.82 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:18 PM PDT 24
Peak memory 215540 kb
Host smart-44123909-dc9d-44ea-ab1c-cebd4ac90f88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934592825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.934592825
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2756888366
Short name T1054
Test name
Test status
Simulation time 118256720 ps
CPU time 3.35 seconds
Started Jun 05 04:34:11 PM PDT 24
Finished Jun 05 04:34:15 PM PDT 24
Peak memory 215688 kb
Host smart-5e46a00b-2dca-424a-8d70-f59ecc9224ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756888366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
756888366
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3558832586
Short name T1006
Test name
Test status
Simulation time 1883731851 ps
CPU time 7.52 seconds
Started Jun 05 04:34:13 PM PDT 24
Finished Jun 05 04:34:22 PM PDT 24
Peak memory 215712 kb
Host smart-2f492a24-7c26-4f02-8850-a7faa659340e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558832586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3558832586
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3434972728
Short name T983
Test name
Test status
Simulation time 24351714 ps
CPU time 0.72 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:34 PM PDT 24
Peak memory 204276 kb
Host smart-452ae53a-f332-4e09-973f-e375af0ce215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434972728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3434972728
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2802433608
Short name T1062
Test name
Test status
Simulation time 68967596 ps
CPU time 0.73 seconds
Started Jun 05 04:34:30 PM PDT 24
Finished Jun 05 04:34:32 PM PDT 24
Peak memory 204004 kb
Host smart-85a91a7b-20a3-44be-89b8-f7cf6852e023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802433608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2802433608
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.419466636
Short name T979
Test name
Test status
Simulation time 104254611 ps
CPU time 0.73 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:35 PM PDT 24
Peak memory 204332 kb
Host smart-6d83d2af-11c7-4694-9cbc-cd65ec28185c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419466636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.419466636
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3585304203
Short name T986
Test name
Test status
Simulation time 30093383 ps
CPU time 0.7 seconds
Started Jun 05 04:34:35 PM PDT 24
Finished Jun 05 04:34:38 PM PDT 24
Peak memory 204172 kb
Host smart-5783a675-7c98-4340-925c-0d3bea923526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585304203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3585304203
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1763180593
Short name T1063
Test name
Test status
Simulation time 42185704 ps
CPU time 0.7 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:36 PM PDT 24
Peak memory 204028 kb
Host smart-c52ef57e-b7f4-46af-a0ae-342cac3588a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763180593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1763180593
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1709708066
Short name T981
Test name
Test status
Simulation time 28081347 ps
CPU time 0.76 seconds
Started Jun 05 04:34:32 PM PDT 24
Finished Jun 05 04:34:37 PM PDT 24
Peak memory 204332 kb
Host smart-de4a1c5c-0fc1-484c-b8b3-6fb9f61639f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709708066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1709708066
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2655233895
Short name T1022
Test name
Test status
Simulation time 11805937 ps
CPU time 0.71 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:38 PM PDT 24
Peak memory 204288 kb
Host smart-042bfe02-4966-487f-86a8-1b3715bde98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655233895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2655233895
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2782059249
Short name T1100
Test name
Test status
Simulation time 16650386 ps
CPU time 0.79 seconds
Started Jun 05 04:34:25 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 204336 kb
Host smart-964a4030-6a4d-4afc-9af8-198122da9c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782059249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2782059249
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2400363924
Short name T1069
Test name
Test status
Simulation time 139481094 ps
CPU time 0.75 seconds
Started Jun 05 04:34:34 PM PDT 24
Finished Jun 05 04:34:37 PM PDT 24
Peak memory 204068 kb
Host smart-8a2318ee-75ae-4896-bc8c-3bb4d18d1a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400363924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2400363924
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3718004921
Short name T1028
Test name
Test status
Simulation time 16914684 ps
CPU time 0.75 seconds
Started Jun 05 04:34:28 PM PDT 24
Finished Jun 05 04:34:30 PM PDT 24
Peak memory 204012 kb
Host smart-63d89ba8-1c68-409c-bcb0-e9474f9c89c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718004921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3718004921
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3050739270
Short name T91
Test name
Test status
Simulation time 60130882 ps
CPU time 1.92 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:15 PM PDT 24
Peak memory 215672 kb
Host smart-ccc5f40b-0d65-4a4d-be77-fd9192222bc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050739270 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3050739270
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3214911391
Short name T119
Test name
Test status
Simulation time 30470991 ps
CPU time 1.96 seconds
Started Jun 05 04:34:20 PM PDT 24
Finished Jun 05 04:34:23 PM PDT 24
Peak memory 215620 kb
Host smart-bbc1e510-9c2f-44cd-a62e-208a7aef9ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214911391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
214911391
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1720614935
Short name T1019
Test name
Test status
Simulation time 18780031 ps
CPU time 0.76 seconds
Started Jun 05 04:34:11 PM PDT 24
Finished Jun 05 04:34:12 PM PDT 24
Peak memory 204040 kb
Host smart-611a1907-200d-4f63-b4d3-08f33947e7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720614935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
720614935
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3292168681
Short name T1038
Test name
Test status
Simulation time 45907858 ps
CPU time 2.88 seconds
Started Jun 05 04:34:07 PM PDT 24
Finished Jun 05 04:34:11 PM PDT 24
Peak memory 215520 kb
Host smart-122c518a-5ba5-40a0-b967-baa7ca699ea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292168681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3292168681
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1578210262
Short name T1057
Test name
Test status
Simulation time 221246501 ps
CPU time 5.2 seconds
Started Jun 05 04:34:02 PM PDT 24
Finished Jun 05 04:34:09 PM PDT 24
Peak memory 215716 kb
Host smart-7711573c-0eb6-4a1f-a531-f2f66a85fd36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578210262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
578210262
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4180501878
Short name T94
Test name
Test status
Simulation time 4219426508 ps
CPU time 22.67 seconds
Started Jun 05 04:34:02 PM PDT 24
Finished Jun 05 04:34:26 PM PDT 24
Peak memory 215692 kb
Host smart-be1d7093-2489-4c30-9146-d18db3985464
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180501878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4180501878
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2176978259
Short name T95
Test name
Test status
Simulation time 184223676 ps
CPU time 3.66 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:17 PM PDT 24
Peak memory 218476 kb
Host smart-50217cec-be44-4817-8c5d-29d6e482a9c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176978259 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2176978259
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.530518043
Short name T120
Test name
Test status
Simulation time 33144531 ps
CPU time 1.88 seconds
Started Jun 05 04:34:04 PM PDT 24
Finished Jun 05 04:34:07 PM PDT 24
Peak memory 215600 kb
Host smart-8be93bff-60e2-444a-b4d0-42a8872d1f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530518043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.530518043
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2495502689
Short name T985
Test name
Test status
Simulation time 26457554 ps
CPU time 0.76 seconds
Started Jun 05 04:34:40 PM PDT 24
Finished Jun 05 04:34:43 PM PDT 24
Peak memory 204340 kb
Host smart-bb92c3f9-9812-4b06-b3cc-f75a39e12625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495502689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
495502689
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3822451988
Short name T1037
Test name
Test status
Simulation time 4253167120 ps
CPU time 4.69 seconds
Started Jun 05 04:34:10 PM PDT 24
Finished Jun 05 04:34:16 PM PDT 24
Peak memory 215612 kb
Host smart-9688bc35-f544-42a3-9419-df21152e6194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822451988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3822451988
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.931500150
Short name T1085
Test name
Test status
Simulation time 368811402 ps
CPU time 2.26 seconds
Started Jun 05 04:34:37 PM PDT 24
Finished Jun 05 04:34:41 PM PDT 24
Peak memory 215928 kb
Host smart-27b2b663-3dca-456f-a895-6e7b3b50e5ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931500150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.931500150
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.57465695
Short name T1002
Test name
Test status
Simulation time 810913966 ps
CPU time 13.39 seconds
Started Jun 05 04:34:31 PM PDT 24
Finished Jun 05 04:34:46 PM PDT 24
Peak memory 215620 kb
Host smart-ec1ef248-05d4-425c-b1b3-3943d1e11279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57465695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_t
l_intg_err.57465695
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2419870935
Short name T142
Test name
Test status
Simulation time 604932694 ps
CPU time 3.78 seconds
Started Jun 05 04:34:26 PM PDT 24
Finished Jun 05 04:34:31 PM PDT 24
Peak memory 218408 kb
Host smart-5171c3b4-6bd6-493a-bf5a-db66b3f32f39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419870935 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2419870935
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2298029523
Short name T1087
Test name
Test status
Simulation time 1008355860 ps
CPU time 1.95 seconds
Started Jun 05 04:34:08 PM PDT 24
Finished Jun 05 04:34:11 PM PDT 24
Peak memory 207272 kb
Host smart-9e99401f-51e9-4660-9036-082350fdcedd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298029523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
298029523
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3038091960
Short name T1035
Test name
Test status
Simulation time 11825513 ps
CPU time 0.76 seconds
Started Jun 05 04:34:08 PM PDT 24
Finished Jun 05 04:34:10 PM PDT 24
Peak memory 204332 kb
Host smart-c74f4482-5c36-4c59-8531-eea00d4aff0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038091960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
038091960
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1001277385
Short name T1084
Test name
Test status
Simulation time 199215893 ps
CPU time 3.75 seconds
Started Jun 05 04:34:16 PM PDT 24
Finished Jun 05 04:34:20 PM PDT 24
Peak memory 215588 kb
Host smart-6d5f4ff4-f6e7-4f6a-a8a0-cb9594790eff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001277385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1001277385
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.118908648
Short name T1088
Test name
Test status
Simulation time 165223886 ps
CPU time 4.2 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:20 PM PDT 24
Peak memory 215848 kb
Host smart-0a621687-7743-47f7-b42a-dfa6aa03f8b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118908648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.118908648
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.524142435
Short name T1055
Test name
Test status
Simulation time 93693902 ps
CPU time 1.87 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:15 PM PDT 24
Peak memory 215764 kb
Host smart-51b16889-6770-45e6-aacf-f49a28523b17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524142435 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.524142435
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.838265260
Short name T1077
Test name
Test status
Simulation time 74143626 ps
CPU time 2 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:18 PM PDT 24
Peak memory 215616 kb
Host smart-f51327cd-dfb6-471b-b7fc-9754f25e416c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838265260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.838265260
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3622677542
Short name T1083
Test name
Test status
Simulation time 14359987 ps
CPU time 0.71 seconds
Started Jun 05 04:34:01 PM PDT 24
Finished Jun 05 04:34:03 PM PDT 24
Peak memory 204028 kb
Host smart-a36c84a0-9e62-4c56-9ba7-71a76fb72fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622677542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
622677542
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2412903769
Short name T1080
Test name
Test status
Simulation time 557333494 ps
CPU time 3.41 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:19 PM PDT 24
Peak memory 215604 kb
Host smart-bce961af-bb56-410f-b4e9-bf66c0ad7be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412903769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2412903769
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2459077056
Short name T1053
Test name
Test status
Simulation time 409531797 ps
CPU time 6.9 seconds
Started Jun 05 04:34:23 PM PDT 24
Finished Jun 05 04:34:31 PM PDT 24
Peak memory 216276 kb
Host smart-76f954a4-9b93-4770-b3fb-7893e0895255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459077056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2459077056
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1902378399
Short name T1068
Test name
Test status
Simulation time 364148424 ps
CPU time 1.88 seconds
Started Jun 05 04:34:10 PM PDT 24
Finished Jun 05 04:34:13 PM PDT 24
Peak memory 216696 kb
Host smart-9c4a5a21-5f97-4b7c-8336-2fc76affde87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902378399 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1902378399
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2554810196
Short name T138
Test name
Test status
Simulation time 81261025 ps
CPU time 2.11 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:15 PM PDT 24
Peak memory 215608 kb
Host smart-489873eb-0278-45e3-8ef0-006c8b93fc2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554810196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
554810196
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3445156249
Short name T1018
Test name
Test status
Simulation time 17525419 ps
CPU time 0.74 seconds
Started Jun 05 04:34:13 PM PDT 24
Finished Jun 05 04:34:14 PM PDT 24
Peak memory 204324 kb
Host smart-30cfc889-0e08-4cbd-bff2-556f30688b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445156249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
445156249
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.8022546
Short name T1093
Test name
Test status
Simulation time 71689136 ps
CPU time 1.83 seconds
Started Jun 05 04:34:14 PM PDT 24
Finished Jun 05 04:34:17 PM PDT 24
Peak memory 215600 kb
Host smart-12ff32f2-4f51-4cdf-a3cd-c05b501900cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8022546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_
device_same_csr_outstanding.8022546
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3407996932
Short name T93
Test name
Test status
Simulation time 287540640 ps
CPU time 2.11 seconds
Started Jun 05 04:34:11 PM PDT 24
Finished Jun 05 04:34:14 PM PDT 24
Peak memory 215836 kb
Host smart-88f3bf0b-a390-452c-a464-452f46d743aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407996932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
407996932
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2231889533
Short name T1032
Test name
Test status
Simulation time 4353506138 ps
CPU time 22.37 seconds
Started Jun 05 04:34:12 PM PDT 24
Finished Jun 05 04:34:35 PM PDT 24
Peak memory 216068 kb
Host smart-993623e5-366f-40e9-b35e-6be5e638ef2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231889533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2231889533
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1927880378
Short name T937
Test name
Test status
Simulation time 13509493 ps
CPU time 0.76 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:40:53 PM PDT 24
Peak memory 205000 kb
Host smart-59b366c8-619f-43d5-9600-bfa7189c1593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927880378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
927880378
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2192476960
Short name T764
Test name
Test status
Simulation time 97745849 ps
CPU time 2.32 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:40:54 PM PDT 24
Peak memory 224756 kb
Host smart-925cbbf3-1680-48c3-906c-5c47c80f1c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192476960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2192476960
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2281913954
Short name T674
Test name
Test status
Simulation time 27688540 ps
CPU time 0.82 seconds
Started Jun 05 05:40:46 PM PDT 24
Finished Jun 05 05:40:48 PM PDT 24
Peak memory 207276 kb
Host smart-b8693692-370b-49f4-8f04-05d194e5fe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281913954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2281913954
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2940299415
Short name T689
Test name
Test status
Simulation time 1283858800 ps
CPU time 30.2 seconds
Started Jun 05 05:40:50 PM PDT 24
Finished Jun 05 05:41:20 PM PDT 24
Peak memory 241380 kb
Host smart-c1781166-44e9-4ac3-8aa1-2d1368f39156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940299415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2940299415
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3633545979
Short name T620
Test name
Test status
Simulation time 62675397038 ps
CPU time 150.72 seconds
Started Jun 05 05:40:50 PM PDT 24
Finished Jun 05 05:43:22 PM PDT 24
Peak memory 236688 kb
Host smart-954130fc-c79f-48d9-a55f-98507344c7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633545979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3633545979
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.481601234
Short name T484
Test name
Test status
Simulation time 7592788402 ps
CPU time 15.13 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:41:07 PM PDT 24
Peak memory 233160 kb
Host smart-0af67a59-7025-4a37-ab19-022b00493d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481601234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.481601234
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4222158139
Short name T782
Test name
Test status
Simulation time 706002794 ps
CPU time 5.42 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:40:57 PM PDT 24
Peak memory 233124 kb
Host smart-9c0746fc-c4da-4bf9-a654-85bb52de8328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222158139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4222158139
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4278553946
Short name T325
Test name
Test status
Simulation time 2558861122 ps
CPU time 15.73 seconds
Started Jun 05 05:40:53 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 241016 kb
Host smart-c96aa4b0-e47e-4989-9bca-a30b35eef1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278553946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4278553946
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3453066674
Short name T957
Test name
Test status
Simulation time 25298430 ps
CPU time 1.05 seconds
Started Jun 05 05:40:44 PM PDT 24
Finished Jun 05 05:40:46 PM PDT 24
Peak memory 218304 kb
Host smart-caaa3fe4-63fc-4bd5-ac06-aa582db36a72
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453066674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3453066674
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2142330832
Short name T923
Test name
Test status
Simulation time 12823215784 ps
CPU time 14.38 seconds
Started Jun 05 05:40:47 PM PDT 24
Finished Jun 05 05:41:02 PM PDT 24
Peak memory 233112 kb
Host smart-bf38f8a8-b6b7-42b0-a8ab-9536d4189d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142330832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2142330832
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4275158494
Short name T961
Test name
Test status
Simulation time 751417582 ps
CPU time 5.35 seconds
Started Jun 05 05:40:44 PM PDT 24
Finished Jun 05 05:40:51 PM PDT 24
Peak memory 233164 kb
Host smart-fb0bdc67-0a56-43bc-ac46-dc78c1ca80d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275158494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4275158494
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2927028953
Short name T775
Test name
Test status
Simulation time 296659753 ps
CPU time 3.44 seconds
Started Jun 05 05:40:54 PM PDT 24
Finished Jun 05 05:40:58 PM PDT 24
Peak memory 222624 kb
Host smart-4a8a0084-8469-44a2-bab4-6048fc9343f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2927028953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2927028953
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2359676146
Short name T530
Test name
Test status
Simulation time 5888738066 ps
CPU time 19.06 seconds
Started Jun 05 05:40:46 PM PDT 24
Finished Jun 05 05:41:06 PM PDT 24
Peak memory 217004 kb
Host smart-a6adbfdc-06fd-462e-aa12-2e86ab151b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359676146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2359676146
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.515072789
Short name T701
Test name
Test status
Simulation time 476016813 ps
CPU time 2.52 seconds
Started Jun 05 05:40:43 PM PDT 24
Finished Jun 05 05:40:47 PM PDT 24
Peak memory 216748 kb
Host smart-171fa269-7f3f-4adb-bb00-59b16aa97f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515072789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.515072789
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4281399357
Short name T859
Test name
Test status
Simulation time 335995734 ps
CPU time 3.58 seconds
Started Jun 05 05:40:46 PM PDT 24
Finished Jun 05 05:40:51 PM PDT 24
Peak memory 216840 kb
Host smart-c55ae5c5-6822-40df-90eb-81c138423bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281399357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4281399357
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.298139987
Short name T342
Test name
Test status
Simulation time 11370417 ps
CPU time 0.72 seconds
Started Jun 05 05:40:45 PM PDT 24
Finished Jun 05 05:40:46 PM PDT 24
Peak memory 205948 kb
Host smart-0de462c7-9873-4a01-8e91-784bab508d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298139987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.298139987
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2250628587
Short name T855
Test name
Test status
Simulation time 833910121 ps
CPU time 5.08 seconds
Started Jun 05 05:40:50 PM PDT 24
Finished Jun 05 05:40:56 PM PDT 24
Peak memory 233204 kb
Host smart-ab6ae3a2-318f-40d5-9470-cc17cd2bc816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250628587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2250628587
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1132896261
Short name T486
Test name
Test status
Simulation time 15872312 ps
CPU time 0.74 seconds
Started Jun 05 05:40:52 PM PDT 24
Finished Jun 05 05:40:53 PM PDT 24
Peak memory 205732 kb
Host smart-96738ddd-487d-488b-906e-beefce51d768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132896261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
132896261
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.675382331
Short name T550
Test name
Test status
Simulation time 848481444 ps
CPU time 6.61 seconds
Started Jun 05 05:40:53 PM PDT 24
Finished Jun 05 05:41:00 PM PDT 24
Peak memory 224952 kb
Host smart-a9ef6a9e-3b81-4aeb-a334-c1b1c76fd0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675382331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.675382331
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3414783900
Short name T868
Test name
Test status
Simulation time 70006222 ps
CPU time 0.8 seconds
Started Jun 05 05:41:01 PM PDT 24
Finished Jun 05 05:41:03 PM PDT 24
Peak memory 206860 kb
Host smart-c2cf14d2-d47a-4e62-99a5-467cabc0a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414783900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3414783900
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1515927649
Short name T262
Test name
Test status
Simulation time 5049515087 ps
CPU time 68.4 seconds
Started Jun 05 05:40:50 PM PDT 24
Finished Jun 05 05:41:59 PM PDT 24
Peak memory 256768 kb
Host smart-3ecbf8e9-fe6a-4643-920b-de9f078c0bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515927649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1515927649
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2700991671
Short name T64
Test name
Test status
Simulation time 38272800464 ps
CPU time 86.79 seconds
Started Jun 05 05:40:52 PM PDT 24
Finished Jun 05 05:42:20 PM PDT 24
Peak memory 254544 kb
Host smart-5f0a46e8-802c-4729-8e30-53712cc50ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700991671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2700991671
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1855781792
Short name T406
Test name
Test status
Simulation time 1093142365 ps
CPU time 21.23 seconds
Started Jun 05 05:40:49 PM PDT 24
Finished Jun 05 05:41:11 PM PDT 24
Peak memory 239940 kb
Host smart-90cd5d03-32e5-41d2-9b61-fa6b8928750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855781792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1855781792
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1072830260
Short name T399
Test name
Test status
Simulation time 1640103372 ps
CPU time 15.84 seconds
Started Jun 05 05:40:52 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 233132 kb
Host smart-8f41b0e6-df83-4845-a185-f5c2452f7f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072830260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1072830260
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3858511624
Short name T836
Test name
Test status
Simulation time 12434649837 ps
CPU time 10.09 seconds
Started Jun 05 05:40:50 PM PDT 24
Finished Jun 05 05:41:01 PM PDT 24
Peak memory 241352 kb
Host smart-960d8a0c-508d-4781-a112-b5acb94d1674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858511624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3858511624
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.17778083
Short name T717
Test name
Test status
Simulation time 15914022 ps
CPU time 1.06 seconds
Started Jun 05 05:41:01 PM PDT 24
Finished Jun 05 05:41:04 PM PDT 24
Peak memory 218208 kb
Host smart-766a69c1-49a0-4c91-b184-935b08630179
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17778083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.17778083
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3431780999
Short name T560
Test name
Test status
Simulation time 3652311460 ps
CPU time 19.59 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:41:11 PM PDT 24
Peak memory 241312 kb
Host smart-0f923402-07b3-4437-8a9c-1e90c704841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431780999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3431780999
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2666874855
Short name T155
Test name
Test status
Simulation time 2299644421 ps
CPU time 8.69 seconds
Started Jun 05 05:40:52 PM PDT 24
Finished Jun 05 05:41:02 PM PDT 24
Peak memory 225024 kb
Host smart-a08ae04e-875a-4ed2-acfe-d41ecece2363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666874855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2666874855
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1618922982
Short name T901
Test name
Test status
Simulation time 169813635 ps
CPU time 3.37 seconds
Started Jun 05 05:40:50 PM PDT 24
Finished Jun 05 05:40:54 PM PDT 24
Peak memory 222820 kb
Host smart-e892ca27-d0ae-4231-94bb-cba7fbaf572b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1618922982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1618922982
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2056809098
Short name T63
Test name
Test status
Simulation time 233061470 ps
CPU time 1.02 seconds
Started Jun 05 05:40:54 PM PDT 24
Finished Jun 05 05:40:55 PM PDT 24
Peak memory 235208 kb
Host smart-308095a2-184d-427e-ac4a-325364d25bbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056809098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2056809098
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.864915728
Short name T528
Test name
Test status
Simulation time 4503657681 ps
CPU time 27.2 seconds
Started Jun 05 05:40:52 PM PDT 24
Finished Jun 05 05:41:20 PM PDT 24
Peak memory 225136 kb
Host smart-23d9f056-5aaa-4788-8143-af7921677f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864915728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.864915728
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1114775074
Short name T376
Test name
Test status
Simulation time 9303094772 ps
CPU time 49.69 seconds
Started Jun 05 05:40:53 PM PDT 24
Finished Jun 05 05:41:43 PM PDT 24
Peak memory 216828 kb
Host smart-2ee13cb7-784c-458d-b8e3-72291e33440e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114775074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1114775074
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2790911153
Short name T304
Test name
Test status
Simulation time 3334472679 ps
CPU time 2.29 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:40:53 PM PDT 24
Peak memory 208380 kb
Host smart-c0a19bb7-04ed-45f8-a0c1-5057c1b24ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790911153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2790911153
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1333930249
Short name T332
Test name
Test status
Simulation time 243609528 ps
CPU time 1.13 seconds
Started Jun 05 05:40:48 PM PDT 24
Finished Jun 05 05:40:50 PM PDT 24
Peak memory 208292 kb
Host smart-5af0fc56-196c-4c3c-8419-6e13ed3f1f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333930249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1333930249
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1788997206
Short name T754
Test name
Test status
Simulation time 25194682 ps
CPU time 0.83 seconds
Started Jun 05 05:40:50 PM PDT 24
Finished Jun 05 05:40:52 PM PDT 24
Peak memory 206252 kb
Host smart-9525da2a-13e0-49e3-a7fa-ecb179cb630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788997206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1788997206
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.747539870
Short name T510
Test name
Test status
Simulation time 6725256847 ps
CPU time 7.19 seconds
Started Jun 05 05:40:49 PM PDT 24
Finished Jun 05 05:40:57 PM PDT 24
Peak memory 225012 kb
Host smart-d0ea08fd-af3b-499a-a473-c83730c71030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747539870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.747539870
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2071636271
Short name T86
Test name
Test status
Simulation time 99281301 ps
CPU time 3.06 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:41:31 PM PDT 24
Peak memory 224968 kb
Host smart-5afc6136-936c-4b20-961b-f2411cdad61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071636271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2071636271
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2372482204
Short name T621
Test name
Test status
Simulation time 22847051 ps
CPU time 0.79 seconds
Started Jun 05 05:41:31 PM PDT 24
Finished Jun 05 05:41:32 PM PDT 24
Peak memory 206944 kb
Host smart-3f8077d4-c403-46a6-a027-7fdea5713b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372482204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2372482204
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.303709322
Short name T922
Test name
Test status
Simulation time 19424745128 ps
CPU time 152.14 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:44:01 PM PDT 24
Peak memory 249628 kb
Host smart-5984739e-eb47-4c38-9bdc-25afeeb4d338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303709322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.303709322
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3670489079
Short name T68
Test name
Test status
Simulation time 29108174494 ps
CPU time 72.03 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 241424 kb
Host smart-b26fb042-e58a-44cd-9a5a-c1267fdf88f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670489079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3670489079
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3287908401
Short name T165
Test name
Test status
Simulation time 63028230401 ps
CPU time 637.27 seconds
Started Jun 05 05:41:30 PM PDT 24
Finished Jun 05 05:52:08 PM PDT 24
Peak memory 265740 kb
Host smart-c7136131-0da4-43ca-a694-f76f86a7f254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287908401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3287908401
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2167082485
Short name T4
Test name
Test status
Simulation time 4296374475 ps
CPU time 17.36 seconds
Started Jun 05 05:41:31 PM PDT 24
Finished Jun 05 05:41:49 PM PDT 24
Peak memory 241548 kb
Host smart-ba45103b-2e9f-4768-adeb-64420b3780f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167082485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2167082485
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.124138849
Short name T663
Test name
Test status
Simulation time 259760153 ps
CPU time 5.2 seconds
Started Jun 05 05:41:25 PM PDT 24
Finished Jun 05 05:41:31 PM PDT 24
Peak memory 224900 kb
Host smart-7bcde759-a0b8-4363-9960-1752a08d6efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124138849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.124138849
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1151819544
Short name T396
Test name
Test status
Simulation time 553041342 ps
CPU time 3.45 seconds
Started Jun 05 05:41:30 PM PDT 24
Finished Jun 05 05:41:34 PM PDT 24
Peak memory 233152 kb
Host smart-21e0e932-9c77-480d-9147-0b9ba00e4c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151819544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1151819544
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1160955337
Short name T869
Test name
Test status
Simulation time 88599780 ps
CPU time 1.08 seconds
Started Jun 05 05:41:21 PM PDT 24
Finished Jun 05 05:41:23 PM PDT 24
Peak memory 217052 kb
Host smart-07940be5-8edf-4d68-9ace-c42144aa6547
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160955337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1160955337
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3115395434
Short name T341
Test name
Test status
Simulation time 346446383 ps
CPU time 5.83 seconds
Started Jun 05 05:41:21 PM PDT 24
Finished Jun 05 05:41:28 PM PDT 24
Peak memory 241188 kb
Host smart-6a013053-2d17-44a1-9daf-273a66e8bf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115395434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3115395434
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.787438371
Short name T455
Test name
Test status
Simulation time 15166796487 ps
CPU time 18.51 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:41:38 PM PDT 24
Peak memory 240496 kb
Host smart-7847c0d9-c5f5-4ae4-a84d-af2d1daae986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787438371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.787438371
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2625328580
Short name T971
Test name
Test status
Simulation time 3518373319 ps
CPU time 12.7 seconds
Started Jun 05 05:41:31 PM PDT 24
Finished Jun 05 05:41:44 PM PDT 24
Peak memory 223036 kb
Host smart-b380b801-7143-48fe-b076-c769b54fdc57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2625328580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2625328580
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.181696292
Short name T438
Test name
Test status
Simulation time 393944270 ps
CPU time 2.02 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:41:22 PM PDT 24
Peak memory 216792 kb
Host smart-794e5d2b-489d-4d74-abca-a8a1dacdca2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181696292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.181696292
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1961207913
Short name T310
Test name
Test status
Simulation time 124182117434 ps
CPU time 25.68 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:41:46 PM PDT 24
Peak memory 216728 kb
Host smart-a397bf2b-b631-4a6e-8def-d857215425b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961207913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1961207913
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.132984797
Short name T581
Test name
Test status
Simulation time 435260103 ps
CPU time 1.93 seconds
Started Jun 05 05:41:32 PM PDT 24
Finished Jun 05 05:41:35 PM PDT 24
Peak memory 208620 kb
Host smart-f573e74d-c6c6-410d-8fcb-a87210bc32a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132984797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.132984797
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.923401146
Short name T466
Test name
Test status
Simulation time 212677499 ps
CPU time 0.79 seconds
Started Jun 05 05:41:21 PM PDT 24
Finished Jun 05 05:41:22 PM PDT 24
Peak memory 206244 kb
Host smart-8141548c-79cc-492f-95ff-b87bd02c68e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923401146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.923401146
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1489029221
Short name T188
Test name
Test status
Simulation time 18243552185 ps
CPU time 30.66 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:41:59 PM PDT 24
Peak memory 233244 kb
Host smart-9a87c70e-f8be-440c-870c-88c8df93ec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489029221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1489029221
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2151829800
Short name T301
Test name
Test status
Simulation time 35915606 ps
CPU time 0.71 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:41:31 PM PDT 24
Peak memory 204964 kb
Host smart-ca9ce61c-f6ee-44dd-b306-4b405c3ccdbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151829800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2151829800
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2279470622
Short name T463
Test name
Test status
Simulation time 95970684 ps
CPU time 2.88 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:32 PM PDT 24
Peak memory 233328 kb
Host smart-2812f432-abe6-4b30-8400-f3a471955ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279470622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2279470622
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4116115766
Short name T414
Test name
Test status
Simulation time 14418526 ps
CPU time 0.78 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:30 PM PDT 24
Peak memory 206952 kb
Host smart-c094ef6c-43ca-4d56-a30c-d7dc2c74e0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116115766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4116115766
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1127660676
Short name T659
Test name
Test status
Simulation time 3977787030 ps
CPU time 24.64 seconds
Started Jun 05 05:41:24 PM PDT 24
Finished Jun 05 05:41:49 PM PDT 24
Peak memory 218268 kb
Host smart-57a1f180-85d4-44fc-8121-513965ad04c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127660676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1127660676
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1120325649
Short name T638
Test name
Test status
Simulation time 3348575988 ps
CPU time 14.49 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:41:45 PM PDT 24
Peak memory 233300 kb
Host smart-f1b32fe6-73be-4d50-9a7f-d3d60a7f3d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120325649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1120325649
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3939872463
Short name T281
Test name
Test status
Simulation time 1282901223 ps
CPU time 9.49 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 241352 kb
Host smart-6bba572a-e824-40b5-8b82-40223e0103ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939872463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3939872463
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3336684606
Short name T512
Test name
Test status
Simulation time 1920059790 ps
CPU time 3.35 seconds
Started Jun 05 05:41:25 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 224920 kb
Host smart-c93ffdcd-2902-448d-9131-a17f1637fef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336684606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3336684606
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2329140258
Short name T322
Test name
Test status
Simulation time 203232069 ps
CPU time 2.42 seconds
Started Jun 05 05:41:26 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 223840 kb
Host smart-d0afe40b-af3b-4734-9a63-9bf47484fd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329140258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2329140258
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1052662327
Short name T683
Test name
Test status
Simulation time 11221112751 ps
CPU time 29.43 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:42:00 PM PDT 24
Peak memory 233148 kb
Host smart-0e8151d1-4e2a-42c0-bef5-5981004297ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052662327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1052662327
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2482908076
Short name T161
Test name
Test status
Simulation time 2875245035 ps
CPU time 10.83 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 257004 kb
Host smart-90c4391b-b184-4aec-95c7-ac4c95d555d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482908076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2482908076
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1287900620
Short name T519
Test name
Test status
Simulation time 919227833 ps
CPU time 4.67 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:41:32 PM PDT 24
Peak memory 222972 kb
Host smart-8c67bb92-35c7-451b-ba37-1a1c49bae58d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1287900620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1287900620
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3301325094
Short name T6
Test name
Test status
Simulation time 135878647 ps
CPU time 0.96 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:30 PM PDT 24
Peak memory 207104 kb
Host smart-47685f0d-26ea-4189-8139-092e1c237e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301325094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3301325094
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1146264367
Short name T286
Test name
Test status
Simulation time 7451823403 ps
CPU time 45.37 seconds
Started Jun 05 05:41:26 PM PDT 24
Finished Jun 05 05:42:12 PM PDT 24
Peak memory 217080 kb
Host smart-32b02ff3-fc68-4894-9b4c-5baa718b7fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146264367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1146264367
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.339704848
Short name T9
Test name
Test status
Simulation time 1872044627 ps
CPU time 3.63 seconds
Started Jun 05 05:41:26 PM PDT 24
Finished Jun 05 05:41:31 PM PDT 24
Peak memory 216696 kb
Host smart-cfe7c0de-5d76-4342-88df-115b3be9b2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339704848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.339704848
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.891989536
Short name T295
Test name
Test status
Simulation time 56648080 ps
CPU time 1.7 seconds
Started Jun 05 05:41:26 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 216864 kb
Host smart-ab362bc7-d9da-4527-9a8b-4812955fefbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891989536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.891989536
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2479952703
Short name T358
Test name
Test status
Simulation time 50245693 ps
CPU time 0.71 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:30 PM PDT 24
Peak memory 206196 kb
Host smart-3c9f24b1-52cc-48a7-9a50-901bf7b1bfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479952703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2479952703
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3215605434
Short name T593
Test name
Test status
Simulation time 524105914 ps
CPU time 6.38 seconds
Started Jun 05 05:41:26 PM PDT 24
Finished Jun 05 05:41:33 PM PDT 24
Peak memory 224968 kb
Host smart-af8a0140-b2ea-457e-9948-b5f987cfda09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215605434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3215605434
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1180525216
Short name T691
Test name
Test status
Simulation time 49443694 ps
CPU time 0.73 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:30 PM PDT 24
Peak memory 205088 kb
Host smart-d73ed026-4928-4e59-86d3-2d350bf76010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180525216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1180525216
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.224047684
Short name T437
Test name
Test status
Simulation time 4517439329 ps
CPU time 22.02 seconds
Started Jun 05 05:41:32 PM PDT 24
Finished Jun 05 05:41:55 PM PDT 24
Peak memory 224988 kb
Host smart-6d032c5f-6a08-4fcc-bec2-4cade9fd4b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224047684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.224047684
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1307455625
Short name T365
Test name
Test status
Simulation time 25433528 ps
CPU time 0.84 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 205904 kb
Host smart-0f0c470b-a6ce-405a-a4c7-90482da63d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307455625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1307455625
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.597434641
Short name T567
Test name
Test status
Simulation time 8487990555 ps
CPU time 35.98 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 249800 kb
Host smart-776f41f0-4bf9-4020-9cf8-06b3986dcf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597434641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.597434641
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.134491187
Short name T824
Test name
Test status
Simulation time 108762337301 ps
CPU time 269.54 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:45:57 PM PDT 24
Peak memory 239008 kb
Host smart-46bb7ac0-ecc0-430c-9927-67aa1df06979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134491187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.134491187
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4027775071
Short name T597
Test name
Test status
Simulation time 593464748 ps
CPU time 10.79 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:40 PM PDT 24
Peak memory 233436 kb
Host smart-334b43da-6cbe-46d0-8ad1-b8d4391281d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027775071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4027775071
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1500019108
Short name T847
Test name
Test status
Simulation time 5110866962 ps
CPU time 23.52 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:41:53 PM PDT 24
Peak memory 233200 kb
Host smart-76589c92-a2c5-4011-8ae8-6228f94e079a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500019108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1500019108
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1700436595
Short name T821
Test name
Test status
Simulation time 17348544246 ps
CPU time 29.77 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:59 PM PDT 24
Peak memory 228708 kb
Host smart-67ccc6c0-fd20-44cf-8dcf-a34a4db68b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700436595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1700436595
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2861078923
Short name T21
Test name
Test status
Simulation time 52776618 ps
CPU time 1.03 seconds
Started Jun 05 05:41:30 PM PDT 24
Finished Jun 05 05:41:31 PM PDT 24
Peak memory 217068 kb
Host smart-0ff2e345-92d4-4e5d-9bca-4e672d2d7e37
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861078923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2861078923
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.119742114
Short name T861
Test name
Test status
Simulation time 216064442 ps
CPU time 2.4 seconds
Started Jun 05 05:41:26 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 225060 kb
Host smart-9c45d769-519b-45b4-8705-a2746066278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119742114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.119742114
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.38568875
Short name T831
Test name
Test status
Simulation time 1355184132 ps
CPU time 10.02 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 233136 kb
Host smart-605b39de-ed58-4122-93dc-93ef03d2750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38568875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.38568875
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.293020205
Short name T811
Test name
Test status
Simulation time 5268480903 ps
CPU time 12.24 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:42 PM PDT 24
Peak memory 220884 kb
Host smart-e3dbf409-7242-4909-856b-ba11ffa45ae6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=293020205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.293020205
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1675494014
Short name T146
Test name
Test status
Simulation time 81538759451 ps
CPU time 93.28 seconds
Started Jun 05 05:41:26 PM PDT 24
Finished Jun 05 05:43:00 PM PDT 24
Peak memory 256560 kb
Host smart-4953bb0a-5c91-482e-bb29-93ae6978786d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675494014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1675494014
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3599548506
Short name T498
Test name
Test status
Simulation time 6248393075 ps
CPU time 33.65 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 216796 kb
Host smart-ff47df57-468b-4f22-91db-903a8bcdcfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599548506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3599548506
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.403706807
Short name T633
Test name
Test status
Simulation time 1248015209 ps
CPU time 4.78 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:41:35 PM PDT 24
Peak memory 216744 kb
Host smart-8abdec19-6e83-4247-9330-3080b3b1a1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403706807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.403706807
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.114226821
Short name T640
Test name
Test status
Simulation time 131677778 ps
CPU time 5.09 seconds
Started Jun 05 05:41:32 PM PDT 24
Finished Jun 05 05:41:37 PM PDT 24
Peak memory 216816 kb
Host smart-da8621c4-d128-4a8e-ab3b-6520e99d86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114226821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.114226821
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.333472775
Short name T397
Test name
Test status
Simulation time 34310361 ps
CPU time 0.78 seconds
Started Jun 05 05:41:31 PM PDT 24
Finished Jun 05 05:41:33 PM PDT 24
Peak memory 206404 kb
Host smart-0c824d1e-32b0-4fb8-b7a5-a1662779ca20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333472775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.333472775
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1929518406
Short name T966
Test name
Test status
Simulation time 320741639 ps
CPU time 2.17 seconds
Started Jun 05 05:41:29 PM PDT 24
Finished Jun 05 05:41:32 PM PDT 24
Peak memory 222728 kb
Host smart-722764ac-6a01-4c12-bacf-97ff46d82a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929518406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1929518406
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.226304671
Short name T518
Test name
Test status
Simulation time 14800751 ps
CPU time 0.76 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:41:36 PM PDT 24
Peak memory 205108 kb
Host smart-ee72d014-18f3-4781-868f-a8131345c16e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226304671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.226304671
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4019357696
Short name T680
Test name
Test status
Simulation time 1232714019 ps
CPU time 6.94 seconds
Started Jun 05 05:41:37 PM PDT 24
Finished Jun 05 05:41:45 PM PDT 24
Peak memory 224980 kb
Host smart-58c3456a-00b0-4f9c-8b89-e74282a136b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019357696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4019357696
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2849620056
Short name T812
Test name
Test status
Simulation time 39737680 ps
CPU time 0.76 seconds
Started Jun 05 05:41:28 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 205880 kb
Host smart-4fefe2d6-0f04-48d5-99d2-1f0ec15991d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849620056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2849620056
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1196167929
Short name T763
Test name
Test status
Simulation time 26214004809 ps
CPU time 189.71 seconds
Started Jun 05 05:41:37 PM PDT 24
Finished Jun 05 05:44:48 PM PDT 24
Peak memory 254012 kb
Host smart-4301539d-f471-418e-ba42-aa7e795caa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196167929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1196167929
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3466834685
Short name T815
Test name
Test status
Simulation time 49226767835 ps
CPU time 104.66 seconds
Started Jun 05 05:41:35 PM PDT 24
Finished Jun 05 05:43:20 PM PDT 24
Peak memory 241536 kb
Host smart-b3476709-ba47-42a3-84ed-5ed5b0d84be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466834685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3466834685
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4016860113
Short name T718
Test name
Test status
Simulation time 8286430298 ps
CPU time 36.81 seconds
Started Jun 05 05:41:32 PM PDT 24
Finished Jun 05 05:42:09 PM PDT 24
Peak memory 249704 kb
Host smart-188b7974-ea0a-476e-b462-b16eafde6e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016860113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4016860113
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2593526119
Short name T558
Test name
Test status
Simulation time 978657598 ps
CPU time 3.01 seconds
Started Jun 05 05:41:35 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 224868 kb
Host smart-d9b1c02f-f7e1-4da1-bf03-f967821cec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593526119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2593526119
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4248648858
Short name T186
Test name
Test status
Simulation time 21298635798 ps
CPU time 48.56 seconds
Started Jun 05 05:41:36 PM PDT 24
Finished Jun 05 05:42:25 PM PDT 24
Peak memory 233204 kb
Host smart-755b7e7b-6d28-4a28-8c9e-0e6747bb92f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248648858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4248648858
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1699423002
Short name T598
Test name
Test status
Simulation time 24304523 ps
CPU time 1.01 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 217088 kb
Host smart-155f78fe-27ca-4c77-b21e-df3c319d944f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699423002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1699423002
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4011788146
Short name T51
Test name
Test status
Simulation time 4263778615 ps
CPU time 10.64 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:41:45 PM PDT 24
Peak memory 233212 kb
Host smart-70ca7f0e-39f9-486a-aa2a-9ce3e7ef372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011788146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4011788146
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3069544433
Short name T629
Test name
Test status
Simulation time 649562450 ps
CPU time 5.56 seconds
Started Jun 05 05:41:43 PM PDT 24
Finished Jun 05 05:41:49 PM PDT 24
Peak memory 233136 kb
Host smart-e4dbff39-7a8c-4094-bf9f-140dd5fd7be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069544433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3069544433
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2674534332
Short name T475
Test name
Test status
Simulation time 151079049 ps
CPU time 4.74 seconds
Started Jun 05 05:41:37 PM PDT 24
Finished Jun 05 05:41:42 PM PDT 24
Peak memory 223288 kb
Host smart-0136404a-018c-436f-a4eb-491ac60828d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2674534332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2674534332
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3670536448
Short name T619
Test name
Test status
Simulation time 5255928090 ps
CPU time 132.92 seconds
Started Jun 05 05:41:33 PM PDT 24
Finished Jun 05 05:43:47 PM PDT 24
Peak memory 266104 kb
Host smart-b9c50286-3f81-4348-a6c7-60570c2ca22d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670536448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3670536448
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3383691180
Short name T852
Test name
Test status
Simulation time 60808336 ps
CPU time 0.72 seconds
Started Jun 05 05:41:33 PM PDT 24
Finished Jun 05 05:41:34 PM PDT 24
Peak memory 206076 kb
Host smart-2fbc6c49-136a-4242-b9f4-39a3af0add3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383691180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3383691180
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3229369575
Short name T548
Test name
Test status
Simulation time 1534027575 ps
CPU time 2.97 seconds
Started Jun 05 05:41:27 PM PDT 24
Finished Jun 05 05:41:31 PM PDT 24
Peak memory 216516 kb
Host smart-21fc8353-3b70-4a15-a7bc-afe5c40a18d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229369575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3229369575
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2697585795
Short name T409
Test name
Test status
Simulation time 73704246 ps
CPU time 1 seconds
Started Jun 05 05:41:37 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 207392 kb
Host smart-3995bad1-9e8e-4bc4-8799-09ecf0af2eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697585795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2697585795
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2539023190
Short name T716
Test name
Test status
Simulation time 215233477 ps
CPU time 1.05 seconds
Started Jun 05 05:41:37 PM PDT 24
Finished Jun 05 05:41:38 PM PDT 24
Peak memory 206660 kb
Host smart-6a4a4f7e-fec4-430b-8c8a-b19bb84b5764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539023190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2539023190
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2047046739
Short name T248
Test name
Test status
Simulation time 2870837959 ps
CPU time 6.37 seconds
Started Jun 05 05:41:35 PM PDT 24
Finished Jun 05 05:41:42 PM PDT 24
Peak memory 233208 kb
Host smart-b2b55c3a-905d-4f53-a39a-cd3b8abe9ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047046739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2047046739
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1265541830
Short name T28
Test name
Test status
Simulation time 14324383 ps
CPU time 0.8 seconds
Started Jun 05 05:41:35 PM PDT 24
Finished Jun 05 05:41:36 PM PDT 24
Peak memory 205808 kb
Host smart-6645d386-fb87-4d0b-914d-c41e06bf57a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265541830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1265541830
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2637123232
Short name T470
Test name
Test status
Simulation time 51386866 ps
CPU time 2.54 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:41:38 PM PDT 24
Peak memory 224988 kb
Host smart-5f26492e-b030-4364-bab7-7b0ae72bb712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637123232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2637123232
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3963824774
Short name T941
Test name
Test status
Simulation time 63671460 ps
CPU time 0.81 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:41 PM PDT 24
Peak memory 206948 kb
Host smart-a3e397cd-561b-4121-ab05-4a541a7183d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963824774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3963824774
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.955270810
Short name T451
Test name
Test status
Simulation time 63727035939 ps
CPU time 213.33 seconds
Started Jun 05 05:41:35 PM PDT 24
Finished Jun 05 05:45:09 PM PDT 24
Peak memory 237224 kb
Host smart-ab69d7a5-a0cb-4f92-954a-3d3ed6569f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955270810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.955270810
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2904870934
Short name T894
Test name
Test status
Simulation time 15677560310 ps
CPU time 126.52 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:43:47 PM PDT 24
Peak memory 249724 kb
Host smart-50e89a49-25a1-4766-80d3-d82e9c9807d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904870934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2904870934
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3279405727
Short name T364
Test name
Test status
Simulation time 1186747300 ps
CPU time 23.65 seconds
Started Jun 05 05:41:33 PM PDT 24
Finished Jun 05 05:41:58 PM PDT 24
Peak memory 239860 kb
Host smart-0c896e86-c48a-4873-870f-94a4aad38cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279405727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3279405727
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1355869050
Short name T471
Test name
Test status
Simulation time 1686677037 ps
CPU time 19.01 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:41:54 PM PDT 24
Peak memory 224956 kb
Host smart-cf6642be-1507-41eb-be1c-d212690acd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355869050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1355869050
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3351362773
Short name T657
Test name
Test status
Simulation time 7004300407 ps
CPU time 43.91 seconds
Started Jun 05 05:41:31 PM PDT 24
Finished Jun 05 05:42:16 PM PDT 24
Peak memory 238788 kb
Host smart-32a14479-2776-4e80-a3b4-17fc00d8b76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351362773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3351362773
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.689169358
Short name T796
Test name
Test status
Simulation time 210989159 ps
CPU time 1.04 seconds
Started Jun 05 05:41:36 PM PDT 24
Finished Jun 05 05:41:37 PM PDT 24
Peak memory 218308 kb
Host smart-37f5390c-88ad-472f-bfb3-b22846cc2a7d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689169358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.689169358
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3753651703
Short name T476
Test name
Test status
Simulation time 5104254628 ps
CPU time 14.34 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:55 PM PDT 24
Peak memory 224916 kb
Host smart-16c80573-a292-46d0-9ec6-3e42227a479b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753651703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3753651703
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.82920435
Short name T690
Test name
Test status
Simulation time 3589446092 ps
CPU time 12.62 seconds
Started Jun 05 05:41:36 PM PDT 24
Finished Jun 05 05:41:49 PM PDT 24
Peak memory 225020 kb
Host smart-8951310d-d874-467b-94f5-5b7f06e8f016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82920435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.82920435
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2930087330
Short name T746
Test name
Test status
Simulation time 5900713653 ps
CPU time 12.11 seconds
Started Jun 05 05:41:38 PM PDT 24
Finished Jun 05 05:41:51 PM PDT 24
Peak memory 216892 kb
Host smart-6a257ad2-9855-4d6b-ac01-6b0860a8a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930087330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2930087330
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2984604238
Short name T307
Test name
Test status
Simulation time 585436543 ps
CPU time 4.01 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 216784 kb
Host smart-31b199fc-36ab-4ed8-a892-514b98db952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984604238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2984604238
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.916137935
Short name T908
Test name
Test status
Simulation time 43901560 ps
CPU time 0.85 seconds
Started Jun 05 05:41:32 PM PDT 24
Finished Jun 05 05:41:34 PM PDT 24
Peak memory 206328 kb
Host smart-4195b2d9-068b-45bf-999d-2ff999fce1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916137935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.916137935
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.458475649
Short name T818
Test name
Test status
Simulation time 106843139 ps
CPU time 0.94 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:41:36 PM PDT 24
Peak memory 206264 kb
Host smart-676ff207-6af4-4bb5-8b06-a5f0bf8a3820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458475649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.458475649
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2218004408
Short name T898
Test name
Test status
Simulation time 61880872 ps
CPU time 2.15 seconds
Started Jun 05 05:41:37 PM PDT 24
Finished Jun 05 05:41:40 PM PDT 24
Peak memory 223712 kb
Host smart-7886b81e-8c12-4f03-a9f3-aa53790b578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218004408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2218004408
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2605659308
Short name T428
Test name
Test status
Simulation time 53671496 ps
CPU time 0.76 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:52 PM PDT 24
Peak memory 206080 kb
Host smart-6acf04ce-70a3-4bbc-98b0-23be366817c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605659308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2605659308
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.439936654
Short name T698
Test name
Test status
Simulation time 302761166 ps
CPU time 2.44 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:43 PM PDT 24
Peak memory 233208 kb
Host smart-1be53dc5-f179-4451-8c2f-e8758cc21813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439936654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.439936654
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3135926864
Short name T934
Test name
Test status
Simulation time 18493053 ps
CPU time 0.78 seconds
Started Jun 05 05:41:34 PM PDT 24
Finished Jun 05 05:41:35 PM PDT 24
Peak memory 205900 kb
Host smart-2d8d2538-662a-462f-99a3-ec09a10aaab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135926864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3135926864
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.486834620
Short name T925
Test name
Test status
Simulation time 78303496236 ps
CPU time 276.35 seconds
Started Jun 05 05:41:43 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 255100 kb
Host smart-6ef39547-474a-4bce-a1a3-1d2afa0b272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486834620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.486834620
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.995364828
Short name T832
Test name
Test status
Simulation time 97277768482 ps
CPU time 193.19 seconds
Started Jun 05 05:41:42 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 254144 kb
Host smart-809ef4b1-dcf1-4b6c-8751-55f77e149a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995364828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.995364828
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3215458898
Short name T30
Test name
Test status
Simulation time 161713886236 ps
CPU time 571.51 seconds
Started Jun 05 05:41:41 PM PDT 24
Finished Jun 05 05:51:13 PM PDT 24
Peak memory 274296 kb
Host smart-06e59ed5-2346-4e92-9a64-5407e65de8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215458898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3215458898
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1690714202
Short name T415
Test name
Test status
Simulation time 76552647 ps
CPU time 2.96 seconds
Started Jun 05 05:41:41 PM PDT 24
Finished Jun 05 05:41:44 PM PDT 24
Peak memory 233168 kb
Host smart-f46bec8f-af24-4d5b-8a0b-f0ca522b85d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690714202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1690714202
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3728494411
Short name T886
Test name
Test status
Simulation time 35426623 ps
CPU time 2.51 seconds
Started Jun 05 05:41:37 PM PDT 24
Finished Jun 05 05:41:41 PM PDT 24
Peak memory 232968 kb
Host smart-36201f4a-961e-4820-94da-7fa7f9c42e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728494411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3728494411
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1297904342
Short name T67
Test name
Test status
Simulation time 454089777 ps
CPU time 4.99 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:55 PM PDT 24
Peak memory 219100 kb
Host smart-2065f798-bd9a-41e7-bbc2-77243b5ca72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297904342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1297904342
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1865589393
Short name T23
Test name
Test status
Simulation time 105329221 ps
CPU time 1.04 seconds
Started Jun 05 05:41:36 PM PDT 24
Finished Jun 05 05:41:38 PM PDT 24
Peak memory 217268 kb
Host smart-1384cd0d-29cd-4e78-ade4-f0d8e9d8cde0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865589393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1865589393
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1116893991
Short name T610
Test name
Test status
Simulation time 31181516566 ps
CPU time 19.8 seconds
Started Jun 05 05:41:44 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 233200 kb
Host smart-33357f1d-e075-4644-bc3b-e41321cf7c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116893991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1116893991
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1719155280
Short name T413
Test name
Test status
Simulation time 9463164786 ps
CPU time 14.71 seconds
Started Jun 05 05:41:36 PM PDT 24
Finished Jun 05 05:41:51 PM PDT 24
Peak memory 233240 kb
Host smart-d7104be6-e969-4fd0-a722-1dd530169b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719155280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1719155280
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2119055742
Short name T976
Test name
Test status
Simulation time 888437228 ps
CPU time 3.84 seconds
Started Jun 05 05:41:42 PM PDT 24
Finished Jun 05 05:41:46 PM PDT 24
Peak memory 219720 kb
Host smart-b3764317-9427-4032-b849-0e62cc73c62a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2119055742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2119055742
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1259109763
Short name T967
Test name
Test status
Simulation time 9168954977 ps
CPU time 106.96 seconds
Started Jun 05 05:41:38 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 251532 kb
Host smart-d2f2d665-f441-4471-b144-7e752f650bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259109763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1259109763
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3085654963
Short name T577
Test name
Test status
Simulation time 16467323610 ps
CPU time 13.21 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:54 PM PDT 24
Peak memory 216988 kb
Host smart-52fcd263-5134-4884-90f2-510af60e6e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085654963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3085654963
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.322055598
Short name T605
Test name
Test status
Simulation time 3722488291 ps
CPU time 5.54 seconds
Started Jun 05 05:41:35 PM PDT 24
Finished Jun 05 05:41:41 PM PDT 24
Peak memory 216840 kb
Host smart-f332942d-05bd-4c83-ac8b-e274a64a4447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322055598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.322055598
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2455207485
Short name T557
Test name
Test status
Simulation time 3845617996 ps
CPU time 4.04 seconds
Started Jun 05 05:41:38 PM PDT 24
Finished Jun 05 05:41:43 PM PDT 24
Peak memory 217168 kb
Host smart-0fa80a87-00c8-4f93-829e-69355080c3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455207485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2455207485
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4178384845
Short name T744
Test name
Test status
Simulation time 119250184 ps
CPU time 0.76 seconds
Started Jun 05 05:41:37 PM PDT 24
Finished Jun 05 05:41:39 PM PDT 24
Peak memory 206264 kb
Host smart-9d1b3ab3-1eb1-4781-b583-b6defd8594ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178384845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4178384845
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1489308415
Short name T768
Test name
Test status
Simulation time 8754601134 ps
CPU time 29.3 seconds
Started Jun 05 05:41:42 PM PDT 24
Finished Jun 05 05:42:12 PM PDT 24
Peak memory 249248 kb
Host smart-1b058ef4-573b-49d3-8202-34d75e2d89f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489308415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1489308415
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1463268880
Short name T315
Test name
Test status
Simulation time 15865373 ps
CPU time 0.72 seconds
Started Jun 05 05:41:39 PM PDT 24
Finished Jun 05 05:41:41 PM PDT 24
Peak memory 205708 kb
Host smart-955aaa08-50fc-4818-8784-07d1d253c6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463268880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1463268880
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2782711861
Short name T533
Test name
Test status
Simulation time 1360818016 ps
CPU time 4.91 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:46 PM PDT 24
Peak memory 224932 kb
Host smart-887c2ebf-03e0-465b-9e56-3b742ce416fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782711861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2782711861
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2469277120
Short name T323
Test name
Test status
Simulation time 43956944 ps
CPU time 0.75 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:42 PM PDT 24
Peak memory 207244 kb
Host smart-2a558aab-a29b-4a2d-9f2c-2e8bd37ed030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469277120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2469277120
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4207290550
Short name T74
Test name
Test status
Simulation time 17919735781 ps
CPU time 214.94 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:45:25 PM PDT 24
Peak memory 258080 kb
Host smart-c030aebf-66a8-4da2-b0ca-a431efad1a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207290550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4207290550
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4004638496
Short name T235
Test name
Test status
Simulation time 3626976571 ps
CPU time 94.05 seconds
Started Jun 05 05:41:41 PM PDT 24
Finished Jun 05 05:43:16 PM PDT 24
Peak memory 249724 kb
Host smart-9d73400f-02e0-4cee-8a6b-b4207a0a4eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004638496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4004638496
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1235957411
Short name T664
Test name
Test status
Simulation time 2442792354 ps
CPU time 7.93 seconds
Started Jun 05 05:41:41 PM PDT 24
Finished Jun 05 05:41:50 PM PDT 24
Peak memory 233252 kb
Host smart-18d609be-105d-4cb2-aa91-4819b935db6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235957411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1235957411
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3721646847
Short name T453
Test name
Test status
Simulation time 3113745025 ps
CPU time 12.64 seconds
Started Jun 05 05:41:38 PM PDT 24
Finished Jun 05 05:41:51 PM PDT 24
Peak memory 249612 kb
Host smart-95b6afe6-cd11-4c55-ab52-e37423d1b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721646847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3721646847
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3715319287
Short name T854
Test name
Test status
Simulation time 114057764 ps
CPU time 1.16 seconds
Started Jun 05 05:41:42 PM PDT 24
Finished Jun 05 05:41:44 PM PDT 24
Peak memory 217064 kb
Host smart-26c7aa88-1270-454a-a550-9091073b46ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715319287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3715319287
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2584650397
Short name T448
Test name
Test status
Simulation time 35660863 ps
CPU time 2.23 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:43 PM PDT 24
Peak memory 232992 kb
Host smart-e80e87cb-5dc8-4ce7-9c3b-77a749de2ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584650397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2584650397
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1380889529
Short name T253
Test name
Test status
Simulation time 2019429655 ps
CPU time 7.17 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:48 PM PDT 24
Peak memory 233104 kb
Host smart-e8ce64fa-1b3a-40b7-a57f-6eebb9d43fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380889529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1380889529
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3722031994
Short name T425
Test name
Test status
Simulation time 195382594 ps
CPU time 4.23 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:45 PM PDT 24
Peak memory 222796 kb
Host smart-69f5e104-7029-45a3-ad7a-8d4e012aeb76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3722031994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3722031994
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2719566014
Short name T204
Test name
Test status
Simulation time 46597187098 ps
CPU time 435.35 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:48:57 PM PDT 24
Peak memory 266392 kb
Host smart-9a7ac642-e168-47e3-a96b-77a1667f95e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719566014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2719566014
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1109457379
Short name T713
Test name
Test status
Simulation time 4815624581 ps
CPU time 27.89 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:42:09 PM PDT 24
Peak memory 217068 kb
Host smart-d19640ef-73c7-482e-94fc-3e0375e585f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109457379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1109457379
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3563332904
Short name T434
Test name
Test status
Simulation time 1864515467 ps
CPU time 5.14 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:56 PM PDT 24
Peak memory 216696 kb
Host smart-86b2f745-2b52-43c7-9a59-bd41517d9b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563332904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3563332904
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3026208914
Short name T513
Test name
Test status
Simulation time 58954738 ps
CPU time 1.09 seconds
Started Jun 05 05:41:40 PM PDT 24
Finished Jun 05 05:41:42 PM PDT 24
Peak memory 216604 kb
Host smart-442849b9-6697-44d1-83ef-e6bb446e8356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026208914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3026208914
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2622174291
Short name T500
Test name
Test status
Simulation time 176954018 ps
CPU time 0.75 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:51 PM PDT 24
Peak memory 206064 kb
Host smart-08b483dd-4414-44ef-8e43-5eb934a8111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622174291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2622174291
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4019704413
Short name T879
Test name
Test status
Simulation time 3823340177 ps
CPU time 4.85 seconds
Started Jun 05 05:41:39 PM PDT 24
Finished Jun 05 05:41:45 PM PDT 24
Peak memory 236808 kb
Host smart-96126720-c3db-4eb5-9767-b6b04a319552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019704413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4019704413
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4152991478
Short name T329
Test name
Test status
Simulation time 43712208 ps
CPU time 0.72 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:51 PM PDT 24
Peak memory 205772 kb
Host smart-91572435-d713-455b-b24a-03709365ef03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152991478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4152991478
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2288907052
Short name T695
Test name
Test status
Simulation time 3666672847 ps
CPU time 8.4 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:42:00 PM PDT 24
Peak memory 233256 kb
Host smart-d734aaff-5e01-4d9d-8a4f-9c64ed0a2d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288907052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2288907052
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3803132070
Short name T595
Test name
Test status
Simulation time 30402685 ps
CPU time 0.81 seconds
Started Jun 05 05:41:41 PM PDT 24
Finished Jun 05 05:41:42 PM PDT 24
Peak memory 206284 kb
Host smart-bead1385-0114-4630-a0e4-7eedfa7ea1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803132070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3803132070
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1049712069
Short name T601
Test name
Test status
Simulation time 11304675062 ps
CPU time 63.09 seconds
Started Jun 05 05:41:51 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 249612 kb
Host smart-f65d69de-5f19-48db-829c-8c281cc4e920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049712069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1049712069
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2642702227
Short name T200
Test name
Test status
Simulation time 7224362204 ps
CPU time 133.97 seconds
Started Jun 05 05:41:49 PM PDT 24
Finished Jun 05 05:44:04 PM PDT 24
Peak memory 266144 kb
Host smart-ae92ce6c-09a7-4c56-a2f3-9bbb55a3a3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642702227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2642702227
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.345651944
Short name T521
Test name
Test status
Simulation time 64488359455 ps
CPU time 176.17 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:44:46 PM PDT 24
Peak memory 249992 kb
Host smart-85a3299c-9df0-4e65-b9be-8ee80117f0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345651944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.345651944
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2048603763
Short name T874
Test name
Test status
Simulation time 843701589 ps
CPU time 5.14 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:56 PM PDT 24
Peak memory 224948 kb
Host smart-f21bcd76-0a75-4cc4-b01f-fcc2b9d8dc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048603763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2048603763
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3346657629
Short name T771
Test name
Test status
Simulation time 5731382006 ps
CPU time 13.63 seconds
Started Jun 05 05:41:52 PM PDT 24
Finished Jun 05 05:42:06 PM PDT 24
Peak memory 233200 kb
Host smart-658ec30e-3125-46be-87bb-ee2f60e7a140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346657629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3346657629
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3066087091
Short name T412
Test name
Test status
Simulation time 17373246109 ps
CPU time 86.79 seconds
Started Jun 05 05:41:51 PM PDT 24
Finished Jun 05 05:43:18 PM PDT 24
Peak memory 233188 kb
Host smart-c06b85e3-3135-42ab-9ffa-44da5c903f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066087091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3066087091
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2312914731
Short name T585
Test name
Test status
Simulation time 16980546 ps
CPU time 1.03 seconds
Started Jun 05 05:41:41 PM PDT 24
Finished Jun 05 05:41:43 PM PDT 24
Peak memory 217268 kb
Host smart-82442902-df58-4c3f-93a0-b9020b9c91bd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312914731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2312914731
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3616098857
Short name T522
Test name
Test status
Simulation time 4726215213 ps
CPU time 14.04 seconds
Started Jun 05 05:41:52 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 233204 kb
Host smart-c5999a09-81e2-4d2b-848e-243c05c7a3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616098857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3616098857
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2399995599
Short name T890
Test name
Test status
Simulation time 2159464082 ps
CPU time 4.53 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:56 PM PDT 24
Peak memory 224956 kb
Host smart-cb6b01f0-6dc4-4dca-9a92-bf5b1ebdab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399995599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2399995599
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3203135018
Short name T889
Test name
Test status
Simulation time 2476766193 ps
CPU time 5.53 seconds
Started Jun 05 05:41:48 PM PDT 24
Finished Jun 05 05:41:54 PM PDT 24
Peak memory 219248 kb
Host smart-e22fa9cc-6ea7-4572-9ff9-fee658e32ebd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3203135018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3203135018
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3516643284
Short name T350
Test name
Test status
Simulation time 2827926071 ps
CPU time 15.32 seconds
Started Jun 05 05:41:52 PM PDT 24
Finished Jun 05 05:42:08 PM PDT 24
Peak memory 216864 kb
Host smart-9dd15d0f-9046-4166-a0a6-64e5c898fe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516643284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3516643284
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.462961119
Short name T320
Test name
Test status
Simulation time 1070558841 ps
CPU time 4.3 seconds
Started Jun 05 05:41:51 PM PDT 24
Finished Jun 05 05:41:56 PM PDT 24
Peak memory 216704 kb
Host smart-6fb067bb-f3de-4ac0-bcc9-e0d4a354929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462961119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.462961119
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3972849303
Short name T442
Test name
Test status
Simulation time 2277598435 ps
CPU time 3.65 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:54 PM PDT 24
Peak memory 216840 kb
Host smart-86fcdfdc-0dc8-49f5-9976-f5bf96687936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972849303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3972849303
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4136623143
Short name T313
Test name
Test status
Simulation time 34870005 ps
CPU time 0.82 seconds
Started Jun 05 05:41:51 PM PDT 24
Finished Jun 05 05:41:52 PM PDT 24
Peak memory 206240 kb
Host smart-c00c015e-8274-4223-bc09-a5cde14c6e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136623143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4136623143
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2814009036
Short name T445
Test name
Test status
Simulation time 11666748828 ps
CPU time 9.63 seconds
Started Jun 05 05:41:48 PM PDT 24
Finished Jun 05 05:41:58 PM PDT 24
Peak memory 225048 kb
Host smart-1316820f-356a-411d-87a0-15f6e13cb5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814009036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2814009036
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.54045401
Short name T504
Test name
Test status
Simulation time 12654219 ps
CPU time 0.71 seconds
Started Jun 05 05:41:48 PM PDT 24
Finished Jun 05 05:41:49 PM PDT 24
Peak memory 205124 kb
Host smart-4ea15e71-52a5-40c6-b1fb-a84fd45958be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54045401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.54045401
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.351743058
Short name T942
Test name
Test status
Simulation time 121567043 ps
CPU time 3.13 seconds
Started Jun 05 05:41:48 PM PDT 24
Finished Jun 05 05:41:52 PM PDT 24
Peak memory 233132 kb
Host smart-b2d9ff96-4dda-48a6-af02-3cd0cdce95a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351743058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.351743058
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1142667951
Short name T546
Test name
Test status
Simulation time 175915403 ps
CPU time 0.79 seconds
Started Jun 05 05:41:49 PM PDT 24
Finished Jun 05 05:41:51 PM PDT 24
Peak memory 206968 kb
Host smart-d9d72ed8-0067-49fe-a120-b9cd50862fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142667951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1142667951
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.880831164
Short name T954
Test name
Test status
Simulation time 33385329134 ps
CPU time 306.62 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:46:58 PM PDT 24
Peak memory 257528 kb
Host smart-9896d091-899a-4050-ba9b-97fc179cdba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880831164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.880831164
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2362674545
Short name T43
Test name
Test status
Simulation time 75828604170 ps
CPU time 331.44 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:47:22 PM PDT 24
Peak memory 249732 kb
Host smart-d92ac951-4891-47df-b7e8-b2fca2c16549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362674545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2362674545
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.106962874
Short name T98
Test name
Test status
Simulation time 484608429 ps
CPU time 4.06 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:55 PM PDT 24
Peak memory 232116 kb
Host smart-e41f36f8-4c5e-49cb-b141-7c18300ed309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106962874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.106962874
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3059127356
Short name T897
Test name
Test status
Simulation time 829575311 ps
CPU time 8.38 seconds
Started Jun 05 05:41:49 PM PDT 24
Finished Jun 05 05:41:58 PM PDT 24
Peak memory 224880 kb
Host smart-6226bc81-c39d-49d1-95c0-e004d03396d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059127356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3059127356
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2633136838
Short name T197
Test name
Test status
Simulation time 2505077297 ps
CPU time 9.62 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:42:01 PM PDT 24
Peak memory 224988 kb
Host smart-b8d9e221-8f76-43ef-9afd-33bca56a93d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633136838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2633136838
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1039117583
Short name T887
Test name
Test status
Simulation time 24871773 ps
CPU time 1.03 seconds
Started Jun 05 05:41:49 PM PDT 24
Finished Jun 05 05:41:51 PM PDT 24
Peak memory 217068 kb
Host smart-ac01ae54-e593-4131-8de1-2c803fe87a7b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039117583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1039117583
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1416097626
Short name T202
Test name
Test status
Simulation time 3005103504 ps
CPU time 5.64 seconds
Started Jun 05 05:41:51 PM PDT 24
Finished Jun 05 05:41:57 PM PDT 24
Peak memory 233124 kb
Host smart-ed3be715-dfeb-4700-800d-632c396f6dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416097626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1416097626
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3049701365
Short name T366
Test name
Test status
Simulation time 498585699 ps
CPU time 2.54 seconds
Started Jun 05 05:41:52 PM PDT 24
Finished Jun 05 05:41:55 PM PDT 24
Peak memory 233144 kb
Host smart-b780a771-deae-414e-943a-9456ca14d3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049701365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3049701365
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2374912782
Short name T503
Test name
Test status
Simulation time 2442545853 ps
CPU time 16.82 seconds
Started Jun 05 05:41:48 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 219744 kb
Host smart-05887e2e-942b-4772-91c9-e3df314d4bc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2374912782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2374912782
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1187255788
Short name T444
Test name
Test status
Simulation time 155574433 ps
CPU time 1 seconds
Started Jun 05 05:41:52 PM PDT 24
Finished Jun 05 05:41:53 PM PDT 24
Peak memory 207376 kb
Host smart-68a6652e-a03a-44af-888a-f75b2f2416e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187255788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1187255788
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.995042321
Short name T460
Test name
Test status
Simulation time 608125971 ps
CPU time 4.45 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:55 PM PDT 24
Peak memory 216852 kb
Host smart-2dccc375-7df4-4d4c-9cb2-5d3f6230093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995042321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.995042321
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3778640672
Short name T911
Test name
Test status
Simulation time 7466058853 ps
CPU time 22.19 seconds
Started Jun 05 05:41:51 PM PDT 24
Finished Jun 05 05:42:14 PM PDT 24
Peak memory 216784 kb
Host smart-b1a488f8-c3a1-4728-906c-f62049003157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778640672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3778640672
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2025627316
Short name T411
Test name
Test status
Simulation time 360612764 ps
CPU time 5.35 seconds
Started Jun 05 05:41:52 PM PDT 24
Finished Jun 05 05:41:58 PM PDT 24
Peak memory 216976 kb
Host smart-fb90e81c-077a-4215-a90f-a844c11fb917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025627316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2025627316
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1531437657
Short name T520
Test name
Test status
Simulation time 118880026 ps
CPU time 0.98 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:52 PM PDT 24
Peak memory 207248 kb
Host smart-39f183fa-313b-4d7b-bd2e-326a5cb49d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531437657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1531437657
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1988528877
Short name T924
Test name
Test status
Simulation time 70407009 ps
CPU time 2.62 seconds
Started Jun 05 05:41:51 PM PDT 24
Finished Jun 05 05:41:54 PM PDT 24
Peak memory 233152 kb
Host smart-10d2aac7-10cc-4686-bb36-a9a057991e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988528877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1988528877
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3823180523
Short name T316
Test name
Test status
Simulation time 12133741 ps
CPU time 0.69 seconds
Started Jun 05 05:41:58 PM PDT 24
Finished Jun 05 05:41:59 PM PDT 24
Peak memory 205124 kb
Host smart-3c26301c-9d85-442f-9ca5-17010412c15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823180523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3823180523
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1597004235
Short name T334
Test name
Test status
Simulation time 100421462 ps
CPU time 3.21 seconds
Started Jun 05 05:42:00 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 224968 kb
Host smart-c941ca03-7123-45e5-9e97-380bc2d759fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597004235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1597004235
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3994575151
Short name T308
Test name
Test status
Simulation time 13424636 ps
CPU time 0.86 seconds
Started Jun 05 05:41:50 PM PDT 24
Finished Jun 05 05:41:52 PM PDT 24
Peak memory 206936 kb
Host smart-fba45883-2f57-4e0e-97db-74e0d672cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994575151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3994575151
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3742430017
Short name T163
Test name
Test status
Simulation time 272428075770 ps
CPU time 530.77 seconds
Started Jun 05 05:42:07 PM PDT 24
Finished Jun 05 05:50:58 PM PDT 24
Peak memory 250620 kb
Host smart-04efb36a-2562-479d-95a7-b16fd4bc2fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742430017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3742430017
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2033410263
Short name T111
Test name
Test status
Simulation time 38772019567 ps
CPU time 82.14 seconds
Started Jun 05 05:42:00 PM PDT 24
Finished Jun 05 05:43:23 PM PDT 24
Peak memory 241436 kb
Host smart-66860d18-d180-4201-9982-71c2b16a6804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033410263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2033410263
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.4196230629
Short name T210
Test name
Test status
Simulation time 135380929144 ps
CPU time 289.46 seconds
Started Jun 05 05:42:00 PM PDT 24
Finished Jun 05 05:46:51 PM PDT 24
Peak memory 255864 kb
Host smart-29abf1d4-e786-4357-b96e-7e565c57964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196230629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.4196230629
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2843429061
Short name T834
Test name
Test status
Simulation time 10117576076 ps
CPU time 37.42 seconds
Started Jun 05 05:42:00 PM PDT 24
Finished Jun 05 05:42:38 PM PDT 24
Peak memory 249596 kb
Host smart-48613c93-f528-46b2-9e2b-e269b5e5bfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843429061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2843429061
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.691126032
Short name T347
Test name
Test status
Simulation time 408478640 ps
CPU time 4.03 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 233300 kb
Host smart-8f236010-1502-4d79-b1ef-a7f1861df948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691126032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.691126032
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3293587844
Short name T439
Test name
Test status
Simulation time 7077091184 ps
CPU time 25.32 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:28 PM PDT 24
Peak memory 241332 kb
Host smart-c2c23671-a92a-46d5-87f2-4b4838dadadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293587844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3293587844
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1259797745
Short name T895
Test name
Test status
Simulation time 65683262 ps
CPU time 1.04 seconds
Started Jun 05 05:41:48 PM PDT 24
Finished Jun 05 05:41:50 PM PDT 24
Peak memory 217028 kb
Host smart-d49fad7c-0109-4158-8b10-8adf6be9ead4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259797745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1259797745
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2160876543
Short name T682
Test name
Test status
Simulation time 7799079964 ps
CPU time 4.08 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 233180 kb
Host smart-d58c0c86-ab2b-4f17-a677-6c76edd28d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160876543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2160876543
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1937819398
Short name T192
Test name
Test status
Simulation time 82117718 ps
CPU time 2.46 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:02 PM PDT 24
Peak memory 233144 kb
Host smart-6f776a76-42fc-4650-a94e-d2500dcf45fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937819398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1937819398
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2595708591
Short name T902
Test name
Test status
Simulation time 571389572 ps
CPU time 5.56 seconds
Started Jun 05 05:41:58 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 223212 kb
Host smart-c589e0fc-8956-44f6-8b0e-b97203e8a3c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2595708591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2595708591
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1901321404
Short name T127
Test name
Test status
Simulation time 23070463623 ps
CPU time 235.45 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:46:02 PM PDT 24
Peak memory 254852 kb
Host smart-761cf2e0-ba46-41d0-84e9-340cfda4b2d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901321404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1901321404
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1575865309
Short name T905
Test name
Test status
Simulation time 1160898543 ps
CPU time 5.93 seconds
Started Jun 05 05:41:49 PM PDT 24
Finished Jun 05 05:41:55 PM PDT 24
Peak memory 216804 kb
Host smart-8d76dcf7-7feb-4fe5-ab74-a01f1a4171f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575865309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1575865309
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2135056098
Short name T877
Test name
Test status
Simulation time 36900134 ps
CPU time 0.71 seconds
Started Jun 05 05:41:51 PM PDT 24
Finished Jun 05 05:41:52 PM PDT 24
Peak memory 206044 kb
Host smart-71123089-15b7-4168-a030-fddd0d5f2139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135056098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2135056098
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2654336398
Short name T917
Test name
Test status
Simulation time 198129990 ps
CPU time 0.9 seconds
Started Jun 05 05:41:55 PM PDT 24
Finished Jun 05 05:41:57 PM PDT 24
Peak memory 206348 kb
Host smart-d142ccc2-d4e5-49ab-a89d-0012601a315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654336398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2654336398
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2395001151
Short name T926
Test name
Test status
Simulation time 71495447 ps
CPU time 0.87 seconds
Started Jun 05 05:41:56 PM PDT 24
Finished Jun 05 05:41:57 PM PDT 24
Peak memory 206240 kb
Host smart-c5abaac7-d64b-4c12-96bf-6712c843cd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395001151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2395001151
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3540427860
Short name T193
Test name
Test status
Simulation time 852955494 ps
CPU time 5.45 seconds
Started Jun 05 05:41:58 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 224988 kb
Host smart-7e42e4e3-c2f0-4664-8aac-f2336b26cd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540427860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3540427860
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2620754926
Short name T311
Test name
Test status
Simulation time 34988064 ps
CPU time 0.7 seconds
Started Jun 05 05:40:57 PM PDT 24
Finished Jun 05 05:40:59 PM PDT 24
Peak memory 205124 kb
Host smart-b2144d09-3ae5-44ee-a451-0de7e51e9965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620754926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
620754926
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2378861927
Short name T404
Test name
Test status
Simulation time 78965954 ps
CPU time 3.74 seconds
Started Jun 05 05:41:00 PM PDT 24
Finished Jun 05 05:41:06 PM PDT 24
Peak memory 233092 kb
Host smart-dd5019a3-036c-4caa-b7df-399bb8462777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378861927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2378861927
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2000936543
Short name T53
Test name
Test status
Simulation time 17821285 ps
CPU time 0.78 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:40:53 PM PDT 24
Peak memory 205856 kb
Host smart-6b5d09e8-1f73-4479-a569-f2e6df81dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000936543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2000936543
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1377889557
Short name T219
Test name
Test status
Simulation time 19075676382 ps
CPU time 110.42 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:42:51 PM PDT 24
Peak memory 254308 kb
Host smart-99e84326-828b-4318-9453-a54bcd63201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377889557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1377889557
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3216851683
Short name T15
Test name
Test status
Simulation time 33273779752 ps
CPU time 150.75 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:43:32 PM PDT 24
Peak memory 252528 kb
Host smart-0d730a27-7b40-493a-81d1-67566a84766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216851683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3216851683
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.775531386
Short name T710
Test name
Test status
Simulation time 5298654808 ps
CPU time 22.49 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:41:23 PM PDT 24
Peak memory 240056 kb
Host smart-ab13b70c-5f70-4a9a-afb3-acf24e32b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775531386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.775531386
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1734268787
Short name T352
Test name
Test status
Simulation time 2923864467 ps
CPU time 10.15 seconds
Started Jun 05 05:40:58 PM PDT 24
Finished Jun 05 05:41:10 PM PDT 24
Peak memory 224952 kb
Host smart-27dee72f-1ee6-4d16-8070-a379dab7a8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734268787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1734268787
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3000002961
Short name T641
Test name
Test status
Simulation time 31939923200 ps
CPU time 80.15 seconds
Started Jun 05 05:40:53 PM PDT 24
Finished Jun 05 05:42:14 PM PDT 24
Peak memory 224884 kb
Host smart-ebb1c104-6517-49e0-b5a7-ad4567144f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000002961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3000002961
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.240543023
Short name T529
Test name
Test status
Simulation time 43623361 ps
CPU time 1.07 seconds
Started Jun 05 05:40:53 PM PDT 24
Finished Jun 05 05:40:55 PM PDT 24
Peak memory 217080 kb
Host smart-a839ff13-642f-4998-b304-ce2fd0b8e275
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240543023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.240543023
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1519374180
Short name T327
Test name
Test status
Simulation time 71744787 ps
CPU time 2.11 seconds
Started Jun 05 05:40:52 PM PDT 24
Finished Jun 05 05:40:55 PM PDT 24
Peak memory 223432 kb
Host smart-e534fd21-bf62-44fd-b566-cc9ce8a823c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519374180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1519374180
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.968235558
Short name T172
Test name
Test status
Simulation time 1424045338 ps
CPU time 4.79 seconds
Started Jun 05 05:40:55 PM PDT 24
Finished Jun 05 05:41:00 PM PDT 24
Peak memory 224904 kb
Host smart-c6a7f0e8-d96c-409e-951f-3f95c34129ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968235558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.968235558
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3449218781
Short name T569
Test name
Test status
Simulation time 2765136340 ps
CPU time 11.07 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:41:12 PM PDT 24
Peak memory 222808 kb
Host smart-15ebebf7-feff-4fa3-bd44-64c282fbaf37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3449218781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3449218781
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2493695599
Short name T61
Test name
Test status
Simulation time 63127158 ps
CPU time 1.07 seconds
Started Jun 05 05:40:58 PM PDT 24
Finished Jun 05 05:41:00 PM PDT 24
Peak memory 235212 kb
Host smart-0aea2664-9e0c-4d01-a2a7-1a0b15059b93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493695599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2493695599
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.584092329
Short name T150
Test name
Test status
Simulation time 47506182 ps
CPU time 1.05 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:41:01 PM PDT 24
Peak memory 207272 kb
Host smart-0ad227ae-0555-42ba-a206-b174dbcec916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584092329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.584092329
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3360039577
Short name T288
Test name
Test status
Simulation time 5309701500 ps
CPU time 19.74 seconds
Started Jun 05 05:40:51 PM PDT 24
Finished Jun 05 05:41:11 PM PDT 24
Peak memory 216932 kb
Host smart-4e03418c-3cb1-40a7-b0f0-7b206f63f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360039577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3360039577
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.933551700
Short name T921
Test name
Test status
Simulation time 8248741564 ps
CPU time 8.19 seconds
Started Jun 05 05:41:01 PM PDT 24
Finished Jun 05 05:41:11 PM PDT 24
Peak memory 216716 kb
Host smart-6d25e3fe-3ad3-4d0d-b4fe-131f1b1560de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933551700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.933551700
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3974423640
Short name T849
Test name
Test status
Simulation time 22582624 ps
CPU time 0.8 seconds
Started Jun 05 05:41:01 PM PDT 24
Finished Jun 05 05:41:03 PM PDT 24
Peak memory 206308 kb
Host smart-6e402765-34e8-4e17-9022-65a0a9e4cdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974423640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3974423640
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3504821959
Short name T487
Test name
Test status
Simulation time 139860808 ps
CPU time 0.84 seconds
Started Jun 05 05:40:50 PM PDT 24
Finished Jun 05 05:40:51 PM PDT 24
Peak memory 206192 kb
Host smart-2de5f830-8589-40e2-bb0a-425f69e47383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504821959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3504821959
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.218311464
Short name T274
Test name
Test status
Simulation time 1224627720 ps
CPU time 4.41 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:41:05 PM PDT 24
Peak memory 233096 kb
Host smart-f41ae50a-f63a-4dfc-9941-62ada2814890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218311464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.218311464
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.65539443
Short name T658
Test name
Test status
Simulation time 12595612 ps
CPU time 0.72 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:42:08 PM PDT 24
Peak memory 205108 kb
Host smart-2e9aaacf-be2f-4b7e-9414-a9e1146103e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65539443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.65539443
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1790921018
Short name T702
Test name
Test status
Simulation time 1177872520 ps
CPU time 7.56 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 224700 kb
Host smart-8698b14b-5114-4edf-a99c-43b05b3952a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790921018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1790921018
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3041067092
Short name T355
Test name
Test status
Simulation time 20134645 ps
CPU time 0.8 seconds
Started Jun 05 05:42:01 PM PDT 24
Finished Jun 05 05:42:02 PM PDT 24
Peak memory 205932 kb
Host smart-2d87125f-13bb-4296-92ac-1c755b048161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041067092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3041067092
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4069308351
Short name T866
Test name
Test status
Simulation time 5216261120 ps
CPU time 11.88 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:12 PM PDT 24
Peak memory 217956 kb
Host smart-0f2ef7be-a3b8-4190-8086-3fb9485a024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069308351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4069308351
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4224988956
Short name T265
Test name
Test status
Simulation time 4223953497 ps
CPU time 54.5 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 224296 kb
Host smart-d61de44b-f4d3-4070-8ef0-e8dd397c8387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224988956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4224988956
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3867658092
Short name T793
Test name
Test status
Simulation time 186801007 ps
CPU time 3.87 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:06 PM PDT 24
Peak memory 233176 kb
Host smart-702fe3b9-e941-4f95-80cc-a4984c5a5328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867658092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3867658092
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1290652778
Short name T502
Test name
Test status
Simulation time 1159278122 ps
CPU time 3.95 seconds
Started Jun 05 05:42:01 PM PDT 24
Finished Jun 05 05:42:06 PM PDT 24
Peak memory 233120 kb
Host smart-524b1f5f-d15d-496c-810f-31d1e3a92eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290652778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1290652778
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1112753570
Short name T443
Test name
Test status
Simulation time 13708176393 ps
CPU time 33.29 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:32 PM PDT 24
Peak memory 233136 kb
Host smart-08036258-46b9-4d6b-985f-22c117ac3cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112753570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1112753570
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1106311521
Short name T765
Test name
Test status
Simulation time 212141299 ps
CPU time 4.76 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 233120 kb
Host smart-b8326c79-576a-4a6c-8472-227469fc0f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106311521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1106311521
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.583420298
Short name T660
Test name
Test status
Simulation time 29572416008 ps
CPU time 45.27 seconds
Started Jun 05 05:41:57 PM PDT 24
Finished Jun 05 05:42:43 PM PDT 24
Peak memory 234240 kb
Host smart-303eff80-db62-4af7-aa84-d3b626caac41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583420298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.583420298
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.161074224
Short name T808
Test name
Test status
Simulation time 1298807943 ps
CPU time 16.34 seconds
Started Jun 05 05:42:00 PM PDT 24
Finished Jun 05 05:42:17 PM PDT 24
Peak memory 223456 kb
Host smart-3cc47455-ca45-46c7-a763-05b6f5c7a1b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=161074224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.161074224
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2590353418
Short name T52
Test name
Test status
Simulation time 52306849934 ps
CPU time 23.5 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:26 PM PDT 24
Peak memory 216884 kb
Host smart-1b992d7f-baff-4eaf-bc62-8b51f97dac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590353418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2590353418
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2151825120
Short name T767
Test name
Test status
Simulation time 19823644 ps
CPU time 0.71 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:00 PM PDT 24
Peak memory 205764 kb
Host smart-1ea7bac5-9fdd-4229-84ab-6a3d1ee725db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151825120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2151825120
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2539199127
Short name T293
Test name
Test status
Simulation time 58957633 ps
CPU time 0.81 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:00 PM PDT 24
Peak memory 206324 kb
Host smart-baac4bba-44e7-4691-bcda-d8e559ae4c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539199127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2539199127
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3051277570
Short name T299
Test name
Test status
Simulation time 856002459 ps
CPU time 0.96 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 206240 kb
Host smart-711ed2f0-9a62-416f-ad51-dfe851aa7167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051277570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3051277570
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.186935536
Short name T844
Test name
Test status
Simulation time 2583127620 ps
CPU time 12.34 seconds
Started Jun 05 05:41:58 PM PDT 24
Finished Jun 05 05:42:11 PM PDT 24
Peak memory 233232 kb
Host smart-90577dae-947e-41d1-a85a-abc4ca0c91cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186935536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.186935536
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3713146844
Short name T435
Test name
Test status
Simulation time 10896988 ps
CPU time 0.69 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 205724 kb
Host smart-625cae70-0140-481f-a225-a5956f5778df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713146844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3713146844
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2837997040
Short name T384
Test name
Test status
Simulation time 2597172629 ps
CPU time 13.98 seconds
Started Jun 05 05:42:01 PM PDT 24
Finished Jun 05 05:42:16 PM PDT 24
Peak memory 233252 kb
Host smart-5caf452a-32fa-46cc-b310-6f1a8fb7bdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837997040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2837997040
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.863945677
Short name T968
Test name
Test status
Simulation time 56735267 ps
CPU time 0.78 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 207296 kb
Host smart-bccf4799-e276-48bb-ac67-84c33c757b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863945677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.863945677
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2470487514
Short name T224
Test name
Test status
Simulation time 7601832903 ps
CPU time 99.47 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:43:42 PM PDT 24
Peak memory 249636 kb
Host smart-b2fabc6d-97eb-464c-8c94-c717d3a8342a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470487514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2470487514
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2553576368
Short name T751
Test name
Test status
Simulation time 13530912750 ps
CPU time 38.8 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:42:46 PM PDT 24
Peak memory 237100 kb
Host smart-db985129-0d93-4650-87a3-4d8a6c625585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553576368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2553576368
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3291259340
Short name T929
Test name
Test status
Simulation time 5706188374 ps
CPU time 42.07 seconds
Started Jun 05 05:42:01 PM PDT 24
Finished Jun 05 05:42:44 PM PDT 24
Peak memory 251024 kb
Host smart-b498cccd-25fa-4a8d-b000-83d6249364d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291259340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3291259340
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3412900536
Short name T508
Test name
Test status
Simulation time 1462327587 ps
CPU time 20.71 seconds
Started Jun 05 05:42:03 PM PDT 24
Finished Jun 05 05:42:24 PM PDT 24
Peak memory 233148 kb
Host smart-52cc1fd6-3595-417e-8908-569e41fcdcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412900536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3412900536
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4193322255
Short name T446
Test name
Test status
Simulation time 13134812045 ps
CPU time 34.66 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:34 PM PDT 24
Peak memory 224992 kb
Host smart-ab5e0a6a-5c86-41cf-b2bd-21ddb411d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193322255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4193322255
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3694145676
Short name T177
Test name
Test status
Simulation time 116479254 ps
CPU time 2.55 seconds
Started Jun 05 05:42:03 PM PDT 24
Finished Jun 05 05:42:06 PM PDT 24
Peak memory 233196 kb
Host smart-3517b53e-85e6-4c10-b9f7-c88ae3da7f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694145676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3694145676
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3151057077
Short name T838
Test name
Test status
Simulation time 30809024746 ps
CPU time 28.21 seconds
Started Jun 05 05:41:58 PM PDT 24
Finished Jun 05 05:42:27 PM PDT 24
Peak memory 249400 kb
Host smart-710dddc5-aee8-4a6e-a915-31df5f1ab626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151057077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3151057077
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.783945711
Short name T700
Test name
Test status
Simulation time 3164940298 ps
CPU time 4.05 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 224788 kb
Host smart-5e8350bc-ee37-4878-a5ab-eb7f5fe5191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783945711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.783945711
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2964525425
Short name T820
Test name
Test status
Simulation time 341481924 ps
CPU time 5.19 seconds
Started Jun 05 05:42:05 PM PDT 24
Finished Jun 05 05:42:11 PM PDT 24
Peak memory 219648 kb
Host smart-96a4fa8c-1962-4fae-87ea-66339191ec26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2964525425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2964525425
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.400053256
Short name T686
Test name
Test status
Simulation time 15520686465 ps
CPU time 32.01 seconds
Started Jun 05 05:42:01 PM PDT 24
Finished Jun 05 05:42:34 PM PDT 24
Peak memory 216872 kb
Host smart-f1f6c546-b56a-4fa4-99e8-eb51e27771d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400053256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.400053256
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1390503282
Short name T583
Test name
Test status
Simulation time 651797217 ps
CPU time 2.15 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 216680 kb
Host smart-cb4ed8ad-7fa5-4140-9634-23f0e648df54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390503282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1390503282
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1388369897
Short name T383
Test name
Test status
Simulation time 109194012 ps
CPU time 2.22 seconds
Started Jun 05 05:42:01 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 216852 kb
Host smart-3a2eb31c-47dc-42c8-a65d-95a4d394c17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388369897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1388369897
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3820779031
Short name T464
Test name
Test status
Simulation time 23713842 ps
CPU time 0.79 seconds
Started Jun 05 05:41:59 PM PDT 24
Finished Jun 05 05:42:01 PM PDT 24
Peak memory 206252 kb
Host smart-73768c3e-51f1-4d58-af9a-7b152399bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820779031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3820779031
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3171691989
Short name T482
Test name
Test status
Simulation time 18299554304 ps
CPU time 5.21 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:42:10 PM PDT 24
Peak memory 233252 kb
Host smart-1acc0e3d-8bbf-4d19-a96d-6e4cc10a4272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171691989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3171691989
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3584858512
Short name T762
Test name
Test status
Simulation time 34427040 ps
CPU time 0.69 seconds
Started Jun 05 05:42:05 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 205760 kb
Host smart-a4591c6f-6d9b-4b24-8763-7d55ad0916d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584858512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3584858512
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2136378551
Short name T615
Test name
Test status
Simulation time 610595868 ps
CPU time 2.48 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 224968 kb
Host smart-c23a041e-4b58-47ef-8874-cdb644acd144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136378551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2136378551
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3421020434
Short name T602
Test name
Test status
Simulation time 68784220 ps
CPU time 0.77 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 206944 kb
Host smart-59ae13ca-d85a-48e4-9d61-8581e0e9ae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421020434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3421020434
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.898136393
Short name T893
Test name
Test status
Simulation time 24502634115 ps
CPU time 52.82 seconds
Started Jun 05 05:42:03 PM PDT 24
Finished Jun 05 05:42:56 PM PDT 24
Peak memory 235140 kb
Host smart-0c405936-2554-4ed3-95b9-c93cd8036c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898136393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.898136393
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3632176825
Short name T891
Test name
Test status
Simulation time 7768011852 ps
CPU time 104.88 seconds
Started Jun 05 05:42:00 PM PDT 24
Finished Jun 05 05:43:46 PM PDT 24
Peak memory 257912 kb
Host smart-93e3babf-6af6-44c6-9611-d8894a3b1fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632176825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3632176825
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4091741318
Short name T420
Test name
Test status
Simulation time 57198659360 ps
CPU time 351.92 seconds
Started Jun 05 05:42:10 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 256464 kb
Host smart-bb4ee4ea-2d47-4344-ad10-612eb2743757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091741318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4091741318
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1223119844
Short name T684
Test name
Test status
Simulation time 1767444975 ps
CPU time 19.61 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:42:25 PM PDT 24
Peak memory 233152 kb
Host smart-4c22ed54-728e-44c2-a306-5028a4479c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223119844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1223119844
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1104690565
Short name T571
Test name
Test status
Simulation time 231042646 ps
CPU time 3.65 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:42:09 PM PDT 24
Peak memory 224876 kb
Host smart-e2445109-779a-4c43-9521-c75fa5406cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104690565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1104690565
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.159084007
Short name T636
Test name
Test status
Simulation time 75627416 ps
CPU time 2.22 seconds
Started Jun 05 05:42:09 PM PDT 24
Finished Jun 05 05:42:12 PM PDT 24
Peak memory 223604 kb
Host smart-d9b4eee0-cf20-4f79-9980-2e57334b658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159084007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.159084007
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.150336754
Short name T158
Test name
Test status
Simulation time 660719523 ps
CPU time 3.28 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:06 PM PDT 24
Peak memory 233096 kb
Host smart-4a0618a8-f0ad-42fd-8536-4dcbabb482ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150336754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.150336754
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1929489002
Short name T191
Test name
Test status
Simulation time 622278167 ps
CPU time 2.48 seconds
Started Jun 05 05:42:03 PM PDT 24
Finished Jun 05 05:42:06 PM PDT 24
Peak memory 228128 kb
Host smart-171dccc9-01d7-4234-a2b2-24944095a4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929489002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1929489002
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.173117893
Short name T589
Test name
Test status
Simulation time 953912203 ps
CPU time 4.79 seconds
Started Jun 05 05:42:08 PM PDT 24
Finished Jun 05 05:42:14 PM PDT 24
Peak memory 219236 kb
Host smart-2b89ec27-76c2-44bc-805f-aa49bdc8270f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=173117893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.173117893
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4044751961
Short name T45
Test name
Test status
Simulation time 34089420190 ps
CPU time 316.22 seconds
Started Jun 05 05:42:07 PM PDT 24
Finished Jun 05 05:47:24 PM PDT 24
Peak memory 250724 kb
Host smart-5735e875-79ae-4f43-a6ef-edd4f4112ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044751961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4044751961
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2335166604
Short name T603
Test name
Test status
Simulation time 3372258700 ps
CPU time 14.2 seconds
Started Jun 05 05:42:03 PM PDT 24
Finished Jun 05 05:42:18 PM PDT 24
Peak memory 216840 kb
Host smart-bd0bcf54-e6f7-4332-afe5-ead39cf25021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335166604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2335166604
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1661065567
Short name T11
Test name
Test status
Simulation time 4354372076 ps
CPU time 6.95 seconds
Started Jun 05 05:42:05 PM PDT 24
Finished Jun 05 05:42:12 PM PDT 24
Peak memory 216772 kb
Host smart-9a01d926-ac3f-4045-92b7-17dd4ce84831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661065567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1661065567
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2086744698
Short name T801
Test name
Test status
Simulation time 79834537 ps
CPU time 1.6 seconds
Started Jun 05 05:42:02 PM PDT 24
Finished Jun 05 05:42:04 PM PDT 24
Peak memory 217100 kb
Host smart-3b84a9d9-ea65-4bcd-bedc-806f8db232b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086744698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2086744698
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3818324193
Short name T678
Test name
Test status
Simulation time 230438338 ps
CPU time 0.88 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 206248 kb
Host smart-f4bb9f8b-a0af-4603-a208-eaf47a7d0ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818324193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3818324193
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1081101716
Short name T566
Test name
Test status
Simulation time 128601384 ps
CPU time 2.32 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 232980 kb
Host smart-5e9c11b8-b58f-494f-ae59-c1d909755e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081101716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1081101716
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2518547805
Short name T635
Test name
Test status
Simulation time 42780934 ps
CPU time 0.76 seconds
Started Jun 05 05:42:13 PM PDT 24
Finished Jun 05 05:42:14 PM PDT 24
Peak memory 205108 kb
Host smart-f8f85e05-9e8a-463b-864e-94de5afc2b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518547805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2518547805
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.799602979
Short name T563
Test name
Test status
Simulation time 265957459 ps
CPU time 2.28 seconds
Started Jun 05 05:42:08 PM PDT 24
Finished Jun 05 05:42:10 PM PDT 24
Peak memory 218832 kb
Host smart-1056529d-85b6-48d4-9c22-1947727b0f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799602979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.799602979
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2804909570
Short name T294
Test name
Test status
Simulation time 46188698 ps
CPU time 0.83 seconds
Started Jun 05 05:42:04 PM PDT 24
Finished Jun 05 05:42:05 PM PDT 24
Peak memory 206976 kb
Host smart-ead189a8-ca46-4ba1-bfa7-c3c3fdc20081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804909570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2804909570
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2901229964
Short name T408
Test name
Test status
Simulation time 5340425335 ps
CPU time 44.47 seconds
Started Jun 05 05:42:08 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 237056 kb
Host smart-a8b43e88-742c-4ae6-b489-f39d379f0393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901229964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2901229964
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3477549991
Short name T392
Test name
Test status
Simulation time 8994975629 ps
CPU time 103.06 seconds
Started Jun 05 05:42:10 PM PDT 24
Finished Jun 05 05:43:54 PM PDT 24
Peak memory 249716 kb
Host smart-b39d3557-9945-4325-99d2-279d07a7aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477549991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3477549991
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.603099634
Short name T282
Test name
Test status
Simulation time 695635719 ps
CPU time 8.39 seconds
Started Jun 05 05:42:07 PM PDT 24
Finished Jun 05 05:42:16 PM PDT 24
Peak memory 249560 kb
Host smart-2734795f-5930-48e0-b82d-2f82587e89c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603099634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.603099634
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1846028074
Short name T651
Test name
Test status
Simulation time 2500465559 ps
CPU time 21.91 seconds
Started Jun 05 05:42:07 PM PDT 24
Finished Jun 05 05:42:30 PM PDT 24
Peak memory 224940 kb
Host smart-931ae02b-e14b-4314-9515-892624ee646c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846028074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1846028074
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3461552455
Short name T401
Test name
Test status
Simulation time 6055106194 ps
CPU time 11.46 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:42:18 PM PDT 24
Peak memory 233168 kb
Host smart-adac21b6-c857-49a2-a798-7bc500300ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461552455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3461552455
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3356523596
Short name T326
Test name
Test status
Simulation time 1759139994 ps
CPU time 8.26 seconds
Started Jun 05 05:42:10 PM PDT 24
Finished Jun 05 05:42:19 PM PDT 24
Peak memory 233144 kb
Host smart-eff865f4-e301-4eb8-be18-15b0f5698341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356523596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3356523596
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4195776233
Short name T462
Test name
Test status
Simulation time 1263034471 ps
CPU time 7.56 seconds
Started Jun 05 05:42:03 PM PDT 24
Finished Jun 05 05:42:11 PM PDT 24
Peak memory 233176 kb
Host smart-0ad61c96-e2ac-4b17-bc47-7cac0848731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195776233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4195776233
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2112907685
Short name T872
Test name
Test status
Simulation time 567317712 ps
CPU time 7.29 seconds
Started Jun 05 05:42:05 PM PDT 24
Finished Jun 05 05:42:13 PM PDT 24
Peak memory 222988 kb
Host smart-2fc267c1-78c6-4eee-8f0f-70fd850b73a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2112907685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2112907685
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3317021802
Short name T148
Test name
Test status
Simulation time 135299152407 ps
CPU time 295.85 seconds
Started Jun 05 05:42:09 PM PDT 24
Finished Jun 05 05:47:05 PM PDT 24
Peak memory 251196 kb
Host smart-59c81b73-732e-45aa-9e98-e165ae00ec45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317021802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3317021802
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.456198977
Short name T725
Test name
Test status
Simulation time 4196210360 ps
CPU time 13.78 seconds
Started Jun 05 05:42:05 PM PDT 24
Finished Jun 05 05:42:19 PM PDT 24
Peak memory 216960 kb
Host smart-7e017efa-801a-401b-9107-ba079ad9e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456198977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.456198977
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3004805415
Short name T526
Test name
Test status
Simulation time 3906890801 ps
CPU time 5.91 seconds
Started Jun 05 05:42:05 PM PDT 24
Finished Jun 05 05:42:12 PM PDT 24
Peak memory 217024 kb
Host smart-c5829510-51af-4f2b-adbf-cf81c42738f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004805415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3004805415
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3479263947
Short name T582
Test name
Test status
Simulation time 39166094 ps
CPU time 0.83 seconds
Started Jun 05 05:42:05 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 207004 kb
Host smart-e2cb28dc-9232-4610-8e15-eba911959731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479263947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3479263947
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.755585361
Short name T679
Test name
Test status
Simulation time 26124231 ps
CPU time 0.74 seconds
Started Jun 05 05:42:07 PM PDT 24
Finished Jun 05 05:42:09 PM PDT 24
Peak memory 206252 kb
Host smart-a44cab93-6bb8-4e57-b56c-1145ef565d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755585361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.755585361
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3087761098
Short name T125
Test name
Test status
Simulation time 154701314 ps
CPU time 2.58 seconds
Started Jun 05 05:42:08 PM PDT 24
Finished Jun 05 05:42:11 PM PDT 24
Peak memory 224976 kb
Host smart-ba083c31-0fa7-4d04-aa85-26b6d5b140d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087761098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3087761098
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1287566217
Short name T319
Test name
Test status
Simulation time 35724735 ps
CPU time 0.72 seconds
Started Jun 05 05:42:10 PM PDT 24
Finished Jun 05 05:42:11 PM PDT 24
Peak memory 205116 kb
Host smart-eb2490e6-67f2-42ab-b611-628379e46057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287566217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1287566217
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3680158372
Short name T667
Test name
Test status
Simulation time 827400268 ps
CPU time 2.91 seconds
Started Jun 05 05:42:10 PM PDT 24
Finished Jun 05 05:42:14 PM PDT 24
Peak memory 233120 kb
Host smart-491a7dcb-5d69-4479-affd-69f3e2c6e159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680158372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3680158372
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2214022971
Short name T672
Test name
Test status
Simulation time 13888779 ps
CPU time 0.75 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 205852 kb
Host smart-a2bd8106-ef9f-4c5f-9ccf-965c629794f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214022971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2214022971
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2555715182
Short name T208
Test name
Test status
Simulation time 151807063561 ps
CPU time 267.98 seconds
Started Jun 05 05:42:10 PM PDT 24
Finished Jun 05 05:46:39 PM PDT 24
Peak memory 249592 kb
Host smart-fe586a6f-3207-46b5-b950-0dff07eb1899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555715182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2555715182
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1365413832
Short name T742
Test name
Test status
Simulation time 21989414339 ps
CPU time 219.63 seconds
Started Jun 05 05:42:11 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 250064 kb
Host smart-7dbe1765-743c-4e8f-ad48-e4c2bbd54dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365413832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1365413832
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1802736151
Short name T345
Test name
Test status
Simulation time 115118841 ps
CPU time 4.16 seconds
Started Jun 05 05:42:11 PM PDT 24
Finished Jun 05 05:42:16 PM PDT 24
Peak memory 224972 kb
Host smart-a6f150ef-a119-485b-9c7a-9e31ab82c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802736151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1802736151
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.240740484
Short name T348
Test name
Test status
Simulation time 3350417811 ps
CPU time 16.73 seconds
Started Jun 05 05:42:09 PM PDT 24
Finished Jun 05 05:42:26 PM PDT 24
Peak memory 233208 kb
Host smart-5550e30d-cd04-4c4e-bd45-6f72cba338c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240740484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.240740484
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2372683451
Short name T947
Test name
Test status
Simulation time 11260339904 ps
CPU time 93.6 seconds
Started Jun 05 05:42:10 PM PDT 24
Finished Jun 05 05:43:44 PM PDT 24
Peak memory 241408 kb
Host smart-21b5f503-1b81-4ecc-bdc7-9b5cae506538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372683451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2372683451
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.566376548
Short name T251
Test name
Test status
Simulation time 3307658597 ps
CPU time 13.39 seconds
Started Jun 05 05:42:08 PM PDT 24
Finished Jun 05 05:42:22 PM PDT 24
Peak memory 241240 kb
Host smart-6f2cba4a-ed70-41e3-aa34-1fd088f1c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566376548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.566376548
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.448852516
Short name T800
Test name
Test status
Simulation time 1308644503 ps
CPU time 4.36 seconds
Started Jun 05 05:42:08 PM PDT 24
Finished Jun 05 05:42:13 PM PDT 24
Peak memory 224864 kb
Host smart-36104df7-55b6-4959-953e-04d5cf7b5e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448852516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.448852516
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.458148339
Short name T858
Test name
Test status
Simulation time 444879675 ps
CPU time 6.03 seconds
Started Jun 05 05:42:07 PM PDT 24
Finished Jun 05 05:42:13 PM PDT 24
Peak memory 223408 kb
Host smart-ffe85eb2-ceff-479f-9db4-6ce45aca4612
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=458148339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.458148339
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.497572352
Short name T770
Test name
Test status
Simulation time 14213268952 ps
CPU time 105.29 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:43:52 PM PDT 24
Peak memory 249692 kb
Host smart-573d71de-1e58-4f40-9256-fe392923a49e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497572352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.497572352
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2079217533
Short name T810
Test name
Test status
Simulation time 5328281224 ps
CPU time 21.06 seconds
Started Jun 05 05:42:10 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 216844 kb
Host smart-e2b07a32-85b9-46c4-bf3f-4e425d1e26a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079217533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2079217533
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1489872697
Short name T696
Test name
Test status
Simulation time 2517666028 ps
CPU time 6.27 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:42:12 PM PDT 24
Peak memory 216976 kb
Host smart-eacf9eea-c5c0-4f76-8251-9870dfcb869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489872697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1489872697
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.907584731
Short name T368
Test name
Test status
Simulation time 136559473 ps
CPU time 1.73 seconds
Started Jun 05 05:42:08 PM PDT 24
Finished Jun 05 05:42:10 PM PDT 24
Peak memory 216848 kb
Host smart-8d43e807-5f13-49db-ab5e-e42590200c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907584731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.907584731
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3524896972
Short name T339
Test name
Test status
Simulation time 54858232 ps
CPU time 0.83 seconds
Started Jun 05 05:42:06 PM PDT 24
Finished Jun 05 05:42:07 PM PDT 24
Peak memory 206256 kb
Host smart-67688792-4d57-4469-92d9-5450ffd7e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524896972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3524896972
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1983497205
Short name T728
Test name
Test status
Simulation time 688697132 ps
CPU time 2.17 seconds
Started Jun 05 05:42:09 PM PDT 24
Finished Jun 05 05:42:12 PM PDT 24
Peak memory 224684 kb
Host smart-7dfaddba-d915-48f1-80ab-2813e8e8e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983497205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1983497205
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1297145027
Short name T867
Test name
Test status
Simulation time 30258012 ps
CPU time 0.82 seconds
Started Jun 05 05:42:13 PM PDT 24
Finished Jun 05 05:42:14 PM PDT 24
Peak memory 206044 kb
Host smart-ceaa903c-5f1f-404b-907d-d90d422b5707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297145027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1297145027
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1200571522
Short name T645
Test name
Test status
Simulation time 534090345 ps
CPU time 5.91 seconds
Started Jun 05 05:42:16 PM PDT 24
Finished Jun 05 05:42:22 PM PDT 24
Peak memory 225132 kb
Host smart-48096bc4-7935-45da-ad7c-b86039d4de45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200571522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1200571522
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4106039141
Short name T331
Test name
Test status
Simulation time 46023291 ps
CPU time 0.73 seconds
Started Jun 05 05:42:12 PM PDT 24
Finished Jun 05 05:42:13 PM PDT 24
Peak memory 205904 kb
Host smart-3a10937c-c77e-43ee-86c4-210da5ad4ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106039141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4106039141
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1556291106
Short name T354
Test name
Test status
Simulation time 343306204 ps
CPU time 6.26 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:42:33 PM PDT 24
Peak memory 234628 kb
Host smart-3845ec5f-f6e6-4785-ac63-dd3a4acdce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556291106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1556291106
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2422139780
Short name T538
Test name
Test status
Simulation time 3258973059 ps
CPU time 50.33 seconds
Started Jun 05 05:42:14 PM PDT 24
Finished Jun 05 05:43:05 PM PDT 24
Peak memory 234532 kb
Host smart-68ff6d91-c888-40d2-aa09-99d12002aa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422139780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2422139780
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2436352467
Short name T608
Test name
Test status
Simulation time 271605015 ps
CPU time 5.37 seconds
Started Jun 05 05:42:15 PM PDT 24
Finished Jun 05 05:42:21 PM PDT 24
Peak memory 224972 kb
Host smart-cfac789b-3d2e-4179-921f-97898f3643e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436352467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2436352467
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2078540664
Short name T259
Test name
Test status
Simulation time 7734057422 ps
CPU time 14.16 seconds
Started Jun 05 05:42:15 PM PDT 24
Finished Jun 05 05:42:29 PM PDT 24
Peak memory 233184 kb
Host smart-8825c9b6-bbd4-4ba2-9fc1-34d54f4418ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078540664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2078540664
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4236275891
Short name T944
Test name
Test status
Simulation time 1175395338 ps
CPU time 6.76 seconds
Started Jun 05 05:42:13 PM PDT 24
Finished Jun 05 05:42:20 PM PDT 24
Peak memory 233196 kb
Host smart-4ea22b58-00fe-400c-9f8c-84945f5c7e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236275891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4236275891
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1491719879
Short name T505
Test name
Test status
Simulation time 22428275650 ps
CPU time 10.3 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:36 PM PDT 24
Peak memory 241040 kb
Host smart-77f77f2d-2535-4993-83c4-49e07e7799c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491719879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1491719879
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3860958169
Short name T540
Test name
Test status
Simulation time 1590423313 ps
CPU time 5.04 seconds
Started Jun 05 05:42:14 PM PDT 24
Finished Jun 05 05:42:19 PM PDT 24
Peak memory 240684 kb
Host smart-a5d24801-bc1c-49df-a844-1079b9d7f866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860958169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3860958169
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1734293062
Short name T715
Test name
Test status
Simulation time 4547980606 ps
CPU time 22.98 seconds
Started Jun 05 05:42:17 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 223028 kb
Host smart-861e9cf5-9262-4d1a-a763-d8cf940d19b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1734293062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1734293062
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2512246664
Short name T423
Test name
Test status
Simulation time 65915993 ps
CPU time 1.09 seconds
Started Jun 05 05:42:20 PM PDT 24
Finished Jun 05 05:42:22 PM PDT 24
Peak memory 207596 kb
Host smart-9a4d2d18-4dca-4003-a580-3a0df3286fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512246664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2512246664
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1525055733
Short name T407
Test name
Test status
Simulation time 8054907044 ps
CPU time 22.8 seconds
Started Jun 05 05:42:14 PM PDT 24
Finished Jun 05 05:42:38 PM PDT 24
Peak memory 217040 kb
Host smart-2b51dc59-f4e8-43be-8199-b198eb94fec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525055733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1525055733
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2174858865
Short name T677
Test name
Test status
Simulation time 8578063800 ps
CPU time 25.23 seconds
Started Jun 05 05:42:09 PM PDT 24
Finished Jun 05 05:42:34 PM PDT 24
Peak memory 216824 kb
Host smart-6a452a5a-eadd-4d80-a7fc-4be3a4ec19fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174858865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2174858865
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3808368958
Short name T394
Test name
Test status
Simulation time 329907869 ps
CPU time 2.24 seconds
Started Jun 05 05:42:18 PM PDT 24
Finished Jun 05 05:42:20 PM PDT 24
Peak memory 216844 kb
Host smart-cf6bbb21-ad96-4478-bc64-0291b7feda8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808368958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3808368958
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2335799312
Short name T647
Test name
Test status
Simulation time 53337902 ps
CPU time 0.82 seconds
Started Jun 05 05:42:15 PM PDT 24
Finished Jun 05 05:42:17 PM PDT 24
Peak memory 206248 kb
Host smart-72ad77de-0eb5-428b-9b9d-dbb43a1eacc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335799312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2335799312
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3699357128
Short name T676
Test name
Test status
Simulation time 259371581 ps
CPU time 3.39 seconds
Started Jun 05 05:42:20 PM PDT 24
Finished Jun 05 05:42:24 PM PDT 24
Peak memory 224756 kb
Host smart-73bfe0bd-cc01-4532-b52b-716e6325eaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699357128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3699357128
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.970120864
Short name T534
Test name
Test status
Simulation time 12278733 ps
CPU time 0.68 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:27 PM PDT 24
Peak memory 206108 kb
Host smart-fcbb0ba4-3ebe-44e4-83ca-9e9dd0888c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970120864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.970120864
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1209676558
Short name T825
Test name
Test status
Simulation time 581111555 ps
CPU time 5.63 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:32 PM PDT 24
Peak memory 233140 kb
Host smart-c0ecee21-cc0e-44af-a99f-b3c58f7289c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209676558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1209676558
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4262577453
Short name T599
Test name
Test status
Simulation time 24516804 ps
CPU time 0.79 seconds
Started Jun 05 05:42:13 PM PDT 24
Finished Jun 05 05:42:14 PM PDT 24
Peak memory 207296 kb
Host smart-502c8489-c17d-459e-a59e-a099ad66802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262577453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4262577453
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1322064405
Short name T402
Test name
Test status
Simulation time 1324024205 ps
CPU time 20.31 seconds
Started Jun 05 05:42:22 PM PDT 24
Finished Jun 05 05:42:43 PM PDT 24
Peak memory 241076 kb
Host smart-7a16be07-a0bc-455a-9d4d-8b83ba3ecdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322064405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1322064405
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1619162645
Short name T222
Test name
Test status
Simulation time 8153292383 ps
CPU time 33.4 seconds
Started Jun 05 05:42:21 PM PDT 24
Finished Jun 05 05:42:55 PM PDT 24
Peak memory 220864 kb
Host smart-b082f89f-308e-47ef-969e-b04be23c5379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619162645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1619162645
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.891426782
Short name T783
Test name
Test status
Simulation time 167436594 ps
CPU time 5.22 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 233180 kb
Host smart-2e100403-897a-4f4c-9b61-9fc3591710e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891426782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.891426782
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2966179855
Short name T544
Test name
Test status
Simulation time 44102245 ps
CPU time 2.46 seconds
Started Jun 05 05:42:16 PM PDT 24
Finished Jun 05 05:42:19 PM PDT 24
Peak memory 227276 kb
Host smart-cfcfee6b-627b-428e-8407-a7132e42a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966179855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2966179855
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3388413406
Short name T711
Test name
Test status
Simulation time 7994689895 ps
CPU time 19.88 seconds
Started Jun 05 05:42:14 PM PDT 24
Finished Jun 05 05:42:34 PM PDT 24
Peak memory 240996 kb
Host smart-d46ff8c8-85ae-4b3a-8502-86d6c10bc31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388413406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3388413406
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3279477987
Short name T180
Test name
Test status
Simulation time 245349409 ps
CPU time 4.24 seconds
Started Jun 05 05:42:22 PM PDT 24
Finished Jun 05 05:42:26 PM PDT 24
Peak memory 224932 kb
Host smart-f9b101c1-ad9f-4ec5-8555-f02edf082caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279477987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3279477987
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4195705724
Short name T639
Test name
Test status
Simulation time 22604173371 ps
CPU time 16.96 seconds
Started Jun 05 05:42:16 PM PDT 24
Finished Jun 05 05:42:33 PM PDT 24
Peak memory 233148 kb
Host smart-822c919e-2306-4bfa-8057-e0105d2361c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195705724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4195705724
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1947317386
Short name T137
Test name
Test status
Simulation time 992283452 ps
CPU time 8.04 seconds
Started Jun 05 05:42:16 PM PDT 24
Finished Jun 05 05:42:24 PM PDT 24
Peak memory 219176 kb
Host smart-cf3d52ce-789e-4f89-b126-634da4c00ff2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947317386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1947317386
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.297126715
Short name T199
Test name
Test status
Simulation time 21569400170 ps
CPU time 126.88 seconds
Started Jun 05 05:42:14 PM PDT 24
Finished Jun 05 05:44:22 PM PDT 24
Peak memory 249724 kb
Host smart-746b0632-5cae-4d8e-bc4a-b8605d6a42a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297126715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.297126715
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3224042420
Short name T814
Test name
Test status
Simulation time 370990024 ps
CPU time 7.03 seconds
Started Jun 05 05:42:17 PM PDT 24
Finished Jun 05 05:42:25 PM PDT 24
Peak memory 216812 kb
Host smart-1cfa6a91-8a09-4c2c-b264-6954154502ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224042420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3224042420
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.736019395
Short name T853
Test name
Test status
Simulation time 218070976 ps
CPU time 1.44 seconds
Started Jun 05 05:42:14 PM PDT 24
Finished Jun 05 05:42:16 PM PDT 24
Peak memory 208096 kb
Host smart-ee78afa4-e6f0-436d-9895-abd20d25953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736019395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.736019395
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2130078403
Short name T359
Test name
Test status
Simulation time 12883191 ps
CPU time 0.68 seconds
Started Jun 05 05:42:18 PM PDT 24
Finished Jun 05 05:42:19 PM PDT 24
Peak memory 205976 kb
Host smart-21505650-d956-4a4a-b500-ab9d41e0e4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130078403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2130078403
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3948485558
Short name T303
Test name
Test status
Simulation time 41989233 ps
CPU time 0.8 seconds
Started Jun 05 05:42:15 PM PDT 24
Finished Jun 05 05:42:17 PM PDT 24
Peak memory 206424 kb
Host smart-13bcbe9a-c344-4746-bdc6-d64088b3125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948485558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3948485558
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.441136674
Short name T426
Test name
Test status
Simulation time 44359557 ps
CPU time 2.36 seconds
Started Jun 05 05:42:14 PM PDT 24
Finished Jun 05 05:42:17 PM PDT 24
Peak memory 224764 kb
Host smart-da0bedd8-4198-442b-80e0-a2b9a82b69c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441136674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.441136674
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2081203797
Short name T652
Test name
Test status
Simulation time 146898853 ps
CPU time 0.72 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:42:28 PM PDT 24
Peak memory 205744 kb
Host smart-fe49b29a-bece-48b8-b327-2d9a5d9ea882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081203797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2081203797
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1199762503
Short name T328
Test name
Test status
Simulation time 10504516701 ps
CPU time 15.22 seconds
Started Jun 05 05:42:23 PM PDT 24
Finished Jun 05 05:42:38 PM PDT 24
Peak memory 233220 kb
Host smart-0603e248-052b-4302-9629-4b3b3234df65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199762503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1199762503
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2540630808
Short name T374
Test name
Test status
Simulation time 61703837 ps
CPU time 0.79 seconds
Started Jun 05 05:42:15 PM PDT 24
Finished Jun 05 05:42:16 PM PDT 24
Peak memory 206952 kb
Host smart-ce7e76e3-c799-43d1-8ea9-a3bb91ac40e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540630808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2540630808
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1170898920
Short name T156
Test name
Test status
Simulation time 27732265123 ps
CPU time 225.39 seconds
Started Jun 05 05:42:24 PM PDT 24
Finished Jun 05 05:46:10 PM PDT 24
Peak memory 255004 kb
Host smart-6cf036c5-d213-4b57-87a6-aa0fbfeb3639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170898920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1170898920
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3676931960
Short name T237
Test name
Test status
Simulation time 74194614507 ps
CPU time 372.33 seconds
Started Jun 05 05:42:24 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 253488 kb
Host smart-363659ed-c27f-461e-a43c-b870e40d812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676931960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3676931960
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2902627323
Short name T618
Test name
Test status
Simulation time 77261087 ps
CPU time 2.63 seconds
Started Jun 05 05:42:24 PM PDT 24
Finished Jun 05 05:42:27 PM PDT 24
Peak memory 224960 kb
Host smart-79099575-4b40-42b5-8ede-8f469ddb61d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902627323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2902627323
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2929238596
Short name T807
Test name
Test status
Simulation time 60885559 ps
CPU time 2.2 seconds
Started Jun 05 05:42:22 PM PDT 24
Finished Jun 05 05:42:25 PM PDT 24
Peak memory 232964 kb
Host smart-e40547ee-6e32-4c43-be43-61ae00bd701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929238596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2929238596
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.398646963
Short name T494
Test name
Test status
Simulation time 3651535072 ps
CPU time 16.47 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:42:43 PM PDT 24
Peak memory 233184 kb
Host smart-ae5dc4e6-c160-4395-93c0-e031b4f01431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398646963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.398646963
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.685695862
Short name T249
Test name
Test status
Simulation time 2510075099 ps
CPU time 7.62 seconds
Started Jun 05 05:42:22 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 233184 kb
Host smart-e6bb5614-8d0a-4d06-a496-497f432b2185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685695862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.685695862
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.429311975
Short name T884
Test name
Test status
Simulation time 336768616 ps
CPU time 5.8 seconds
Started Jun 05 05:42:23 PM PDT 24
Finished Jun 05 05:42:29 PM PDT 24
Peak memory 233148 kb
Host smart-fe531a9a-abd0-4c63-afcd-c4b30d5399d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429311975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.429311975
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1979491708
Short name T517
Test name
Test status
Simulation time 1916652775 ps
CPU time 5.22 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:42:32 PM PDT 24
Peak memory 222844 kb
Host smart-2f82081c-b452-4eb8-b22d-9b8df1510f34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1979491708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1979491708
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.653510341
Short name T772
Test name
Test status
Simulation time 199174451 ps
CPU time 1.05 seconds
Started Jun 05 05:42:23 PM PDT 24
Finished Jun 05 05:42:24 PM PDT 24
Peak memory 207304 kb
Host smart-3825116e-e5c3-478e-ab19-929acc88c24c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653510341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.653510341
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2210184901
Short name T382
Test name
Test status
Simulation time 20805607913 ps
CPU time 18.67 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:42:46 PM PDT 24
Peak memory 217116 kb
Host smart-3923c37a-c9a9-4b0b-8b45-586c1d984fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210184901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2210184901
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2430141328
Short name T388
Test name
Test status
Simulation time 1146783445 ps
CPU time 6.66 seconds
Started Jun 05 05:42:14 PM PDT 24
Finished Jun 05 05:42:21 PM PDT 24
Peak memory 216636 kb
Host smart-e58d4c64-4a35-4c00-a54d-7487c1dd42f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430141328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2430141328
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2174725024
Short name T873
Test name
Test status
Simulation time 71357424 ps
CPU time 1.47 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:27 PM PDT 24
Peak memory 216884 kb
Host smart-a51c08c4-9836-4eca-9550-6fdc96b4c60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174725024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2174725024
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.728619163
Short name T794
Test name
Test status
Simulation time 116524978 ps
CPU time 1.03 seconds
Started Jun 05 05:42:12 PM PDT 24
Finished Jun 05 05:42:13 PM PDT 24
Peak memory 206656 kb
Host smart-e938f414-96fc-4f1c-85cb-f5882c29f1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728619163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.728619163
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1165265709
Short name T774
Test name
Test status
Simulation time 1997960071 ps
CPU time 4.08 seconds
Started Jun 05 05:42:22 PM PDT 24
Finished Jun 05 05:42:27 PM PDT 24
Peak memory 233128 kb
Host smart-b73f1d3f-f077-4be9-bd55-82585a51c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165265709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1165265709
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3553693192
Short name T479
Test name
Test status
Simulation time 55983229 ps
CPU time 0.75 seconds
Started Jun 05 05:42:27 PM PDT 24
Finished Jun 05 05:42:29 PM PDT 24
Peak memory 205744 kb
Host smart-65610ccb-5223-4cb6-8558-7adf07b6e542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553693192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3553693192
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2022803939
Short name T433
Test name
Test status
Simulation time 142319698 ps
CPU time 2.48 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:28 PM PDT 24
Peak memory 227656 kb
Host smart-124c4628-bf26-41bb-b50e-2963d0886e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022803939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2022803939
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2181800108
Short name T309
Test name
Test status
Simulation time 26521479 ps
CPU time 0.77 seconds
Started Jun 05 05:42:22 PM PDT 24
Finished Jun 05 05:42:23 PM PDT 24
Peak memory 207272 kb
Host smart-cd7bc7d4-d52f-4914-a01a-af3714d1d832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181800108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2181800108
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.125185510
Short name T587
Test name
Test status
Simulation time 18417309168 ps
CPU time 85.8 seconds
Started Jun 05 05:42:24 PM PDT 24
Finished Jun 05 05:43:50 PM PDT 24
Peak memory 240956 kb
Host smart-05cc5493-cc10-421c-a24b-5480f328f841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125185510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.125185510
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2981142649
Short name T616
Test name
Test status
Simulation time 3258910834 ps
CPU time 44.33 seconds
Started Jun 05 05:42:29 PM PDT 24
Finished Jun 05 05:43:15 PM PDT 24
Peak memory 249764 kb
Host smart-8798f217-34e7-4056-99c1-a34f89778c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981142649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2981142649
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3541176216
Short name T209
Test name
Test status
Simulation time 34860495932 ps
CPU time 271.58 seconds
Started Jun 05 05:42:27 PM PDT 24
Finished Jun 05 05:47:00 PM PDT 24
Peak memory 254924 kb
Host smart-6fa0a367-1910-44b0-8630-d3517570c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541176216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3541176216
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4290843324
Short name T736
Test name
Test status
Simulation time 649456305 ps
CPU time 12.33 seconds
Started Jun 05 05:42:27 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 224948 kb
Host smart-78028ac9-027a-43e2-a04d-5684feda4122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290843324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4290843324
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3177039841
Short name T183
Test name
Test status
Simulation time 527581650 ps
CPU time 5.48 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 225080 kb
Host smart-ba32e794-37c8-4c1d-9c41-d4472f63fc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177039841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3177039841
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.304029579
Short name T786
Test name
Test status
Simulation time 5326601833 ps
CPU time 9.91 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:36 PM PDT 24
Peak memory 233228 kb
Host smart-c8d4bf1c-fde1-4e73-8cd7-bfabcdd211ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304029579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.304029579
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.785695551
Short name T693
Test name
Test status
Simulation time 45260652603 ps
CPU time 28.22 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 249084 kb
Host smart-08af815e-45d4-45f5-a32e-6152d57fcdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785695551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.785695551
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2669014410
Short name T468
Test name
Test status
Simulation time 264201106 ps
CPU time 3.44 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:29 PM PDT 24
Peak memory 233168 kb
Host smart-1fb8a9e3-1c72-4666-b4ea-378fd40b4ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669014410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2669014410
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.810562037
Short name T136
Test name
Test status
Simulation time 3140319167 ps
CPU time 5.27 seconds
Started Jun 05 05:42:29 PM PDT 24
Finished Jun 05 05:42:35 PM PDT 24
Peak memory 223296 kb
Host smart-7ff6fd25-87cd-40b7-9057-6560126a306c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=810562037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.810562037
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1822977454
Short name T145
Test name
Test status
Simulation time 3431709749 ps
CPU time 80.38 seconds
Started Jun 05 05:42:24 PM PDT 24
Finished Jun 05 05:43:45 PM PDT 24
Peak memory 252768 kb
Host smart-c273f518-d943-4d88-985d-56405ed2227d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822977454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1822977454
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3056233362
Short name T586
Test name
Test status
Simulation time 2032209400 ps
CPU time 12.22 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:42:39 PM PDT 24
Peak memory 216840 kb
Host smart-e286eade-4ef6-4048-839a-a4109ac6ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056233362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3056233362
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.661581906
Short name T634
Test name
Test status
Simulation time 2126136237 ps
CPU time 4.62 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 216664 kb
Host smart-b9ed1030-3997-4a16-9b12-0c78e3707f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661581906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.661581906
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.160390955
Short name T974
Test name
Test status
Simulation time 11655473 ps
CPU time 0.73 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:26 PM PDT 24
Peak memory 205972 kb
Host smart-bef37d16-c041-49d2-8c0b-2bdee2526ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160390955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.160390955
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3290791034
Short name T822
Test name
Test status
Simulation time 281721246 ps
CPU time 0.76 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:42:27 PM PDT 24
Peak memory 206264 kb
Host smart-09f76bea-0c14-4e85-8bac-0f99de2a5d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290791034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3290791034
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3444017169
Short name T559
Test name
Test status
Simulation time 6887381528 ps
CPU time 23.63 seconds
Started Jun 05 05:42:28 PM PDT 24
Finished Jun 05 05:42:52 PM PDT 24
Peak memory 233352 kb
Host smart-b73bbf18-04cf-4b0b-8fd7-9fee294cd1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444017169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3444017169
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1196558777
Short name T949
Test name
Test status
Simulation time 49821451 ps
CPU time 0.74 seconds
Started Jun 05 05:42:30 PM PDT 24
Finished Jun 05 05:42:32 PM PDT 24
Peak memory 205108 kb
Host smart-2eb6cb86-9b23-4b2b-8032-e76bf682457e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196558777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1196558777
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3135078179
Short name T617
Test name
Test status
Simulation time 402424184 ps
CPU time 3.25 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:42:42 PM PDT 24
Peak memory 224984 kb
Host smart-3c179223-fe4a-4923-b78b-b7ae4c5c39ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135078179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3135078179
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2460142978
Short name T300
Test name
Test status
Simulation time 15592541 ps
CPU time 0.79 seconds
Started Jun 05 05:42:29 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 207428 kb
Host smart-eb1aec08-dc17-43b3-b44d-944315b26c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460142978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2460142978
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1737275423
Short name T788
Test name
Test status
Simulation time 156901806 ps
CPU time 0.79 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:26 PM PDT 24
Peak memory 216308 kb
Host smart-8aa20e01-087a-4838-8bc5-5bcc01f1544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737275423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1737275423
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1455986510
Short name T369
Test name
Test status
Simulation time 23162945738 ps
CPU time 44.42 seconds
Started Jun 05 05:42:26 PM PDT 24
Finished Jun 05 05:43:11 PM PDT 24
Peak memory 251908 kb
Host smart-da152177-8f70-4252-84e9-a576b3a9230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455986510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1455986510
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1219125507
Short name T234
Test name
Test status
Simulation time 6065045850 ps
CPU time 129.35 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 253572 kb
Host smart-32a0fc82-9b90-4103-a665-db42470cd522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219125507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1219125507
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3008790037
Short name T813
Test name
Test status
Simulation time 2382780695 ps
CPU time 27.63 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 241156 kb
Host smart-7284e7c6-875f-40e6-b9ea-e64056e27e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008790037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3008790037
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3940821629
Short name T875
Test name
Test status
Simulation time 776888925 ps
CPU time 5.57 seconds
Started Jun 05 05:42:33 PM PDT 24
Finished Jun 05 05:42:39 PM PDT 24
Peak memory 233132 kb
Host smart-e2867bb4-c2d6-4742-b79c-912ee41400ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940821629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3940821629
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2569472324
Short name T536
Test name
Test status
Simulation time 32399393519 ps
CPU time 79.92 seconds
Started Jun 05 05:42:27 PM PDT 24
Finished Jun 05 05:43:48 PM PDT 24
Peak memory 233196 kb
Host smart-7531d3ae-6b0a-44ca-b3fa-025269f17676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569472324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2569472324
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.279128576
Short name T231
Test name
Test status
Simulation time 285305635 ps
CPU time 3.11 seconds
Started Jun 05 05:42:28 PM PDT 24
Finished Jun 05 05:42:32 PM PDT 24
Peak memory 224900 kb
Host smart-3393d72e-e048-414d-89f9-bf8d22810237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279128576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.279128576
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2541269461
Short name T802
Test name
Test status
Simulation time 1807262090 ps
CPU time 8.99 seconds
Started Jun 05 05:42:29 PM PDT 24
Finished Jun 05 05:42:39 PM PDT 24
Peak memory 240628 kb
Host smart-1263ea59-c6b0-4786-aa87-b777fae931b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541269461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2541269461
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3259166191
Short name T343
Test name
Test status
Simulation time 812263995 ps
CPU time 10.15 seconds
Started Jun 05 05:42:27 PM PDT 24
Finished Jun 05 05:42:38 PM PDT 24
Peak memory 219552 kb
Host smart-451c72cd-5c27-4151-bc66-85b87237fc6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3259166191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3259166191
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.79897456
Short name T432
Test name
Test status
Simulation time 12781814640 ps
CPU time 9.06 seconds
Started Jun 05 05:42:31 PM PDT 24
Finished Jun 05 05:42:41 PM PDT 24
Peak memory 220048 kb
Host smart-d9861c78-0550-45cc-9fac-1b5282134b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79897456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.79897456
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.387689122
Short name T792
Test name
Test status
Simulation time 3929185691 ps
CPU time 5.14 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 216836 kb
Host smart-be116b3c-ecc7-46e5-b3a4-1fc5b950f167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387689122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.387689122
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2267722460
Short name T302
Test name
Test status
Simulation time 113311568 ps
CPU time 1.54 seconds
Started Jun 05 05:42:30 PM PDT 24
Finished Jun 05 05:42:32 PM PDT 24
Peak memory 216852 kb
Host smart-c707e825-d50b-4d6e-a0e6-89de055fbc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267722460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2267722460
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2552696363
Short name T335
Test name
Test status
Simulation time 130098336 ps
CPU time 0.76 seconds
Started Jun 05 05:42:30 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 206256 kb
Host smart-24726ca3-0e8a-49b4-9cb0-9f805e58ded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552696363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2552696363
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3260296540
Short name T495
Test name
Test status
Simulation time 5653733345 ps
CPU time 16.72 seconds
Started Jun 05 05:42:25 PM PDT 24
Finished Jun 05 05:42:43 PM PDT 24
Peak memory 240852 kb
Host smart-c7aec92e-f975-46c3-9b2a-91cf676ccdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260296540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3260296540
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4154803513
Short name T552
Test name
Test status
Simulation time 15782131 ps
CPU time 0.71 seconds
Started Jun 05 05:41:08 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 205744 kb
Host smart-6e6f4934-ccb1-4af5-9e0a-db84b3522b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154803513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
154803513
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.272478237
Short name T84
Test name
Test status
Simulation time 85003551 ps
CPU time 2.36 seconds
Started Jun 05 05:40:57 PM PDT 24
Finished Jun 05 05:41:01 PM PDT 24
Peak memory 225128 kb
Host smart-0fec31e8-e075-46e6-8867-69260abc0e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272478237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.272478237
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1323077902
Short name T826
Test name
Test status
Simulation time 72283090 ps
CPU time 0.86 seconds
Started Jun 05 05:40:56 PM PDT 24
Finished Jun 05 05:40:57 PM PDT 24
Peak memory 206952 kb
Host smart-3797baae-201d-4433-a1c9-1b1dde8115e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323077902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1323077902
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1472780968
Short name T27
Test name
Test status
Simulation time 44607241134 ps
CPU time 89.75 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 249592 kb
Host smart-de6a6867-77b1-4f96-ac75-b72d9b43500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472780968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1472780968
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4091173719
Short name T724
Test name
Test status
Simulation time 409540600560 ps
CPU time 392.13 seconds
Started Jun 05 05:41:00 PM PDT 24
Finished Jun 05 05:47:34 PM PDT 24
Peak memory 249916 kb
Host smart-7443d892-6f0a-43f8-a370-b5cc59ffad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091173719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4091173719
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1401545136
Short name T650
Test name
Test status
Simulation time 693058451 ps
CPU time 7.91 seconds
Started Jun 05 05:40:58 PM PDT 24
Finished Jun 05 05:41:08 PM PDT 24
Peak memory 249492 kb
Host smart-abb844a3-90f6-4e75-b80c-70b100298dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401545136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1401545136
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1120386269
Short name T181
Test name
Test status
Simulation time 197043790 ps
CPU time 3.69 seconds
Started Jun 05 05:40:58 PM PDT 24
Finished Jun 05 05:41:03 PM PDT 24
Peak memory 225076 kb
Host smart-08b30990-624c-4e80-8bc5-69587ccac4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120386269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1120386269
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4265238989
Short name T840
Test name
Test status
Simulation time 6262957240 ps
CPU time 63.51 seconds
Started Jun 05 05:40:58 PM PDT 24
Finished Jun 05 05:42:02 PM PDT 24
Peak memory 249496 kb
Host smart-dd78dcb0-a142-4f4f-832a-98840e637307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265238989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4265238989
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3230219402
Short name T361
Test name
Test status
Simulation time 47598651 ps
CPU time 1.08 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:41:02 PM PDT 24
Peak memory 217064 kb
Host smart-de0822b8-c04c-4414-bc81-220c11dd5684
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230219402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3230219402
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.276371827
Short name T1
Test name
Test status
Simulation time 2312013480 ps
CPU time 8.23 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 233200 kb
Host smart-e5b07553-cbd5-4132-9ad4-59878653666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276371827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
276371827
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.10770582
Short name T187
Test name
Test status
Simulation time 2741579775 ps
CPU time 4.04 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:41:05 PM PDT 24
Peak memory 224996 kb
Host smart-a0c05fba-e2d9-4848-9d7a-1deb0570b77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10770582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.10770582
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.781702696
Short name T939
Test name
Test status
Simulation time 3703318366 ps
CPU time 11.73 seconds
Started Jun 05 05:41:02 PM PDT 24
Finished Jun 05 05:41:15 PM PDT 24
Peak memory 223384 kb
Host smart-a4e57b0a-c6df-4a50-8f2f-d18eaded96c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=781702696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.781702696
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.411776954
Short name T59
Test name
Test status
Simulation time 34602723 ps
CPU time 1.03 seconds
Started Jun 05 05:41:00 PM PDT 24
Finished Jun 05 05:41:03 PM PDT 24
Peak memory 235108 kb
Host smart-ebd1215b-dffb-402b-a9db-0a02f27fabe4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411776954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.411776954
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2913364470
Short name T149
Test name
Test status
Simulation time 37819925303 ps
CPU time 307.67 seconds
Started Jun 05 05:40:57 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 266104 kb
Host smart-72049a75-b633-448f-b151-86015ece9bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913364470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2913364470
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2531812593
Short name T588
Test name
Test status
Simulation time 19297011874 ps
CPU time 24.71 seconds
Started Jun 05 05:40:57 PM PDT 24
Finished Jun 05 05:41:23 PM PDT 24
Peak memory 216888 kb
Host smart-5451d75d-d056-4d89-9b2e-2f6d8de25897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531812593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2531812593
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2475547628
Short name T333
Test name
Test status
Simulation time 500249122 ps
CPU time 3.97 seconds
Started Jun 05 05:40:57 PM PDT 24
Finished Jun 05 05:41:02 PM PDT 24
Peak memory 216704 kb
Host smart-ec76b314-8f8b-4c72-bedd-325a21e66f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475547628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2475547628
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2122953264
Short name T554
Test name
Test status
Simulation time 39095363 ps
CPU time 2.27 seconds
Started Jun 05 05:40:59 PM PDT 24
Finished Jun 05 05:41:03 PM PDT 24
Peak memory 216304 kb
Host smart-b1aaaf7f-90a6-49fa-8759-299e43c24c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122953264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2122953264
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1994026314
Short name T324
Test name
Test status
Simulation time 31087422 ps
CPU time 0.79 seconds
Started Jun 05 05:40:58 PM PDT 24
Finished Jun 05 05:41:00 PM PDT 24
Peak memory 206240 kb
Host smart-212aa52a-8f2b-42e3-a52a-fb67388d0766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994026314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1994026314
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1354214546
Short name T784
Test name
Test status
Simulation time 1749986782 ps
CPU time 6.2 seconds
Started Jun 05 05:40:55 PM PDT 24
Finished Jun 05 05:41:02 PM PDT 24
Peak memory 233160 kb
Host smart-57910f1b-62f4-4920-b99a-054e3a2b6a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354214546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1354214546
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1941256771
Short name T975
Test name
Test status
Simulation time 56860007 ps
CPU time 0.76 seconds
Started Jun 05 05:42:31 PM PDT 24
Finished Jun 05 05:42:33 PM PDT 24
Peak memory 206096 kb
Host smart-aec9424e-2e7c-4509-96e4-3b8efe4933bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941256771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1941256771
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3275225198
Short name T436
Test name
Test status
Simulation time 3473237528 ps
CPU time 16.9 seconds
Started Jun 05 05:42:30 PM PDT 24
Finished Jun 05 05:42:48 PM PDT 24
Peak memory 225036 kb
Host smart-4362fedb-b6ba-4c60-b766-76a9b3476d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275225198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3275225198
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.724852766
Short name T337
Test name
Test status
Simulation time 84761308 ps
CPU time 0.8 seconds
Started Jun 05 05:42:33 PM PDT 24
Finished Jun 05 05:42:34 PM PDT 24
Peak memory 206968 kb
Host smart-371f8506-0c51-40af-b6c0-949388a03788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724852766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.724852766
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4003632334
Short name T46
Test name
Test status
Simulation time 5472089636 ps
CPU time 27.61 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:43:06 PM PDT 24
Peak memory 241384 kb
Host smart-34432446-4212-4692-b0cf-fa8e7c87c840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003632334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4003632334
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3070573704
Short name T201
Test name
Test status
Simulation time 178584973729 ps
CPU time 452.08 seconds
Started Jun 05 05:42:30 PM PDT 24
Finished Jun 05 05:50:03 PM PDT 24
Peak memory 251208 kb
Host smart-606e4f73-7ca4-48e2-9ec3-f7e8af7dbf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070573704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3070573704
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1786054734
Short name T171
Test name
Test status
Simulation time 48248751387 ps
CPU time 487.62 seconds
Started Jun 05 05:42:31 PM PDT 24
Finished Jun 05 05:50:39 PM PDT 24
Peak memory 251448 kb
Host smart-93b7d96b-8c16-4985-9f85-e7b9a4b1e255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786054734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1786054734
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1795119793
Short name T133
Test name
Test status
Simulation time 494960516 ps
CPU time 6.31 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:42:45 PM PDT 24
Peak memory 224952 kb
Host smart-d27f21e0-ce30-4daa-9849-5258ac24254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795119793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1795119793
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.852557980
Short name T622
Test name
Test status
Simulation time 872236531 ps
CPU time 8.92 seconds
Started Jun 05 05:42:27 PM PDT 24
Finished Jun 05 05:42:37 PM PDT 24
Peak memory 224884 kb
Host smart-59806dfb-7197-4a22-84f1-9e05cc9b3409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852557980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.852557980
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4010965292
Short name T481
Test name
Test status
Simulation time 3737995329 ps
CPU time 35.03 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:43:08 PM PDT 24
Peak memory 239960 kb
Host smart-8a9ee69b-53d6-4e4e-91f2-b1c3088bd2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010965292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4010965292
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2469638425
Short name T809
Test name
Test status
Simulation time 523529076 ps
CPU time 5.88 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:42:38 PM PDT 24
Peak memory 233148 kb
Host smart-9b3c9dd5-9128-493d-9571-52f47b2ed89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469638425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2469638425
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1884423926
Short name T547
Test name
Test status
Simulation time 14260165256 ps
CPU time 11.86 seconds
Started Jun 05 05:42:31 PM PDT 24
Finished Jun 05 05:42:44 PM PDT 24
Peak memory 233072 kb
Host smart-f444cff5-8229-4e4b-9f8e-5ace69cbc1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884423926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1884423926
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.705986880
Short name T687
Test name
Test status
Simulation time 1430875907 ps
CPU time 10.05 seconds
Started Jun 05 05:42:31 PM PDT 24
Finished Jun 05 05:42:42 PM PDT 24
Peak memory 220780 kb
Host smart-febbb2f1-1e8a-4778-b2b6-c6de2aa14436
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=705986880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.705986880
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2866388539
Short name T351
Test name
Test status
Simulation time 151409932 ps
CPU time 1.12 seconds
Started Jun 05 05:42:29 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 215820 kb
Host smart-b56a6f8d-3f9c-4f2f-968c-a5c398573302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866388539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2866388539
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3793753428
Short name T592
Test name
Test status
Simulation time 7684809917 ps
CPU time 5.04 seconds
Started Jun 05 05:42:31 PM PDT 24
Finished Jun 05 05:42:37 PM PDT 24
Peak memory 216764 kb
Host smart-2734bc24-7b85-4398-b604-49a0a7fa7c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793753428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3793753428
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2675663707
Short name T574
Test name
Test status
Simulation time 1375305132 ps
CPU time 5.3 seconds
Started Jun 05 05:42:29 PM PDT 24
Finished Jun 05 05:42:35 PM PDT 24
Peak memory 216772 kb
Host smart-ee0bc42b-5f69-4b96-b2bc-6c15b1746d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675663707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2675663707
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2069173591
Short name T913
Test name
Test status
Simulation time 2189135893 ps
CPU time 5.34 seconds
Started Jun 05 05:42:27 PM PDT 24
Finished Jun 05 05:42:33 PM PDT 24
Peak memory 216904 kb
Host smart-46d05260-3d24-4bfd-a691-380806dffcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069173591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2069173591
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1316082931
Short name T459
Test name
Test status
Simulation time 167133271 ps
CPU time 0.88 seconds
Started Jun 05 05:42:29 PM PDT 24
Finished Jun 05 05:42:30 PM PDT 24
Peak memory 206244 kb
Host smart-6d9c399f-444e-4075-aead-a3cb1afe69ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316082931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1316082931
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.509812498
Short name T878
Test name
Test status
Simulation time 22097116978 ps
CPU time 24.47 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:42:57 PM PDT 24
Peak memory 241328 kb
Host smart-9578f0d7-425c-4732-9be3-991e96ffb8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509812498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.509812498
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3257877649
Short name T375
Test name
Test status
Simulation time 30746566 ps
CPU time 0.68 seconds
Started Jun 05 05:42:40 PM PDT 24
Finished Jun 05 05:42:41 PM PDT 24
Peak memory 205776 kb
Host smart-3f17c053-62c4-4a88-a664-15530b7c4213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257877649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3257877649
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.792414754
Short name T83
Test name
Test status
Simulation time 166563107 ps
CPU time 2.56 seconds
Started Jun 05 05:42:28 PM PDT 24
Finished Jun 05 05:42:31 PM PDT 24
Peak memory 224964 kb
Host smart-ad13d713-9efc-404a-8918-b6bd7646ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792414754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.792414754
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2365495125
Short name T962
Test name
Test status
Simulation time 22860980 ps
CPU time 0.81 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:42:34 PM PDT 24
Peak memory 206944 kb
Host smart-6275d5ef-3c4c-45b9-84dc-b369ae839d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365495125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2365495125
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2521606853
Short name T13
Test name
Test status
Simulation time 6903223936 ps
CPU time 34.63 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 249596 kb
Host smart-5ba8f75a-0cbf-4997-bbad-4e07633cec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521606853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2521606853
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.329203805
Short name T75
Test name
Test status
Simulation time 25201593936 ps
CPU time 268.32 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:47:06 PM PDT 24
Peak memory 249688 kb
Host smart-d0151abc-35dd-4016-b0fb-f80a6d622f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329203805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.329203805
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.702368939
Short name T507
Test name
Test status
Simulation time 37850896 ps
CPU time 3.49 seconds
Started Jun 05 05:42:39 PM PDT 24
Finished Jun 05 05:42:43 PM PDT 24
Peak memory 232944 kb
Host smart-99ec5f76-bc5c-4b7d-a047-7664fbc25ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702368939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.702368939
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3569109239
Short name T611
Test name
Test status
Simulation time 660659099 ps
CPU time 3.97 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:42 PM PDT 24
Peak memory 233156 kb
Host smart-a9f29de1-5a9a-4fec-ad9e-29df9dd25194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569109239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3569109239
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2043323251
Short name T863
Test name
Test status
Simulation time 12220497093 ps
CPU time 24.97 seconds
Started Jun 05 05:42:40 PM PDT 24
Finished Jun 05 05:43:06 PM PDT 24
Peak memory 233196 kb
Host smart-9a61813b-5219-4615-a61f-5646af9897b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043323251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2043323251
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2253672894
Short name T229
Test name
Test status
Simulation time 957543554 ps
CPU time 4.18 seconds
Started Jun 05 05:42:39 PM PDT 24
Finished Jun 05 05:42:44 PM PDT 24
Peak memory 233076 kb
Host smart-093bf70a-923e-4c74-969a-db60c3328c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253672894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2253672894
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1472071930
Short name T349
Test name
Test status
Simulation time 240972934 ps
CPU time 3.25 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:42:36 PM PDT 24
Peak memory 224972 kb
Host smart-2f037d25-c1b5-4b61-b042-cb1a5e51b5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472071930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1472071930
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3781025726
Short name T516
Test name
Test status
Simulation time 3436287174 ps
CPU time 18.57 seconds
Started Jun 05 05:42:29 PM PDT 24
Finished Jun 05 05:42:48 PM PDT 24
Peak memory 219180 kb
Host smart-82398e53-919e-41f0-bd55-00be1f05c917
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3781025726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3781025726
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3560959917
Short name T969
Test name
Test status
Simulation time 42556849745 ps
CPU time 527.16 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:51:25 PM PDT 24
Peak memory 297852 kb
Host smart-79df534b-bed2-46e0-855d-71e1dbb6b3c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560959917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3560959917
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2491539154
Short name T627
Test name
Test status
Simulation time 4309100297 ps
CPU time 8.09 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:46 PM PDT 24
Peak memory 216864 kb
Host smart-acf97379-fb35-4dc3-80e0-b9ab20f38f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491539154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2491539154
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1298849155
Short name T935
Test name
Test status
Simulation time 6593729392 ps
CPU time 14.84 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 216768 kb
Host smart-f3b0e6b3-c3d6-4b57-b721-56cdad81fba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298849155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1298849155
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3182269636
Short name T964
Test name
Test status
Simulation time 46073065 ps
CPU time 1.44 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 216792 kb
Host smart-c0ee0178-7465-4190-9ccd-797117bf6261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182269636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3182269636
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3364936387
Short name T888
Test name
Test status
Simulation time 21868864 ps
CPU time 0.78 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:42:33 PM PDT 24
Peak memory 206240 kb
Host smart-3e65ddd0-45c7-4db8-971f-876927231c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364936387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3364936387
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.842377238
Short name T781
Test name
Test status
Simulation time 1995008210 ps
CPU time 7.2 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 239056 kb
Host smart-bb28e41f-030e-4644-b38b-e740347e761a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842377238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.842377238
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1988685494
Short name T912
Test name
Test status
Simulation time 18422237 ps
CPU time 0.76 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:42:38 PM PDT 24
Peak memory 205728 kb
Host smart-0eda0758-046a-43cb-bfbb-ac9d32997ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988685494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1988685494
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2748964578
Short name T740
Test name
Test status
Simulation time 553209509 ps
CPU time 4.06 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:42 PM PDT 24
Peak memory 224988 kb
Host smart-b031688d-140e-47b2-9bd0-7609e0c3c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748964578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2748964578
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1178694679
Short name T760
Test name
Test status
Simulation time 18041561 ps
CPU time 0.78 seconds
Started Jun 05 05:42:34 PM PDT 24
Finished Jun 05 05:42:35 PM PDT 24
Peak memory 206948 kb
Host smart-b1837c5d-85bf-4149-b1ac-e34cbe1e348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178694679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1178694679
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4149879929
Short name T205
Test name
Test status
Simulation time 535014288730 ps
CPU time 459.59 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:50:17 PM PDT 24
Peak memory 268672 kb
Host smart-506dd304-45f8-40b1-823f-bb37238a2d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149879929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4149879929
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.518243492
Short name T162
Test name
Test status
Simulation time 53287610506 ps
CPU time 554.01 seconds
Started Jun 05 05:42:35 PM PDT 24
Finished Jun 05 05:51:49 PM PDT 24
Peak memory 249796 kb
Host smart-41d979ba-fd06-4d63-a987-e7dc6d43eece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518243492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.518243492
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3724234130
Short name T73
Test name
Test status
Simulation time 46103205469 ps
CPU time 157.12 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:45:15 PM PDT 24
Peak memory 266056 kb
Host smart-ff5f76e2-3298-4a54-abad-3b7f05de98bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724234130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3724234130
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1134792561
Short name T562
Test name
Test status
Simulation time 385277041 ps
CPU time 5.96 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:42:43 PM PDT 24
Peak memory 233168 kb
Host smart-3c0161d5-c266-46db-884e-8107a695c6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134792561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1134792561
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.388534804
Short name T732
Test name
Test status
Simulation time 131215582 ps
CPU time 3.33 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 224904 kb
Host smart-1fadac1a-7019-4ec4-aa3e-ce264d2d01b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388534804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.388534804
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3439588950
Short name T258
Test name
Test status
Simulation time 1581404979 ps
CPU time 10.72 seconds
Started Jun 05 05:42:35 PM PDT 24
Finished Jun 05 05:42:46 PM PDT 24
Peak memory 233108 kb
Host smart-4d066f2a-d6f2-4de1-ab24-fa3050dd9eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439588950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3439588950
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2348722659
Short name T943
Test name
Test status
Simulation time 324621862 ps
CPU time 5.49 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:43 PM PDT 24
Peak memory 241120 kb
Host smart-9e89d1ad-354e-4b1a-80de-ded9077451f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348722659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2348722659
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3186771375
Short name T737
Test name
Test status
Simulation time 228497851 ps
CPU time 3.82 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:42 PM PDT 24
Peak memory 224952 kb
Host smart-1e96efe7-125d-4a34-a509-60109c04ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186771375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3186771375
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2391644937
Short name T730
Test name
Test status
Simulation time 967700989 ps
CPU time 10.36 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:42:47 PM PDT 24
Peak memory 222688 kb
Host smart-892a419e-1849-45e4-9c06-7bb4f0d9c474
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2391644937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2391644937
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4087115418
Short name T478
Test name
Test status
Simulation time 234969140 ps
CPU time 1.16 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:42:39 PM PDT 24
Peak memory 207572 kb
Host smart-9ab8b23d-8023-4789-8a0e-862897a42df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087115418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4087115418
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2105776889
Short name T885
Test name
Test status
Simulation time 2427491038 ps
CPU time 15.38 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:42:52 PM PDT 24
Peak memory 216904 kb
Host smart-e1e78a67-8f8e-481c-9a6e-757e9be54ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105776889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2105776889
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1334423862
Short name T297
Test name
Test status
Simulation time 1778221159 ps
CPU time 6.77 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:42:46 PM PDT 24
Peak memory 216668 kb
Host smart-f51d77c8-34af-47d8-a9ed-87e5d9bfb73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334423862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1334423862
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.730784181
Short name T661
Test name
Test status
Simulation time 115910401 ps
CPU time 1.41 seconds
Started Jun 05 05:42:39 PM PDT 24
Finished Jun 05 05:42:42 PM PDT 24
Peak memory 208552 kb
Host smart-7d9f77a7-29ac-49f7-9aab-f15d0f7dff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730784181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.730784181
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2014488328
Short name T456
Test name
Test status
Simulation time 142608191 ps
CPU time 0.82 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 206256 kb
Host smart-daef56ac-a261-45d8-bcf6-68a357a0279a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014488328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2014488328
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3152326486
Short name T777
Test name
Test status
Simulation time 2174647335 ps
CPU time 5.66 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:42:45 PM PDT 24
Peak memory 233228 kb
Host smart-8708f791-5000-47c5-89f5-253307c7e99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152326486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3152326486
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4068666414
Short name T712
Test name
Test status
Simulation time 19099021 ps
CPU time 0.73 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:42:59 PM PDT 24
Peak memory 204952 kb
Host smart-4e39a65c-a51a-455d-9ebb-37c5208a6e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068666414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4068666414
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1257961260
Short name T857
Test name
Test status
Simulation time 327064964 ps
CPU time 2.43 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:42:41 PM PDT 24
Peak memory 224956 kb
Host smart-272e43b6-e3a1-493c-b094-64042d292f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257961260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1257961260
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1481737580
Short name T545
Test name
Test status
Simulation time 36384043 ps
CPU time 0.81 seconds
Started Jun 05 05:42:35 PM PDT 24
Finished Jun 05 05:42:36 PM PDT 24
Peak memory 206948 kb
Host smart-c78eccdb-fb86-4c1a-974b-a09a70035167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481737580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1481737580
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2945837393
Short name T904
Test name
Test status
Simulation time 2548104497 ps
CPU time 55.12 seconds
Started Jun 05 05:42:46 PM PDT 24
Finished Jun 05 05:43:41 PM PDT 24
Peak memory 249600 kb
Host smart-b8d2e441-a19b-4be2-8131-a5d157bf9abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945837393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2945837393
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1687724564
Short name T973
Test name
Test status
Simulation time 163156266153 ps
CPU time 387.58 seconds
Started Jun 05 05:42:40 PM PDT 24
Finished Jun 05 05:49:09 PM PDT 24
Peak memory 249732 kb
Host smart-203c820f-0fd2-4cbd-84b8-2b82efc11a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687724564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1687724564
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.142698578
Short name T225
Test name
Test status
Simulation time 22892102112 ps
CPU time 77.13 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:44:15 PM PDT 24
Peak memory 254656 kb
Host smart-ec645926-4d42-4f09-b4bb-096d8da8af28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142698578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.142698578
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.520030239
Short name T830
Test name
Test status
Simulation time 441041022 ps
CPU time 5.17 seconds
Started Jun 05 05:42:32 PM PDT 24
Finished Jun 05 05:42:38 PM PDT 24
Peak memory 233120 kb
Host smart-a1b93812-417e-4a94-93c5-655a54400efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520030239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.520030239
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3722001525
Short name T727
Test name
Test status
Simulation time 5878048772 ps
CPU time 16.69 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 233152 kb
Host smart-73579c5c-055e-4bed-b648-85cfab941d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722001525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3722001525
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3473435894
Short name T576
Test name
Test status
Simulation time 885423227 ps
CPU time 20.18 seconds
Started Jun 05 05:42:38 PM PDT 24
Finished Jun 05 05:42:59 PM PDT 24
Peak memory 249588 kb
Host smart-dfaf728e-f70a-440c-a8d1-ea222cac9771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473435894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3473435894
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2814535015
Short name T735
Test name
Test status
Simulation time 226609885 ps
CPU time 2.04 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 223548 kb
Host smart-9bf0f23f-e43f-4397-80eb-fc0ca9b467ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814535015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2814535015
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1848738682
Short name T705
Test name
Test status
Simulation time 210936856 ps
CPU time 3.16 seconds
Started Jun 05 05:42:35 PM PDT 24
Finished Jun 05 05:42:39 PM PDT 24
Peak memory 228500 kb
Host smart-29448c09-71e6-4534-85a7-35140c6b0571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848738682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1848738682
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3032042217
Short name T134
Test name
Test status
Simulation time 332881801 ps
CPU time 4.56 seconds
Started Jun 05 05:42:42 PM PDT 24
Finished Jun 05 05:42:48 PM PDT 24
Peak memory 220404 kb
Host smart-285f1c75-20d5-41bb-8b2b-b2e457e310f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3032042217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3032042217
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4002875344
Short name T189
Test name
Test status
Simulation time 2858801671 ps
CPU time 43.12 seconds
Started Jun 05 05:42:41 PM PDT 24
Finished Jun 05 05:43:25 PM PDT 24
Peak memory 234804 kb
Host smart-6b3f1639-4f04-45d2-80b6-5e3c9d7a2c04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002875344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4002875344
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3043442941
Short name T955
Test name
Test status
Simulation time 2673228666 ps
CPU time 24.36 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:43:02 PM PDT 24
Peak memory 216876 kb
Host smart-0a3a9420-4b95-443f-b13f-4336f8d70b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043442941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3043442941
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2711186224
Short name T417
Test name
Test status
Simulation time 7103900557 ps
CPU time 8.19 seconds
Started Jun 05 05:42:36 PM PDT 24
Finished Jun 05 05:42:45 PM PDT 24
Peak memory 216780 kb
Host smart-34f6972d-6ef1-48e9-b4d9-43484ec20176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711186224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2711186224
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2150742671
Short name T287
Test name
Test status
Simulation time 1992197163 ps
CPU time 3.14 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:41 PM PDT 24
Peak memory 216916 kb
Host smart-bf56eb12-b82d-4297-8779-17fd2781156d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150742671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2150742671
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2267120909
Short name T596
Test name
Test status
Simulation time 86082379 ps
CPU time 0.78 seconds
Started Jun 05 05:42:37 PM PDT 24
Finished Jun 05 05:42:39 PM PDT 24
Peak memory 206208 kb
Host smart-ee5c9efd-af15-4e67-b14d-dc6e1229daeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267120909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2267120909
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2360373828
Short name T273
Test name
Test status
Simulation time 13049182584 ps
CPU time 21.93 seconds
Started Jun 05 05:42:35 PM PDT 24
Finished Jun 05 05:42:58 PM PDT 24
Peak memory 241436 kb
Host smart-7e7c5093-6178-443c-bc9c-a677e82cfc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360373828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2360373828
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1211635378
Short name T441
Test name
Test status
Simulation time 35025991 ps
CPU time 0.72 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:42:59 PM PDT 24
Peak memory 205580 kb
Host smart-c584f39c-bf22-4fe3-8aca-048d81c8093e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211635378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1211635378
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1376453417
Short name T556
Test name
Test status
Simulation time 520475362 ps
CPU time 3.81 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:03 PM PDT 24
Peak memory 232984 kb
Host smart-a385f5ae-4940-4362-9e5c-41d69b0e9cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376453417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1376453417
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1152960893
Short name T395
Test name
Test status
Simulation time 16630029 ps
CPU time 0.79 seconds
Started Jun 05 05:42:46 PM PDT 24
Finished Jun 05 05:42:47 PM PDT 24
Peak memory 206892 kb
Host smart-0be01dc5-9944-4650-82d3-ccb20a279abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152960893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1152960893
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3800783596
Short name T244
Test name
Test status
Simulation time 1700104399 ps
CPU time 23.75 seconds
Started Jun 05 05:42:43 PM PDT 24
Finished Jun 05 05:43:07 PM PDT 24
Peak memory 224924 kb
Host smart-0b32bd7c-7563-4afa-8244-019688f489c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800783596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3800783596
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2584759222
Short name T49
Test name
Test status
Simulation time 495008121937 ps
CPU time 325.61 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:48:23 PM PDT 24
Peak memory 257728 kb
Host smart-0527df5f-6aee-4f7a-8b74-f46f93185445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584759222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2584759222
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.363887433
Short name T283
Test name
Test status
Simulation time 1575242253 ps
CPU time 8.92 seconds
Started Jun 05 05:42:44 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 224932 kb
Host smart-5342e070-2183-4096-8010-e5cc3d4efb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363887433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.363887433
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1368056464
Short name T267
Test name
Test status
Simulation time 1509654654 ps
CPU time 10.19 seconds
Started Jun 05 05:42:44 PM PDT 24
Finished Jun 05 05:42:55 PM PDT 24
Peak memory 224904 kb
Host smart-9adba5e6-a5cf-4d3b-be37-7b0801f76cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368056464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1368056464
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.253312514
Short name T7
Test name
Test status
Simulation time 5585398380 ps
CPU time 18.84 seconds
Started Jun 05 05:42:45 PM PDT 24
Finished Jun 05 05:43:04 PM PDT 24
Peak memory 225128 kb
Host smart-4aca73a1-f793-47c9-bae2-e1af3a9f2386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253312514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.253312514
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2598136974
Short name T708
Test name
Test status
Simulation time 909890731 ps
CPU time 2.81 seconds
Started Jun 05 05:42:43 PM PDT 24
Finished Jun 05 05:42:47 PM PDT 24
Peak memory 224936 kb
Host smart-3c093beb-e052-4d18-8bdf-2d13fef9de32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598136974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2598136974
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1831719427
Short name T845
Test name
Test status
Simulation time 1099900884 ps
CPU time 6.3 seconds
Started Jun 05 05:42:43 PM PDT 24
Finished Jun 05 05:42:50 PM PDT 24
Peak memory 224948 kb
Host smart-7c347c5a-5f26-4339-8743-b842e3e55e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831719427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1831719427
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1250830330
Short name T551
Test name
Test status
Simulation time 1643291712 ps
CPU time 15.13 seconds
Started Jun 05 05:42:46 PM PDT 24
Finished Jun 05 05:43:02 PM PDT 24
Peak memory 220592 kb
Host smart-062740a9-fa68-467f-9d84-e1b19899da12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1250830330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1250830330
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4157614745
Short name T206
Test name
Test status
Simulation time 233368394591 ps
CPU time 660.2 seconds
Started Jun 05 05:42:43 PM PDT 24
Finished Jun 05 05:53:44 PM PDT 24
Peak memory 267948 kb
Host smart-ce41771e-2608-4c16-921c-3924bff601ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157614745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4157614745
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2203045385
Short name T759
Test name
Test status
Simulation time 308747814 ps
CPU time 2.13 seconds
Started Jun 05 05:42:44 PM PDT 24
Finished Jun 05 05:42:47 PM PDT 24
Peak memory 216920 kb
Host smart-d6112a9b-1e7c-4831-a239-f1c888625c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203045385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2203045385
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2695001834
Short name T579
Test name
Test status
Simulation time 11114972 ps
CPU time 0.69 seconds
Started Jun 05 05:42:41 PM PDT 24
Finished Jun 05 05:42:42 PM PDT 24
Peak memory 206056 kb
Host smart-f0885fad-1ab4-4aeb-b763-2e95e0e9a898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695001834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2695001834
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3356597573
Short name T353
Test name
Test status
Simulation time 56769980 ps
CPU time 0.94 seconds
Started Jun 05 05:42:40 PM PDT 24
Finished Jun 05 05:42:42 PM PDT 24
Peak memory 207412 kb
Host smart-0dce15d8-de70-4ee4-9c77-1d36551e30cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356597573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3356597573
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3445647563
Short name T614
Test name
Test status
Simulation time 55376723 ps
CPU time 0.74 seconds
Started Jun 05 05:42:45 PM PDT 24
Finished Jun 05 05:42:47 PM PDT 24
Peak memory 206248 kb
Host smart-06a347f5-676b-4aaf-aeac-bc4483a01a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445647563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3445647563
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3145331848
Short name T565
Test name
Test status
Simulation time 833190581 ps
CPU time 3.2 seconds
Started Jun 05 05:42:43 PM PDT 24
Finished Jun 05 05:42:48 PM PDT 24
Peak memory 224964 kb
Host smart-29e4fcd2-4105-4838-8218-94d3018f8142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145331848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3145331848
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1101297917
Short name T959
Test name
Test status
Simulation time 12630807 ps
CPU time 0.73 seconds
Started Jun 05 05:42:43 PM PDT 24
Finished Jun 05 05:42:44 PM PDT 24
Peak memory 206092 kb
Host smart-564e1e9d-46b8-4dd9-bce9-c7a399f1507f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101297917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1101297917
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3603925664
Short name T245
Test name
Test status
Simulation time 448494737 ps
CPU time 6.17 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:43:04 PM PDT 24
Peak memory 224768 kb
Host smart-b104fc1a-fbe2-43ef-ad9b-ffb3aece83da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603925664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3603925664
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4118271333
Short name T714
Test name
Test status
Simulation time 74712522 ps
CPU time 0.8 seconds
Started Jun 05 05:42:44 PM PDT 24
Finished Jun 05 05:42:46 PM PDT 24
Peak memory 206952 kb
Host smart-7f24d6af-bccb-4a2c-a814-f6061541f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118271333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4118271333
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.28407898
Short name T421
Test name
Test status
Simulation time 693519926 ps
CPU time 14.61 seconds
Started Jun 05 05:42:42 PM PDT 24
Finished Jun 05 05:42:58 PM PDT 24
Peak memory 236152 kb
Host smart-06b9f9ed-d7b7-45a8-83aa-efea3776af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28407898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.28407898
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3055735219
Short name T532
Test name
Test status
Simulation time 9017734027 ps
CPU time 141.22 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:45:19 PM PDT 24
Peak memory 273376 kb
Host smart-93052dc1-ad9e-4152-90b2-7f97aa0e1680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055735219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3055735219
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1845434677
Short name T164
Test name
Test status
Simulation time 3982265563 ps
CPU time 52.92 seconds
Started Jun 05 05:42:44 PM PDT 24
Finished Jun 05 05:43:38 PM PDT 24
Peak memory 238404 kb
Host smart-8923b836-0b33-4cb6-817d-884b22b35592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845434677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1845434677
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2637966078
Short name T71
Test name
Test status
Simulation time 316019913 ps
CPU time 3.66 seconds
Started Jun 05 05:42:46 PM PDT 24
Finished Jun 05 05:42:50 PM PDT 24
Peak memory 224860 kb
Host smart-db5340a2-f873-452e-b51a-2a0818a66717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637966078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2637966078
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3613291125
Short name T892
Test name
Test status
Simulation time 126660620 ps
CPU time 2.46 seconds
Started Jun 05 05:42:42 PM PDT 24
Finished Jun 05 05:42:45 PM PDT 24
Peak memory 232956 kb
Host smart-f6e8749c-6ed7-47a7-8d21-a79a91c638d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613291125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3613291125
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1390899654
Short name T685
Test name
Test status
Simulation time 97666771 ps
CPU time 3.63 seconds
Started Jun 05 05:42:44 PM PDT 24
Finished Jun 05 05:42:48 PM PDT 24
Peak memory 227912 kb
Host smart-6c7bce91-474b-46af-891c-e2e282238546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390899654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1390899654
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.132314419
Short name T739
Test name
Test status
Simulation time 3814724810 ps
CPU time 5.99 seconds
Started Jun 05 05:42:41 PM PDT 24
Finished Jun 05 05:42:47 PM PDT 24
Peak memory 224972 kb
Host smart-02c6e5cb-4e3d-4cd4-bfa3-448aefd19280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132314419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.132314419
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1368262354
Short name T953
Test name
Test status
Simulation time 616231393 ps
CPU time 3.78 seconds
Started Jun 05 05:42:43 PM PDT 24
Finished Jun 05 05:42:48 PM PDT 24
Peak memory 220664 kb
Host smart-b41f993e-c64b-49da-95c1-e63581c3a883
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1368262354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1368262354
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2935604998
Short name T151
Test name
Test status
Simulation time 90669529 ps
CPU time 0.98 seconds
Started Jun 05 05:42:44 PM PDT 24
Finished Jun 05 05:42:46 PM PDT 24
Peak memory 207276 kb
Host smart-9e49cca6-1502-4b6b-8852-5b73f2be6108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935604998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2935604998
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3504299664
Short name T452
Test name
Test status
Simulation time 1847772832 ps
CPU time 8.6 seconds
Started Jun 05 05:42:41 PM PDT 24
Finished Jun 05 05:42:50 PM PDT 24
Peak memory 216828 kb
Host smart-98d45594-317b-41f5-9470-553a403b78b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504299664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3504299664
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1564115789
Short name T80
Test name
Test status
Simulation time 440966073 ps
CPU time 1.33 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:01 PM PDT 24
Peak memory 207244 kb
Host smart-d4c714a8-99fb-4309-b43d-72aa73f97c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564115789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1564115789
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3267503882
Short name T467
Test name
Test status
Simulation time 14604477 ps
CPU time 0.81 seconds
Started Jun 05 05:42:46 PM PDT 24
Finished Jun 05 05:42:47 PM PDT 24
Peak memory 206268 kb
Host smart-55b7db82-da9f-4b52-bca5-fddc27b40b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267503882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3267503882
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.311901490
Short name T561
Test name
Test status
Simulation time 12082449 ps
CPU time 0.74 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:00 PM PDT 24
Peak memory 205800 kb
Host smart-d713b36d-85b3-4b8d-87bc-d253dfcffd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311901490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.311901490
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1544453730
Short name T960
Test name
Test status
Simulation time 2963475492 ps
CPU time 5.22 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:43:02 PM PDT 24
Peak memory 233056 kb
Host smart-984dd247-7a9d-4f1d-b918-48dc17a0e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544453730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1544453730
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3292136215
Short name T490
Test name
Test status
Simulation time 16288681 ps
CPU time 0.75 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:42:52 PM PDT 24
Peak memory 205128 kb
Host smart-0b86c249-e7db-4d9b-8b31-b21e332bbaf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292136215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3292136215
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.818238713
Short name T748
Test name
Test status
Simulation time 1085269503 ps
CPU time 5.99 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:42:58 PM PDT 24
Peak memory 224828 kb
Host smart-8200f140-a3a7-4ca7-8d29-b4b8df509c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818238713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.818238713
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2962476013
Short name T480
Test name
Test status
Simulation time 20199876 ps
CPU time 0.79 seconds
Started Jun 05 05:42:46 PM PDT 24
Finished Jun 05 05:42:48 PM PDT 24
Peak memory 206964 kb
Host smart-81bf3920-f19a-4e2e-abfd-2ed26e2cedfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962476013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2962476013
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3527421695
Short name T948
Test name
Test status
Simulation time 181270318 ps
CPU time 4.01 seconds
Started Jun 05 05:42:48 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 224904 kb
Host smart-5b65c77c-b797-4b22-8c15-f2504526291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527421695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3527421695
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.705139456
Short name T175
Test name
Test status
Simulation time 13247387693 ps
CPU time 107.87 seconds
Started Jun 05 05:42:49 PM PDT 24
Finished Jun 05 05:44:38 PM PDT 24
Peak memory 238036 kb
Host smart-9a9b67c6-fb38-4793-99c7-83f9eccf17e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705139456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.705139456
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3545786319
Short name T624
Test name
Test status
Simulation time 31206477043 ps
CPU time 156.97 seconds
Started Jun 05 05:42:52 PM PDT 24
Finished Jun 05 05:45:30 PM PDT 24
Peak memory 249688 kb
Host smart-263e5264-8c0b-4e3e-b797-6b44eed627ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545786319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3545786319
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.830466647
Short name T278
Test name
Test status
Simulation time 1933714017 ps
CPU time 9.1 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:43:01 PM PDT 24
Peak memory 224744 kb
Host smart-cf4b7025-e31a-4960-a6f0-e217af212cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830466647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.830466647
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3742816766
Short name T776
Test name
Test status
Simulation time 9841621042 ps
CPU time 29.31 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:43:22 PM PDT 24
Peak memory 233236 kb
Host smart-ce511f6d-5202-494f-98bb-8984c3f1a952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742816766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3742816766
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2998729480
Short name T580
Test name
Test status
Simulation time 57907987471 ps
CPU time 126.99 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:44:59 PM PDT 24
Peak memory 233352 kb
Host smart-e8274dd8-ad92-4181-97a6-795424bcb9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998729480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2998729480
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2389429902
Short name T726
Test name
Test status
Simulation time 2980008209 ps
CPU time 11.35 seconds
Started Jun 05 05:42:49 PM PDT 24
Finished Jun 05 05:43:02 PM PDT 24
Peak memory 249072 kb
Host smart-862839a9-ce7e-42cf-8c49-f53576cae7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389429902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2389429902
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3856305123
Short name T509
Test name
Test status
Simulation time 70341632 ps
CPU time 2.28 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 232952 kb
Host smart-469e36b8-a45e-47d6-9cac-3d0a2a4612b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856305123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3856305123
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2750282805
Short name T654
Test name
Test status
Simulation time 1281018633 ps
CPU time 3.34 seconds
Started Jun 05 05:42:49 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 220396 kb
Host smart-641a67bd-4176-4c2c-871b-5dde1357552c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2750282805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2750282805
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.538864706
Short name T44
Test name
Test status
Simulation time 313129476288 ps
CPU time 268.65 seconds
Started Jun 05 05:42:49 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 249696 kb
Host smart-5eb3c452-c8d9-426f-a2cf-e872504b2dee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538864706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.538864706
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2545597012
Short name T72
Test name
Test status
Simulation time 3913176234 ps
CPU time 6.14 seconds
Started Jun 05 05:42:43 PM PDT 24
Finished Jun 05 05:42:49 PM PDT 24
Peak memory 217020 kb
Host smart-7017fe5a-d39b-47af-b7de-8c496ef93bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545597012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2545597012
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2597034778
Short name T758
Test name
Test status
Simulation time 13355132744 ps
CPU time 12.21 seconds
Started Jun 05 05:42:46 PM PDT 24
Finished Jun 05 05:42:59 PM PDT 24
Peak memory 216808 kb
Host smart-0cbc9582-6c32-4eb4-9487-959645348d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597034778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2597034778
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2135090315
Short name T5
Test name
Test status
Simulation time 375763432 ps
CPU time 6.08 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:42:58 PM PDT 24
Peak memory 216916 kb
Host smart-415c9b96-dc2e-4eca-b259-3138166c7a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135090315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2135090315
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2890125070
Short name T594
Test name
Test status
Simulation time 80346784 ps
CPU time 0.73 seconds
Started Jun 05 05:42:52 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 206248 kb
Host smart-7f4bf406-2e0e-4a17-adda-881063f10bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890125070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2890125070
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4260870757
Short name T977
Test name
Test status
Simulation time 17327424422 ps
CPU time 8.16 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:43:00 PM PDT 24
Peak memory 233196 kb
Host smart-6fe4b83b-ead3-4793-8b76-2bbb91dc4c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260870757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4260870757
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2698333309
Short name T305
Test name
Test status
Simulation time 43276817 ps
CPU time 0.7 seconds
Started Jun 05 05:42:49 PM PDT 24
Finished Jun 05 05:42:50 PM PDT 24
Peak memory 205744 kb
Host smart-eff92f5b-03d4-4457-9e64-e3a0221d7b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698333309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2698333309
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1192001891
Short name T668
Test name
Test status
Simulation time 1934089055 ps
CPU time 7.84 seconds
Started Jun 05 05:42:46 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 233208 kb
Host smart-167c5a97-a02e-4c06-96b3-3459804248b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192001891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1192001891
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.310344983
Short name T318
Test name
Test status
Simulation time 50736883 ps
CPU time 0.83 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 206924 kb
Host smart-a9253b59-f26c-41d0-aeee-1be310c567c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310344983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.310344983
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1357394740
Short name T26
Test name
Test status
Simulation time 16349522795 ps
CPU time 27.33 seconds
Started Jun 05 05:42:53 PM PDT 24
Finished Jun 05 05:43:21 PM PDT 24
Peak memory 236188 kb
Host smart-081bbb9b-fc01-4e6e-89bb-eb50133b734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357394740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1357394740
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4076067432
Short name T221
Test name
Test status
Simulation time 5152475329 ps
CPU time 55.08 seconds
Started Jun 05 05:42:52 PM PDT 24
Finished Jun 05 05:43:48 PM PDT 24
Peak memory 254176 kb
Host smart-ad885734-ddeb-4053-a59b-5c08ec2cad2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076067432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4076067432
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1463370513
Short name T972
Test name
Test status
Simulation time 4547468028 ps
CPU time 11.43 seconds
Started Jun 05 05:42:49 PM PDT 24
Finished Jun 05 05:43:01 PM PDT 24
Peak memory 241444 kb
Host smart-4a0cc06d-0a00-45b5-9d71-4c5bb1fd9bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463370513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1463370513
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1040133417
Short name T488
Test name
Test status
Simulation time 2722895849 ps
CPU time 22.81 seconds
Started Jun 05 05:42:49 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 233196 kb
Host smart-23ee28ef-80ec-434f-a70b-b716b9441604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040133417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1040133417
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3081168767
Short name T3
Test name
Test status
Simulation time 1474217011 ps
CPU time 3.59 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:42:55 PM PDT 24
Peak memory 233164 kb
Host smart-5f1baaac-2f31-40e5-b0e6-6e8acefb30ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081168767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3081168767
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1127430018
Short name T769
Test name
Test status
Simulation time 1757252608 ps
CPU time 7.49 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:42:59 PM PDT 24
Peak memory 233152 kb
Host smart-a20cc4c2-4f01-4721-b024-58b633e590ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127430018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1127430018
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1331294928
Short name T257
Test name
Test status
Simulation time 1806421353 ps
CPU time 4.98 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:42:56 PM PDT 24
Peak memory 224848 kb
Host smart-4c3562aa-9d2f-4a1a-bfbc-d0f6fda1a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331294928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1331294928
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2473458832
Short name T379
Test name
Test status
Simulation time 2227773265 ps
CPU time 6.26 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:42:58 PM PDT 24
Peak memory 220460 kb
Host smart-1867aef0-45dd-4562-a2e4-226b94d59ebb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2473458832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2473458832
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2082019843
Short name T238
Test name
Test status
Simulation time 29509648441 ps
CPU time 251.97 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 249724 kb
Host smart-597fc31a-7db1-4497-9d06-5eeb72dfdd72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082019843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2082019843
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2762480889
Short name T50
Test name
Test status
Simulation time 6574223453 ps
CPU time 34.23 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 216864 kb
Host smart-75d4c0bb-6d1e-4d3f-b555-56246af1ef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762480889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2762480889
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3186773092
Short name T958
Test name
Test status
Simulation time 1165898688 ps
CPU time 7.5 seconds
Started Jun 05 05:42:49 PM PDT 24
Finished Jun 05 05:42:57 PM PDT 24
Peak memory 216696 kb
Host smart-96c457d9-abc3-41e8-b22f-867013cc9434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186773092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3186773092
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2085754444
Short name T795
Test name
Test status
Simulation time 164824545 ps
CPU time 1.2 seconds
Started Jun 05 05:42:47 PM PDT 24
Finished Jun 05 05:42:49 PM PDT 24
Peak memory 208352 kb
Host smart-5ba31d3e-8167-41ee-a8e3-30a329bc1cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085754444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2085754444
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2645914399
Short name T656
Test name
Test status
Simulation time 17092713 ps
CPU time 0.77 seconds
Started Jun 05 05:42:52 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 206260 kb
Host smart-f338d974-9e15-4115-be53-15e0cfc4a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645914399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2645914399
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2254477961
Short name T474
Test name
Test status
Simulation time 3150146000 ps
CPU time 6.87 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:42:58 PM PDT 24
Peak memory 224960 kb
Host smart-7cd5ee3f-5c40-42eb-b9ed-2dfff697a067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254477961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2254477961
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1814807042
Short name T55
Test name
Test status
Simulation time 16629582 ps
CPU time 0.7 seconds
Started Jun 05 05:42:59 PM PDT 24
Finished Jun 05 05:43:01 PM PDT 24
Peak memory 205712 kb
Host smart-0828cbab-53a3-418d-8754-d3b5f38b5eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814807042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1814807042
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.26005342
Short name T590
Test name
Test status
Simulation time 728101717 ps
CPU time 7.24 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:06 PM PDT 24
Peak memory 220008 kb
Host smart-7d6b05cb-2b7b-4862-aa98-1417aa9968be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26005342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.26005342
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2303211843
Short name T422
Test name
Test status
Simulation time 50519532 ps
CPU time 0.75 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 206064 kb
Host smart-d8d415f9-fad9-422a-bb3f-70894c56583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303211843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2303211843
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3509563390
Short name T952
Test name
Test status
Simulation time 42283334342 ps
CPU time 45.74 seconds
Started Jun 05 05:42:59 PM PDT 24
Finished Jun 05 05:43:46 PM PDT 24
Peak memory 225148 kb
Host smart-bda17023-b8c8-4c09-94ff-679594b4bcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509563390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3509563390
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2644054039
Short name T20
Test name
Test status
Simulation time 68650101331 ps
CPU time 128.12 seconds
Started Jun 05 05:42:55 PM PDT 24
Finished Jun 05 05:45:04 PM PDT 24
Peak memory 249736 kb
Host smart-81f566bc-8c6c-4a96-8d27-78520cbd76f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644054039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2644054039
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1461738597
Short name T38
Test name
Test status
Simulation time 53088126 ps
CPU time 3.56 seconds
Started Jun 05 05:42:55 PM PDT 24
Finished Jun 05 05:42:59 PM PDT 24
Peak memory 233100 kb
Host smart-b66e9b54-0be8-48b8-9c39-6221b40b6803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461738597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1461738597
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2163541438
Short name T778
Test name
Test status
Simulation time 5501923872 ps
CPU time 16.96 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:43:14 PM PDT 24
Peak memory 233136 kb
Host smart-37b4b820-9458-4b87-a70d-349b31f29189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163541438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2163541438
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3533060234
Short name T791
Test name
Test status
Simulation time 11891695780 ps
CPU time 53.7 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:43:51 PM PDT 24
Peak memory 241356 kb
Host smart-0fa304aa-875c-48bf-9871-cf84a4ee063b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533060234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3533060234
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.295716807
Short name T469
Test name
Test status
Simulation time 5947213324 ps
CPU time 15.2 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:43:11 PM PDT 24
Peak memory 224908 kb
Host smart-541cf0de-05af-4eb8-a751-237728621511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295716807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.295716807
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3710710952
Short name T380
Test name
Test status
Simulation time 281625457 ps
CPU time 3.85 seconds
Started Jun 05 05:42:48 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 224940 kb
Host smart-0ce46fa4-8df1-4768-a28c-584c0672f5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710710952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3710710952
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.115692537
Short name T418
Test name
Test status
Simulation time 2946464063 ps
CPU time 7.38 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:06 PM PDT 24
Peak memory 222996 kb
Host smart-0a52ba68-b69d-4c73-98bf-8a3c708df24b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=115692537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.115692537
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1727144012
Short name T144
Test name
Test status
Simulation time 3472019779 ps
CPU time 30.41 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:29 PM PDT 24
Peak memory 225120 kb
Host smart-eed100d8-6623-458b-8b7c-ad29a8411294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727144012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1727144012
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3755280459
Short name T285
Test name
Test status
Simulation time 9174304914 ps
CPU time 44.85 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:43:36 PM PDT 24
Peak memory 216916 kb
Host smart-c60a6215-c434-4699-8bfa-329a94e6e154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755280459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3755280459
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2161119844
Short name T473
Test name
Test status
Simulation time 5252068548 ps
CPU time 8.79 seconds
Started Jun 05 05:42:53 PM PDT 24
Finished Jun 05 05:43:03 PM PDT 24
Peak memory 216804 kb
Host smart-b459cc04-1d5a-49a1-9c88-f86cc96324b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161119844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2161119844
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2119940524
Short name T485
Test name
Test status
Simulation time 254950526 ps
CPU time 1.47 seconds
Started Jun 05 05:42:50 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 216792 kb
Host smart-eaf73103-c36e-406c-9c78-11403aaffc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119940524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2119940524
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.865983602
Short name T882
Test name
Test status
Simulation time 37012854 ps
CPU time 0.8 seconds
Started Jun 05 05:42:51 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 206244 kb
Host smart-5cd2f44d-6480-4885-b83c-13bb8b40b639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865983602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.865983602
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1261930739
Short name T797
Test name
Test status
Simulation time 32581364421 ps
CPU time 21.55 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:43:18 PM PDT 24
Peak memory 224932 kb
Host smart-58ac08c9-3fcc-4abc-8524-1b598378c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261930739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1261930739
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4269507075
Short name T291
Test name
Test status
Simulation time 101921544 ps
CPU time 0.74 seconds
Started Jun 05 05:43:03 PM PDT 24
Finished Jun 05 05:43:04 PM PDT 24
Peak memory 205760 kb
Host smart-aab2937a-04fa-4e88-96d0-a702c527ff1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269507075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4269507075
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.272822921
Short name T745
Test name
Test status
Simulation time 3217346510 ps
CPU time 16.48 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 224960 kb
Host smart-b5dc2c49-9acc-47bb-b358-c4eabeed1293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272822921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.272822921
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3485479993
Short name T298
Test name
Test status
Simulation time 64305569 ps
CPU time 0.79 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:42:58 PM PDT 24
Peak memory 206892 kb
Host smart-3bb25723-2c34-4ab1-a493-294f79f790d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485479993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3485479993
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3404890482
Short name T340
Test name
Test status
Simulation time 928432776 ps
CPU time 11.39 seconds
Started Jun 05 05:43:00 PM PDT 24
Finished Jun 05 05:43:12 PM PDT 24
Peak memory 233112 kb
Host smart-0f4e2644-9818-4a9f-80ba-53b3b521e5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404890482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3404890482
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.121836592
Short name T527
Test name
Test status
Simulation time 4454761054 ps
CPU time 26.99 seconds
Started Jun 05 05:42:55 PM PDT 24
Finished Jun 05 05:43:22 PM PDT 24
Peak memory 241536 kb
Host smart-58bfaea8-b9b0-4fe3-851d-987c00fd83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121836592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.121836592
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2912443487
Short name T843
Test name
Test status
Simulation time 6877145131 ps
CPU time 16.74 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:15 PM PDT 24
Peak memory 237140 kb
Host smart-6e7d30de-5754-4b5b-8145-0de987bfcec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912443487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2912443487
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2780532317
Short name T848
Test name
Test status
Simulation time 1917987806 ps
CPU time 9.57 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:43:07 PM PDT 24
Peak memory 234564 kb
Host smart-d4d3c552-721e-43a4-89f9-df679cfc7453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780532317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2780532317
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3656083298
Short name T755
Test name
Test status
Simulation time 9342836195 ps
CPU time 22.71 seconds
Started Jun 05 05:43:00 PM PDT 24
Finished Jun 05 05:43:23 PM PDT 24
Peak memory 225004 kb
Host smart-d64115c1-7136-467a-b628-72932ed70b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656083298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3656083298
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2573525105
Short name T946
Test name
Test status
Simulation time 279052979 ps
CPU time 9.77 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:43:06 PM PDT 24
Peak memory 225076 kb
Host smart-28f736a7-b0d7-422c-8e90-862f40b64c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573525105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2573525105
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2443321842
Short name T236
Test name
Test status
Simulation time 801802157 ps
CPU time 8.03 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:43:06 PM PDT 24
Peak memory 249344 kb
Host smart-c5d4e00e-8d7f-4eb6-b5ae-5621f87b3f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443321842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2443321842
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.802692549
Short name T805
Test name
Test status
Simulation time 4546087355 ps
CPU time 11.95 seconds
Started Jun 05 05:42:57 PM PDT 24
Finished Jun 05 05:43:10 PM PDT 24
Peak memory 224960 kb
Host smart-342d1119-337e-498c-bfdf-a4d696df6bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802692549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.802692549
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.742936243
Short name T515
Test name
Test status
Simulation time 3229904430 ps
CPU time 11.75 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:43:09 PM PDT 24
Peak memory 223228 kb
Host smart-2a050781-f045-4e68-aa95-c45ef3870a24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=742936243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.742936243
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.757763778
Short name T260
Test name
Test status
Simulation time 41736143129 ps
CPU time 68.31 seconds
Started Jun 05 05:43:04 PM PDT 24
Finished Jun 05 05:44:13 PM PDT 24
Peak memory 250800 kb
Host smart-04dcc24d-d65c-413f-a964-b573703d154d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757763778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.757763778
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.552892710
Short name T920
Test name
Test status
Simulation time 13385384773 ps
CPU time 27.34 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 216904 kb
Host smart-486a6eaa-3d3f-4cbd-92e0-7444522cd581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552892710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.552892710
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3509636295
Short name T933
Test name
Test status
Simulation time 889318225 ps
CPU time 5.09 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:04 PM PDT 24
Peak memory 216692 kb
Host smart-ce4f9a25-434c-41f5-ad0d-1295dd573fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509636295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3509636295
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.539091862
Short name T289
Test name
Test status
Simulation time 515419108 ps
CPU time 1.85 seconds
Started Jun 05 05:42:59 PM PDT 24
Finished Jun 05 05:43:01 PM PDT 24
Peak memory 216844 kb
Host smart-b1fee383-73cc-40a3-aa06-de4b93e1eb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539091862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.539091862
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3984842777
Short name T816
Test name
Test status
Simulation time 47985031 ps
CPU time 0.85 seconds
Started Jun 05 05:42:56 PM PDT 24
Finished Jun 05 05:42:57 PM PDT 24
Peak memory 206248 kb
Host smart-42dcf7c9-20fb-4b69-8077-93c5e08a6cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984842777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3984842777
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.982852024
Short name T97
Test name
Test status
Simulation time 1429812144 ps
CPU time 2.51 seconds
Started Jun 05 05:42:58 PM PDT 24
Finished Jun 05 05:43:02 PM PDT 24
Peak memory 233160 kb
Host smart-b48832fd-e17c-42ad-a733-0014933655a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982852024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.982852024
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2941963300
Short name T54
Test name
Test status
Simulation time 13012423 ps
CPU time 0.74 seconds
Started Jun 05 05:41:05 PM PDT 24
Finished Jun 05 05:41:07 PM PDT 24
Peak memory 205740 kb
Host smart-ec36ecf6-42b5-492f-822c-366450daf332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941963300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
941963300
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2303454725
Short name T720
Test name
Test status
Simulation time 137282524 ps
CPU time 2.29 seconds
Started Jun 05 05:41:09 PM PDT 24
Finished Jun 05 05:41:12 PM PDT 24
Peak memory 233092 kb
Host smart-df63a023-72dc-42df-8714-a8de44c8f308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303454725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2303454725
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.57196975
Short name T655
Test name
Test status
Simulation time 77315752 ps
CPU time 0.8 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:08 PM PDT 24
Peak memory 206936 kb
Host smart-52cebd07-a967-434c-b217-1746167bfdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57196975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.57196975
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2196864522
Short name T247
Test name
Test status
Simulation time 2903896503 ps
CPU time 20.04 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:27 PM PDT 24
Peak memory 241436 kb
Host smart-6e0062c5-c483-4545-a0eb-fee992fed572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196864522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2196864522
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.392422465
Short name T226
Test name
Test status
Simulation time 21356133886 ps
CPU time 123.83 seconds
Started Jun 05 05:41:05 PM PDT 24
Finished Jun 05 05:43:10 PM PDT 24
Peak memory 257832 kb
Host smart-4ab3a1f5-bb5e-470c-896b-e6b3d17b3847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392422465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.392422465
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.618052966
Short name T263
Test name
Test status
Simulation time 25388000202 ps
CPU time 250.22 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:45:18 PM PDT 24
Peak memory 253288 kb
Host smart-c45b13f8-ce26-4b48-84b0-d5f502606810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618052966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
618052966
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.361318538
Short name T945
Test name
Test status
Simulation time 359734866 ps
CPU time 4.41 seconds
Started Jun 05 05:41:05 PM PDT 24
Finished Jun 05 05:41:10 PM PDT 24
Peak memory 233192 kb
Host smart-793cb92f-c8ba-41e9-acd1-e346c88e92ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361318538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.361318538
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1530080784
Short name T489
Test name
Test status
Simulation time 38976434 ps
CPU time 2.43 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:10 PM PDT 24
Peak memory 224900 kb
Host smart-3c3fb827-0fad-4885-8be0-3b5b4d0c8b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530080784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1530080784
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.133450584
Short name T749
Test name
Test status
Simulation time 2566434753 ps
CPU time 8.82 seconds
Started Jun 05 05:41:07 PM PDT 24
Finished Jun 05 05:41:17 PM PDT 24
Peak memory 233724 kb
Host smart-7537ada2-c251-4294-a5c6-699a3629a7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133450584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.133450584
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.902591459
Short name T22
Test name
Test status
Simulation time 13840770 ps
CPU time 1.06 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:08 PM PDT 24
Peak memory 218308 kb
Host smart-be0dd620-60e8-4fc2-ab42-2856d886e9f7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902591459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.902591459
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2776482878
Short name T841
Test name
Test status
Simulation time 140656998 ps
CPU time 2.19 seconds
Started Jun 05 05:41:07 PM PDT 24
Finished Jun 05 05:41:10 PM PDT 24
Peak memory 223564 kb
Host smart-6c9380b7-34e2-4752-bd8a-114737b0872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776482878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2776482878
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.128040246
Short name T410
Test name
Test status
Simulation time 4162453425 ps
CPU time 3.72 seconds
Started Jun 05 05:41:08 PM PDT 24
Finished Jun 05 05:41:13 PM PDT 24
Peak memory 224988 kb
Host smart-9f5e23ec-32d2-4bc3-bae7-ee5ee3f2f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128040246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.128040246
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1912132785
Short name T535
Test name
Test status
Simulation time 2266358626 ps
CPU time 9.23 seconds
Started Jun 05 05:41:05 PM PDT 24
Finished Jun 05 05:41:15 PM PDT 24
Peak memory 219664 kb
Host smart-c0b49c2c-1cf6-430e-947a-9e420ab485cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1912132785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1912132785
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3196772246
Short name T60
Test name
Test status
Simulation time 36327352 ps
CPU time 0.95 seconds
Started Jun 05 05:41:05 PM PDT 24
Finished Jun 05 05:41:08 PM PDT 24
Peak memory 235096 kb
Host smart-3df0d790-eaef-464c-bf5d-dba0feab5b77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196772246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3196772246
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3477486807
Short name T450
Test name
Test status
Simulation time 56734996 ps
CPU time 1.1 seconds
Started Jun 05 05:41:07 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 208332 kb
Host smart-ac2e0fc2-c7a2-4dc3-b80e-9bce5000804d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477486807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3477486807
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1397295675
Short name T666
Test name
Test status
Simulation time 4638972299 ps
CPU time 16.72 seconds
Started Jun 05 05:41:07 PM PDT 24
Finished Jun 05 05:41:25 PM PDT 24
Peak memory 216872 kb
Host smart-91b17fdf-8876-4078-b60f-b4a494bc3536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397295675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1397295675
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4118973830
Short name T373
Test name
Test status
Simulation time 42608322408 ps
CPU time 8.92 seconds
Started Jun 05 05:41:07 PM PDT 24
Finished Jun 05 05:41:17 PM PDT 24
Peak memory 216820 kb
Host smart-48138caf-31f6-44fc-b955-5f4a02189360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118973830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4118973830
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2370272325
Short name T694
Test name
Test status
Simulation time 33023547 ps
CPU time 0.72 seconds
Started Jun 05 05:41:08 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 206032 kb
Host smart-021d7df2-edce-4cea-ac0f-157bc96d144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370272325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2370272325
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3588168512
Short name T731
Test name
Test status
Simulation time 158374850 ps
CPU time 0.91 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:08 PM PDT 24
Peak memory 207272 kb
Host smart-12c73058-7b40-4e96-8622-a3791f57de3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588168512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3588168512
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3313548612
Short name T950
Test name
Test status
Simulation time 605474443 ps
CPU time 6.25 seconds
Started Jun 05 05:41:05 PM PDT 24
Finished Jun 05 05:41:13 PM PDT 24
Peak memory 233160 kb
Host smart-7b48dc26-6af9-49ea-9c81-9fd2d2f0d8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313548612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3313548612
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.546233151
Short name T883
Test name
Test status
Simulation time 13256005 ps
CPU time 0.76 seconds
Started Jun 05 05:43:01 PM PDT 24
Finished Jun 05 05:43:02 PM PDT 24
Peak memory 205724 kb
Host smart-3d4806d6-fb5f-4fa2-a301-ef0a6a6a8ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546233151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.546233151
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1402500218
Short name T646
Test name
Test status
Simulation time 993743574 ps
CPU time 5.47 seconds
Started Jun 05 05:43:04 PM PDT 24
Finished Jun 05 05:43:10 PM PDT 24
Peak memory 233084 kb
Host smart-914db331-fff5-48c9-8c9f-1ea7bde1699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402500218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1402500218
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.364946529
Short name T734
Test name
Test status
Simulation time 79956132 ps
CPU time 0.81 seconds
Started Jun 05 05:43:02 PM PDT 24
Finished Jun 05 05:43:04 PM PDT 24
Peak memory 205900 kb
Host smart-d398112c-7b11-4cac-9465-010e4243732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364946529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.364946529
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3286549713
Short name T804
Test name
Test status
Simulation time 53924028567 ps
CPU time 195.38 seconds
Started Jun 05 05:43:04 PM PDT 24
Finished Jun 05 05:46:21 PM PDT 24
Peak memory 253880 kb
Host smart-60ea7747-104e-498c-9011-f5ffa1126a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286549713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3286549713
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1107962352
Short name T733
Test name
Test status
Simulation time 10689456258 ps
CPU time 81.51 seconds
Started Jun 05 05:43:03 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 233296 kb
Host smart-6259b030-2932-4b08-9723-e15f1c94faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107962352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1107962352
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2973403780
Short name T951
Test name
Test status
Simulation time 4328850846 ps
CPU time 91.18 seconds
Started Jun 05 05:43:04 PM PDT 24
Finished Jun 05 05:44:36 PM PDT 24
Peak memory 257904 kb
Host smart-759f25b0-3278-4083-86be-47db7013049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973403780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2973403780
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4194311802
Short name T670
Test name
Test status
Simulation time 2092708252 ps
CPU time 10.22 seconds
Started Jun 05 05:43:02 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 238416 kb
Host smart-c776042b-8c84-497e-ad46-16a6f5a06334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194311802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4194311802
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3341488186
Short name T424
Test name
Test status
Simulation time 139136464 ps
CPU time 2.29 seconds
Started Jun 05 05:43:06 PM PDT 24
Finished Jun 05 05:43:09 PM PDT 24
Peak memory 233120 kb
Host smart-ce2ec903-25ec-4fea-bafb-dfdfd7ebed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341488186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3341488186
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.981525881
Short name T276
Test name
Test status
Simulation time 43713874933 ps
CPU time 85.55 seconds
Started Jun 05 05:43:03 PM PDT 24
Finished Jun 05 05:44:29 PM PDT 24
Peak memory 249540 kb
Host smart-966a0b55-900d-4265-b036-565bba96de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981525881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.981525881
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.385536892
Short name T928
Test name
Test status
Simulation time 2095153462 ps
CPU time 3.71 seconds
Started Jun 05 05:43:05 PM PDT 24
Finished Jun 05 05:43:09 PM PDT 24
Peak memory 224944 kb
Host smart-3ef7d702-8627-49f8-927e-47d71d366d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385536892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.385536892
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2478032959
Short name T269
Test name
Test status
Simulation time 4689806928 ps
CPU time 9.09 seconds
Started Jun 05 05:43:01 PM PDT 24
Finished Jun 05 05:43:11 PM PDT 24
Peak memory 233188 kb
Host smart-f220ac89-861d-427a-b9af-89d3133c6e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478032959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2478032959
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1005881979
Short name T779
Test name
Test status
Simulation time 3123037802 ps
CPU time 15.84 seconds
Started Jun 05 05:43:04 PM PDT 24
Finished Jun 05 05:43:20 PM PDT 24
Peak memory 223484 kb
Host smart-8728cbb1-d2c1-4db2-8839-81347927b786
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1005881979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1005881979
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.316907635
Short name T706
Test name
Test status
Simulation time 203284381 ps
CPU time 1.16 seconds
Started Jun 05 05:43:01 PM PDT 24
Finished Jun 05 05:43:03 PM PDT 24
Peak memory 215748 kb
Host smart-07396749-885b-46cb-8ced-efc0c06fe572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316907635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.316907635
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1361241818
Short name T623
Test name
Test status
Simulation time 7795321399 ps
CPU time 40.39 seconds
Started Jun 05 05:43:02 PM PDT 24
Finished Jun 05 05:43:43 PM PDT 24
Peak memory 217088 kb
Host smart-d3f06100-a51b-4015-a386-154c9486bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361241818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1361241818
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3918000829
Short name T549
Test name
Test status
Simulation time 1635018350 ps
CPU time 2.18 seconds
Started Jun 05 05:43:02 PM PDT 24
Finished Jun 05 05:43:05 PM PDT 24
Peak memory 208136 kb
Host smart-46e859e6-fc5d-4bc2-80ff-1e15f984faff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918000829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3918000829
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3577872586
Short name T391
Test name
Test status
Simulation time 269960021 ps
CPU time 1.36 seconds
Started Jun 05 05:43:01 PM PDT 24
Finished Jun 05 05:43:03 PM PDT 24
Peak memory 208612 kb
Host smart-55c8e808-7d49-4024-a69e-2acdf2f080d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577872586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3577872586
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.775353757
Short name T454
Test name
Test status
Simulation time 170178732 ps
CPU time 0.9 seconds
Started Jun 05 05:43:05 PM PDT 24
Finished Jun 05 05:43:06 PM PDT 24
Peak memory 206252 kb
Host smart-e69e6aaf-b7c6-4f6d-9e3a-f3fa8bec3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775353757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.775353757
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1690757910
Short name T167
Test name
Test status
Simulation time 4821961050 ps
CPU time 9.93 seconds
Started Jun 05 05:43:02 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 233192 kb
Host smart-ef78983f-53d8-43ec-9d56-a1bf582fe3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690757910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1690757910
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1158396806
Short name T370
Test name
Test status
Simulation time 93011139 ps
CPU time 0.72 seconds
Started Jun 05 05:43:12 PM PDT 24
Finished Jun 05 05:43:14 PM PDT 24
Peak memory 205120 kb
Host smart-81dae694-e26c-41c5-a86c-5ebc73ba08cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158396806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1158396806
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1098946595
Short name T196
Test name
Test status
Simulation time 215716328 ps
CPU time 3.05 seconds
Started Jun 05 05:43:03 PM PDT 24
Finished Jun 05 05:43:07 PM PDT 24
Peak memory 224980 kb
Host smart-4f72799b-156d-4b4b-be11-8704480e115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098946595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1098946595
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2995123077
Short name T386
Test name
Test status
Simulation time 76449529 ps
CPU time 0.77 seconds
Started Jun 05 05:43:06 PM PDT 24
Finished Jun 05 05:43:07 PM PDT 24
Peak memory 205928 kb
Host smart-3c7b4cf1-153f-45fc-a6ef-9e1b68088899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995123077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2995123077
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2089736994
Short name T40
Test name
Test status
Simulation time 944885689 ps
CPU time 9.34 seconds
Started Jun 05 05:43:04 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 217964 kb
Host smart-4c587432-616f-4df9-aaba-3a6830af57ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089736994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2089736994
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2189175963
Short name T36
Test name
Test status
Simulation time 306355487 ps
CPU time 4.37 seconds
Started Jun 05 05:43:00 PM PDT 24
Finished Jun 05 05:43:05 PM PDT 24
Peak memory 224948 kb
Host smart-360ee377-7c60-422f-8f7d-039a823b0e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189175963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2189175963
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2273708260
Short name T506
Test name
Test status
Simulation time 4256788331 ps
CPU time 40.09 seconds
Started Jun 05 05:43:08 PM PDT 24
Finished Jun 05 05:43:49 PM PDT 24
Peak memory 233180 kb
Host smart-00a373ef-c8e4-4a6a-9d87-553e0c7d6309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273708260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2273708260
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3581850772
Short name T688
Test name
Test status
Simulation time 276458076 ps
CPU time 2.63 seconds
Started Jun 05 05:43:01 PM PDT 24
Finished Jun 05 05:43:05 PM PDT 24
Peak memory 224992 kb
Host smart-c86cc1db-a1c6-4e6d-b420-dbce58788656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581850772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3581850772
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.217240020
Short name T256
Test name
Test status
Simulation time 3558463912 ps
CPU time 12.57 seconds
Started Jun 05 05:43:05 PM PDT 24
Finished Jun 05 05:43:18 PM PDT 24
Peak memory 233212 kb
Host smart-5eeb4ba0-45b7-4f79-b1c0-c48fcce68fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217240020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.217240020
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1058623523
Short name T785
Test name
Test status
Simulation time 2868517482 ps
CPU time 8.45 seconds
Started Jun 05 05:43:03 PM PDT 24
Finished Jun 05 05:43:12 PM PDT 24
Peak memory 219092 kb
Host smart-b77a57dd-bd2d-43ff-9ffd-ca483a37eebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058623523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1058623523
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3176032361
Short name T743
Test name
Test status
Simulation time 494489680 ps
CPU time 6.07 seconds
Started Jun 05 05:43:02 PM PDT 24
Finished Jun 05 05:43:08 PM PDT 24
Peak memory 223244 kb
Host smart-a8db88d5-9ea6-41e6-830a-e961e6115610
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3176032361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3176032361
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.170567094
Short name T907
Test name
Test status
Simulation time 12015176426 ps
CPU time 37.2 seconds
Started Jun 05 05:43:03 PM PDT 24
Finished Jun 05 05:43:41 PM PDT 24
Peak memory 216912 kb
Host smart-4668af06-970e-48e7-bd98-bf91a48b9506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170567094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.170567094
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3685679558
Short name T609
Test name
Test status
Simulation time 6499572024 ps
CPU time 5.48 seconds
Started Jun 05 05:43:06 PM PDT 24
Finished Jun 05 05:43:12 PM PDT 24
Peak memory 216848 kb
Host smart-89431016-8869-4ce8-ac51-1280cd7b4599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685679558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3685679558
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1877903840
Short name T553
Test name
Test status
Simulation time 489566137 ps
CPU time 2.3 seconds
Started Jun 05 05:43:07 PM PDT 24
Finished Jun 05 05:43:10 PM PDT 24
Peak memory 216828 kb
Host smart-6581c029-f189-4d85-b439-473b5b94155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877903840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1877903840
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.246432579
Short name T336
Test name
Test status
Simulation time 14361726 ps
CPU time 0.7 seconds
Started Jun 05 05:43:03 PM PDT 24
Finished Jun 05 05:43:04 PM PDT 24
Peak memory 205944 kb
Host smart-3c86a6c3-0fea-4059-b034-b27f7a1ea057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246432579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.246432579
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.515340985
Short name T537
Test name
Test status
Simulation time 5370836788 ps
CPU time 15.62 seconds
Started Jun 05 05:43:04 PM PDT 24
Finished Jun 05 05:43:20 PM PDT 24
Peak memory 240812 kb
Host smart-4bc8397c-ee5a-443a-83f8-65fa5011e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515340985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.515340985
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3862755614
Short name T750
Test name
Test status
Simulation time 22599729 ps
CPU time 0.74 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:10 PM PDT 24
Peak memory 205736 kb
Host smart-3536d42e-29de-4a36-a466-36235129618b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862755614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3862755614
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3400552063
Short name T600
Test name
Test status
Simulation time 151588043 ps
CPU time 2.68 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:12 PM PDT 24
Peak memory 224972 kb
Host smart-a4c0b3e1-29e9-46ef-852f-21b87baea65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400552063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3400552063
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2639139333
Short name T371
Test name
Test status
Simulation time 36180503 ps
CPU time 0.79 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:11 PM PDT 24
Peak memory 207292 kb
Host smart-6bc12365-d66c-4ed9-a0a4-e29065769c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639139333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2639139333
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2445065622
Short name T213
Test name
Test status
Simulation time 18342946386 ps
CPU time 100.49 seconds
Started Jun 05 05:43:12 PM PDT 24
Finished Jun 05 05:44:53 PM PDT 24
Peak memory 257768 kb
Host smart-d453aebf-6f24-49ee-9a42-e91f8f961029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445065622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2445065622
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1641576418
Short name T662
Test name
Test status
Simulation time 11732108711 ps
CPU time 87.95 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 250080 kb
Host smart-7ee8abdd-b4b9-4591-8101-fe5963342692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641576418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1641576418
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3414711955
Short name T18
Test name
Test status
Simulation time 63992020390 ps
CPU time 206.31 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:46:37 PM PDT 24
Peak memory 250260 kb
Host smart-0b9fb37c-64de-4216-9373-36a21c489e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414711955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3414711955
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2858562867
Short name T284
Test name
Test status
Simulation time 1298051203 ps
CPU time 14.51 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:24 PM PDT 24
Peak memory 249564 kb
Host smart-01db5563-e68b-43aa-b432-6a6450f0bf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858562867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2858562867
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.588820322
Short name T578
Test name
Test status
Simulation time 128111491 ps
CPU time 2.9 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 233104 kb
Host smart-c30eacda-923c-4e64-a1e1-e7f48c5c6f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588820322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.588820322
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1556380566
Short name T360
Test name
Test status
Simulation time 621271871 ps
CPU time 2.32 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:12 PM PDT 24
Peak memory 223668 kb
Host smart-942c7754-d636-4825-95e5-cfe95e21411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556380566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1556380566
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.435925416
Short name T871
Test name
Test status
Simulation time 1229316402 ps
CPU time 3.55 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:14 PM PDT 24
Peak memory 233136 kb
Host smart-03fe5f76-31db-4da0-86af-3034d832043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435925416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.435925416
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1637759922
Short name T860
Test name
Test status
Simulation time 4181876630 ps
CPU time 13.26 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:23 PM PDT 24
Peak memory 241160 kb
Host smart-10ad1dcc-3113-4fb3-8be9-f258217b0b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637759922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1637759922
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2004234778
Short name T653
Test name
Test status
Simulation time 732499175 ps
CPU time 4.68 seconds
Started Jun 05 05:43:07 PM PDT 24
Finished Jun 05 05:43:12 PM PDT 24
Peak memory 223304 kb
Host smart-9e762937-72a1-4123-9615-f01c181c2eaf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2004234778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2004234778
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1452037353
Short name T130
Test name
Test status
Simulation time 129397472944 ps
CPU time 1030.34 seconds
Started Jun 05 05:43:11 PM PDT 24
Finished Jun 05 06:00:22 PM PDT 24
Peak memory 273556 kb
Host smart-645965dd-a257-43d8-a51e-2c69de7c3c47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452037353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1452037353
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1168721110
Short name T631
Test name
Test status
Simulation time 6413227881 ps
CPU time 22.97 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:34 PM PDT 24
Peak memory 216852 kb
Host smart-5a1c9eec-d347-4236-ab8b-564434924200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168721110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1168721110
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1895214158
Short name T756
Test name
Test status
Simulation time 4942833987 ps
CPU time 8.39 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:18 PM PDT 24
Peak memory 216804 kb
Host smart-b3db8745-23cd-4aea-ad5d-4355e95bd2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895214158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1895214158
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.410523142
Short name T381
Test name
Test status
Simulation time 117056825 ps
CPU time 4.99 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:15 PM PDT 24
Peak memory 217184 kb
Host smart-acc34d8f-cee2-426f-8e00-6a2580218570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410523142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.410523142
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1660180203
Short name T317
Test name
Test status
Simulation time 26992810 ps
CPU time 0.7 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:11 PM PDT 24
Peak memory 205960 kb
Host smart-82c9ea83-9272-4343-8984-8ed4a80b7682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660180203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1660180203
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1772199644
Short name T766
Test name
Test status
Simulation time 2538498469 ps
CPU time 3.28 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:14 PM PDT 24
Peak memory 236316 kb
Host smart-8c4a0ad9-bc5f-43d8-8b7a-84703652fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772199644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1772199644
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2708819814
Short name T573
Test name
Test status
Simulation time 23187046 ps
CPU time 0.79 seconds
Started Jun 05 05:43:12 PM PDT 24
Finished Jun 05 05:43:14 PM PDT 24
Peak memory 205720 kb
Host smart-4400ecaa-c10d-4d7e-9a2a-c87fabca5020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708819814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2708819814
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4267276392
Short name T719
Test name
Test status
Simulation time 210018787 ps
CPU time 2.72 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 233168 kb
Host smart-f65229ce-b6df-49a5-a0ea-72d54b004641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267276392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4267276392
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2297150120
Short name T851
Test name
Test status
Simulation time 16958373 ps
CPU time 0.75 seconds
Started Jun 05 05:43:12 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 206272 kb
Host smart-54dec322-1f86-4cca-ac85-db775dc6c9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297150120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2297150120
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.200172832
Short name T752
Test name
Test status
Simulation time 10872095963 ps
CPU time 20.9 seconds
Started Jun 05 05:43:12 PM PDT 24
Finished Jun 05 05:43:34 PM PDT 24
Peak memory 224972 kb
Host smart-da2b4e0f-89ca-4bde-9a27-9d5a61facb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200172832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.200172832
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2379864547
Short name T387
Test name
Test status
Simulation time 18659261752 ps
CPU time 94.44 seconds
Started Jun 05 05:43:12 PM PDT 24
Finished Jun 05 05:44:47 PM PDT 24
Peak memory 240896 kb
Host smart-99ef280e-48a8-4e10-a6ca-e938446bc445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379864547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2379864547
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2049468840
Short name T17
Test name
Test status
Simulation time 45582961706 ps
CPU time 362.03 seconds
Started Jun 05 05:43:11 PM PDT 24
Finished Jun 05 05:49:14 PM PDT 24
Peak memory 256084 kb
Host smart-6d60fcf4-bc9d-44f0-8a12-12391b94b216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049468840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2049468840
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2913310855
Short name T584
Test name
Test status
Simulation time 199303435 ps
CPU time 4.47 seconds
Started Jun 05 05:43:09 PM PDT 24
Finished Jun 05 05:43:14 PM PDT 24
Peak memory 224940 kb
Host smart-519365f9-1aac-4e65-b3b7-e537d882af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913310855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2913310855
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3115850560
Short name T613
Test name
Test status
Simulation time 410984731 ps
CPU time 5.88 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:17 PM PDT 24
Peak memory 224904 kb
Host smart-6946f317-73c8-4a5e-a8bf-48865869209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115850560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3115850560
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2571863481
Short name T692
Test name
Test status
Simulation time 4172129056 ps
CPU time 19.97 seconds
Started Jun 05 05:43:14 PM PDT 24
Finished Jun 05 05:43:34 PM PDT 24
Peak memory 233252 kb
Host smart-a4450149-e7f6-44bd-ab24-ca2fa4160dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571863481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2571863481
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2187748138
Short name T637
Test name
Test status
Simulation time 766932312 ps
CPU time 5.49 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:17 PM PDT 24
Peak memory 224944 kb
Host smart-318a7c60-fa0f-4087-9587-4394f1f63e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187748138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2187748138
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2663621940
Short name T903
Test name
Test status
Simulation time 166457457623 ps
CPU time 30.14 seconds
Started Jun 05 05:43:11 PM PDT 24
Finished Jun 05 05:43:42 PM PDT 24
Peak memory 241388 kb
Host smart-6dc5021a-0f18-4783-8b45-29d2a8cab2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663621940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2663621940
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2218487108
Short name T798
Test name
Test status
Simulation time 202881577 ps
CPU time 3.42 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:43:19 PM PDT 24
Peak memory 219156 kb
Host smart-16de23c2-08d6-4987-ba70-41fa55c2a5f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2218487108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2218487108
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2365973157
Short name T321
Test name
Test status
Simulation time 354225459 ps
CPU time 2.7 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:43:19 PM PDT 24
Peak memory 216868 kb
Host smart-bcb4d6d8-a6c4-4497-a65f-c2722b978ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365973157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2365973157
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2739509324
Short name T356
Test name
Test status
Simulation time 8188127695 ps
CPU time 16.02 seconds
Started Jun 05 05:43:11 PM PDT 24
Finished Jun 05 05:43:28 PM PDT 24
Peak memory 216916 kb
Host smart-38a13723-8a9e-49f4-809a-6e9c1aac042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739509324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2739509324
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1148609367
Short name T753
Test name
Test status
Simulation time 41666840 ps
CPU time 0.72 seconds
Started Jun 05 05:43:11 PM PDT 24
Finished Jun 05 05:43:12 PM PDT 24
Peak memory 205992 kb
Host smart-11b1c0f8-65b3-4920-a8a8-32872dd30453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148609367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1148609367
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1840949693
Short name T292
Test name
Test status
Simulation time 141825568 ps
CPU time 0.71 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:43:17 PM PDT 24
Peak memory 206244 kb
Host smart-86cc91b2-71bc-491f-b51b-37932f62188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840949693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1840949693
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.506563247
Short name T271
Test name
Test status
Simulation time 530725100 ps
CPU time 5.6 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:17 PM PDT 24
Peak memory 233204 kb
Host smart-3d0e5bbe-3e3d-4189-b618-4a1427d559aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506563247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.506563247
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3660033716
Short name T673
Test name
Test status
Simulation time 69104354 ps
CPU time 0.73 seconds
Started Jun 05 05:43:17 PM PDT 24
Finished Jun 05 05:43:18 PM PDT 24
Peak memory 205728 kb
Host smart-9a254a42-22d6-4c53-b96f-284ce96bbdbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660033716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3660033716
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.652065817
Short name T430
Test name
Test status
Simulation time 196427078 ps
CPU time 3.21 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:43:19 PM PDT 24
Peak memory 224968 kb
Host smart-1badf7dd-b01b-4a9d-9dfd-615941d9d6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652065817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.652065817
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1894899983
Short name T312
Test name
Test status
Simulation time 39012449 ps
CPU time 0.78 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:12 PM PDT 24
Peak memory 206948 kb
Host smart-b541df4e-c917-4dc0-bd2b-5d4466076e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894899983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1894899983
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4268616369
Short name T606
Test name
Test status
Simulation time 5351811853 ps
CPU time 25.55 seconds
Started Jun 05 05:43:17 PM PDT 24
Finished Jun 05 05:43:43 PM PDT 24
Peak memory 234228 kb
Host smart-88657669-09b7-45a2-9773-a8bba87f7a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268616369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4268616369
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3470147118
Short name T24
Test name
Test status
Simulation time 625225470 ps
CPU time 10.54 seconds
Started Jun 05 05:43:19 PM PDT 24
Finished Jun 05 05:43:30 PM PDT 24
Peak memory 217804 kb
Host smart-3570bf1c-f5c3-4707-97e5-451443b2c60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470147118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3470147118
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3627779908
Short name T499
Test name
Test status
Simulation time 2560405882 ps
CPU time 45.52 seconds
Started Jun 05 05:43:17 PM PDT 24
Finished Jun 05 05:44:04 PM PDT 24
Peak memory 249736 kb
Host smart-9039b046-05a2-4d5d-ac65-3dbd7e8d1fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627779908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3627779908
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2860078148
Short name T39
Test name
Test status
Simulation time 272365048 ps
CPU time 5.46 seconds
Started Jun 05 05:43:16 PM PDT 24
Finished Jun 05 05:43:22 PM PDT 24
Peak memory 233172 kb
Host smart-367aacf2-989c-4deb-afed-e9d0539e46e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860078148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2860078148
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2070023450
Short name T909
Test name
Test status
Simulation time 1549882919 ps
CPU time 7.26 seconds
Started Jun 05 05:43:16 PM PDT 24
Finished Jun 05 05:43:24 PM PDT 24
Peak memory 224892 kb
Host smart-eb9b7921-22d1-464d-9b28-e359c9519536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070023450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2070023450
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3967875969
Short name T272
Test name
Test status
Simulation time 1983997881 ps
CPU time 14.23 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:43:30 PM PDT 24
Peak memory 249372 kb
Host smart-3994a82d-a309-44ee-8ca0-f683bf2b3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967875969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3967875969
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3614292996
Short name T261
Test name
Test status
Simulation time 128502685 ps
CPU time 3.01 seconds
Started Jun 05 05:43:21 PM PDT 24
Finished Jun 05 05:43:25 PM PDT 24
Peak memory 233164 kb
Host smart-19f22669-b83a-4221-ba05-524df6694681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614292996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3614292996
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3450218914
Short name T612
Test name
Test status
Simulation time 2214875776 ps
CPU time 9.84 seconds
Started Jun 05 05:43:16 PM PDT 24
Finished Jun 05 05:43:27 PM PDT 24
Peak memory 228400 kb
Host smart-024c2c09-daca-4d95-bc2a-be25bc72e8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450218914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3450218914
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1749453915
Short name T741
Test name
Test status
Simulation time 266774082 ps
CPU time 4.19 seconds
Started Jun 05 05:43:16 PM PDT 24
Finished Jun 05 05:43:21 PM PDT 24
Peak memory 223352 kb
Host smart-55a46817-a4bd-4fc3-8380-5b2335c4a00f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749453915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1749453915
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1652553683
Short name T176
Test name
Test status
Simulation time 3429095302 ps
CPU time 75.66 seconds
Started Jun 05 05:43:17 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 250480 kb
Host smart-7ef4b7a8-7d41-44d1-8181-2b15848acabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652553683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1652553683
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1393873721
Short name T290
Test name
Test status
Simulation time 5853173856 ps
CPU time 26.96 seconds
Started Jun 05 05:43:13 PM PDT 24
Finished Jun 05 05:43:41 PM PDT 24
Peak memory 220284 kb
Host smart-94fdc9b4-626a-46a8-ba40-96dea112dc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393873721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1393873721
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1142299538
Short name T81
Test name
Test status
Simulation time 1940160528 ps
CPU time 7.5 seconds
Started Jun 05 05:43:10 PM PDT 24
Finished Jun 05 05:43:18 PM PDT 24
Peak memory 216724 kb
Host smart-2a503b3c-f8da-4948-ac53-701c6ba5b34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142299538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1142299538
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3645436308
Short name T306
Test name
Test status
Simulation time 12275999 ps
CPU time 0.73 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:43:16 PM PDT 24
Peak memory 205988 kb
Host smart-b7e60c90-e6a9-47ea-ac55-ea37ae1f3bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645436308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3645436308
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2438567456
Short name T835
Test name
Test status
Simulation time 30956388 ps
CPU time 0.8 seconds
Started Jun 05 05:43:12 PM PDT 24
Finished Jun 05 05:43:13 PM PDT 24
Peak memory 206240 kb
Host smart-9e7295d3-5102-4eb3-8cf7-12bdccb667ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438567456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2438567456
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3769292236
Short name T625
Test name
Test status
Simulation time 4424499807 ps
CPU time 17.36 seconds
Started Jun 05 05:43:20 PM PDT 24
Finished Jun 05 05:43:38 PM PDT 24
Peak memory 238308 kb
Host smart-71508c3e-0e9e-4961-b842-34506d56c8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769292236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3769292236
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3364453240
Short name T956
Test name
Test status
Simulation time 16197161 ps
CPU time 0.75 seconds
Started Jun 05 05:43:19 PM PDT 24
Finished Jun 05 05:43:21 PM PDT 24
Peak memory 205384 kb
Host smart-f8263115-85ec-4b19-a3ba-deb810c63e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364453240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3364453240
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.620821030
Short name T2
Test name
Test status
Simulation time 364292630 ps
CPU time 2.32 seconds
Started Jun 05 05:43:18 PM PDT 24
Finished Jun 05 05:43:21 PM PDT 24
Peak memory 223716 kb
Host smart-2faec2ea-eae0-4dbb-9310-6a1e626c9530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620821030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.620821030
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1027810741
Short name T604
Test name
Test status
Simulation time 30352796 ps
CPU time 0.77 seconds
Started Jun 05 05:43:19 PM PDT 24
Finished Jun 05 05:43:20 PM PDT 24
Peak memory 206892 kb
Host smart-1b8aa34d-8468-425c-bdd2-3b66bfd100e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027810741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1027810741
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1598997040
Short name T207
Test name
Test status
Simulation time 8821124940 ps
CPU time 51.74 seconds
Started Jun 05 05:43:17 PM PDT 24
Finished Jun 05 05:44:09 PM PDT 24
Peak memory 255348 kb
Host smart-f3f09148-e35d-4bf2-b40d-aba1213338ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598997040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1598997040
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3426217699
Short name T514
Test name
Test status
Simulation time 13289129119 ps
CPU time 87.82 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 240876 kb
Host smart-1175bd82-25d3-4d48-bade-4fd9b92fb9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426217699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3426217699
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.560897323
Short name T212
Test name
Test status
Simulation time 198104160190 ps
CPU time 306.52 seconds
Started Jun 05 05:43:19 PM PDT 24
Finished Jun 05 05:48:26 PM PDT 24
Peak memory 251652 kb
Host smart-1dad2e1d-8c49-43ea-8139-4359c39a5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560897323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.560897323
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.228566862
Short name T492
Test name
Test status
Simulation time 283817142 ps
CPU time 3.44 seconds
Started Jun 05 05:43:20 PM PDT 24
Finished Jun 05 05:43:24 PM PDT 24
Peak memory 224952 kb
Host smart-31e6f087-23a6-404c-aa97-8e28b8f9deba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228566862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.228566862
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3861841785
Short name T915
Test name
Test status
Simulation time 79045951 ps
CPU time 3 seconds
Started Jun 05 05:43:19 PM PDT 24
Finished Jun 05 05:43:23 PM PDT 24
Peak memory 233132 kb
Host smart-5f94f013-b1b7-4515-8f20-2922a441eaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861841785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3861841785
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1251221689
Short name T483
Test name
Test status
Simulation time 183813731 ps
CPU time 3.98 seconds
Started Jun 05 05:43:18 PM PDT 24
Finished Jun 05 05:43:23 PM PDT 24
Peak memory 233144 kb
Host smart-4905fd06-c3bc-4518-a80e-4006ece8fdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251221689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1251221689
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1122228027
Short name T275
Test name
Test status
Simulation time 44192753 ps
CPU time 2.53 seconds
Started Jun 05 05:43:19 PM PDT 24
Finished Jun 05 05:43:22 PM PDT 24
Peak memory 224840 kb
Host smart-b17623ba-f38d-411a-986b-b780dd5b6e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122228027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1122228027
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.934110376
Short name T173
Test name
Test status
Simulation time 2000636067 ps
CPU time 8.23 seconds
Started Jun 05 05:43:18 PM PDT 24
Finished Jun 05 05:43:27 PM PDT 24
Peak memory 233192 kb
Host smart-54ff2ab8-2014-44cb-adc3-f148d7f78f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934110376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.934110376
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1399654334
Short name T780
Test name
Test status
Simulation time 190929145 ps
CPU time 5.06 seconds
Started Jun 05 05:43:18 PM PDT 24
Finished Jun 05 05:43:25 PM PDT 24
Peak memory 222780 kb
Host smart-724f400a-2ce8-4f2e-938b-00f5a10e57a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1399654334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1399654334
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.612652598
Short name T57
Test name
Test status
Simulation time 5485258562 ps
CPU time 28.3 seconds
Started Jun 05 05:43:18 PM PDT 24
Finished Jun 05 05:43:48 PM PDT 24
Peak memory 225132 kb
Host smart-0a25e593-e5aa-43d4-9188-5c96653489ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612652598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.612652598
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3019777012
Short name T864
Test name
Test status
Simulation time 2456247026 ps
CPU time 8.09 seconds
Started Jun 05 05:43:18 PM PDT 24
Finished Jun 05 05:43:27 PM PDT 24
Peak memory 217216 kb
Host smart-686e7b34-a8b4-4c7c-b42c-323ea948e19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019777012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3019777012
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1200494744
Short name T511
Test name
Test status
Simulation time 16052440 ps
CPU time 0.72 seconds
Started Jun 05 05:43:19 PM PDT 24
Finished Jun 05 05:43:21 PM PDT 24
Peak memory 206016 kb
Host smart-af94d668-0dd4-4503-8602-96662f88b7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200494744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1200494744
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1187655083
Short name T721
Test name
Test status
Simulation time 21785228 ps
CPU time 0.94 seconds
Started Jun 05 05:43:19 PM PDT 24
Finished Jun 05 05:43:21 PM PDT 24
Peak memory 207396 kb
Host smart-43f56474-c2c8-417f-926c-d1464f200fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187655083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1187655083
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1432533414
Short name T940
Test name
Test status
Simulation time 85047248 ps
CPU time 0.76 seconds
Started Jun 05 05:43:17 PM PDT 24
Finished Jun 05 05:43:18 PM PDT 24
Peak memory 206424 kb
Host smart-2f521131-f0b8-4723-958e-5b47aab1ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432533414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1432533414
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.571399173
Short name T184
Test name
Test status
Simulation time 1892438310 ps
CPU time 5.85 seconds
Started Jun 05 05:43:21 PM PDT 24
Finished Jun 05 05:43:28 PM PDT 24
Peak memory 224944 kb
Host smart-fc1ad4a0-63cb-46e8-80d0-4373b4262d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571399173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.571399173
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4273549980
Short name T570
Test name
Test status
Simulation time 13852070 ps
CPU time 0.73 seconds
Started Jun 05 05:43:27 PM PDT 24
Finished Jun 05 05:43:29 PM PDT 24
Peak memory 206076 kb
Host smart-2922e41c-207f-4bf0-8807-3df97b07d204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273549980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4273549980
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2670579377
Short name T385
Test name
Test status
Simulation time 91363776 ps
CPU time 2.46 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:28 PM PDT 24
Peak memory 233176 kb
Host smart-4c5b6a7f-e80c-4d6f-ad5c-f61012ddadf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670579377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2670579377
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2878269049
Short name T649
Test name
Test status
Simulation time 57504950 ps
CPU time 0.76 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:43:17 PM PDT 24
Peak memory 206936 kb
Host smart-aafc469d-457b-4844-aed4-e8a779dc8546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878269049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2878269049
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.38543058
Short name T675
Test name
Test status
Simulation time 15420379087 ps
CPU time 24.17 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:48 PM PDT 24
Peak memory 253944 kb
Host smart-38d3159e-644b-41ee-bc9a-e7bccfc68e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38543058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.38543058
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2095999984
Short name T220
Test name
Test status
Simulation time 49601609991 ps
CPU time 173.12 seconds
Started Jun 05 05:43:25 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 266120 kb
Host smart-b33338ad-7204-48da-a2ff-9649e414c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095999984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2095999984
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.232496298
Short name T965
Test name
Test status
Simulation time 48175537892 ps
CPU time 114.88 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:45:20 PM PDT 24
Peak memory 249704 kb
Host smart-f237d8b1-c253-4d7b-8559-f252644fa947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232496298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.232496298
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_intercept.21796964
Short name T918
Test name
Test status
Simulation time 1201747342 ps
CPU time 13.65 seconds
Started Jun 05 05:43:31 PM PDT 24
Finished Jun 05 05:43:45 PM PDT 24
Peak memory 233156 kb
Host smart-b5e3294a-40b2-4618-b243-b5e014f4cb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21796964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.21796964
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1500602704
Short name T681
Test name
Test status
Simulation time 5062666650 ps
CPU time 20.39 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:44 PM PDT 24
Peak memory 233184 kb
Host smart-93ee8f5a-5183-4b7a-8aa3-9cdebe9ab8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500602704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1500602704
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4058902453
Short name T70
Test name
Test status
Simulation time 1419337668 ps
CPU time 4.97 seconds
Started Jun 05 05:43:17 PM PDT 24
Finished Jun 05 05:43:23 PM PDT 24
Peak memory 241228 kb
Host smart-85183c87-35e1-4e34-9fe4-c497cd08cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058902453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.4058902453
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.400638215
Short name T477
Test name
Test status
Simulation time 9044740753 ps
CPU time 7.74 seconds
Started Jun 05 05:43:18 PM PDT 24
Finished Jun 05 05:43:27 PM PDT 24
Peak memory 225008 kb
Host smart-7e9d0830-8aae-460b-b23c-60e93fcab440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400638215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.400638215
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.934791724
Short name T936
Test name
Test status
Simulation time 380958221 ps
CPU time 6.49 seconds
Started Jun 05 05:43:27 PM PDT 24
Finished Jun 05 05:43:34 PM PDT 24
Peak memory 223388 kb
Host smart-aa54b7bc-972d-44db-a34c-d3ba93d2ba64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=934791724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.934791724
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1646342441
Short name T880
Test name
Test status
Simulation time 140840861290 ps
CPU time 510.8 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:51:56 PM PDT 24
Peak memory 274304 kb
Host smart-d8adbfd6-2181-41fb-b41f-8978c7608e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646342441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1646342441
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1561131526
Short name T568
Test name
Test status
Simulation time 10873698472 ps
CPU time 16.67 seconds
Started Jun 05 05:43:15 PM PDT 24
Finished Jun 05 05:43:33 PM PDT 24
Peak memory 220664 kb
Host smart-44833b6c-4f3e-468f-8395-130347a76419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561131526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1561131526
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2149912594
Short name T543
Test name
Test status
Simulation time 2803340963 ps
CPU time 8.43 seconds
Started Jun 05 05:43:17 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 216772 kb
Host smart-a496d069-b92e-4637-b0e8-46b84d77733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149912594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2149912594
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2257968061
Short name T440
Test name
Test status
Simulation time 111198782 ps
CPU time 1.86 seconds
Started Jun 05 05:43:18 PM PDT 24
Finished Jun 05 05:43:21 PM PDT 24
Peak memory 216848 kb
Host smart-8ef91191-d139-4d88-9d22-08cf45d06f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257968061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2257968061
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1571806779
Short name T14
Test name
Test status
Simulation time 61985999 ps
CPU time 0.88 seconds
Started Jun 05 05:43:21 PM PDT 24
Finished Jun 05 05:43:23 PM PDT 24
Peak memory 206256 kb
Host smart-9e924f4d-031e-43fb-864e-07332441efd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571806779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1571806779
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3724144939
Short name T626
Test name
Test status
Simulation time 39484244111 ps
CPU time 9.39 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:33 PM PDT 24
Peak memory 224968 kb
Host smart-948ccf2f-d452-4753-b82e-9e6a6792247f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724144939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3724144939
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3626203621
Short name T914
Test name
Test status
Simulation time 35032790 ps
CPU time 0.7 seconds
Started Jun 05 05:43:26 PM PDT 24
Finished Jun 05 05:43:28 PM PDT 24
Peak memory 205768 kb
Host smart-b8abdf62-96bb-413c-959b-f4e761c227ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626203621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3626203621
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1030756342
Short name T82
Test name
Test status
Simulation time 8798874789 ps
CPU time 17.86 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:43 PM PDT 24
Peak memory 224988 kb
Host smart-9a76ea65-078a-4c1c-805e-f11fedc23e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030756342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1030756342
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3252672012
Short name T938
Test name
Test status
Simulation time 28589300 ps
CPU time 0.77 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 206948 kb
Host smart-68c3dbb1-b838-4188-9e35-ef082cbe929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252672012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3252672012
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.867531686
Short name T833
Test name
Test status
Simulation time 85147621420 ps
CPU time 89.07 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:44:54 PM PDT 24
Peak memory 241404 kb
Host smart-9a8ce262-8645-48ca-ab7a-5d96e2d8c299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867531686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.867531686
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2035478960
Short name T230
Test name
Test status
Simulation time 46396237235 ps
CPU time 265.13 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:47:49 PM PDT 24
Peak memory 254800 kb
Host smart-0f409106-c4f6-43a5-bb05-a661a55f3fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035478960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2035478960
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1807062795
Short name T630
Test name
Test status
Simulation time 70089693571 ps
CPU time 78.93 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 249740 kb
Host smart-0cb3d297-4546-4cef-998e-7167e4d69b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807062795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1807062795
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3301598304
Short name T389
Test name
Test status
Simulation time 5043387932 ps
CPU time 13.89 seconds
Started Jun 05 05:43:26 PM PDT 24
Finished Jun 05 05:43:41 PM PDT 24
Peak memory 225016 kb
Host smart-37a0faab-7761-435e-906c-44222cb4f128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301598304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3301598304
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1926018378
Short name T839
Test name
Test status
Simulation time 71169284 ps
CPU time 3.51 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:27 PM PDT 24
Peak memory 233160 kb
Host smart-c50f1e36-52c3-425f-8d08-8a1c4d54c681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926018378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1926018378
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1908609646
Short name T643
Test name
Test status
Simulation time 72266294220 ps
CPU time 40.21 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:44:04 PM PDT 24
Peak memory 224988 kb
Host smart-1e035162-ab9e-4232-949b-569b40169b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908609646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1908609646
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3235119148
Short name T932
Test name
Test status
Simulation time 12350434363 ps
CPU time 6.76 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:32 PM PDT 24
Peak memory 233224 kb
Host smart-50057b16-a02b-42b8-bf4c-692967e27371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235119148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3235119148
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.687670151
Short name T575
Test name
Test status
Simulation time 512298585 ps
CPU time 2.79 seconds
Started Jun 05 05:43:30 PM PDT 24
Finished Jun 05 05:43:34 PM PDT 24
Peak memory 233164 kb
Host smart-a8a285e0-3da4-49a6-850c-f529d83a31bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687670151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.687670151
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3939723751
Short name T930
Test name
Test status
Simulation time 241358168 ps
CPU time 4.46 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:29 PM PDT 24
Peak memory 223240 kb
Host smart-f101c7e0-45f3-4d7e-bfa6-fac3df587952
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3939723751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3939723751
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.262697657
Short name T607
Test name
Test status
Simulation time 166079120 ps
CPU time 0.97 seconds
Started Jun 05 05:43:31 PM PDT 24
Finished Jun 05 05:43:33 PM PDT 24
Peak memory 207304 kb
Host smart-b9b622a4-3bcf-4f8c-8d22-2248e8adfcea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262697657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.262697657
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1187643405
Short name T458
Test name
Test status
Simulation time 29865393360 ps
CPU time 39.96 seconds
Started Jun 05 05:43:26 PM PDT 24
Finished Jun 05 05:44:08 PM PDT 24
Peak memory 216856 kb
Host smart-c38ffe26-ca79-4e19-8a87-3a5aadc998da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187643405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1187643405
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.646893717
Short name T497
Test name
Test status
Simulation time 1540505191 ps
CPU time 8.57 seconds
Started Jun 05 05:43:27 PM PDT 24
Finished Jun 05 05:43:37 PM PDT 24
Peak memory 216748 kb
Host smart-304c1ffb-9cef-475a-ab04-edbcd40324b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646893717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.646893717
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.794064185
Short name T377
Test name
Test status
Simulation time 249112272 ps
CPU time 6.1 seconds
Started Jun 05 05:43:26 PM PDT 24
Finished Jun 05 05:43:33 PM PDT 24
Peak memory 216784 kb
Host smart-db9fbcfe-8821-4c4f-a0f5-318cea39d4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794064185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.794064185
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3483423625
Short name T8
Test name
Test status
Simulation time 39192522 ps
CPU time 0.72 seconds
Started Jun 05 05:43:25 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 205988 kb
Host smart-a765a37d-98ad-41b4-ae18-53ff1fb936d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483423625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3483423625
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.900295840
Short name T268
Test name
Test status
Simulation time 5081893346 ps
CPU time 8.65 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:33 PM PDT 24
Peak memory 233236 kb
Host smart-62c7ded4-1b99-417c-9939-3d485266db91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900295840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.900295840
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2305724905
Short name T919
Test name
Test status
Simulation time 41199687 ps
CPU time 0.76 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 205724 kb
Host smart-965243fb-3250-4dcc-9012-abdb5f10aea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305724905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2305724905
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1983580595
Short name T461
Test name
Test status
Simulation time 62879113 ps
CPU time 2.28 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 224904 kb
Host smart-ec5b3c2e-40e2-43ae-8f36-fdc02ac381c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983580595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1983580595
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.608498734
Short name T699
Test name
Test status
Simulation time 34555116 ps
CPU time 0.79 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:25 PM PDT 24
Peak memory 206960 kb
Host smart-591e3e2f-56fc-4f66-92ae-0bce127dcc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608498734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.608498734
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.316961043
Short name T252
Test name
Test status
Simulation time 12837814134 ps
CPU time 75 seconds
Started Jun 05 05:43:26 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 252920 kb
Host smart-cfbb0a85-6b3d-461f-8abd-fe77ad6dfe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316961043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.316961043
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3942455837
Short name T671
Test name
Test status
Simulation time 30350099989 ps
CPU time 75.26 seconds
Started Jun 05 05:43:30 PM PDT 24
Finished Jun 05 05:44:46 PM PDT 24
Peak memory 250264 kb
Host smart-903228d9-d8c7-450f-ba07-6e168c4932d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942455837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3942455837
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2096045936
Short name T531
Test name
Test status
Simulation time 585462375 ps
CPU time 3.48 seconds
Started Jun 05 05:43:25 PM PDT 24
Finished Jun 05 05:43:30 PM PDT 24
Peak memory 224936 kb
Host smart-d0ee34ce-8e2a-43fc-9cdc-53cf9b634306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096045936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2096045936
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1653581319
Short name T817
Test name
Test status
Simulation time 361394149 ps
CPU time 6.95 seconds
Started Jun 05 05:43:26 PM PDT 24
Finished Jun 05 05:43:35 PM PDT 24
Peak memory 224936 kb
Host smart-68dd7260-1a0f-4cb8-9fa3-58c505533fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653581319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1653581319
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4058648131
Short name T48
Test name
Test status
Simulation time 2882442356 ps
CPU time 13.18 seconds
Started Jun 05 05:43:25 PM PDT 24
Finished Jun 05 05:43:39 PM PDT 24
Peak memory 250668 kb
Host smart-576589a9-8829-47ce-8160-4dade1fb443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058648131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4058648131
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.429424859
Short name T185
Test name
Test status
Simulation time 1106287091 ps
CPU time 6.65 seconds
Started Jun 05 05:43:30 PM PDT 24
Finished Jun 05 05:43:37 PM PDT 24
Peak memory 233160 kb
Host smart-2aaf110b-e726-4fec-a4c6-e5c20526162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429424859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.429424859
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2865902192
Short name T842
Test name
Test status
Simulation time 109326840 ps
CPU time 2.17 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:27 PM PDT 24
Peak memory 225112 kb
Host smart-ae687a34-2feb-4c7c-b972-a711f3c653bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865902192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2865902192
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3398514482
Short name T496
Test name
Test status
Simulation time 1748602517 ps
CPU time 5.48 seconds
Started Jun 05 05:43:26 PM PDT 24
Finished Jun 05 05:43:33 PM PDT 24
Peak memory 220452 kb
Host smart-bc4c9ffd-bd26-4b82-ba41-fda3b851be07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3398514482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3398514482
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.728371912
Short name T314
Test name
Test status
Simulation time 106504582 ps
CPU time 1.12 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:26 PM PDT 24
Peak memory 207668 kb
Host smart-4d4deaa2-7a62-403d-a50a-e8b89e4f1ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728371912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.728371912
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1665126723
Short name T642
Test name
Test status
Simulation time 1622088106 ps
CPU time 5.26 seconds
Started Jun 05 05:43:24 PM PDT 24
Finished Jun 05 05:43:31 PM PDT 24
Peak memory 216988 kb
Host smart-7875611c-2ae6-4086-964c-96c71b968e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665126723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1665126723
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4080695581
Short name T344
Test name
Test status
Simulation time 41206450675 ps
CPU time 19.33 seconds
Started Jun 05 05:43:26 PM PDT 24
Finished Jun 05 05:43:47 PM PDT 24
Peak memory 216836 kb
Host smart-6a8bc6ce-ec80-4d2f-a053-c8a3d3699001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080695581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4080695581
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.58791819
Short name T69
Test name
Test status
Simulation time 10146361 ps
CPU time 0.69 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:24 PM PDT 24
Peak memory 205948 kb
Host smart-c9ce0e79-ed2f-482c-9080-4a71075a1016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58791819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.58791819
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1413049501
Short name T773
Test name
Test status
Simulation time 177729069 ps
CPU time 0.92 seconds
Started Jun 05 05:43:25 PM PDT 24
Finished Jun 05 05:43:27 PM PDT 24
Peak memory 206240 kb
Host smart-3748d704-0c70-4a73-baa7-432624d75f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413049501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1413049501
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.99698835
Short name T896
Test name
Test status
Simulation time 54602407948 ps
CPU time 12.49 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:37 PM PDT 24
Peak memory 225064 kb
Host smart-8bef09e5-47f9-4725-b490-c214da2b8736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99698835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.99698835
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1851179224
Short name T644
Test name
Test status
Simulation time 11566648 ps
CPU time 0.75 seconds
Started Jun 05 05:43:31 PM PDT 24
Finished Jun 05 05:43:33 PM PDT 24
Peak memory 205760 kb
Host smart-bc907895-e39f-4fa3-aa1a-e7858ecba83e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851179224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1851179224
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2630223999
Short name T363
Test name
Test status
Simulation time 11913811606 ps
CPU time 29.73 seconds
Started Jun 05 05:43:32 PM PDT 24
Finished Jun 05 05:44:03 PM PDT 24
Peak memory 233220 kb
Host smart-1f8ddb43-8b4e-489c-ab3e-ce5fc38c0042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630223999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2630223999
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3186982282
Short name T790
Test name
Test status
Simulation time 45088417 ps
CPU time 0.8 seconds
Started Jun 05 05:43:23 PM PDT 24
Finished Jun 05 05:43:25 PM PDT 24
Peak memory 206980 kb
Host smart-33aa4d99-84b0-4c0e-b0f1-da402675c032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186982282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3186982282
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1682382898
Short name T419
Test name
Test status
Simulation time 23412182217 ps
CPU time 76.93 seconds
Started Jun 05 05:43:32 PM PDT 24
Finished Jun 05 05:44:50 PM PDT 24
Peak memory 253140 kb
Host smart-8b078ff8-831b-456b-a06c-1729ea083010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682382898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1682382898
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.5876796
Short name T128
Test name
Test status
Simulation time 52935581607 ps
CPU time 150.14 seconds
Started Jun 05 05:43:33 PM PDT 24
Finished Jun 05 05:46:04 PM PDT 24
Peak memory 251576 kb
Host smart-b08c6439-654d-4ed7-b1ce-149d6c46e8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5876796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.5876796
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3654104286
Short name T34
Test name
Test status
Simulation time 212551854444 ps
CPU time 243.34 seconds
Started Jun 05 05:43:32 PM PDT 24
Finished Jun 05 05:47:36 PM PDT 24
Peak memory 241476 kb
Host smart-50d923e6-ed2d-4dcb-911d-87cbec4642e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654104286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3654104286
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.231755770
Short name T881
Test name
Test status
Simulation time 655490235 ps
CPU time 6.22 seconds
Started Jun 05 05:43:32 PM PDT 24
Finished Jun 05 05:43:39 PM PDT 24
Peak memory 224956 kb
Host smart-8c784500-5521-49dd-bf60-0453e5d7c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231755770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.231755770
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3720648985
Short name T738
Test name
Test status
Simulation time 6070836291 ps
CPU time 11.11 seconds
Started Jun 05 05:43:29 PM PDT 24
Finished Jun 05 05:43:41 PM PDT 24
Peak memory 224956 kb
Host smart-5101fea7-dcbd-41a4-857e-0233252cd4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720648985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3720648985
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2781862546
Short name T190
Test name
Test status
Simulation time 4945825306 ps
CPU time 9.06 seconds
Started Jun 05 05:43:30 PM PDT 24
Finished Jun 05 05:43:40 PM PDT 24
Peak memory 240780 kb
Host smart-9f61a1fe-8331-42f6-b0cc-ebbda818d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781862546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2781862546
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2749180349
Short name T31
Test name
Test status
Simulation time 32569876240 ps
CPU time 25.79 seconds
Started Jun 05 05:43:32 PM PDT 24
Finished Jun 05 05:43:59 PM PDT 24
Peak memory 233220 kb
Host smart-59554b8f-d006-4787-a43d-9df4b3b13bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749180349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2749180349
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3096616613
Short name T906
Test name
Test status
Simulation time 144181180 ps
CPU time 2.65 seconds
Started Jun 05 05:43:31 PM PDT 24
Finished Jun 05 05:43:35 PM PDT 24
Peak memory 233280 kb
Host smart-836f6c1f-6c0b-49d7-ad61-73e13da339eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096616613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3096616613
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1586214463
Short name T35
Test name
Test status
Simulation time 695438317 ps
CPU time 5.36 seconds
Started Jun 05 05:43:31 PM PDT 24
Finished Jun 05 05:43:37 PM PDT 24
Peak memory 220332 kb
Host smart-f70d1a39-7db9-42b0-9a59-a9a22782cfa6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1586214463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1586214463
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4117396584
Short name T56
Test name
Test status
Simulation time 20944015584 ps
CPU time 193.7 seconds
Started Jun 05 05:43:32 PM PDT 24
Finished Jun 05 05:46:47 PM PDT 24
Peak memory 264704 kb
Host smart-e410509f-c9ce-4768-9f08-8a84c905a263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117396584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4117396584
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3715477833
Short name T398
Test name
Test status
Simulation time 635666592 ps
CPU time 12.65 seconds
Started Jun 05 05:43:30 PM PDT 24
Finished Jun 05 05:43:43 PM PDT 24
Peak memory 216780 kb
Host smart-f4194bdb-2c88-426c-ae75-6916d1789e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715477833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3715477833
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1284600643
Short name T829
Test name
Test status
Simulation time 658447803 ps
CPU time 1.82 seconds
Started Jun 05 05:43:31 PM PDT 24
Finished Jun 05 05:43:34 PM PDT 24
Peak memory 208276 kb
Host smart-921ccf21-06f8-4ec7-b993-ee7de8abc51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284600643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1284600643
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.797054966
Short name T542
Test name
Test status
Simulation time 42027249 ps
CPU time 1.02 seconds
Started Jun 05 05:43:30 PM PDT 24
Finished Jun 05 05:43:32 PM PDT 24
Peak memory 207704 kb
Host smart-dc299778-0fc8-4c59-888f-cca84c06a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797054966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.797054966
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3373427837
Short name T723
Test name
Test status
Simulation time 104475705 ps
CPU time 0.88 seconds
Started Jun 05 05:43:32 PM PDT 24
Finished Jun 05 05:43:33 PM PDT 24
Peak memory 206208 kb
Host smart-0ca4fb74-b4b2-4f50-b772-4f87b78a90e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373427837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3373427837
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.642787790
Short name T270
Test name
Test status
Simulation time 2056641778 ps
CPU time 6.7 seconds
Started Jun 05 05:43:32 PM PDT 24
Finished Jun 05 05:43:39 PM PDT 24
Peak memory 224936 kb
Host smart-e1f17b63-23eb-4002-82eb-0978fa5fbab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642787790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.642787790
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3847709384
Short name T799
Test name
Test status
Simulation time 15497764 ps
CPU time 0.75 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:41:15 PM PDT 24
Peak memory 206112 kb
Host smart-01bfde33-3ed7-4320-bbdc-dbc01efe957e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847709384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
847709384
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2092511734
Short name T970
Test name
Test status
Simulation time 2127177635 ps
CPU time 22.38 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 224948 kb
Host smart-095d7419-2c6e-44a0-8096-a66bd71c0b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092511734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2092511734
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2385150051
Short name T416
Test name
Test status
Simulation time 21630961 ps
CPU time 0.77 seconds
Started Jun 05 05:41:04 PM PDT 24
Finished Jun 05 05:41:05 PM PDT 24
Peak memory 205936 kb
Host smart-47d246ea-a1b4-4c13-9102-7bc58653d4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385150051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2385150051
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2287586760
Short name T405
Test name
Test status
Simulation time 2783502598 ps
CPU time 39.33 seconds
Started Jun 05 05:41:08 PM PDT 24
Finished Jun 05 05:41:48 PM PDT 24
Peak memory 239656 kb
Host smart-6d4e6ca8-45d6-4915-a3d8-7b1642205d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287586760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2287586760
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3630959437
Short name T217
Test name
Test status
Simulation time 385330473829 ps
CPU time 284.63 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:45:52 PM PDT 24
Peak memory 250636 kb
Host smart-fd541977-cd1d-48c6-9bd1-f10153487141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630959437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3630959437
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1594735536
Short name T280
Test name
Test status
Simulation time 200194823 ps
CPU time 5.46 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:12 PM PDT 24
Peak memory 229876 kb
Host smart-60540a8f-42cb-4dd6-9afb-88ec559575f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594735536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1594735536
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2927702272
Short name T346
Test name
Test status
Simulation time 276168624 ps
CPU time 2.94 seconds
Started Jun 05 05:41:09 PM PDT 24
Finished Jun 05 05:41:12 PM PDT 24
Peak memory 233120 kb
Host smart-a73f4c13-aab8-4821-ad2e-673a7c326602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927702272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2927702272
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1615158382
Short name T846
Test name
Test status
Simulation time 2489436197 ps
CPU time 11.11 seconds
Started Jun 05 05:41:08 PM PDT 24
Finished Jun 05 05:41:20 PM PDT 24
Peak memory 224968 kb
Host smart-5cf559cf-758d-42b0-b08c-f2f3376249c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615158382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1615158382
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.222373172
Short name T393
Test name
Test status
Simulation time 87666024 ps
CPU time 1.07 seconds
Started Jun 05 05:41:08 PM PDT 24
Finished Jun 05 05:41:10 PM PDT 24
Peak memory 218308 kb
Host smart-b129439f-0d4f-49f7-8833-6a9b8a0f4fba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222373172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.222373172
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3437583939
Short name T255
Test name
Test status
Simulation time 60543150 ps
CPU time 2.62 seconds
Started Jun 05 05:41:05 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 233132 kb
Host smart-19eea682-db91-4d2f-809e-f9b6aa2f6e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437583939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3437583939
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3562870389
Short name T266
Test name
Test status
Simulation time 22086665078 ps
CPU time 19.21 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:26 PM PDT 24
Peak memory 233204 kb
Host smart-f2d41f30-edf2-4baf-8c8d-cef91aa2babf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562870389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3562870389
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3172674857
Short name T910
Test name
Test status
Simulation time 708555805 ps
CPU time 6.72 seconds
Started Jun 05 05:41:09 PM PDT 24
Finished Jun 05 05:41:16 PM PDT 24
Peak memory 223484 kb
Host smart-3e889fc8-7762-4225-827e-dc932ac29534
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3172674857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3172674857
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2239110322
Short name T250
Test name
Test status
Simulation time 15410177230 ps
CPU time 123.22 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:43:19 PM PDT 24
Peak memory 256848 kb
Host smart-ec6a9d39-b759-4739-8426-dc2359fc15d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239110322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2239110322
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4065871513
Short name T378
Test name
Test status
Simulation time 29511238800 ps
CPU time 27.79 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:35 PM PDT 24
Peak memory 216932 kb
Host smart-3439eff5-2d5a-4d54-a489-90a0a2aa6a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065871513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4065871513
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.584505771
Short name T472
Test name
Test status
Simulation time 2716865852 ps
CPU time 2.36 seconds
Started Jun 05 05:41:05 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 216588 kb
Host smart-89898dfa-a4f4-4faf-b6ec-2a592c6ff771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584505771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.584505771
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.232766709
Short name T524
Test name
Test status
Simulation time 88647521 ps
CPU time 0.96 seconds
Started Jun 05 05:41:07 PM PDT 24
Finished Jun 05 05:41:09 PM PDT 24
Peak memory 207384 kb
Host smart-6c59aaf3-7c97-44b7-90f8-a3d7cbf65e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232766709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.232766709
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4177727164
Short name T828
Test name
Test status
Simulation time 255184657 ps
CPU time 0.95 seconds
Started Jun 05 05:41:06 PM PDT 24
Finished Jun 05 05:41:08 PM PDT 24
Peak memory 206256 kb
Host smart-ca5cc4bb-dbb5-444b-bec9-7df7bfcf2bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177727164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4177727164
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2751440918
Short name T264
Test name
Test status
Simulation time 93517798 ps
CPU time 2.73 seconds
Started Jun 05 05:41:07 PM PDT 24
Finished Jun 05 05:41:11 PM PDT 24
Peak memory 233152 kb
Host smart-88ede6b4-8cce-42c7-a612-fb60b77c3798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751440918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2751440918
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.987051234
Short name T539
Test name
Test status
Simulation time 12631810 ps
CPU time 0.74 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:41:14 PM PDT 24
Peak memory 205736 kb
Host smart-f5694a6d-9f58-4dbb-a83a-3a48ac44dc59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987051234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.987051234
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1498520607
Short name T827
Test name
Test status
Simulation time 283448560 ps
CPU time 2.58 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:41:15 PM PDT 24
Peak memory 224912 kb
Host smart-56681a35-84f6-45ad-923f-05e6aecf4d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498520607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1498520607
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2640965496
Short name T697
Test name
Test status
Simulation time 32013846 ps
CPU time 0.78 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:41:14 PM PDT 24
Peak memory 206936 kb
Host smart-6709f8a6-c2d6-4b47-a448-30230b6ae16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640965496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2640965496
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.4020537812
Short name T227
Test name
Test status
Simulation time 3424297812 ps
CPU time 74.19 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:42:28 PM PDT 24
Peak memory 250424 kb
Host smart-8dd2b1da-d138-4fa7-9c3e-9df7b97ecb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020537812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.4020537812
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1611934469
Short name T129
Test name
Test status
Simulation time 9817638237 ps
CPU time 102.47 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:42:55 PM PDT 24
Peak memory 251068 kb
Host smart-01a17966-08e2-4594-a03a-af8c829fd07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611934469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1611934469
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3713966921
Short name T214
Test name
Test status
Simulation time 9137224805 ps
CPU time 95.28 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:42:50 PM PDT 24
Peak memory 262372 kb
Host smart-769ae24c-fdfc-43f9-b00b-c5ab5fa47b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713966921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3713966921
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4143745999
Short name T806
Test name
Test status
Simulation time 1224474795 ps
CPU time 11.28 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:27 PM PDT 24
Peak memory 233148 kb
Host smart-6226f79c-1301-4a7d-8964-9d8a721da860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143745999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4143745999
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.633680223
Short name T431
Test name
Test status
Simulation time 472992437 ps
CPU time 3.2 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:41:15 PM PDT 24
Peak memory 219056 kb
Host smart-82f1aa7f-45e0-41e0-bb4b-7b530119c433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633680223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.633680223
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.474666643
Short name T823
Test name
Test status
Simulation time 56635540874 ps
CPU time 95.28 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:42:49 PM PDT 24
Peak memory 251236 kb
Host smart-e3706655-1fa7-4d24-a911-07ad14bb93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474666643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.474666643
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3459671239
Short name T963
Test name
Test status
Simulation time 90066142 ps
CPU time 1.18 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:41:14 PM PDT 24
Peak memory 217080 kb
Host smart-60034ec0-8c39-4e3f-bda0-4c75cd18fc9e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459671239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3459671239
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2676389569
Short name T523
Test name
Test status
Simulation time 278352797 ps
CPU time 2.32 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:41:18 PM PDT 24
Peak memory 218936 kb
Host smart-a2e09763-c528-431c-883e-2e37187ef9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676389569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2676389569
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4284531492
Short name T457
Test name
Test status
Simulation time 191322373 ps
CPU time 4.28 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:41:19 PM PDT 24
Peak memory 224888 kb
Host smart-9bb9bc02-79a3-4544-986a-d17298972c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284531492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4284531492
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1720653432
Short name T803
Test name
Test status
Simulation time 162747223 ps
CPU time 3.56 seconds
Started Jun 05 05:41:16 PM PDT 24
Finished Jun 05 05:41:20 PM PDT 24
Peak memory 220604 kb
Host smart-962ea518-05a9-473a-a76e-460eefd41a26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1720653432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1720653432
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1292955929
Short name T232
Test name
Test status
Simulation time 83805077167 ps
CPU time 605.44 seconds
Started Jun 05 05:41:11 PM PDT 24
Finished Jun 05 05:51:17 PM PDT 24
Peak memory 253860 kb
Host smart-f1dd8418-969d-45d6-8900-d4346c8a9e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292955929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1292955929
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1343023959
Short name T372
Test name
Test status
Simulation time 63248582 ps
CPU time 0.78 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:41:13 PM PDT 24
Peak memory 206056 kb
Host smart-5b35b8aa-6725-46aa-8d78-30f2e69f475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343023959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1343023959
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2745989248
Short name T669
Test name
Test status
Simulation time 10293629140 ps
CPU time 10.73 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:26 PM PDT 24
Peak memory 216776 kb
Host smart-52f9b649-9514-4a35-944d-b74c5e5dcee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745989248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2745989248
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2401199534
Short name T591
Test name
Test status
Simulation time 552645973 ps
CPU time 3.65 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:41:18 PM PDT 24
Peak memory 216976 kb
Host smart-4f0d6239-d44a-4dbc-a21e-285cda90cbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401199534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2401199534
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4084541807
Short name T390
Test name
Test status
Simulation time 101109380 ps
CPU time 1.05 seconds
Started Jun 05 05:41:16 PM PDT 24
Finished Jun 05 05:41:18 PM PDT 24
Peak memory 207272 kb
Host smart-adfb754c-221f-4de2-8b2f-a73f87152324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084541807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4084541807
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1476586139
Short name T338
Test name
Test status
Simulation time 1547521679 ps
CPU time 5.63 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:21 PM PDT 24
Peak memory 224936 kb
Host smart-2c60896b-f0c4-49d8-a5b1-2ad5f7682804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476586139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1476586139
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.434164310
Short name T330
Test name
Test status
Simulation time 26734982 ps
CPU time 0.78 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:16 PM PDT 24
Peak memory 205664 kb
Host smart-8f6b5ed8-98fc-4fff-b4c2-e384fb50c29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434164310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.434164310
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1579097614
Short name T246
Test name
Test status
Simulation time 409020084 ps
CPU time 3.16 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:41:18 PM PDT 24
Peak memory 233188 kb
Host smart-ae03a580-92e3-469e-884d-4af5347a69ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579097614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1579097614
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.138701769
Short name T501
Test name
Test status
Simulation time 20380114 ps
CPU time 0.76 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:41:16 PM PDT 24
Peak memory 205932 kb
Host smart-99ebb61c-700a-4d3b-9ec6-3b2855df34bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138701769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.138701769
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1601199137
Short name T357
Test name
Test status
Simulation time 8192393953 ps
CPU time 23.08 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:41:38 PM PDT 24
Peak memory 224976 kb
Host smart-ca3b57c8-ba91-4942-b25b-eab69cbc87ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601199137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1601199137
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.876774938
Short name T709
Test name
Test status
Simulation time 40921030098 ps
CPU time 96.1 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:42:51 PM PDT 24
Peak memory 249716 kb
Host smart-5fee373e-6487-4865-8f0b-ed152ecab011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876774938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.876774938
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1825949894
Short name T447
Test name
Test status
Simulation time 2581245518 ps
CPU time 65.35 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:42:19 PM PDT 24
Peak memory 252792 kb
Host smart-baa2f194-de73-4771-a11a-712166502e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825949894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1825949894
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1176548778
Short name T277
Test name
Test status
Simulation time 2396179427 ps
CPU time 13.84 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:41:27 PM PDT 24
Peak memory 234916 kb
Host smart-82be6ac3-8a16-4ca5-bc2f-d8bdff55ee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176548778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1176548778
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.371246261
Short name T761
Test name
Test status
Simulation time 61979645 ps
CPU time 2.63 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:19 PM PDT 24
Peak memory 227520 kb
Host smart-5f6ab13b-2edc-4ac1-90e0-3dd40b2a7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371246261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.371246261
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2916961130
Short name T862
Test name
Test status
Simulation time 45407182618 ps
CPU time 96.86 seconds
Started Jun 05 05:41:17 PM PDT 24
Finished Jun 05 05:42:54 PM PDT 24
Peak memory 233180 kb
Host smart-82ba5bfc-1308-4859-b8af-58c85721797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916961130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2916961130
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2525528468
Short name T66
Test name
Test status
Simulation time 48021417 ps
CPU time 1.1 seconds
Started Jun 05 05:41:16 PM PDT 24
Finished Jun 05 05:41:17 PM PDT 24
Peak memory 217068 kb
Host smart-664f9e82-536e-4e5a-a9ad-9a8c67c8bfb9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525528468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2525528468
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2858669136
Short name T170
Test name
Test status
Simulation time 4798643627 ps
CPU time 8.68 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:41:22 PM PDT 24
Peak memory 233176 kb
Host smart-c12dae29-a9b2-4339-a722-d0d2b4f70a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858669136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2858669136
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4177049493
Short name T703
Test name
Test status
Simulation time 377408041 ps
CPU time 6.49 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:41:21 PM PDT 24
Peak memory 240884 kb
Host smart-59a786a3-8e2b-4de7-813a-89ed74d537dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177049493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4177049493
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4191381789
Short name T367
Test name
Test status
Simulation time 1190998915 ps
CPU time 12.25 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:41:26 PM PDT 24
Peak memory 219660 kb
Host smart-c093502f-3553-45f6-a182-0c29093694c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4191381789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4191381789
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2453182206
Short name T152
Test name
Test status
Simulation time 1729543078 ps
CPU time 3.42 seconds
Started Jun 05 05:41:16 PM PDT 24
Finished Jun 05 05:41:20 PM PDT 24
Peak memory 225040 kb
Host smart-d16268b1-91ad-47bc-9ad3-e06a021d9734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453182206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2453182206
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4105270870
Short name T665
Test name
Test status
Simulation time 7933665879 ps
CPU time 37.8 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:54 PM PDT 24
Peak memory 216900 kb
Host smart-82e33562-44aa-4913-bf80-2269bcb1e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105270870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4105270870
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.838090087
Short name T722
Test name
Test status
Simulation time 12387526 ps
CPU time 0.77 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:41:13 PM PDT 24
Peak memory 206032 kb
Host smart-971bdb9f-c5a4-41e9-b00d-9248cb6269cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838090087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.838090087
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2103088099
Short name T628
Test name
Test status
Simulation time 109317306 ps
CPU time 2.26 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:18 PM PDT 24
Peak memory 216828 kb
Host smart-dcdf3b3a-629e-4d3e-a14c-9b187d7bfe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103088099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2103088099
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.71297467
Short name T632
Test name
Test status
Simulation time 25784601 ps
CPU time 0.74 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:41:15 PM PDT 24
Peak memory 206240 kb
Host smart-e36c5de6-2de8-45e7-b40b-ca9cf7631a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71297467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.71297467
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1863670149
Short name T876
Test name
Test status
Simulation time 81126887 ps
CPU time 2.32 seconds
Started Jun 05 05:41:12 PM PDT 24
Finished Jun 05 05:41:14 PM PDT 24
Peak memory 223640 kb
Host smart-c606371d-d5ba-4564-9a9f-af1a5ac0078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863670149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1863670149
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.307530569
Short name T493
Test name
Test status
Simulation time 19354340 ps
CPU time 0.7 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:41:21 PM PDT 24
Peak memory 205716 kb
Host smart-98753d85-6ffe-4a29-bf14-fc0f6404a708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307530569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.307530569
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4275184792
Short name T525
Test name
Test status
Simulation time 58761325 ps
CPU time 2.9 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:41:23 PM PDT 24
Peak memory 233116 kb
Host smart-d8274fc5-41b8-44f1-87ff-e3c9c80363d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275184792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4275184792
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3186343307
Short name T449
Test name
Test status
Simulation time 70880478 ps
CPU time 0.79 seconds
Started Jun 05 05:41:16 PM PDT 24
Finished Jun 05 05:41:18 PM PDT 24
Peak memory 206912 kb
Host smart-b6b7efcc-2a9c-49b2-a32b-cb07818ad1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186343307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3186343307
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4016628951
Short name T159
Test name
Test status
Simulation time 6331392325 ps
CPU time 79.1 seconds
Started Jun 05 05:41:30 PM PDT 24
Finished Jun 05 05:42:50 PM PDT 24
Peak memory 256752 kb
Host smart-00f9b8f4-7737-400d-b34a-1a29998e2707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016628951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4016628951
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4098581250
Short name T856
Test name
Test status
Simulation time 22642107435 ps
CPU time 37.01 seconds
Started Jun 05 05:41:23 PM PDT 24
Finished Jun 05 05:42:00 PM PDT 24
Peak memory 237016 kb
Host smart-2da2140b-b3d5-4a41-8ba6-118a3c4fa2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098581250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4098581250
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3177995129
Short name T564
Test name
Test status
Simulation time 575624955 ps
CPU time 6.11 seconds
Started Jun 05 05:41:25 PM PDT 24
Finished Jun 05 05:41:31 PM PDT 24
Peak memory 241332 kb
Host smart-83449478-6c93-49a7-8198-87a960453e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177995129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3177995129
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4151388139
Short name T747
Test name
Test status
Simulation time 5444150860 ps
CPU time 18.12 seconds
Started Jun 05 05:41:22 PM PDT 24
Finished Jun 05 05:41:41 PM PDT 24
Peak memory 233204 kb
Host smart-c04f6510-ccbf-4c06-a54c-f95fe68cadf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151388139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4151388139
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2355766212
Short name T850
Test name
Test status
Simulation time 5527133952 ps
CPU time 13.71 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:41:33 PM PDT 24
Peak memory 233244 kb
Host smart-09b7034f-6adc-483f-aec7-6d4f339914d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355766212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2355766212
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2236918383
Short name T403
Test name
Test status
Simulation time 255099606 ps
CPU time 1.1 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:17 PM PDT 24
Peak memory 217036 kb
Host smart-a0edca15-247b-413e-b4fe-63005633b947
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236918383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2236918383
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2837150893
Short name T555
Test name
Test status
Simulation time 356693100 ps
CPU time 4.35 seconds
Started Jun 05 05:41:22 PM PDT 24
Finished Jun 05 05:41:27 PM PDT 24
Peak memory 233144 kb
Host smart-1974a28a-be3e-4c7f-8e92-29a20e1fbd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837150893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2837150893
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3746961993
Short name T870
Test name
Test status
Simulation time 884527322 ps
CPU time 5 seconds
Started Jun 05 05:41:22 PM PDT 24
Finished Jun 05 05:41:27 PM PDT 24
Peak memory 233068 kb
Host smart-53e9bf9f-4e61-421f-b730-dc22b20d981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746961993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3746961993
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4069863266
Short name T429
Test name
Test status
Simulation time 3883958904 ps
CPU time 8.03 seconds
Started Jun 05 05:41:18 PM PDT 24
Finished Jun 05 05:41:27 PM PDT 24
Peak memory 220480 kb
Host smart-d5c4f9da-c4e7-4092-9c55-32f588e6a2d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4069863266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4069863266
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.325958361
Short name T704
Test name
Test status
Simulation time 7677199477 ps
CPU time 40.27 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:56 PM PDT 24
Peak memory 216880 kb
Host smart-e6bf0bf2-76f1-41cd-bf57-ba946f1ab2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325958361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.325958361
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.589022895
Short name T427
Test name
Test status
Simulation time 10173667611 ps
CPU time 10.87 seconds
Started Jun 05 05:41:13 PM PDT 24
Finished Jun 05 05:41:25 PM PDT 24
Peak memory 216744 kb
Host smart-ebca98e8-3bb4-4093-acf7-27520dba3038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589022895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.589022895
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3794883321
Short name T787
Test name
Test status
Simulation time 24268382 ps
CPU time 1.2 seconds
Started Jun 05 05:41:14 PM PDT 24
Finished Jun 05 05:41:16 PM PDT 24
Peak memory 208520 kb
Host smart-b92223b3-0349-43ae-b827-827d33a9fc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794883321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3794883321
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2658896515
Short name T837
Test name
Test status
Simulation time 36512690 ps
CPU time 0.71 seconds
Started Jun 05 05:41:15 PM PDT 24
Finished Jun 05 05:41:16 PM PDT 24
Peak memory 205932 kb
Host smart-60767937-0072-4ada-953d-f165c6df2945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658896515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2658896515
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.795596202
Short name T757
Test name
Test status
Simulation time 116724379 ps
CPU time 2.46 seconds
Started Jun 05 05:41:21 PM PDT 24
Finished Jun 05 05:41:24 PM PDT 24
Peak memory 224912 kb
Host smart-a7537eb4-1d2f-4b6d-9109-a57b9dfa937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795596202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.795596202
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.95078451
Short name T47
Test name
Test status
Simulation time 81772922 ps
CPU time 0.69 seconds
Started Jun 05 05:41:20 PM PDT 24
Finished Jun 05 05:41:21 PM PDT 24
Peak memory 205720 kb
Host smart-9b458767-90cb-4534-b73e-04130c158bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95078451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.95078451
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4049626502
Short name T195
Test name
Test status
Simulation time 308315083 ps
CPU time 5 seconds
Started Jun 05 05:41:20 PM PDT 24
Finished Jun 05 05:41:26 PM PDT 24
Peak memory 233120 kb
Host smart-76227a10-0fd9-4aaa-af61-e0bf1433e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049626502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4049626502
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2876278276
Short name T789
Test name
Test status
Simulation time 25286726 ps
CPU time 0.76 seconds
Started Jun 05 05:41:20 PM PDT 24
Finished Jun 05 05:41:22 PM PDT 24
Peak memory 205924 kb
Host smart-3f425e41-a65c-4d1d-916b-80103cec1de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876278276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2876278276
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4212928936
Short name T194
Test name
Test status
Simulation time 27869276941 ps
CPU time 86.75 seconds
Started Jun 05 05:41:31 PM PDT 24
Finished Jun 05 05:42:58 PM PDT 24
Peak memory 250740 kb
Host smart-0e106395-831f-40dd-8800-6382de8af868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212928936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4212928936
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1341555860
Short name T899
Test name
Test status
Simulation time 28506555018 ps
CPU time 299.52 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:46:19 PM PDT 24
Peak memory 249756 kb
Host smart-89cb10bc-e16f-49cd-b870-2ef0d2535cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341555860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1341555860
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3509588885
Short name T19
Test name
Test status
Simulation time 26152317069 ps
CPU time 236.73 seconds
Started Jun 05 05:41:21 PM PDT 24
Finished Jun 05 05:45:19 PM PDT 24
Peak memory 257912 kb
Host smart-fa6136c6-6141-4197-8ee3-5a509f998ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509588885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3509588885
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1013748489
Short name T729
Test name
Test status
Simulation time 630131549 ps
CPU time 5.17 seconds
Started Jun 05 05:41:31 PM PDT 24
Finished Jun 05 05:41:37 PM PDT 24
Peak memory 224932 kb
Host smart-064a2c77-1633-49b2-a285-db4d67739091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013748489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1013748489
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1562596109
Short name T927
Test name
Test status
Simulation time 262483701 ps
CPU time 4.97 seconds
Started Jun 05 05:41:31 PM PDT 24
Finished Jun 05 05:41:36 PM PDT 24
Peak memory 224896 kb
Host smart-fbf9f279-6ee5-4c00-b25a-14db31a0b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562596109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1562596109
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1606309360
Short name T541
Test name
Test status
Simulation time 119486102534 ps
CPU time 124.45 seconds
Started Jun 05 05:41:18 PM PDT 24
Finished Jun 05 05:43:23 PM PDT 24
Peak memory 240676 kb
Host smart-7e679509-1480-41d0-9965-bbdc0780e77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606309360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1606309360
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.609856375
Short name T648
Test name
Test status
Simulation time 102217689 ps
CPU time 1.03 seconds
Started Jun 05 05:41:20 PM PDT 24
Finished Jun 05 05:41:22 PM PDT 24
Peak memory 218292 kb
Host smart-f70bbaec-6b80-4dcb-8789-8a7c6e1fe252
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609856375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.609856375
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.963943297
Short name T865
Test name
Test status
Simulation time 187065777 ps
CPU time 2.41 seconds
Started Jun 05 05:41:17 PM PDT 24
Finished Jun 05 05:41:20 PM PDT 24
Peak memory 224696 kb
Host smart-8512831d-6635-4fa5-b38b-b04505795eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963943297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
963943297
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3776461733
Short name T491
Test name
Test status
Simulation time 31839868 ps
CPU time 2.05 seconds
Started Jun 05 05:41:30 PM PDT 24
Finished Jun 05 05:41:32 PM PDT 24
Peak memory 218820 kb
Host smart-dc4c97f5-7751-4b96-9fb4-e32eafcaf35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776461733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3776461733
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1742816846
Short name T85
Test name
Test status
Simulation time 2839571880 ps
CPU time 10.19 seconds
Started Jun 05 05:41:18 PM PDT 24
Finished Jun 05 05:41:30 PM PDT 24
Peak memory 223284 kb
Host smart-f4d55cca-afdc-4cec-a4e5-59bf52e8de3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1742816846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1742816846
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.556080586
Short name T819
Test name
Test status
Simulation time 1432650569 ps
CPU time 10.62 seconds
Started Jun 05 05:41:22 PM PDT 24
Finished Jun 05 05:41:33 PM PDT 24
Peak memory 216840 kb
Host smart-76f1d06a-3c98-4900-b120-02f0fa378612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556080586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.556080586
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.960235592
Short name T900
Test name
Test status
Simulation time 5144961852 ps
CPU time 14.3 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:41:34 PM PDT 24
Peak memory 216792 kb
Host smart-93119405-63e7-4550-8fab-cc141a452693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960235592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.960235592
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2808986545
Short name T707
Test name
Test status
Simulation time 667916321 ps
CPU time 1.43 seconds
Started Jun 05 05:41:20 PM PDT 24
Finished Jun 05 05:41:22 PM PDT 24
Peak memory 208504 kb
Host smart-c0e49cf3-0114-4eee-94cb-a0ca0a3da9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808986545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2808986545
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1710464942
Short name T465
Test name
Test status
Simulation time 17840886 ps
CPU time 0.83 seconds
Started Jun 05 05:41:20 PM PDT 24
Finished Jun 05 05:41:21 PM PDT 24
Peak memory 206240 kb
Host smart-ac7d6090-7ac1-4fa4-abe2-b9dbb2d49255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710464942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1710464942
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.262380195
Short name T178
Test name
Test status
Simulation time 8954254691 ps
CPU time 30.03 seconds
Started Jun 05 05:41:19 PM PDT 24
Finished Jun 05 05:41:50 PM PDT 24
Peak memory 241280 kb
Host smart-68d662fc-ee01-4279-bb04-5198b880b929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262380195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.262380195
Directory /workspace/9.spi_device_upload/latest
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