Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3984824	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4202275

1

T1

2

T2

16719

T3

3063

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4666124	1			T1	1		T2	22889		T3	2214
values[0x0]	1759538	1			T2	8310		T3	1470		T4	3
values[0x1]	1761437	1			T1	5		T2	8483		T3	1501

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2817349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5369750

1

T1

3

T2

23821

T3

3596

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30346	1			T2	113		T6	3		T7	14
valid_sources[0x01]	32158	1			T2	130		T6	2		T7	14
valid_sources[0x02]	30452	1			T2	163		T7	12		T8	84
valid_sources[0x03]	32634	1			T2	78		T3	23		T5	2
valid_sources[0x04]	30415	1			T2	111		T5	9		T6	8
valid_sources[0x05]	33728	1			T2	192		T7	17		T8	66
valid_sources[0x06]	30587	1			T2	153		T5	5		T6	3
valid_sources[0x07]	31497	1			T2	186		T6	7		T7	14
valid_sources[0x08]	33418	1			T2	109		T5	3		T6	3
valid_sources[0x09]	33190	1			T2	160		T3	1		T5	2
valid_sources[0x0a]	30148	1			T2	153		T3	1		T5	31
valid_sources[0x0b]	32689	1			T2	79		T3	2		T5	15
valid_sources[0x0c]	30856	1			T2	107		T7	18		T8	68
valid_sources[0x0d]	33590	1			T2	118		T3	86		T5	6
valid_sources[0x0e]	32438	1			T2	233		T3	18		T7	11
valid_sources[0x0f]	31048	1			T2	168		T3	1		T5	5
valid_sources[0x10]	32629	1			T2	164		T3	190		T7	10
valid_sources[0x11]	30548	1			T2	175		T5	1		T6	6
valid_sources[0x12]	31508	1			T2	150		T6	4		T7	19
valid_sources[0x13]	29482	1			T2	160		T6	5		T7	12
valid_sources[0x14]	30532	1			T2	123		T6	11		T7	12
valid_sources[0x15]	31031	1			T2	212		T3	4		T5	4
valid_sources[0x16]	31540	1			T2	79		T5	11		T6	7
valid_sources[0x17]	28302	1			T2	196		T5	6		T6	5
valid_sources[0x18]	32980	1			T2	161		T5	4		T6	9
valid_sources[0x19]	34259	1			T2	150		T3	74		T7	11
valid_sources[0x1a]	30940	1			T2	122		T3	7		T5	5
valid_sources[0x1b]	30973	1			T2	117		T7	26		T8	73
valid_sources[0x1c]	33609	1			T2	128		T3	45		T6	9
valid_sources[0x1d]	29428	1			T2	178		T3	1		T5	3
valid_sources[0x1e]	31698	1			T2	111		T3	4		T6	2
valid_sources[0x1f]	30581	1			T2	247		T5	14		T6	5
valid_sources[0x20]	30321	1			T2	147		T6	3		T7	17
valid_sources[0x21]	30832	1			T2	126		T5	4		T6	4
valid_sources[0x22]	29818	1			T2	176		T3	4		T7	17
valid_sources[0x23]	31441	1			T2	193		T6	7		T7	13
valid_sources[0x24]	30810	1			T2	182		T6	15		T7	18
valid_sources[0x25]	31793	1			T2	163		T3	2		T6	2
valid_sources[0x26]	39270	1			T2	116		T5	19		T6	12
valid_sources[0x27]	34958	1			T2	164		T6	5		T7	17
valid_sources[0x28]	29579	1			T2	207		T5	6		T6	4
valid_sources[0x29]	31674	1			T2	121		T5	10		T6	1
valid_sources[0x2a]	28596	1			T2	115		T6	1		T7	14
valid_sources[0x2b]	35412	1			T2	147		T5	16		T6	2
valid_sources[0x2c]	31028	1			T2	147		T5	3		T6	6
valid_sources[0x2d]	31920	1			T2	153		T5	4		T6	14
valid_sources[0x2e]	38479	1			T2	140		T6	1		T7	12
valid_sources[0x2f]	30831	1			T2	203		T5	5		T7	11
valid_sources[0x30]	29857	1			T2	128		T5	2		T6	6
valid_sources[0x31]	32483	1			T2	172		T6	2		T7	17
valid_sources[0x32]	31043	1			T2	113		T3	1		T5	2
valid_sources[0x33]	32372	1			T2	116		T7	15		T8	89
valid_sources[0x34]	35181	1			T2	177		T3	3		T5	1
valid_sources[0x35]	31263	1			T2	184		T5	1		T6	3
valid_sources[0x36]	31683	1			T2	164		T6	6		T7	19
valid_sources[0x37]	31014	1			T2	149		T3	1		T6	1
valid_sources[0x38]	29192	1			T2	168		T6	6		T7	9
valid_sources[0x39]	35461	1			T2	148		T6	1		T7	11
valid_sources[0x3a]	32031	1			T2	140		T6	6		T7	14
valid_sources[0x3b]	29892	1			T2	153		T5	2		T6	12
valid_sources[0x3c]	31332	1			T2	189		T3	470		T5	3
valid_sources[0x3d]	32943	1			T2	129		T3	12		T5	13
valid_sources[0x3e]	32459	1			T2	238		T3	2		T5	1
valid_sources[0x3f]	40616	1			T2	181		T3	119		T6	6
valid_sources[0x40]	30236	1			T2	139		T5	11		T6	11
valid_sources[0x41]	31802	1			T2	174		T3	1		T5	26
valid_sources[0x42]	32828	1			T2	146		T3	67		T5	1
valid_sources[0x43]	29554	1			T2	95		T6	14		T7	13
valid_sources[0x44]	29605	1			T2	181		T5	8		T6	9
valid_sources[0x45]	32307	1			T2	177		T6	5		T7	14
valid_sources[0x46]	31195	1			T2	129		T6	8		T7	16
valid_sources[0x47]	32359	1			T2	196		T7	16		T8	61
valid_sources[0x48]	32564	1			T2	131		T3	2		T7	17
valid_sources[0x49]	32517	1			T2	207		T3	1172		T7	17
valid_sources[0x4a]	34177	1			T2	155		T7	18		T8	85
valid_sources[0x4b]	31293	1			T2	142		T5	8		T6	11
valid_sources[0x4c]	31519	1			T2	220		T5	4		T6	4
valid_sources[0x4d]	30356	1			T2	104		T5	2		T6	4
valid_sources[0x4e]	33642	1			T2	175		T3	1		T5	1
valid_sources[0x4f]	32013	1			T2	142		T6	10		T7	18
valid_sources[0x50]	30247	1			T2	145		T5	13		T7	15
valid_sources[0x51]	30362	1			T2	139		T5	5		T6	5
valid_sources[0x52]	35960	1			T2	152		T5	4		T6	1
valid_sources[0x53]	29015	1			T2	165		T6	3		T7	19
valid_sources[0x54]	30442	1			T2	130		T7	14		T8	90
valid_sources[0x55]	35201	1			T2	231		T5	13		T6	5
valid_sources[0x56]	33007	1			T2	212		T3	83		T6	10
valid_sources[0x57]	34570	1			T2	111		T6	1		T7	12
valid_sources[0x58]	28525	1			T2	166		T3	1		T5	7
valid_sources[0x59]	31980	1			T2	137		T3	161		T7	21
valid_sources[0x5a]	31601	1			T2	147		T6	7		T7	15
valid_sources[0x5b]	42797	1			T2	145		T5	2		T7	12
valid_sources[0x5c]	31103	1			T2	92		T5	15		T6	11
valid_sources[0x5d]	30949	1			T2	166		T3	136		T5	1
valid_sources[0x5e]	34184	1			T2	151		T3	1		T6	4
valid_sources[0x5f]	32235	1			T2	164		T6	5		T7	13
valid_sources[0x60]	30619	1			T2	216		T6	1		T7	18
valid_sources[0x61]	32013	1			T2	103		T5	9		T7	27
valid_sources[0x62]	30934	1			T2	202		T5	3		T6	2
valid_sources[0x63]	31245	1			T2	185		T6	1		T7	10
valid_sources[0x64]	31621	1			T2	153		T3	7		T5	27
valid_sources[0x65]	31396	1			T2	134		T7	17		T8	74
valid_sources[0x66]	31029	1			T2	145		T4	1		T5	2
valid_sources[0x67]	33007	1			T2	128		T5	7		T6	5
valid_sources[0x68]	30332	1			T2	173		T6	18		T7	9
valid_sources[0x69]	34874	1			T2	212		T5	22		T7	17
valid_sources[0x6a]	31870	1			T2	98		T3	2		T5	3
valid_sources[0x6b]	38655	1			T1	3		T2	191		T6	2
valid_sources[0x6c]	47380	1			T2	211		T6	2		T7	16
valid_sources[0x6d]	32634	1			T2	136		T3	324		T5	3
valid_sources[0x6e]	30825	1			T2	146		T3	4		T6	7
valid_sources[0x6f]	30274	1			T2	184		T3	2		T6	4
valid_sources[0x70]	32679	1			T2	189		T3	1		T7	8
valid_sources[0x71]	32776	1			T2	170		T6	6		T7	16
valid_sources[0x72]	31218	1			T2	174		T5	19		T6	6
valid_sources[0x73]	30706	1			T2	214		T3	131		T6	6
valid_sources[0x74]	31570	1			T2	158		T5	5		T6	2
valid_sources[0x75]	31088	1			T2	132		T3	2		T6	7
valid_sources[0x76]	31710	1			T2	208		T5	5		T6	1
valid_sources[0x77]	30582	1			T2	143		T3	3		T6	4
valid_sources[0x78]	33539	1			T2	132		T3	1		T5	13
valid_sources[0x79]	30987	1			T2	152		T6	8		T7	26
valid_sources[0x7a]	30531	1			T2	103		T6	8		T7	14
valid_sources[0x7b]	28461	1			T2	106		T7	12		T8	92
valid_sources[0x7c]	31935	1			T2	170		T3	11		T5	7
valid_sources[0x7d]	29474	1			T2	123		T5	15		T6	5
valid_sources[0x7e]	32095	1			T2	149		T3	92		T5	13
valid_sources[0x7f]	31714	1			T2	192		T6	5		T7	12
valid_sources[0x80]	29372	1			T2	131		T3	4		T5	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1047925

1

T2

2364

T3

750

T5

2

values[0x0]

all_enables

biggest_size

1589374

1

T2

7180

T3

1180

T4

1

values[0x1]

all_enables

biggest_size

1564976

1

T1

2

T2

7175

T3

1133