Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4004708

1

T1

4

T2

22963

T3

2122

full_word

4201437

1

T1

2

T2

16719

T3

3063

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8205725	1			T1	6		T2	39682		T3	5185
auto[TlIntgErrCmd]	139	1			T90	11		T92	7		T93	4
auto[TlIntgErrData]	136	1			T90	8		T92	9		T93	5
auto[TlIntgErrBoth]	145	1			T90	11		T92	4		T93	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4667804

1

T1

1

T2

22889

T3

2214

auto[1]

3538341

1

T1

5

T2

16793

T3

2971

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3619568	1			T1	1		T2	20525		T3	1464
auto[TlIntgErrNone]	partial	auto[1]	384747	1			T1	3		T2	2438		T3	658
auto[TlIntgErrNone]	full_word	auto[0]	1048046	1			T2	2364		T3	750		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	3153364	1			T1	2		T2	14355		T3	2313
auto[TlIntgErrCmd]	partial	auto[0]	66	1			T90	8		T92	4		T93	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T90	3		T92	3		T93	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T258	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T93	1		T104	2		T143	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T90	7		T92	4		T93	1
auto[TlIntgErrData]	partial	auto[1]	67	1			T90	1		T92	5		T93	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T93	1		T259	1		T260	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T256	1		T261	1		T260	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T90	1		T92	1		T104	5
auto[TlIntgErrBoth]	partial	auto[1]	85	1			T90	8		T92	3		T93	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T90	2		T259	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T257	1		T262	1		T260	1