Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425541073	2584075	0	0
DepthKnown_A	425541073	425411279	0	0
RvalidKnown_A	425541073	425411279	0	0
WreadyKnown_A	425541073	425411279	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	2584075	0	0
T2	178611	7485	0	0
T3	117346	832	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	1663	0	0
T8	447173	10815	0	0
T9	418352	0	0	0
T10	275880	13316	0	0
T11	124822	832	0	0
T12	0	1664	0	0
T13	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425541073	2744791	0	0
DepthKnown_A	425541073	425411279	0	0
RvalidKnown_A	425541073	425411279	0	0
WreadyKnown_A	425541073	425411279	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	2744791	0	0
T2	178611	4992	0	0
T3	117346	832	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	3821	0	0
T7	93764	832	0	0
T8	447173	19701	0	0
T9	418352	0	0	0
T10	275880	17995	0	0
T11	124822	832	0	0
T12	0	1664	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425541073	167668	0	0
DepthKnown_A	425541073	425411279	0	0
RvalidKnown_A	425541073	425411279	0	0
WreadyKnown_A	425541073	425411279	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	167668	0	0
T2	178611	1064	0	0
T3	117346	619	0	0
T4	923	0	0	0
T5	20698	0	0	0
T6	96714	0	0	0
T7	93764	0	0	0
T8	447173	1006	0	0
T9	418352	0	0	0
T10	275880	423	0	0
T11	124822	0	0	0
T12	0	635	0	0
T13	0	64	0	0
T15	0	446	0	0
T16	0	835	0	0
T17	0	13	0	0
T23	0	425	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425541073	346409	0	0
DepthKnown_A	425541073	425411279	0	0
RvalidKnown_A	425541073	425411279	0	0
WreadyKnown_A	425541073	425411279	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	346409	0	0
T2	178611	1064	0	0
T3	117346	619	0	0
T4	923	0	0	0
T5	20698	0	0	0
T6	96714	0	0	0
T7	93764	0	0	0
T8	447173	4190	0	0
T9	418352	0	0	0
T10	275880	1089	0	0
T11	124822	0	0	0
T12	0	635	0	0
T13	0	64	0	0
T15	0	446	0	0
T16	0	835	0	0
T17	0	13	0	0
T23	0	425	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425541073	6774638	0	0
DepthKnown_A	425541073	425411279	0	0
RvalidKnown_A	425541073	425411279	0	0
WreadyKnown_A	425541073	425411279	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	6774638	0	0
T1	951	6	0	0
T2	178611	33786	0	0
T3	117346	3756	0	0
T4	923	10	0	0
T5	20698	49	0	0
T6	96714	199	0	0
T7	93764	3126	0	0
T8	447173	12319	0	0
T9	418352	778	0	0
T10	275880	10242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	425541073	12913637	0	0
DepthKnown_A	425541073	425411279	0	0
RvalidKnown_A	425541073	425411279	0	0
WreadyKnown_A	425541073	425411279	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	12913637	0	0
T1	951	6	0	0
T2	178611	33626	0	0
T3	117346	3734	0	0
T4	923	10	0	0
T5	20698	49	0	0
T6	96714	836	0	0
T7	93764	3126	0	0
T8	447173	44278	0	0
T9	418352	778	0	0
T10	275880	22480	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425541073	425411279	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0