Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	682114847	551225255	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	682114847	3219565	0	0
GntImpliesValid_A	682114847	3219565	0	0
GrantKnown_A	682114847	551225255	0	0
IdxKnown_A	682114847	551225255	0	0
IndexIsCorrect_A	682114847	3219565	0	0
LockArbDecision_A	682114847	0	0	0
NoReadyValidNoGrant_A	682114847	0	0	0
ReadyAndValidImplyGrant_A	682114847	3219565	0	0
ReqAndReadyImplyGrant_A	682114847	3219565	0	0
ReqImpliesValid_A	682114847	3219565	0	0
ReqStaysHighUntilGranted0_M	682114847	0	0	0
RoundRobin_A	682114847	5	0	926
ValidKnown_A	682114847	551225255	0	0
gen_data_port_assertion.DataFlow_A	682114847	3219565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	551225255	0	0
T1	951	861	0	0
T2	1339145	753623	0	0
T3	541742	326774	0	0
T4	923	860	0	0
T5	164830	92679	0	0
T6	124198	110386	0	0
T7	438244	265434	0	0
T8	1432491	931782	0	0
T9	549346	479094	0	0
T10	951546	610735	0	0
T11	60696	30348	0	0
T12	308762	151842	0	0
T13	0	13402	0	0
T14	0	27792	0	0
T15	0	65496	0	0
T16	0	159648	0	0
T17	0	1008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	3219565	0	0
T2	1339145	17467	0	0
T3	541742	6341	0	0
T4	923	0	0	0
T5	164830	832	0	0
T6	124198	832	0	0
T7	438244	832	0	0
T8	1432491	14392	0	0
T9	549346	0	0	0
T10	951546	12152	0	0
T11	185518	832	0	0
T12	308762	6457	0	0
T13	0	1156	0	0
T15	0	2478	0	0
T16	0	7068	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	6716	0	0
T36	0	6090	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	3219565	0	0
T2	1339145	17467	0	0
T3	541742	6341	0	0
T4	923	0	0	0
T5	164830	832	0	0
T6	124198	832	0	0
T7	438244	832	0	0
T8	1432491	14392	0	0
T9	549346	0	0	0
T10	951546	12152	0	0
T11	185518	832	0	0
T12	308762	6457	0	0
T13	0	1156	0	0
T15	0	2478	0	0
T16	0	7068	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	6716	0	0
T36	0	6090	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	551225255	0	0
T1	951	861	0	0
T2	1339145	753623	0	0
T3	541742	326774	0	0
T4	923	860	0	0
T5	164830	92679	0	0
T6	124198	110386	0	0
T7	438244	265434	0	0
T8	1432491	931782	0	0
T9	549346	479094	0	0
T10	951546	610735	0	0
T11	60696	30348	0	0
T12	308762	151842	0	0
T13	0	13402	0	0
T14	0	27792	0	0
T15	0	65496	0	0
T16	0	159648	0	0
T17	0	1008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	551225255	0	0
T1	951	861	0	0
T2	1339145	753623	0	0
T3	541742	326774	0	0
T4	923	860	0	0
T5	164830	92679	0	0
T6	124198	110386	0	0
T7	438244	265434	0	0
T8	1432491	931782	0	0
T9	549346	479094	0	0
T10	951546	610735	0	0
T11	60696	30348	0	0
T12	308762	151842	0	0
T13	0	13402	0	0
T14	0	27792	0	0
T15	0	65496	0	0
T16	0	159648	0	0
T17	0	1008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	3219565	0	0
T2	1339145	17467	0	0
T3	541742	6341	0	0
T4	923	0	0	0
T5	164830	832	0	0
T6	124198	832	0	0
T7	438244	832	0	0
T8	1432491	14392	0	0
T9	549346	0	0	0
T10	951546	12152	0	0
T11	185518	832	0	0
T12	308762	6457	0	0
T13	0	1156	0	0
T15	0	2478	0	0
T16	0	7068	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	6716	0	0
T36	0	6090	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	3219565	0	0
T2	1339145	17467	0	0
T3	541742	6341	0	0
T4	923	0	0	0
T5	164830	832	0	0
T6	124198	832	0	0
T7	438244	832	0	0
T8	1432491	14392	0	0
T9	549346	0	0	0
T10	951546	12152	0	0
T11	185518	832	0	0
T12	308762	6457	0	0
T13	0	1156	0	0
T15	0	2478	0	0
T16	0	7068	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	6716	0	0
T36	0	6090	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	3219565	0	0
T2	1339145	17467	0	0
T3	541742	6341	0	0
T4	923	0	0	0
T5	164830	832	0	0
T6	124198	832	0	0
T7	438244	832	0	0
T8	1432491	14392	0	0
T9	549346	0	0	0
T10	951546	12152	0	0
T11	185518	832	0	0
T12	308762	6457	0	0
T13	0	1156	0	0
T15	0	2478	0	0
T16	0	7068	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	6716	0	0
T36	0	6090	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	3219565	0	0
T2	1339145	17467	0	0
T3	541742	6341	0	0
T4	923	0	0	0
T5	164830	832	0	0
T6	124198	832	0	0
T7	438244	832	0	0
T8	1432491	14392	0	0
T9	549346	0	0	0
T10	951546	12152	0	0
T11	185518	832	0	0
T12	308762	6457	0	0
T13	0	1156	0	0
T15	0	2478	0	0
T16	0	7068	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	6716	0	0
T36	0	6090	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	5	0	926
T37	565910	1	0	1
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	4468	0	0	1
T42	331851	0	0	1
T43	1043	0	0	1
T44	2208	0	0	1
T45	215323	0	0	1
T46	795	0	0	1
T47	12810	0	0	1
T48	6506	0	0	1
T49	224479	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	551225255	0	0
T1	951	861	0	0
T2	1339145	753623	0	0
T3	541742	326774	0	0
T4	923	860	0	0
T5	164830	92679	0	0
T6	124198	110386	0	0
T7	438244	265434	0	0
T8	1432491	931782	0	0
T9	549346	479094	0	0
T10	951546	610735	0	0
T11	60696	30348	0	0
T12	308762	151842	0	0
T13	0	13402	0	0
T14	0	27792	0	0
T15	0	65496	0	0
T16	0	159648	0	0
T17	0	1008	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682114847	3219565	0	0
T2	1339145	17467	0	0
T3	541742	6341	0	0
T4	923	0	0	0
T5	164830	832	0	0
T6	124198	832	0	0
T7	438244	832	0	0
T8	1432491	14392	0	0
T9	549346	0	0	0
T10	951546	12152	0	0
T11	185518	832	0	0
T12	308762	6457	0	0
T13	0	1156	0	0
T15	0	2478	0	0
T16	0	7068	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	6716	0	0
T36	0	6090	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Unreachable
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	129466618	26169209	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	129466618	636464	0	0
GntImpliesValid_A	129466618	636464	0	0
GrantKnown_A	129466618	26169209	0	0
IdxKnown_A	129466618	26169209	0	0
IndexIsCorrect_A	129466618	636464	0	0
LockArbDecision_A	129466618	0	0	0
NoReadyValidNoGrant_A	129466618	0	0	0
ReadyAndValidImplyGrant_A	129466618	636464	0	0
ReqAndReadyImplyGrant_A	129466618	636464	0	0
ReqImpliesValid_A	129466618	636464	0	0
ReqStaysHighUntilGranted0_M	129466618	0	0	0
RoundRobin_A	129466618	0	0	0
ValidKnown_A	129466618	26169209	0	0
gen_data_port_assertion.DataFlow_A	129466618	636464	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	26169209	0	0
T2	580267	116072	0	0
T3	212198	149512	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	205144	0	0
T9	65497	60824	0	0
T10	337833	8488	0	0
T11	30348	0	0	0
T12	154381	84168	0	0
T14	0	27792	0	0
T15	0	65496	0	0
T16	0	159648	0	0
T17	0	1008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	636464	0	0
T2	580267	4329	0	0
T3	212198	3132	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	4204	0	0
T9	65497	0	0	0
T10	337833	302	0	0
T11	30348	0	0	0
T12	154381	3349	0	0
T15	0	2218	0	0
T16	0	4450	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	3624	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	636464	0	0
T2	580267	4329	0	0
T3	212198	3132	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	4204	0	0
T9	65497	0	0	0
T10	337833	302	0	0
T11	30348	0	0	0
T12	154381	3349	0	0
T15	0	2218	0	0
T16	0	4450	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	3624	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	26169209	0	0
T2	580267	116072	0	0
T3	212198	149512	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	205144	0	0
T9	65497	60824	0	0
T10	337833	8488	0	0
T11	30348	0	0	0
T12	154381	84168	0	0
T14	0	27792	0	0
T15	0	65496	0	0
T16	0	159648	0	0
T17	0	1008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	26169209	0	0
T2	580267	116072	0	0
T3	212198	149512	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	205144	0	0
T9	65497	60824	0	0
T10	337833	8488	0	0
T11	30348	0	0	0
T12	154381	84168	0	0
T14	0	27792	0	0
T15	0	65496	0	0
T16	0	159648	0	0
T17	0	1008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	636464	0	0
T2	580267	4329	0	0
T3	212198	3132	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	4204	0	0
T9	65497	0	0	0
T10	337833	302	0	0
T11	30348	0	0	0
T12	154381	3349	0	0
T15	0	2218	0	0
T16	0	4450	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	3624	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	636464	0	0
T2	580267	4329	0	0
T3	212198	3132	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	4204	0	0
T9	65497	0	0	0
T10	337833	302	0	0
T11	30348	0	0	0
T12	154381	3349	0	0
T15	0	2218	0	0
T16	0	4450	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	3624	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	636464	0	0
T2	580267	4329	0	0
T3	212198	3132	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	4204	0	0
T9	65497	0	0	0
T10	337833	302	0	0
T11	30348	0	0	0
T12	154381	3349	0	0
T15	0	2218	0	0
T16	0	4450	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	3624	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	636464	0	0
T2	580267	4329	0	0
T3	212198	3132	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	4204	0	0
T9	65497	0	0	0
T10	337833	302	0	0
T11	30348	0	0	0
T12	154381	3349	0	0
T15	0	2218	0	0
T16	0	4450	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	3624	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	26169209	0	0
T2	580267	116072	0	0
T3	212198	149512	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	205144	0	0
T9	65497	60824	0	0
T10	337833	8488	0	0
T11	30348	0	0	0
T12	154381	84168	0	0
T14	0	27792	0	0
T15	0	65496	0	0
T16	0	159648	0	0
T17	0	1008	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	636464	0	0
T2	580267	4329	0	0
T3	212198	3132	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	4204	0	0
T9	65497	0	0	0
T10	337833	302	0	0
T11	30348	0	0	0
T12	154381	3349	0	0
T15	0	2218	0	0
T16	0	4450	0	0
T17	0	58	0	0
T23	0	2467	0	0
T24	0	3624	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	129466618	101957584	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	129466618	532285	0	0
GntImpliesValid_A	129466618	532285	0	0
GrantKnown_A	129466618	101957584	0	0
IdxKnown_A	129466618	101957584	0	0
IndexIsCorrect_A	129466618	532285	0	0
LockArbDecision_A	129466618	0	0	0
NoReadyValidNoGrant_A	129466618	0	0	0
ReadyAndValidImplyGrant_A	129466618	532285	0	0
ReqAndReadyImplyGrant_A	129466618	532285	0	0
ReqImpliesValid_A	129466618	532285	0	0
ReqStaysHighUntilGranted0_M	129466618	0	0	0
RoundRobin_A	129466618	0	0	0
ValidKnown_A	129466618	101957584	0	0
gen_data_port_assertion.DataFlow_A	129466618	532285	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	101957584	0	0
T2	580267	458946	0	0
T3	212198	60013	0	0
T5	72066	72066	0	0
T6	13742	13742	0	0
T7	172240	171760	0	0
T8	492659	279763	0	0
T9	65497	0	0	0
T10	337833	326375	0	0
T11	30348	30348	0	0
T12	154381	67674	0	0
T13	0	13402	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	532285	0	0
T2	580267	5864	0	0
T3	212198	860	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	661	0	0
T9	65497	0	0	0
T10	337833	2094	0	0
T11	30348	0	0	0
T12	154381	5	0	0
T13	0	258	0	0
T15	0	260	0	0
T16	0	2618	0	0
T24	0	3092	0	0
T36	0	6090	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	532285	0	0
T2	580267	5864	0	0
T3	212198	860	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	661	0	0
T9	65497	0	0	0
T10	337833	2094	0	0
T11	30348	0	0	0
T12	154381	5	0	0
T13	0	258	0	0
T15	0	260	0	0
T16	0	2618	0	0
T24	0	3092	0	0
T36	0	6090	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	101957584	0	0
T2	580267	458946	0	0
T3	212198	60013	0	0
T5	72066	72066	0	0
T6	13742	13742	0	0
T7	172240	171760	0	0
T8	492659	279763	0	0
T9	65497	0	0	0
T10	337833	326375	0	0
T11	30348	30348	0	0
T12	154381	67674	0	0
T13	0	13402	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	101957584	0	0
T2	580267	458946	0	0
T3	212198	60013	0	0
T5	72066	72066	0	0
T6	13742	13742	0	0
T7	172240	171760	0	0
T8	492659	279763	0	0
T9	65497	0	0	0
T10	337833	326375	0	0
T11	30348	30348	0	0
T12	154381	67674	0	0
T13	0	13402	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	532285	0	0
T2	580267	5864	0	0
T3	212198	860	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	661	0	0
T9	65497	0	0	0
T10	337833	2094	0	0
T11	30348	0	0	0
T12	154381	5	0	0
T13	0	258	0	0
T15	0	260	0	0
T16	0	2618	0	0
T24	0	3092	0	0
T36	0	6090	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	532285	0	0
T2	580267	5864	0	0
T3	212198	860	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	661	0	0
T9	65497	0	0	0
T10	337833	2094	0	0
T11	30348	0	0	0
T12	154381	5	0	0
T13	0	258	0	0
T15	0	260	0	0
T16	0	2618	0	0
T24	0	3092	0	0
T36	0	6090	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	532285	0	0
T2	580267	5864	0	0
T3	212198	860	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	661	0	0
T9	65497	0	0	0
T10	337833	2094	0	0
T11	30348	0	0	0
T12	154381	5	0	0
T13	0	258	0	0
T15	0	260	0	0
T16	0	2618	0	0
T24	0	3092	0	0
T36	0	6090	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	532285	0	0
T2	580267	5864	0	0
T3	212198	860	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	661	0	0
T9	65497	0	0	0
T10	337833	2094	0	0
T11	30348	0	0	0
T12	154381	5	0	0
T13	0	258	0	0
T15	0	260	0	0
T16	0	2618	0	0
T24	0	3092	0	0
T36	0	6090	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	101957584	0	0
T2	580267	458946	0	0
T3	212198	60013	0	0
T5	72066	72066	0	0
T6	13742	13742	0	0
T7	172240	171760	0	0
T8	492659	279763	0	0
T9	65497	0	0	0
T10	337833	326375	0	0
T11	30348	30348	0	0
T12	154381	67674	0	0
T13	0	13402	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129466618	532285	0	0
T2	580267	5864	0	0
T3	212198	860	0	0
T5	72066	0	0	0
T6	13742	0	0	0
T7	172240	0	0	0
T8	492659	661	0	0
T9	65497	0	0	0
T10	337833	2094	0	0
T11	30348	0	0	0
T12	154381	5	0	0
T13	0	258	0	0
T15	0	260	0	0
T16	0	2618	0	0
T24	0	3092	0	0
T36	0	6090	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423181611	423098462	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	423181611	2050816	0	0
GntImpliesValid_A	423181611	2050816	0	0
GrantKnown_A	423181611	423098462	0	0
IdxKnown_A	423181611	423098462	0	0
IndexIsCorrect_A	423181611	2050816	0	0
LockArbDecision_A	423181611	0	0	0
NoReadyValidNoGrant_A	423181611	0	0	0
ReadyAndValidImplyGrant_A	423181611	2050816	0	0
ReqAndReadyImplyGrant_A	423181611	2050816	0	0
ReqImpliesValid_A	423181611	2050816	0	0
ReqStaysHighUntilGranted0_M	423181611	0	0	0
RoundRobin_A	423181611	5	0	926
ValidKnown_A	423181611	423098462	0	0
gen_data_port_assertion.DataFlow_A	423181611	2050816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	2050816	0	0
T2	178611	7274	0	0
T3	117346	2349	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	832	0	0
T8	447173	9527	0	0
T9	418352	0	0	0
T10	275880	9756	0	0
T11	124822	832	0	0
T12	0	3103	0	0
T13	0	898	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	2050816	0	0
T2	178611	7274	0	0
T3	117346	2349	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	832	0	0
T8	447173	9527	0	0
T9	418352	0	0	0
T10	275880	9756	0	0
T11	124822	832	0	0
T12	0	3103	0	0
T13	0	898	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	2050816	0	0
T2	178611	7274	0	0
T3	117346	2349	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	832	0	0
T8	447173	9527	0	0
T9	418352	0	0	0
T10	275880	9756	0	0
T11	124822	832	0	0
T12	0	3103	0	0
T13	0	898	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	2050816	0	0
T2	178611	7274	0	0
T3	117346	2349	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	832	0	0
T8	447173	9527	0	0
T9	418352	0	0	0
T10	275880	9756	0	0
T11	124822	832	0	0
T12	0	3103	0	0
T13	0	898	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	2050816	0	0
T2	178611	7274	0	0
T3	117346	2349	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	832	0	0
T8	447173	9527	0	0
T9	418352	0	0	0
T10	275880	9756	0	0
T11	124822	832	0	0
T12	0	3103	0	0
T13	0	898	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	2050816	0	0
T2	178611	7274	0	0
T3	117346	2349	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	832	0	0
T8	447173	9527	0	0
T9	418352	0	0	0
T10	275880	9756	0	0
T11	124822	832	0	0
T12	0	3103	0	0
T13	0	898	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	5	0	926
T37	565910	1	0	1
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	4468	0	0	1
T42	331851	0	0	1
T43	1043	0	0	1
T44	2208	0	0	1
T45	215323	0	0	1
T46	795	0	0	1
T47	12810	0	0	1
T48	6506	0	0	1
T49	224479	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	423098462	0	0
T1	951	861	0	0
T2	178611	178605	0	0
T3	117346	117249	0	0
T4	923	860	0	0
T5	20698	20613	0	0
T6	96714	96644	0	0
T7	93764	93674	0	0
T8	447173	446875	0	0
T9	418352	418270	0	0
T10	275880	275872	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423181611	2050816	0	0
T2	178611	7274	0	0
T3	117346	2349	0	0
T4	923	0	0	0
T5	20698	832	0	0
T6	96714	832	0	0
T7	93764	832	0	0
T8	447173	9527	0	0
T9	418352	0	0	0
T10	275880	9756	0	0
T11	124822	832	0	0
T12	0	3103	0	0
T13	0	898	0	0