Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3660943	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4025967

1

T1

946

T2

30928

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4326241	1			T1	119		T2	60068		T3	1
values[0x0]	1679609	1			T1	470		T2	462		T3	20
values[0x1]	1681060	1			T1	429		T2	441		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2592284	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5094626

1

T1

960

T2

36952

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28524	1			T4	4		T6	18		T7	17
valid_sources[0x01]	28443	1			T4	3		T5	2		T6	10
valid_sources[0x02]	27950	1			T4	3		T5	2		T6	11
valid_sources[0x03]	30620	1			T4	3		T5	5		T6	9
valid_sources[0x04]	30114	1			T4	3		T5	4		T6	15
valid_sources[0x05]	26503	1			T4	5		T5	3		T6	8
valid_sources[0x06]	33414	1			T4	6		T5	5		T6	9
valid_sources[0x07]	29710	1			T4	1		T5	3		T6	9
valid_sources[0x08]	29310	1			T3	1		T4	6		T5	4
valid_sources[0x09]	31669	1			T3	1		T4	4		T5	3
valid_sources[0x0a]	30291	1			T4	1		T5	6		T6	8
valid_sources[0x0b]	28361	1			T4	1		T5	2		T6	9
valid_sources[0x0c]	28238	1			T4	3		T5	4		T6	8
valid_sources[0x0d]	31899	1			T4	3		T5	7		T6	17
valid_sources[0x0e]	29610	1			T4	2		T5	5		T6	13
valid_sources[0x0f]	27559	1			T4	9		T5	3		T6	15
valid_sources[0x10]	25820	1			T4	4		T5	4		T6	15
valid_sources[0x11]	29625	1			T4	6		T5	3		T6	13
valid_sources[0x12]	31104	1			T4	4		T5	2		T6	10
valid_sources[0x13]	29113	1			T4	3		T5	5		T6	19
valid_sources[0x14]	28013	1			T4	1		T5	3		T6	13
valid_sources[0x15]	27513	1			T4	5		T5	4		T6	8
valid_sources[0x16]	30530	1			T4	2		T5	4		T6	12
valid_sources[0x17]	31229	1			T4	7		T5	7		T6	14
valid_sources[0x18]	28132	1			T4	2		T5	3		T6	11
valid_sources[0x19]	28304	1			T3	1		T4	7		T5	2
valid_sources[0x1a]	27777	1			T4	3		T5	1		T6	11
valid_sources[0x1b]	28224	1			T1	456		T4	1		T5	1
valid_sources[0x1c]	27867	1			T4	6		T5	5		T6	11
valid_sources[0x1d]	30005	1			T3	1		T4	1		T5	1
valid_sources[0x1e]	30156	1			T4	2		T5	2		T6	9
valid_sources[0x1f]	29078	1			T4	5		T5	5		T6	9
valid_sources[0x20]	29986	1			T4	4		T5	4		T6	9
valid_sources[0x21]	27160	1			T4	2		T5	1		T6	9
valid_sources[0x22]	29587	1			T4	4		T5	4		T6	17
valid_sources[0x23]	30877	1			T4	3		T5	3		T6	6
valid_sources[0x24]	29427	1			T4	4		T5	4		T6	7
valid_sources[0x25]	30600	1			T4	1		T5	3		T6	8
valid_sources[0x26]	27627	1			T3	1		T4	9		T5	1
valid_sources[0x27]	29986	1			T4	2		T5	3		T6	16
valid_sources[0x28]	27052	1			T4	5		T5	1		T6	15
valid_sources[0x29]	27385	1			T1	562		T4	6		T5	4
valid_sources[0x2a]	27958	1			T4	4		T5	3		T6	13
valid_sources[0x2b]	37463	1			T4	5		T5	2		T6	14
valid_sources[0x2c]	28838	1			T3	1		T4	1		T5	1
valid_sources[0x2d]	29722	1			T4	3		T5	6		T6	8
valid_sources[0x2e]	28931	1			T4	2		T5	5		T6	8
valid_sources[0x2f]	30676	1			T4	9		T5	3		T6	12
valid_sources[0x30]	35449	1			T4	4		T5	2		T6	8
valid_sources[0x31]	30384	1			T4	4		T5	5		T6	9
valid_sources[0x32]	30803	1			T4	6		T5	1		T6	7
valid_sources[0x33]	28150	1			T4	3		T5	3		T6	10
valid_sources[0x34]	28113	1			T4	3		T5	2		T6	14
valid_sources[0x35]	27519	1			T5	3		T6	14		T7	10
valid_sources[0x36]	29858	1			T4	4		T5	3		T6	6
valid_sources[0x37]	26983	1			T4	3		T5	7		T6	10
valid_sources[0x38]	28962	1			T4	2		T5	5		T6	12
valid_sources[0x39]	29516	1			T4	3		T5	3		T6	10
valid_sources[0x3a]	29884	1			T4	2		T5	3		T6	12
valid_sources[0x3b]	31401	1			T4	6		T5	4		T6	15
valid_sources[0x3c]	27602	1			T4	1		T5	6		T6	11
valid_sources[0x3d]	27823	1			T4	2		T5	6		T6	17
valid_sources[0x3e]	27762	1			T3	1		T4	3		T5	2
valid_sources[0x3f]	28132	1			T3	1		T4	7		T5	7
valid_sources[0x40]	28296	1			T3	1		T4	7		T6	10
valid_sources[0x41]	30834	1			T4	3		T5	5		T6	8
valid_sources[0x42]	28468	1			T4	4		T5	9		T6	11
valid_sources[0x43]	30930	1			T3	1		T4	2		T5	3
valid_sources[0x44]	30523	1			T4	2		T5	2		T6	8
valid_sources[0x45]	28760	1			T4	1		T5	4		T6	14
valid_sources[0x46]	26995	1			T4	1		T5	1		T6	8
valid_sources[0x47]	28291	1			T4	7		T5	2		T6	14
valid_sources[0x48]	30647	1			T4	5		T5	5		T6	14
valid_sources[0x49]	30062	1			T4	4		T5	6		T6	4
valid_sources[0x4a]	36605	1			T4	1		T5	2		T6	13
valid_sources[0x4b]	27984	1			T3	1		T4	5		T5	2
valid_sources[0x4c]	29019	1			T3	1		T4	2		T5	5
valid_sources[0x4d]	28323	1			T4	4		T5	7		T6	14
valid_sources[0x4e]	33184	1			T4	1		T5	1		T6	11
valid_sources[0x4f]	27958	1			T4	5		T5	3		T6	2
valid_sources[0x50]	30106	1			T4	1		T5	3		T6	12
valid_sources[0x51]	26478	1			T4	8		T5	4		T6	11
valid_sources[0x52]	29431	1			T4	6		T5	3		T6	11
valid_sources[0x53]	28814	1			T4	1		T5	2		T6	7
valid_sources[0x54]	28173	1			T3	1		T4	6		T5	3
valid_sources[0x55]	28719	1			T4	4		T5	4		T6	10
valid_sources[0x56]	31567	1			T4	6		T5	5		T6	12
valid_sources[0x57]	30303	1			T4	4		T5	2		T6	13
valid_sources[0x58]	27125	1			T4	4		T5	1		T6	16
valid_sources[0x59]	26855	1			T4	3		T5	2		T6	8
valid_sources[0x5a]	29479	1			T4	4		T5	3		T6	7
valid_sources[0x5b]	28954	1			T4	3		T5	4		T6	5
valid_sources[0x5c]	38034	1			T4	2		T5	3		T6	9
valid_sources[0x5d]	29194	1			T4	3		T5	6		T6	14
valid_sources[0x5e]	29118	1			T4	4		T5	1		T6	8
valid_sources[0x5f]	31830	1			T4	3		T5	5		T6	13
valid_sources[0x60]	34885	1			T4	2		T5	2		T6	7
valid_sources[0x61]	30091	1			T3	1		T4	2		T5	5
valid_sources[0x62]	30739	1			T4	4		T5	7		T6	15
valid_sources[0x63]	30627	1			T4	4		T5	4		T6	9
valid_sources[0x64]	46391	1			T3	1		T4	1		T5	4
valid_sources[0x65]	27890	1			T4	1		T5	6		T6	7
valid_sources[0x66]	29602	1			T4	5		T5	3		T6	15
valid_sources[0x67]	28985	1			T4	3		T5	1		T6	9
valid_sources[0x68]	31186	1			T3	1		T4	5		T5	4
valid_sources[0x69]	29413	1			T4	3		T5	3		T6	8
valid_sources[0x6a]	30412	1			T4	6		T5	5		T6	10
valid_sources[0x6b]	29847	1			T4	6		T5	3		T6	6
valid_sources[0x6c]	29071	1			T4	5		T5	3		T6	8
valid_sources[0x6d]	27053	1			T3	1		T4	3		T5	2
valid_sources[0x6e]	29895	1			T4	4		T5	3		T6	12
valid_sources[0x6f]	28079	1			T3	1		T4	5		T5	6
valid_sources[0x70]	27372	1			T4	4		T5	2		T6	11
valid_sources[0x71]	32073	1			T4	3		T5	4		T6	13
valid_sources[0x72]	29823	1			T4	3		T5	2		T6	15
valid_sources[0x73]	29151	1			T4	5		T5	2		T6	7
valid_sources[0x74]	28728	1			T3	1		T4	2		T5	4
valid_sources[0x75]	28635	1			T4	3		T5	5		T6	4
valid_sources[0x76]	32260	1			T3	1		T4	1		T5	4
valid_sources[0x77]	29415	1			T4	5		T5	2		T6	14
valid_sources[0x78]	29159	1			T3	1		T4	1		T5	1
valid_sources[0x79]	31014	1			T4	2		T5	3		T6	14
valid_sources[0x7a]	26643	1			T3	1		T4	2		T5	1
valid_sources[0x7b]	28996	1			T4	4		T5	9		T6	9
valid_sources[0x7c]	31445	1			T4	5		T5	3		T6	6
valid_sources[0x7d]	29945	1			T4	8		T5	4		T6	12
valid_sources[0x7e]	30631	1			T4	4		T5	11		T6	12
valid_sources[0x7f]	51401	1			T2	20558		T4	6		T5	4
valid_sources[0x80]	27632	1			T5	6		T6	16		T7	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1001296

1

T1

51

T2

30034

T3

1

values[0x0]

all_enables

biggest_size

1523840

1

T1

468

T2

460

T3

17

values[0x1]

all_enables

biggest_size

1500831

1

T1

427

T2

434

T3

15