Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3680117

1

T1

72

T2

30043

T3

8

full_word

4024918

1

T1

946

T2

30928

T3

33

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7704665	1			T1	1018		T2	60971		T3	41
auto[TlIntgErrCmd]	112	1			T95	3		T97	2		T98	3
auto[TlIntgErrData]	126	1			T95	2		T97	4		T98	6
auto[TlIntgErrBoth]	132	1			T95	5		T97	4		T98	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4328010

1

T1

119

T2

60068

T3

1

auto[1]

3377025

1

T1

899

T2

903

T3

40

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3326448	1			T1	68		T2	30034		T4	4
auto[TlIntgErrNone]	partial	auto[1]	353339	1			T1	4		T2	9		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	1001397	1			T1	51		T2	30034		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3023481	1			T1	895		T2	894		T3	32
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T95	1		T97	1		T98	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T95	2		T97	1		T98	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T238	1		T239	1		T236	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T110	1		T140	1		T239	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T97	1		T98	3		T111	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T95	2		T97	3		T98	3
auto[TlIntgErrData]	full_word	auto[0]	13	1			T140	1		T240	1		T238	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T111	1		T240	1		T236	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T95	3		T97	2		T111	1
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T95	1		T97	2		T98	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T111	1		T140	1		T239	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T95	1		T239	1		T236	1