Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T14
1	0	Unreachable
1	1	Covered	T13,T14,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T20,T21

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T20,T21
1	0	Covered	T14,T20,T21

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T14,T20,T21

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	673353810	537778591	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	673353810	3182015	0	0
GntImpliesValid_A	673353810	3182015	0	0
GrantKnown_A	673353810	537778591	0	0
IdxKnown_A	673353810	537778591	0	0
IndexIsCorrect_A	673353810	3182015	0	0
LockArbDecision_A	673353810	0	0	0
NoReadyValidNoGrant_A	673353810	0	0	0
ReadyAndValidImplyGrant_A	673353810	3182015	0	0
ReqAndReadyImplyGrant_A	673353810	3182015	0	0
ReqImpliesValid_A	673353810	3182015	0	0
ReqStaysHighUntilGranted0_M	673353810	0	0	0
RoundRobin_A	673353810	3	0	926
ValidKnown_A	673353810	537778591	0	0
gen_data_port_assertion.DataFlow_A	673353810	3182015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	537778591	0	0
T1	20961	20764	0	0
T2	1081916	1081769	0	0
T3	5055	4069	0	0
T4	833271	729157	0	0
T5	2675	2587	0	0
T6	84468	64216	0	0
T7	71000	48020	0	0
T8	1137	1086	0	0
T9	38624	28868	0	0
T10	76727	58225	0	0
T11	18414	9002	0	0
T12	28926	28926	0	0
T13	2664	2664	0	0
T14	0	151280	0	0
T15	0	56032	0	0
T16	0	29840	0	0
T17	0	20744	0	0
T20	0	62352	0	0
T21	0	116240	0	0
T22	0	249912	0	0
T29	0	109728	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	3182015	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	2664	177	0	0
T14	1217174	8871	0	0
T15	115660	2557	0	0
T16	62292	0	0	0
T17	44934	0	0	0
T20	683908	2835	0	0
T21	409426	4846	0	0
T22	0	2548	0	0
T23	0	2664	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	16842	0	0
T32	0	8810	0	0
T33	35258	0	0	0
T35	202882	0	0	0
T51	314672	0	0	0
T52	133646	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	3182015	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	2664	177	0	0
T14	1217174	8871	0	0
T15	115660	2557	0	0
T16	62292	0	0	0
T17	44934	0	0	0
T20	683908	2835	0	0
T21	409426	4846	0	0
T22	0	2548	0	0
T23	0	2664	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	16842	0	0
T32	0	8810	0	0
T33	35258	0	0	0
T35	202882	0	0	0
T51	314672	0	0	0
T52	133646	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	537778591	0	0
T1	20961	20764	0	0
T2	1081916	1081769	0	0
T3	5055	4069	0	0
T4	833271	729157	0	0
T5	2675	2587	0	0
T6	84468	64216	0	0
T7	71000	48020	0	0
T8	1137	1086	0	0
T9	38624	28868	0	0
T10	76727	58225	0	0
T11	18414	9002	0	0
T12	28926	28926	0	0
T13	2664	2664	0	0
T14	0	151280	0	0
T15	0	56032	0	0
T16	0	29840	0	0
T17	0	20744	0	0
T20	0	62352	0	0
T21	0	116240	0	0
T22	0	249912	0	0
T29	0	109728	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	537778591	0	0
T1	20961	20764	0	0
T2	1081916	1081769	0	0
T3	5055	4069	0	0
T4	833271	729157	0	0
T5	2675	2587	0	0
T6	84468	64216	0	0
T7	71000	48020	0	0
T8	1137	1086	0	0
T9	38624	28868	0	0
T10	76727	58225	0	0
T11	18414	9002	0	0
T12	28926	28926	0	0
T13	2664	2664	0	0
T14	0	151280	0	0
T15	0	56032	0	0
T16	0	29840	0	0
T17	0	20744	0	0
T20	0	62352	0	0
T21	0	116240	0	0
T22	0	249912	0	0
T29	0	109728	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	3182015	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	2664	177	0	0
T14	1217174	8871	0	0
T15	115660	2557	0	0
T16	62292	0	0	0
T17	44934	0	0	0
T20	683908	2835	0	0
T21	409426	4846	0	0
T22	0	2548	0	0
T23	0	2664	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	16842	0	0
T32	0	8810	0	0
T33	35258	0	0	0
T35	202882	0	0	0
T51	314672	0	0	0
T52	133646	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	3182015	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	2664	177	0	0
T14	1217174	8871	0	0
T15	115660	2557	0	0
T16	62292	0	0	0
T17	44934	0	0	0
T20	683908	2835	0	0
T21	409426	4846	0	0
T22	0	2548	0	0
T23	0	2664	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	16842	0	0
T32	0	8810	0	0
T33	35258	0	0	0
T35	202882	0	0	0
T51	314672	0	0	0
T52	133646	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	3182015	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	2664	177	0	0
T14	1217174	8871	0	0
T15	115660	2557	0	0
T16	62292	0	0	0
T17	44934	0	0	0
T20	683908	2835	0	0
T21	409426	4846	0	0
T22	0	2548	0	0
T23	0	2664	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	16842	0	0
T32	0	8810	0	0
T33	35258	0	0	0
T35	202882	0	0	0
T51	314672	0	0	0
T52	133646	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	3182015	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	2664	177	0	0
T14	1217174	8871	0	0
T15	115660	2557	0	0
T16	62292	0	0	0
T17	44934	0	0	0
T20	683908	2835	0	0
T21	409426	4846	0	0
T22	0	2548	0	0
T23	0	2664	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	16842	0	0
T32	0	8810	0	0
T33	35258	0	0	0
T35	202882	0	0	0
T51	314672	0	0	0
T52	133646	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	3	0	926
T53	998537	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	113651	0	0	1
T57	1053	0	0	1
T58	229582	0	0	1
T59	324007	0	0	1
T60	276348	0	0	1
T61	429637	0	0	1
T62	75969	0	0	1
T63	805636	0	0	1
T64	633967	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	537778591	0	0
T1	20961	20764	0	0
T2	1081916	1081769	0	0
T3	5055	4069	0	0
T4	833271	729157	0	0
T5	2675	2587	0	0
T6	84468	64216	0	0
T7	71000	48020	0	0
T8	1137	1086	0	0
T9	38624	28868	0	0
T10	76727	58225	0	0
T11	18414	9002	0	0
T12	28926	28926	0	0
T13	2664	2664	0	0
T14	0	151280	0	0
T15	0	56032	0	0
T16	0	29840	0	0
T17	0	20744	0	0
T20	0	62352	0	0
T21	0	116240	0	0
T22	0	249912	0	0
T29	0	109728	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	673353810	3182015	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	2664	177	0	0
T14	1217174	8871	0	0
T15	115660	2557	0	0
T16	62292	0	0	0
T17	44934	0	0	0
T20	683908	2835	0	0
T21	409426	4846	0	0
T22	0	2548	0	0
T23	0	2664	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	16842	0	0
T32	0	8810	0	0
T33	35258	0	0	0
T35	202882	0	0	0
T51	314672	0	0	0
T52	133646	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T14
1	0	Unreachable
1	1	Covered	T13,T14,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T14,T15
0	0	1	Unreachable
0	0	0	Covered	T3,T13,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	134221485	26879286	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	134221485	621946	0	0
GntImpliesValid_A	134221485	621946	0	0
GrantKnown_A	134221485	26879286	0	0
IdxKnown_A	134221485	26879286	0	0
IndexIsCorrect_A	134221485	621946	0	0
LockArbDecision_A	134221485	0	0	0
NoReadyValidNoGrant_A	134221485	0	0	0
ReadyAndValidImplyGrant_A	134221485	621946	0	0
ReqAndReadyImplyGrant_A	134221485	621946	0	0
ReqImpliesValid_A	134221485	621946	0	0
ReqStaysHighUntilGranted0_M	134221485	0	0	0
RoundRobin_A	134221485	0	0	0
ValidKnown_A	134221485	26879286	0	0
gen_data_port_assertion.DataFlow_A	134221485	621946	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	26879286	0	0
T3	936	936	0	0
T4	103519	0	0	0
T5	16	0	0	0
T6	20152	0	0	0
T7	22637	0	0	0
T9	9168	0	0	0
T10	18294	0	0	0
T11	9207	0	0	0
T12	28926	0	0	0
T13	2664	2664	0	0
T14	0	151280	0	0
T15	0	56032	0	0
T16	0	29840	0	0
T17	0	20744	0	0
T20	0	62352	0	0
T21	0	116240	0	0
T22	0	249912	0	0
T29	0	109728	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	621946	0	0
T13	2664	177	0	0
T14	608587	3621	0	0
T15	57830	2557	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	2831	0	0
T21	0	4451	0	0
T22	0	2548	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	7460	0	0
T32	0	2155	0	0
T33	35258	0	0	0
T35	101441	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	621946	0	0
T13	2664	177	0	0
T14	608587	3621	0	0
T15	57830	2557	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	2831	0	0
T21	0	4451	0	0
T22	0	2548	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	7460	0	0
T32	0	2155	0	0
T33	35258	0	0	0
T35	101441	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	26879286	0	0
T3	936	936	0	0
T4	103519	0	0	0
T5	16	0	0	0
T6	20152	0	0	0
T7	22637	0	0	0
T9	9168	0	0	0
T10	18294	0	0	0
T11	9207	0	0	0
T12	28926	0	0	0
T13	2664	2664	0	0
T14	0	151280	0	0
T15	0	56032	0	0
T16	0	29840	0	0
T17	0	20744	0	0
T20	0	62352	0	0
T21	0	116240	0	0
T22	0	249912	0	0
T29	0	109728	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	26879286	0	0
T3	936	936	0	0
T4	103519	0	0	0
T5	16	0	0	0
T6	20152	0	0	0
T7	22637	0	0	0
T9	9168	0	0	0
T10	18294	0	0	0
T11	9207	0	0	0
T12	28926	0	0	0
T13	2664	2664	0	0
T14	0	151280	0	0
T15	0	56032	0	0
T16	0	29840	0	0
T17	0	20744	0	0
T20	0	62352	0	0
T21	0	116240	0	0
T22	0	249912	0	0
T29	0	109728	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	621946	0	0
T13	2664	177	0	0
T14	608587	3621	0	0
T15	57830	2557	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	2831	0	0
T21	0	4451	0	0
T22	0	2548	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	7460	0	0
T32	0	2155	0	0
T33	35258	0	0	0
T35	101441	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	621946	0	0
T13	2664	177	0	0
T14	608587	3621	0	0
T15	57830	2557	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	2831	0	0
T21	0	4451	0	0
T22	0	2548	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	7460	0	0
T32	0	2155	0	0
T33	35258	0	0	0
T35	101441	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	621946	0	0
T13	2664	177	0	0
T14	608587	3621	0	0
T15	57830	2557	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	2831	0	0
T21	0	4451	0	0
T22	0	2548	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	7460	0	0
T32	0	2155	0	0
T33	35258	0	0	0
T35	101441	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	621946	0	0
T13	2664	177	0	0
T14	608587	3621	0	0
T15	57830	2557	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	2831	0	0
T21	0	4451	0	0
T22	0	2548	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	7460	0	0
T32	0	2155	0	0
T33	35258	0	0	0
T35	101441	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	26879286	0	0
T3	936	936	0	0
T4	103519	0	0	0
T5	16	0	0	0
T6	20152	0	0	0
T7	22637	0	0	0
T9	9168	0	0	0
T10	18294	0	0	0
T11	9207	0	0	0
T12	28926	0	0	0
T13	2664	2664	0	0
T14	0	151280	0	0
T15	0	56032	0	0
T16	0	29840	0	0
T17	0	20744	0	0
T20	0	62352	0	0
T21	0	116240	0	0
T22	0	249912	0	0
T29	0	109728	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	621946	0	0
T13	2664	177	0	0
T14	608587	3621	0	0
T15	57830	2557	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	2831	0	0
T21	0	4451	0	0
T22	0	2548	0	0
T29	0	3555	0	0
T30	0	2736	0	0
T31	0	7460	0	0
T32	0	2155	0	0
T33	35258	0	0	0
T35	101441	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T20,T21

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T20,T21
1	0	Covered	T14,T20,T21

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T14,T20,T21

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T20,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T14,T20,T21
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T14,T20,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T14,T20,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	134221485	106073494	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	134221485	519895	0	0
GntImpliesValid_A	134221485	519895	0	0
GrantKnown_A	134221485	106073494	0	0
IdxKnown_A	134221485	106073494	0	0
IndexIsCorrect_A	134221485	519895	0	0
LockArbDecision_A	134221485	0	0	0
NoReadyValidNoGrant_A	134221485	0	0	0
ReadyAndValidImplyGrant_A	134221485	519895	0	0
ReqAndReadyImplyGrant_A	134221485	519895	0	0
ReqImpliesValid_A	134221485	519895	0	0
ReqStaysHighUntilGranted0_M	134221485	0	0	0
RoundRobin_A	134221485	0	0	0
ValidKnown_A	134221485	106073494	0	0
gen_data_port_assertion.DataFlow_A	134221485	519895	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	106073494	0	0
T1	14040	13936	0	0
T2	119939	119866	0	0
T3	936	0	0	0
T4	103519	102996	0	0
T5	16	16	0	0
T6	20152	20152	0	0
T7	22637	22384	0	0
T9	9168	8672	0	0
T10	18294	18136	0	0
T11	9207	9002	0	0
T12	0	28926	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	519895	0	0
T14	608587	5250	0	0
T15	57830	0	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	4	0	0
T21	409426	395	0	0
T23	0	2664	0	0
T31	0	9382	0	0
T32	0	6655	0	0
T35	101441	0	0	0
T37	0	7567	0	0
T38	0	6740	0	0
T43	13144	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0
T65	0	985	0	0
T66	0	285	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	519895	0	0
T14	608587	5250	0	0
T15	57830	0	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	4	0	0
T21	409426	395	0	0
T23	0	2664	0	0
T31	0	9382	0	0
T32	0	6655	0	0
T35	101441	0	0	0
T37	0	7567	0	0
T38	0	6740	0	0
T43	13144	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0
T65	0	985	0	0
T66	0	285	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	106073494	0	0
T1	14040	13936	0	0
T2	119939	119866	0	0
T3	936	0	0	0
T4	103519	102996	0	0
T5	16	16	0	0
T6	20152	20152	0	0
T7	22637	22384	0	0
T9	9168	8672	0	0
T10	18294	18136	0	0
T11	9207	9002	0	0
T12	0	28926	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	106073494	0	0
T1	14040	13936	0	0
T2	119939	119866	0	0
T3	936	0	0	0
T4	103519	102996	0	0
T5	16	16	0	0
T6	20152	20152	0	0
T7	22637	22384	0	0
T9	9168	8672	0	0
T10	18294	18136	0	0
T11	9207	9002	0	0
T12	0	28926	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	519895	0	0
T14	608587	5250	0	0
T15	57830	0	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	4	0	0
T21	409426	395	0	0
T23	0	2664	0	0
T31	0	9382	0	0
T32	0	6655	0	0
T35	101441	0	0	0
T37	0	7567	0	0
T38	0	6740	0	0
T43	13144	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0
T65	0	985	0	0
T66	0	285	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	519895	0	0
T14	608587	5250	0	0
T15	57830	0	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	4	0	0
T21	409426	395	0	0
T23	0	2664	0	0
T31	0	9382	0	0
T32	0	6655	0	0
T35	101441	0	0	0
T37	0	7567	0	0
T38	0	6740	0	0
T43	13144	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0
T65	0	985	0	0
T66	0	285	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	519895	0	0
T14	608587	5250	0	0
T15	57830	0	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	4	0	0
T21	409426	395	0	0
T23	0	2664	0	0
T31	0	9382	0	0
T32	0	6655	0	0
T35	101441	0	0	0
T37	0	7567	0	0
T38	0	6740	0	0
T43	13144	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0
T65	0	985	0	0
T66	0	285	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	519895	0	0
T14	608587	5250	0	0
T15	57830	0	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	4	0	0
T21	409426	395	0	0
T23	0	2664	0	0
T31	0	9382	0	0
T32	0	6655	0	0
T35	101441	0	0	0
T37	0	7567	0	0
T38	0	6740	0	0
T43	13144	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0
T65	0	985	0	0
T66	0	285	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	106073494	0	0
T1	14040	13936	0	0
T2	119939	119866	0	0
T3	936	0	0	0
T4	103519	102996	0	0
T5	16	16	0	0
T6	20152	20152	0	0
T7	22637	22384	0	0
T9	9168	8672	0	0
T10	18294	18136	0	0
T11	9207	9002	0	0
T12	0	28926	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134221485	519895	0	0
T14	608587	5250	0	0
T15	57830	0	0	0
T16	31146	0	0	0
T17	22467	0	0	0
T20	341954	4	0	0
T21	409426	395	0	0
T23	0	2664	0	0
T31	0	9382	0	0
T32	0	6655	0	0
T35	101441	0	0	0
T37	0	7567	0	0
T38	0	6740	0	0
T43	13144	0	0	0
T51	157336	0	0	0
T52	66823	0	0	0
T65	0	985	0	0
T66	0	285	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404910840	404825811	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	404910840	2040174	0	0
GntImpliesValid_A	404910840	2040174	0	0
GrantKnown_A	404910840	404825811	0	0
IdxKnown_A	404910840	404825811	0	0
IndexIsCorrect_A	404910840	2040174	0	0
LockArbDecision_A	404910840	0	0	0
NoReadyValidNoGrant_A	404910840	0	0	0
ReadyAndValidImplyGrant_A	404910840	2040174	0	0
ReqAndReadyImplyGrant_A	404910840	2040174	0	0
ReqImpliesValid_A	404910840	2040174	0	0
ReqStaysHighUntilGranted0_M	404910840	0	0	0
RoundRobin_A	404910840	3	0	926
ValidKnown_A	404910840	404825811	0	0
gen_data_port_assertion.DataFlow_A	404910840	2040174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	404825811	0	0
T1	6921	6828	0	0
T2	961977	961903	0	0
T3	3183	3133	0	0
T4	626233	626161	0	0
T5	2643	2571	0	0
T6	44164	44064	0	0
T7	25726	25636	0	0
T8	1137	1086	0	0
T9	20288	20196	0	0
T10	40139	40089	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	2040174	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	2040174	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	404825811	0	0
T1	6921	6828	0	0
T2	961977	961903	0	0
T3	3183	3133	0	0
T4	626233	626161	0	0
T5	2643	2571	0	0
T6	44164	44064	0	0
T7	25726	25636	0	0
T8	1137	1086	0	0
T9	20288	20196	0	0
T10	40139	40089	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	404825811	0	0
T1	6921	6828	0	0
T2	961977	961903	0	0
T3	3183	3133	0	0
T4	626233	626161	0	0
T5	2643	2571	0	0
T6	44164	44064	0	0
T7	25726	25636	0	0
T8	1137	1086	0	0
T9	20288	20196	0	0
T10	40139	40089	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	2040174	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	2040174	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	2040174	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	2040174	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	3	0	926
T53	998537	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	113651	0	0	1
T57	1053	0	0	1
T58	229582	0	0	1
T59	324007	0	0	1
T60	276348	0	0	1
T61	429637	0	0	1
T62	75969	0	0	1
T63	805636	0	0	1
T64	633967	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	404825811	0	0
T1	6921	6828	0	0
T2	961977	961903	0	0
T3	3183	3133	0	0
T4	626233	626161	0	0
T5	2643	2571	0	0
T6	44164	44064	0	0
T7	25726	25636	0	0
T8	1137	1086	0	0
T9	20288	20196	0	0
T10	40139	40089	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404910840	2040174	0	0
T1	6921	832	0	0
T2	961977	832	0	0
T3	3183	0	0	0
T4	626233	832	0	0
T5	2643	832	0	0
T6	44164	832	0	0
T7	25726	832	0	0
T8	1137	0	0	0
T9	20288	832	0	0
T10	40139	832	0	0
T11	0	832	0	0
T12	0	832	0	0