Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3771651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4072710

1

T1

57522

T2

3075

T3

2192

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4397943	1			T1	93953		T2	4329		T3	2569
values[0x0]	1722053	1			T1	29685		T2	455		T3	424
values[0x1]	1724365	1			T1	29715		T2	451		T3	477

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2662159	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5182202

1

T1

87722

T2

3477

T3

2453

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28817	1			T1	694		T3	18		T4	11
valid_sources[0x01]	29419	1			T1	718		T3	5		T4	8
valid_sources[0x02]	28062	1			T1	213		T3	14		T4	2
valid_sources[0x03]	29543	1			T1	1277		T3	9		T4	15
valid_sources[0x04]	29798	1			T1	525		T3	9		T5	10
valid_sources[0x05]	28527	1			T1	597		T3	21		T4	8
valid_sources[0x06]	27283	1			T1	224		T3	12		T4	4
valid_sources[0x07]	28490	1			T1	201		T3	16		T4	14
valid_sources[0x08]	32222	1			T1	674		T3	24		T4	1
valid_sources[0x09]	31166	1			T1	1513		T3	21		T4	9
valid_sources[0x0a]	29973	1			T1	693		T3	11		T4	1
valid_sources[0x0b]	28925	1			T1	444		T3	8		T4	11
valid_sources[0x0c]	30657	1			T1	803		T3	13		T4	2
valid_sources[0x0d]	29262	1			T1	672		T3	18		T4	4
valid_sources[0x0e]	34555	1			T1	256		T3	15		T4	3
valid_sources[0x0f]	30065	1			T1	466		T3	16		T4	4
valid_sources[0x10]	30418	1			T1	770		T3	11		T4	2
valid_sources[0x11]	30294	1			T1	855		T3	10		T4	3
valid_sources[0x12]	33179	1			T1	794		T3	12		T4	6
valid_sources[0x13]	29480	1			T1	514		T3	18		T4	4
valid_sources[0x14]	32992	1			T1	217		T3	24		T5	3
valid_sources[0x15]	28191	1			T1	663		T3	14		T4	5
valid_sources[0x16]	29962	1			T1	1071		T3	13		T4	3
valid_sources[0x17]	30577	1			T1	1288		T3	15		T4	6
valid_sources[0x18]	27746	1			T1	686		T3	11		T5	2
valid_sources[0x19]	28089	1			T1	339		T3	9		T4	3
valid_sources[0x1a]	30888	1			T1	746		T3	10		T4	5
valid_sources[0x1b]	26461	1			T1	717		T3	10		T4	1
valid_sources[0x1c]	29415	1			T1	621		T3	12		T4	4
valid_sources[0x1d]	29205	1			T1	1081		T3	7		T4	4
valid_sources[0x1e]	30106	1			T1	150		T3	18		T4	11
valid_sources[0x1f]	29929	1			T1	332		T3	10		T4	9
valid_sources[0x20]	29266	1			T1	530		T3	6		T4	6
valid_sources[0x21]	27333	1			T1	234		T3	12		T4	8
valid_sources[0x22]	29397	1			T1	513		T3	12		T4	1
valid_sources[0x23]	30665	1			T1	283		T3	12		T4	5
valid_sources[0x24]	32850	1			T1	526		T3	12		T4	10
valid_sources[0x25]	28132	1			T1	505		T3	10		T4	11
valid_sources[0x26]	31764	1			T1	967		T3	13		T4	6
valid_sources[0x27]	26214	1			T1	261		T3	5		T4	3
valid_sources[0x28]	29556	1			T1	641		T3	20		T4	6
valid_sources[0x29]	31743	1			T1	1240		T3	17		T4	14
valid_sources[0x2a]	28685	1			T1	791		T3	23		T4	3
valid_sources[0x2b]	31232	1			T1	690		T3	16		T4	1
valid_sources[0x2c]	31463	1			T1	675		T3	9		T4	7
valid_sources[0x2d]	34881	1			T1	775		T3	21		T4	2
valid_sources[0x2e]	33178	1			T1	150		T2	2748		T3	6
valid_sources[0x2f]	33915	1			T1	351		T3	12		T4	4
valid_sources[0x30]	30900	1			T1	353		T3	6		T4	13
valid_sources[0x31]	26022	1			T1	481		T3	13		T4	4
valid_sources[0x32]	27171	1			T1	483		T3	9		T5	1
valid_sources[0x33]	28173	1			T1	552		T3	19		T4	6
valid_sources[0x34]	28971	1			T1	573		T3	12		T4	20
valid_sources[0x35]	36973	1			T1	857		T3	13		T4	1
valid_sources[0x36]	29251	1			T1	361		T3	6		T4	5
valid_sources[0x37]	28084	1			T1	838		T3	12		T4	11
valid_sources[0x38]	29300	1			T1	704		T3	19		T4	11
valid_sources[0x39]	30955	1			T1	601		T3	12		T4	6
valid_sources[0x3a]	28249	1			T1	845		T3	12		T4	2
valid_sources[0x3b]	32615	1			T1	104		T3	10		T4	6
valid_sources[0x3c]	35449	1			T1	265		T3	10		T4	4
valid_sources[0x3d]	26362	1			T1	761		T3	17		T5	9
valid_sources[0x3e]	26911	1			T1	174		T3	7		T4	4
valid_sources[0x3f]	30159	1			T1	908		T3	8		T4	4
valid_sources[0x40]	30613	1			T1	909		T3	11		T4	7
valid_sources[0x41]	30794	1			T1	569		T3	14		T4	5
valid_sources[0x42]	25059	1			T1	391		T3	9		T4	7
valid_sources[0x43]	30229	1			T1	722		T3	10		T5	7
valid_sources[0x44]	30966	1			T1	1266		T3	22		T4	8
valid_sources[0x45]	27833	1			T1	367		T3	20		T4	3
valid_sources[0x46]	28999	1			T1	479		T3	11		T4	9
valid_sources[0x47]	29316	1			T1	944		T3	8		T4	4
valid_sources[0x48]	31750	1			T1	674		T3	13		T4	2
valid_sources[0x49]	30376	1			T1	1009		T3	17		T4	7
valid_sources[0x4a]	27647	1			T1	555		T3	16		T4	8
valid_sources[0x4b]	28670	1			T1	602		T3	14		T4	12
valid_sources[0x4c]	29893	1			T1	662		T3	15		T4	3
valid_sources[0x4d]	33515	1			T1	312		T3	10		T4	6
valid_sources[0x4e]	31732	1			T1	452		T3	7		T4	2
valid_sources[0x4f]	27451	1			T1	166		T3	17		T5	3
valid_sources[0x50]	33620	1			T1	297		T3	13		T4	7
valid_sources[0x51]	30942	1			T1	782		T3	13		T4	4
valid_sources[0x52]	28411	1			T1	686		T3	9		T4	1
valid_sources[0x53]	32886	1			T1	322		T3	15		T4	8
valid_sources[0x54]	31706	1			T1	496		T3	16		T4	6
valid_sources[0x55]	27784	1			T1	442		T3	15		T4	3
valid_sources[0x56]	48497	1			T1	362		T3	13		T5	6
valid_sources[0x57]	35421	1			T1	349		T3	17		T4	10
valid_sources[0x58]	31914	1			T1	673		T3	13		T4	4
valid_sources[0x59]	35222	1			T1	285		T3	10		T4	3
valid_sources[0x5a]	29281	1			T1	400		T3	16		T5	5
valid_sources[0x5b]	29679	1			T1	891		T3	14		T4	4
valid_sources[0x5c]	27177	1			T1	429		T3	17		T4	2
valid_sources[0x5d]	29375	1			T1	1515		T3	21		T4	18
valid_sources[0x5e]	33640	1			T1	769		T3	17		T5	1
valid_sources[0x5f]	29727	1			T1	547		T3	17		T4	6
valid_sources[0x60]	32015	1			T1	555		T3	6		T4	9
valid_sources[0x61]	29849	1			T1	454		T3	13		T4	2
valid_sources[0x62]	28445	1			T1	415		T3	16		T4	14
valid_sources[0x63]	29043	1			T1	940		T3	12		T4	7
valid_sources[0x64]	28603	1			T1	561		T3	14		T4	11
valid_sources[0x65]	30780	1			T1	811		T3	15		T4	8
valid_sources[0x66]	27990	1			T1	360		T3	14		T5	7
valid_sources[0x67]	29277	1			T1	299		T3	9		T4	12
valid_sources[0x68]	40354	1			T1	749		T3	10		T4	17
valid_sources[0x69]	32180	1			T1	717		T3	15		T4	8
valid_sources[0x6a]	30408	1			T1	392		T3	19		T4	4
valid_sources[0x6b]	27205	1			T1	445		T3	18		T4	6
valid_sources[0x6c]	35891	1			T1	623		T3	15		T4	1
valid_sources[0x6d]	29799	1			T1	889		T3	12		T4	6
valid_sources[0x6e]	28377	1			T1	994		T3	12		T4	9
valid_sources[0x6f]	29499	1			T1	552		T3	13		T4	5
valid_sources[0x70]	27323	1			T1	313		T3	9		T4	5
valid_sources[0x71]	32711	1			T1	692		T3	12		T5	5
valid_sources[0x72]	33733	1			T1	569		T3	5		T4	2
valid_sources[0x73]	27035	1			T1	342		T3	14		T5	9
valid_sources[0x74]	30877	1			T1	463		T2	1		T3	3
valid_sources[0x75]	27905	1			T1	690		T3	17		T4	1
valid_sources[0x76]	30492	1			T1	858		T3	21		T5	2
valid_sources[0x77]	31364	1			T1	1594		T3	8		T4	2
valid_sources[0x78]	31270	1			T1	247		T3	7		T4	1
valid_sources[0x79]	36484	1			T1	78		T2	2482		T3	8
valid_sources[0x7a]	33428	1			T1	411		T3	17		T4	12
valid_sources[0x7b]	28143	1			T1	615		T3	11		T4	11
valid_sources[0x7c]	29180	1			T1	476		T3	13		T4	8
valid_sources[0x7d]	29738	1			T1	364		T3	10		T4	8
valid_sources[0x7e]	32308	1			T1	371		T3	26		T4	4
valid_sources[0x7f]	35001	1			T1	792		T3	19		T5	5
valid_sources[0x80]	31865	1			T1	641		T3	14		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

979333

1

T1

6848

T2

2174

T3

1296

values[0x0]

all_enables

biggest_size

1558583

1

T1

25505

T2

454

T3

424

values[0x1]

all_enables

biggest_size

1534794

1

T1

25169

T2

447

T3

472