Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3788955

1

T1

95831

T2

2160

T3

1278

full_word

4071567

1

T1

57522

T2

3075

T3

2192

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7860142	1			T1	153353		T2	5235		T3	3470
auto[TlIntgErrCmd]	127	1			T89	6		T87	5		T90	8
auto[TlIntgErrData]	117	1			T89	7		T87	4		T90	7
auto[TlIntgErrBoth]	136	1			T89	7		T87	1		T90	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4399227

1

T1

93953

T2

4329

T3

2569

auto[1]

3461295

1

T1

59400

T2

906

T3

901

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3419676	1			T1	87105		T2	2155		T3	1273
auto[TlIntgErrNone]	partial	auto[1]	368938	1			T1	8726		T2	5		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	979364	1			T1	6848		T2	2174		T3	1296
auto[TlIntgErrNone]	full_word	auto[1]	3092164	1			T1	50674		T2	901		T3	896
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T89	4		T87	3		T90	5
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T89	2		T87	2		T90	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T240	1		T241	1		T242	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T243	1		T237	1		T239	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T89	6		T87	2		T90	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T89	1		T87	1		T90	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T239	1		T244	1		T245	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T87	1		T241	2		T242	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T89	2		T90	2		T240	8
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T89	4		T87	1		T90	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T89	1		T240	1		T138	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T243	1		T138	1		T246	1