Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414477099	2546501	0	0
DepthKnown_A	414477099	414348764	0	0
RvalidKnown_A	414477099	414348764	0	0
WreadyKnown_A	414477099	414348764	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	2546501	0	0
T1	755378	20791	0	0
T2	154941	832	0	0
T3	74535	1663	0	0
T4	14885	832	0	0
T5	17305	1663	0	0
T6	159522	1663	0	0
T7	947	0	0	0
T8	405060	4159	0	0
T9	121824	0	0	0
T10	104914	4990	0	0
T11	0	29966	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414477099	3117662	0	0
DepthKnown_A	414477099	414348764	0	0
RvalidKnown_A	414477099	414348764	0	0
WreadyKnown_A	414477099	414348764	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	3117662	0	0
T1	755378	13312	0	0
T2	154941	832	0	0
T3	74535	832	0	0
T4	14885	832	0	0
T5	17305	832	0	0
T6	159522	832	0	0
T7	947	0	0	0
T8	405060	3328	0	0
T9	121824	0	0	0
T10	104914	3328	0	0
T11	0	49815	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414477099	164134	0	0
DepthKnown_A	414477099	414348764	0	0
RvalidKnown_A	414477099	414348764	0	0
WreadyKnown_A	414477099	414348764	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	164134	0	0
T1	755378	1536	0	0
T2	154941	0	0	0
T3	74535	0	0	0
T4	14885	0	0	0
T5	17305	0	0	0
T6	159522	0	0	0
T7	947	0	0	0
T8	405060	96	0	0
T9	121824	520	0	0
T10	104914	347	0	0
T11	0	2407	0	0
T13	0	1163	0	0
T14	0	1033	0	0
T16	0	276	0	0
T17	0	932	0	0
T25	0	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414477099	416867	0	0
DepthKnown_A	414477099	414348764	0	0
RvalidKnown_A	414477099	414348764	0	0
WreadyKnown_A	414477099	414348764	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	416867	0	0
T1	755378	1536	0	0
T2	154941	0	0	0
T3	74535	0	0	0
T4	14885	0	0	0
T5	17305	0	0	0
T6	159522	0	0	0
T7	947	0	0	0
T8	405060	96	0	0
T9	121824	1616	0	0
T10	104914	347	0	0
T11	0	7359	0	0
T13	0	3445	0	0
T14	0	1032	0	0
T16	0	276	0	0
T17	0	4224	0	0
T25	0	739	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414477099	6448174	0	0
DepthKnown_A	414477099	414348764	0	0
RvalidKnown_A	414477099	414348764	0	0
WreadyKnown_A	414477099	414348764	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	6448174	0	0
T1	755378	139252	0	0
T2	154941	4404	0	0
T3	74535	2638	0	0
T4	14885	460	0	0
T5	17305	562	0	0
T6	159522	7448	0	0
T7	947	8	0	0
T8	405060	848	0	0
T9	121824	3354	0	0
T10	104914	21033	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414477099	14755211	0	0
DepthKnown_A	414477099	414348764	0	0
RvalidKnown_A	414477099	414348764	0	0
WreadyKnown_A	414477099	414348764	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	14755211	0	0
T1	755378	138505	0	0
T2	154941	4403	0	0
T3	74535	11577	0	0
T4	14885	460	0	0
T5	17305	562	0	0
T6	159522	23037	0	0
T7	947	8	0	0
T8	405060	1612	0	0
T9	121824	10061	0	0
T10	104914	20789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414477099	414348764	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0