Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T10
1	0	Covered	T1,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T10
1	0	Unreachable
1	1	Covered	T1,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	687690095	548580391	0	0
CheckNGreaterZero_A	2775	2775	0	0
GntImpliesReady_A	687690095	3207241	0	0
GntImpliesValid_A	687690095	3207241	0	0
GrantKnown_A	687690095	548580391	0	0
IdxKnown_A	687690095	548580391	0	0
IndexIsCorrect_A	687690095	3207241	0	0
LockArbDecision_A	687690095	0	0	0
NoReadyValidNoGrant_A	687690095	0	0	0
ReadyAndValidImplyGrant_A	687690095	3207241	0	0
ReqAndReadyImplyGrant_A	687690095	3207241	0	0
ReqImpliesValid_A	687690095	3207241	0	0
ReqStaysHighUntilGranted0_M	687690095	0	0	0
RoundRobin_A	687690095	2	0	925
ValidKnown_A	687690095	548580391	0	0
gen_data_port_assertion.DataFlow_A	687690095	3207241	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	548580391	0	0
T1	971030	1825274	0	0
T2	228731	191450	0	0
T3	92059	82853	0	0
T4	30325	22554	0	0
T5	31705	24371	0	0
T6	198486	178933	0	0
T7	947	895	0	0
T8	798750	601658	0	0
T9	340060	225969	0	0
T10	625362	360580	0	0
T11	356928	425365	0	0
T12	0	13408	0	0
T13	0	165384	0	0
T14	0	397648	0	0
T16	0	79152	0	0
T17	0	545600	0	0
T18	0	213888	0	0
T40	0	3816	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2775	2775	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	3207241	0	0
T1	971030	29211	0	0
T2	228731	832	0	0
T3	92059	832	0	0
T4	30325	832	0	0
T5	31705	832	0	0
T6	198486	832	0	0
T7	947	0	0	0
T8	798750	3818	0	0
T9	340060	3943	0	0
T10	625362	6309	0	0
T11	356928	45813	0	0
T13	0	6543	0	0
T14	0	5749	0	0
T16	0	1740	0	0
T17	0	5413	0	0
T18	0	6641	0	0
T25	0	3517	0	0
T40	0	166	0	0
T41	0	3872	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	3207241	0	0
T1	971030	29211	0	0
T2	228731	832	0	0
T3	92059	832	0	0
T4	30325	832	0	0
T5	31705	832	0	0
T6	198486	832	0	0
T7	947	0	0	0
T8	798750	3818	0	0
T9	340060	3943	0	0
T10	625362	6309	0	0
T11	356928	45813	0	0
T13	0	6543	0	0
T14	0	5749	0	0
T16	0	1740	0	0
T17	0	5413	0	0
T18	0	6641	0	0
T25	0	3517	0	0
T40	0	166	0	0
T41	0	3872	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	548580391	0	0
T1	971030	1825274	0	0
T2	228731	191450	0	0
T3	92059	82853	0	0
T4	30325	22554	0	0
T5	31705	24371	0	0
T6	198486	178933	0	0
T7	947	895	0	0
T8	798750	601658	0	0
T9	340060	225969	0	0
T10	625362	360580	0	0
T11	356928	425365	0	0
T12	0	13408	0	0
T13	0	165384	0	0
T14	0	397648	0	0
T16	0	79152	0	0
T17	0	545600	0	0
T18	0	213888	0	0
T40	0	3816	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	548580391	0	0
T1	971030	1825274	0	0
T2	228731	191450	0	0
T3	92059	82853	0	0
T4	30325	22554	0	0
T5	31705	24371	0	0
T6	198486	178933	0	0
T7	947	895	0	0
T8	798750	601658	0	0
T9	340060	225969	0	0
T10	625362	360580	0	0
T11	356928	425365	0	0
T12	0	13408	0	0
T13	0	165384	0	0
T14	0	397648	0	0
T16	0	79152	0	0
T17	0	545600	0	0
T18	0	213888	0	0
T40	0	3816	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	3207241	0	0
T1	971030	29211	0	0
T2	228731	832	0	0
T3	92059	832	0	0
T4	30325	832	0	0
T5	31705	832	0	0
T6	198486	832	0	0
T7	947	0	0	0
T8	798750	3818	0	0
T9	340060	3943	0	0
T10	625362	6309	0	0
T11	356928	45813	0	0
T13	0	6543	0	0
T14	0	5749	0	0
T16	0	1740	0	0
T17	0	5413	0	0
T18	0	6641	0	0
T25	0	3517	0	0
T40	0	166	0	0
T41	0	3872	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	3207241	0	0
T1	971030	29211	0	0
T2	228731	832	0	0
T3	92059	832	0	0
T4	30325	832	0	0
T5	31705	832	0	0
T6	198486	832	0	0
T7	947	0	0	0
T8	798750	3818	0	0
T9	340060	3943	0	0
T10	625362	6309	0	0
T11	356928	45813	0	0
T13	0	6543	0	0
T14	0	5749	0	0
T16	0	1740	0	0
T17	0	5413	0	0
T18	0	6641	0	0
T25	0	3517	0	0
T40	0	166	0	0
T41	0	3872	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	3207241	0	0
T1	971030	29211	0	0
T2	228731	832	0	0
T3	92059	832	0	0
T4	30325	832	0	0
T5	31705	832	0	0
T6	198486	832	0	0
T7	947	0	0	0
T8	798750	3818	0	0
T9	340060	3943	0	0
T10	625362	6309	0	0
T11	356928	45813	0	0
T13	0	6543	0	0
T14	0	5749	0	0
T16	0	1740	0	0
T17	0	5413	0	0
T18	0	6641	0	0
T25	0	3517	0	0
T40	0	166	0	0
T41	0	3872	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	3207241	0	0
T1	971030	29211	0	0
T2	228731	832	0	0
T3	92059	832	0	0
T4	30325	832	0	0
T5	31705	832	0	0
T6	198486	832	0	0
T7	947	0	0	0
T8	798750	3818	0	0
T9	340060	3943	0	0
T10	625362	6309	0	0
T11	356928	45813	0	0
T13	0	6543	0	0
T14	0	5749	0	0
T16	0	1740	0	0
T17	0	5413	0	0
T18	0	6641	0	0
T25	0	3517	0	0
T40	0	166	0	0
T41	0	3872	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	2	0	925
T42	156287	1	0	1
T43	0	1	0	0
T44	51540	0	0	1
T45	127084	0	0	1
T46	2491	0	0	1
T47	224503	0	0	1
T48	983	0	0	1
T49	1507	0	0	1
T50	2437	0	0	1
T51	101033	0	0	1
T52	11920	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	548580391	0	0
T1	971030	1825274	0	0
T2	228731	191450	0	0
T3	92059	82853	0	0
T4	30325	22554	0	0
T5	31705	24371	0	0
T6	198486	178933	0	0
T7	947	895	0	0
T8	798750	601658	0	0
T9	340060	225969	0	0
T10	625362	360580	0	0
T11	356928	425365	0	0
T12	0	13408	0	0
T13	0	165384	0	0
T14	0	397648	0	0
T16	0	79152	0	0
T17	0	545600	0	0
T18	0	213888	0	0
T40	0	3816	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690095	3207241	0	0
T1	971030	29211	0	0
T2	228731	832	0	0
T3	92059	832	0	0
T4	30325	832	0	0
T5	31705	832	0	0
T6	198486	832	0	0
T7	947	0	0	0
T8	798750	3818	0	0
T9	340060	3943	0	0
T10	625362	6309	0	0
T11	356928	45813	0	0
T13	0	6543	0	0
T14	0	5749	0	0
T16	0	1740	0	0
T17	0	5413	0	0
T18	0	6641	0	0
T25	0	3517	0	0
T40	0	166	0	0
T41	0	3872	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T10
1	0	Covered	T1,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T10
1	0	Unreachable
1	1	Covered	T1,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T9,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T9,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	137740003	29383799	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	137740003	642094	0	0
GntImpliesValid_A	137740003	642094	0	0
GrantKnown_A	137740003	29383799	0	0
IdxKnown_A	137740003	29383799	0	0
IndexIsCorrect_A	137740003	642094	0	0
LockArbDecision_A	137740003	0	0	0
NoReadyValidNoGrant_A	137740003	0	0	0
ReadyAndValidImplyGrant_A	137740003	642094	0	0
ReqAndReadyImplyGrant_A	137740003	642094	0	0
ReqImpliesValid_A	137740003	642094	0	0
ReqStaysHighUntilGranted0_M	137740003	0	0	0
RoundRobin_A	137740003	0	0	0
ValidKnown_A	137740003	29383799	0	0
gen_data_port_assertion.DataFlow_A	137740003	642094	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	29383799	0	0
T1	107826	178712	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	104208	0	0
T10	260224	41104	0	0
T11	178464	275936	0	0
T13	0	165384	0	0
T14	0	397648	0	0
T16	0	79152	0	0
T17	0	545600	0	0
T18	0	213888	0	0
T40	0	3816	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	642094	0	0
T1	107826	7834	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	2759	0	0
T10	260224	1749	0	0
T11	178464	9950	0	0
T13	0	5510	0	0
T14	0	4838	0	0
T16	0	1740	0	0
T17	0	5395	0	0
T18	0	3518	0	0
T40	0	166	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	642094	0	0
T1	107826	7834	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	2759	0	0
T10	260224	1749	0	0
T11	178464	9950	0	0
T13	0	5510	0	0
T14	0	4838	0	0
T16	0	1740	0	0
T17	0	5395	0	0
T18	0	3518	0	0
T40	0	166	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	29383799	0	0
T1	107826	178712	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	104208	0	0
T10	260224	41104	0	0
T11	178464	275936	0	0
T13	0	165384	0	0
T14	0	397648	0	0
T16	0	79152	0	0
T17	0	545600	0	0
T18	0	213888	0	0
T40	0	3816	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	29383799	0	0
T1	107826	178712	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	104208	0	0
T10	260224	41104	0	0
T11	178464	275936	0	0
T13	0	165384	0	0
T14	0	397648	0	0
T16	0	79152	0	0
T17	0	545600	0	0
T18	0	213888	0	0
T40	0	3816	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	642094	0	0
T1	107826	7834	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	2759	0	0
T10	260224	1749	0	0
T11	178464	9950	0	0
T13	0	5510	0	0
T14	0	4838	0	0
T16	0	1740	0	0
T17	0	5395	0	0
T18	0	3518	0	0
T40	0	166	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	642094	0	0
T1	107826	7834	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	2759	0	0
T10	260224	1749	0	0
T11	178464	9950	0	0
T13	0	5510	0	0
T14	0	4838	0	0
T16	0	1740	0	0
T17	0	5395	0	0
T18	0	3518	0	0
T40	0	166	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	642094	0	0
T1	107826	7834	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	2759	0	0
T10	260224	1749	0	0
T11	178464	9950	0	0
T13	0	5510	0	0
T14	0	4838	0	0
T16	0	1740	0	0
T17	0	5395	0	0
T18	0	3518	0	0
T40	0	166	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	642094	0	0
T1	107826	7834	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	2759	0	0
T10	260224	1749	0	0
T11	178464	9950	0	0
T13	0	5510	0	0
T14	0	4838	0	0
T16	0	1740	0	0
T17	0	5395	0	0
T18	0	3518	0	0
T40	0	166	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	29383799	0	0
T1	107826	178712	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	104208	0	0
T10	260224	41104	0	0
T11	178464	275936	0	0
T13	0	165384	0	0
T14	0	397648	0	0
T16	0	79152	0	0
T17	0	545600	0	0
T18	0	213888	0	0
T40	0	3816	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	642094	0	0
T1	107826	7834	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	0	0	0
T9	109118	2759	0	0
T10	260224	1749	0	0
T11	178464	9950	0	0
T13	0	5510	0	0
T14	0	4838	0	0
T16	0	1740	0	0
T17	0	5395	0	0
T18	0	3518	0	0
T40	0	166	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T8,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	137740003	107071748	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	137740003	527762	0	0
GntImpliesValid_A	137740003	527762	0	0
GrantKnown_A	137740003	107071748	0	0
IdxKnown_A	137740003	107071748	0	0
IndexIsCorrect_A	137740003	527762	0	0
LockArbDecision_A	137740003	0	0	0
NoReadyValidNoGrant_A	137740003	0	0	0
ReadyAndValidImplyGrant_A	137740003	527762	0	0
ReqAndReadyImplyGrant_A	137740003	527762	0	0
ReqImpliesValid_A	137740003	527762	0	0
ReqStaysHighUntilGranted0_M	137740003	0	0	0
RoundRobin_A	137740003	0	0	0
ValidKnown_A	137740003	107071748	0	0
gen_data_port_assertion.DataFlow_A	137740003	527762	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	107071748	0	0
T1	107826	891201	0	0
T2	36895	36598	0	0
T3	8762	8368	0	0
T4	7720	7720	0	0
T5	7200	7158	0	0
T6	19482	19482	0	0
T8	196845	196660	0	0
T9	109118	0	0	0
T10	260224	214570	0	0
T11	178464	149429	0	0
T12	0	13408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	527762	0	0
T1	107826	3795	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	389	0	0
T9	109118	0	0	0
T10	260224	271	0	0
T11	178464	9276	0	0
T13	0	1033	0	0
T14	0	911	0	0
T17	0	18	0	0
T18	0	3123	0	0
T25	0	3517	0	0
T41	0	3872	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	527762	0	0
T1	107826	3795	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	389	0	0
T9	109118	0	0	0
T10	260224	271	0	0
T11	178464	9276	0	0
T13	0	1033	0	0
T14	0	911	0	0
T17	0	18	0	0
T18	0	3123	0	0
T25	0	3517	0	0
T41	0	3872	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	107071748	0	0
T1	107826	891201	0	0
T2	36895	36598	0	0
T3	8762	8368	0	0
T4	7720	7720	0	0
T5	7200	7158	0	0
T6	19482	19482	0	0
T8	196845	196660	0	0
T9	109118	0	0	0
T10	260224	214570	0	0
T11	178464	149429	0	0
T12	0	13408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	107071748	0	0
T1	107826	891201	0	0
T2	36895	36598	0	0
T3	8762	8368	0	0
T4	7720	7720	0	0
T5	7200	7158	0	0
T6	19482	19482	0	0
T8	196845	196660	0	0
T9	109118	0	0	0
T10	260224	214570	0	0
T11	178464	149429	0	0
T12	0	13408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	527762	0	0
T1	107826	3795	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	389	0	0
T9	109118	0	0	0
T10	260224	271	0	0
T11	178464	9276	0	0
T13	0	1033	0	0
T14	0	911	0	0
T17	0	18	0	0
T18	0	3123	0	0
T25	0	3517	0	0
T41	0	3872	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	527762	0	0
T1	107826	3795	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	389	0	0
T9	109118	0	0	0
T10	260224	271	0	0
T11	178464	9276	0	0
T13	0	1033	0	0
T14	0	911	0	0
T17	0	18	0	0
T18	0	3123	0	0
T25	0	3517	0	0
T41	0	3872	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	527762	0	0
T1	107826	3795	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	389	0	0
T9	109118	0	0	0
T10	260224	271	0	0
T11	178464	9276	0	0
T13	0	1033	0	0
T14	0	911	0	0
T17	0	18	0	0
T18	0	3123	0	0
T25	0	3517	0	0
T41	0	3872	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	527762	0	0
T1	107826	3795	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	389	0	0
T9	109118	0	0	0
T10	260224	271	0	0
T11	178464	9276	0	0
T13	0	1033	0	0
T14	0	911	0	0
T17	0	18	0	0
T18	0	3123	0	0
T25	0	3517	0	0
T41	0	3872	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	107071748	0	0
T1	107826	891201	0	0
T2	36895	36598	0	0
T3	8762	8368	0	0
T4	7720	7720	0	0
T5	7200	7158	0	0
T6	19482	19482	0	0
T8	196845	196660	0	0
T9	109118	0	0	0
T10	260224	214570	0	0
T11	178464	149429	0	0
T12	0	13408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137740003	527762	0	0
T1	107826	3795	0	0
T2	36895	0	0	0
T3	8762	0	0	0
T4	7720	0	0	0
T5	7200	0	0	0
T6	19482	0	0	0
T8	196845	389	0	0
T9	109118	0	0	0
T10	260224	271	0	0
T11	178464	9276	0	0
T13	0	1033	0	0
T14	0	911	0	0
T17	0	18	0	0
T18	0	3123	0	0
T25	0	3517	0	0
T41	0	3872	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412210089	412124844	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	412210089	2037385	0	0
GntImpliesValid_A	412210089	2037385	0	0
GrantKnown_A	412210089	412124844	0	0
IdxKnown_A	412210089	412124844	0	0
IndexIsCorrect_A	412210089	2037385	0	0
LockArbDecision_A	412210089	0	0	0
NoReadyValidNoGrant_A	412210089	0	0	0
ReadyAndValidImplyGrant_A	412210089	2037385	0	0
ReqAndReadyImplyGrant_A	412210089	2037385	0	0
ReqImpliesValid_A	412210089	2037385	0	0
ReqStaysHighUntilGranted0_M	412210089	0	0	0
RoundRobin_A	412210089	2	0	925
ValidKnown_A	412210089	412124844	0	0
gen_data_port_assertion.DataFlow_A	412210089	2037385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	412124844	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	2037385	0	0
T1	755378	17582	0	0
T2	154941	832	0	0
T3	74535	832	0	0
T4	14885	832	0	0
T5	17305	832	0	0
T6	159522	832	0	0
T7	947	0	0	0
T8	405060	3429	0	0
T9	121824	1184	0	0
T10	104914	4289	0	0
T11	0	26587	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	2037385	0	0
T1	755378	17582	0	0
T2	154941	832	0	0
T3	74535	832	0	0
T4	14885	832	0	0
T5	17305	832	0	0
T6	159522	832	0	0
T7	947	0	0	0
T8	405060	3429	0	0
T9	121824	1184	0	0
T10	104914	4289	0	0
T11	0	26587	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	412124844	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	412124844	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	2037385	0	0
T1	755378	17582	0	0
T2	154941	832	0	0
T3	74535	832	0	0
T4	14885	832	0	0
T5	17305	832	0	0
T6	159522	832	0	0
T7	947	0	0	0
T8	405060	3429	0	0
T9	121824	1184	0	0
T10	104914	4289	0	0
T11	0	26587	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	2037385	0	0
T1	755378	17582	0	0
T2	154941	832	0	0
T3	74535	832	0	0
T4	14885	832	0	0
T5	17305	832	0	0
T6	159522	832	0	0
T7	947	0	0	0
T8	405060	3429	0	0
T9	121824	1184	0	0
T10	104914	4289	0	0
T11	0	26587	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	2037385	0	0
T1	755378	17582	0	0
T2	154941	832	0	0
T3	74535	832	0	0
T4	14885	832	0	0
T5	17305	832	0	0
T6	159522	832	0	0
T7	947	0	0	0
T8	405060	3429	0	0
T9	121824	1184	0	0
T10	104914	4289	0	0
T11	0	26587	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	2037385	0	0
T1	755378	17582	0	0
T2	154941	832	0	0
T3	74535	832	0	0
T4	14885	832	0	0
T5	17305	832	0	0
T6	159522	832	0	0
T7	947	0	0	0
T8	405060	3429	0	0
T9	121824	1184	0	0
T10	104914	4289	0	0
T11	0	26587	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	2	0	925
T42	156287	1	0	1
T43	0	1	0	0
T44	51540	0	0	1
T45	127084	0	0	1
T46	2491	0	0	1
T47	224503	0	0	1
T48	983	0	0	1
T49	1507	0	0	1
T50	2437	0	0	1
T51	101033	0	0	1
T52	11920	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	412124844	0	0
T1	755378	755361	0	0
T2	154941	154852	0	0
T3	74535	74485	0	0
T4	14885	14834	0	0
T5	17305	17213	0	0
T6	159522	159451	0	0
T7	947	895	0	0
T8	405060	404998	0	0
T9	121824	121761	0	0
T10	104914	104906	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412210089	2037385	0	0
T1	755378	17582	0	0
T2	154941	832	0	0
T3	74535	832	0	0
T4	14885	832	0	0
T5	17305	832	0	0
T6	159522	832	0	0
T7	947	0	0	0
T8	405060	3429	0	0
T9	121824	1184	0	0
T10	104914	4289	0	0
T11	0	26587	0	0