Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3757 |
0 |
0 |
T82 |
10643 |
7 |
0 |
0 |
T83 |
5662 |
2 |
0 |
0 |
T84 |
2514 |
97 |
0 |
0 |
T85 |
14173 |
259 |
0 |
0 |
T86 |
2046 |
82 |
0 |
0 |
T88 |
21770 |
347 |
0 |
0 |
T89 |
53680 |
1 |
0 |
0 |
T93 |
5234 |
13 |
0 |
0 |
T94 |
11435 |
186 |
0 |
0 |
T100 |
14626 |
8 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1488 |
0 |
0 |
T68 |
3458 |
5 |
0 |
0 |
T69 |
4677 |
25 |
0 |
0 |
T82 |
10643 |
27 |
0 |
0 |
T83 |
5662 |
7 |
0 |
0 |
T100 |
14626 |
15 |
0 |
0 |
T104 |
6586 |
8 |
0 |
0 |
T106 |
10035 |
3 |
0 |
0 |
T138 |
33323 |
49 |
0 |
0 |
T139 |
14693 |
22 |
0 |
0 |
T140 |
36190 |
52 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1684 |
0 |
0 |
T68 |
3458 |
9 |
0 |
0 |
T69 |
4677 |
15 |
0 |
0 |
T82 |
10643 |
9 |
0 |
0 |
T83 |
5662 |
4 |
0 |
0 |
T100 |
14626 |
19 |
0 |
0 |
T104 |
6586 |
18 |
0 |
0 |
T106 |
10035 |
7 |
0 |
0 |
T138 |
33323 |
55 |
0 |
0 |
T139 |
14693 |
81 |
0 |
0 |
T140 |
36190 |
26 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1850 |
0 |
0 |
T68 |
3458 |
9 |
0 |
0 |
T69 |
4677 |
12 |
0 |
0 |
T82 |
10643 |
12 |
0 |
0 |
T83 |
5662 |
21 |
0 |
0 |
T100 |
14626 |
33 |
0 |
0 |
T104 |
6586 |
21 |
0 |
0 |
T106 |
10035 |
15 |
0 |
0 |
T138 |
33323 |
76 |
0 |
0 |
T139 |
14693 |
19 |
0 |
0 |
T140 |
36190 |
68 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
7465 |
0 |
0 |
T68 |
3458 |
9 |
0 |
0 |
T69 |
4677 |
11 |
0 |
0 |
T82 |
10643 |
14 |
0 |
0 |
T83 |
5662 |
2 |
0 |
0 |
T100 |
14626 |
120 |
0 |
0 |
T104 |
6586 |
75 |
0 |
0 |
T106 |
10035 |
68 |
0 |
0 |
T138 |
33323 |
503 |
0 |
0 |
T139 |
14693 |
27 |
0 |
0 |
T140 |
36190 |
813 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
7233 |
0 |
0 |
T68 |
3458 |
6 |
0 |
0 |
T69 |
4677 |
9 |
0 |
0 |
T82 |
10643 |
14 |
0 |
0 |
T83 |
5662 |
5 |
0 |
0 |
T100 |
14626 |
392 |
0 |
0 |
T104 |
6586 |
64 |
0 |
0 |
T106 |
10035 |
52 |
0 |
0 |
T138 |
33323 |
503 |
0 |
0 |
T139 |
14693 |
45 |
0 |
0 |
T140 |
36190 |
796 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
8033 |
0 |
0 |
T68 |
3458 |
13 |
0 |
0 |
T69 |
4677 |
10 |
0 |
0 |
T82 |
10643 |
243 |
0 |
0 |
T83 |
5662 |
118 |
0 |
0 |
T100 |
14626 |
140 |
0 |
0 |
T104 |
6586 |
102 |
0 |
0 |
T106 |
10035 |
59 |
0 |
0 |
T138 |
33323 |
540 |
0 |
0 |
T139 |
14693 |
39 |
0 |
0 |
T140 |
36190 |
652 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
7304 |
0 |
0 |
T68 |
3458 |
9 |
0 |
0 |
T69 |
4677 |
13 |
0 |
0 |
T82 |
10643 |
128 |
0 |
0 |
T83 |
5662 |
119 |
0 |
0 |
T100 |
14626 |
138 |
0 |
0 |
T104 |
6586 |
47 |
0 |
0 |
T106 |
10035 |
126 |
0 |
0 |
T138 |
33323 |
855 |
0 |
0 |
T139 |
14693 |
59 |
0 |
0 |
T140 |
36190 |
494 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
6664 |
0 |
0 |
T68 |
3458 |
4 |
0 |
0 |
T69 |
4677 |
14 |
0 |
0 |
T82 |
10643 |
128 |
0 |
0 |
T83 |
5662 |
4 |
0 |
0 |
T100 |
14626 |
146 |
0 |
0 |
T104 |
6586 |
68 |
0 |
0 |
T106 |
10035 |
72 |
0 |
0 |
T138 |
33323 |
554 |
0 |
0 |
T139 |
14693 |
6 |
0 |
0 |
T140 |
36190 |
373 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
7260 |
0 |
0 |
T68 |
3458 |
9 |
0 |
0 |
T69 |
4677 |
15 |
0 |
0 |
T82 |
10643 |
224 |
0 |
0 |
T83 |
5662 |
10 |
0 |
0 |
T100 |
14626 |
28 |
0 |
0 |
T104 |
6586 |
102 |
0 |
0 |
T106 |
10035 |
118 |
0 |
0 |
T138 |
33323 |
301 |
0 |
0 |
T139 |
14693 |
65 |
0 |
0 |
T140 |
36190 |
828 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
6872 |
0 |
0 |
T68 |
3458 |
11 |
0 |
0 |
T69 |
4677 |
13 |
0 |
0 |
T82 |
10643 |
239 |
0 |
0 |
T83 |
5662 |
5 |
0 |
0 |
T88 |
21770 |
5 |
0 |
0 |
T100 |
14626 |
269 |
0 |
0 |
T104 |
6586 |
6 |
0 |
0 |
T106 |
10035 |
207 |
0 |
0 |
T138 |
33323 |
645 |
0 |
0 |
T139 |
14693 |
26 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
7654 |
0 |
0 |
T68 |
3458 |
10 |
0 |
0 |
T69 |
4677 |
18 |
0 |
0 |
T82 |
10643 |
132 |
0 |
0 |
T83 |
5662 |
109 |
0 |
0 |
T100 |
14626 |
277 |
0 |
0 |
T104 |
6586 |
3 |
0 |
0 |
T106 |
10035 |
44 |
0 |
0 |
T138 |
33323 |
387 |
0 |
0 |
T139 |
14693 |
14 |
0 |
0 |
T140 |
36190 |
628 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4100 |
0 |
0 |
T68 |
3458 |
12 |
0 |
0 |
T69 |
4677 |
17 |
0 |
0 |
T82 |
10643 |
6 |
0 |
0 |
T83 |
5662 |
15 |
0 |
0 |
T100 |
14626 |
67 |
0 |
0 |
T104 |
6586 |
57 |
0 |
0 |
T106 |
10035 |
37 |
0 |
0 |
T138 |
33323 |
238 |
0 |
0 |
T139 |
14693 |
61 |
0 |
0 |
T140 |
36190 |
247 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3737 |
0 |
0 |
T68 |
3458 |
8 |
0 |
0 |
T69 |
4677 |
2 |
0 |
0 |
T82 |
10643 |
51 |
0 |
0 |
T83 |
5662 |
49 |
0 |
0 |
T100 |
14626 |
73 |
0 |
0 |
T106 |
10035 |
7 |
0 |
0 |
T138 |
33323 |
336 |
0 |
0 |
T139 |
14693 |
46 |
0 |
0 |
T140 |
36190 |
245 |
0 |
0 |
T141 |
9780 |
28 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3790 |
0 |
0 |
T69 |
4677 |
12 |
0 |
0 |
T82 |
10643 |
66 |
0 |
0 |
T83 |
5662 |
50 |
0 |
0 |
T100 |
14626 |
103 |
0 |
0 |
T104 |
6586 |
48 |
0 |
0 |
T106 |
10035 |
34 |
0 |
0 |
T138 |
33323 |
293 |
0 |
0 |
T139 |
14693 |
64 |
0 |
0 |
T140 |
36190 |
182 |
0 |
0 |
T141 |
9780 |
13 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3795 |
0 |
0 |
T68 |
3458 |
12 |
0 |
0 |
T69 |
4677 |
11 |
0 |
0 |
T82 |
10643 |
56 |
0 |
0 |
T83 |
5662 |
52 |
0 |
0 |
T97 |
12355 |
2 |
0 |
0 |
T100 |
14626 |
75 |
0 |
0 |
T104 |
6586 |
27 |
0 |
0 |
T106 |
10035 |
38 |
0 |
0 |
T138 |
33323 |
268 |
0 |
0 |
T139 |
14693 |
52 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3744 |
0 |
0 |
T68 |
3458 |
8 |
0 |
0 |
T69 |
4677 |
11 |
0 |
0 |
T82 |
10643 |
117 |
0 |
0 |
T83 |
5662 |
4 |
0 |
0 |
T100 |
14626 |
81 |
0 |
0 |
T106 |
10035 |
27 |
0 |
0 |
T138 |
33323 |
248 |
0 |
0 |
T139 |
14693 |
42 |
0 |
0 |
T140 |
36190 |
192 |
0 |
0 |
T141 |
9780 |
27 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3324 |
0 |
0 |
T68 |
3458 |
4 |
0 |
0 |
T69 |
4677 |
9 |
0 |
0 |
T82 |
10643 |
20 |
0 |
0 |
T83 |
5662 |
61 |
0 |
0 |
T100 |
14626 |
72 |
0 |
0 |
T104 |
6586 |
44 |
0 |
0 |
T106 |
10035 |
60 |
0 |
0 |
T138 |
33323 |
237 |
0 |
0 |
T139 |
14693 |
66 |
0 |
0 |
T140 |
36190 |
157 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4236 |
0 |
0 |
T68 |
3458 |
11 |
0 |
0 |
T69 |
4677 |
7 |
0 |
0 |
T82 |
10643 |
132 |
0 |
0 |
T83 |
5662 |
3 |
0 |
0 |
T100 |
14626 |
124 |
0 |
0 |
T104 |
6586 |
9 |
0 |
0 |
T106 |
10035 |
50 |
0 |
0 |
T138 |
33323 |
243 |
0 |
0 |
T139 |
14693 |
36 |
0 |
0 |
T140 |
36190 |
311 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3805 |
0 |
0 |
T68 |
3458 |
4 |
0 |
0 |
T69 |
4677 |
17 |
0 |
0 |
T82 |
10643 |
57 |
0 |
0 |
T83 |
5662 |
12 |
0 |
0 |
T100 |
14626 |
94 |
0 |
0 |
T106 |
10035 |
19 |
0 |
0 |
T138 |
33323 |
300 |
0 |
0 |
T139 |
14693 |
39 |
0 |
0 |
T140 |
36190 |
249 |
0 |
0 |
T141 |
9780 |
33 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4106 |
0 |
0 |
T68 |
3458 |
13 |
0 |
0 |
T69 |
4677 |
24 |
0 |
0 |
T82 |
10643 |
57 |
0 |
0 |
T83 |
5662 |
47 |
0 |
0 |
T100 |
14626 |
148 |
0 |
0 |
T104 |
6586 |
7 |
0 |
0 |
T106 |
10035 |
47 |
0 |
0 |
T138 |
33323 |
334 |
0 |
0 |
T139 |
14693 |
67 |
0 |
0 |
T140 |
36190 |
316 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3975 |
0 |
0 |
T68 |
3458 |
10 |
0 |
0 |
T82 |
10643 |
114 |
0 |
0 |
T83 |
5662 |
7 |
0 |
0 |
T100 |
14626 |
80 |
0 |
0 |
T104 |
6586 |
33 |
0 |
0 |
T106 |
10035 |
43 |
0 |
0 |
T138 |
33323 |
269 |
0 |
0 |
T139 |
14693 |
63 |
0 |
0 |
T140 |
36190 |
265 |
0 |
0 |
T141 |
9780 |
57 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4213 |
0 |
0 |
T68 |
3458 |
6 |
0 |
0 |
T69 |
4677 |
6 |
0 |
0 |
T82 |
10643 |
16 |
0 |
0 |
T83 |
5662 |
7 |
0 |
0 |
T100 |
14626 |
70 |
0 |
0 |
T104 |
6586 |
27 |
0 |
0 |
T106 |
10035 |
24 |
0 |
0 |
T138 |
33323 |
335 |
0 |
0 |
T139 |
14693 |
67 |
0 |
0 |
T140 |
36190 |
371 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3838 |
0 |
0 |
T68 |
3458 |
6 |
0 |
0 |
T69 |
4677 |
13 |
0 |
0 |
T82 |
10643 |
52 |
0 |
0 |
T83 |
5662 |
57 |
0 |
0 |
T100 |
14626 |
82 |
0 |
0 |
T104 |
6586 |
10 |
0 |
0 |
T106 |
10035 |
60 |
0 |
0 |
T138 |
33323 |
381 |
0 |
0 |
T139 |
14693 |
31 |
0 |
0 |
T140 |
36190 |
180 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3807 |
0 |
0 |
T68 |
3458 |
15 |
0 |
0 |
T69 |
4677 |
15 |
0 |
0 |
T82 |
10643 |
61 |
0 |
0 |
T83 |
5662 |
52 |
0 |
0 |
T100 |
14626 |
73 |
0 |
0 |
T104 |
6586 |
8 |
0 |
0 |
T106 |
10035 |
63 |
0 |
0 |
T138 |
33323 |
256 |
0 |
0 |
T139 |
14693 |
37 |
0 |
0 |
T140 |
36190 |
184 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4008 |
0 |
0 |
T68 |
3458 |
7 |
0 |
0 |
T69 |
4677 |
3 |
0 |
0 |
T82 |
10643 |
127 |
0 |
0 |
T83 |
5662 |
35 |
0 |
0 |
T100 |
14626 |
69 |
0 |
0 |
T104 |
6586 |
13 |
0 |
0 |
T106 |
10035 |
17 |
0 |
0 |
T138 |
33323 |
369 |
0 |
0 |
T139 |
14693 |
48 |
0 |
0 |
T140 |
36190 |
258 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4158 |
0 |
0 |
T68 |
3458 |
1 |
0 |
0 |
T69 |
4677 |
9 |
0 |
0 |
T82 |
10643 |
9 |
0 |
0 |
T83 |
5662 |
13 |
0 |
0 |
T100 |
14626 |
123 |
0 |
0 |
T104 |
6586 |
21 |
0 |
0 |
T106 |
10035 |
51 |
0 |
0 |
T138 |
33323 |
341 |
0 |
0 |
T139 |
14693 |
74 |
0 |
0 |
T140 |
36190 |
370 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4074 |
0 |
0 |
T68 |
3458 |
13 |
0 |
0 |
T69 |
4677 |
16 |
0 |
0 |
T82 |
10643 |
126 |
0 |
0 |
T83 |
5662 |
64 |
0 |
0 |
T100 |
14626 |
129 |
0 |
0 |
T104 |
6586 |
35 |
0 |
0 |
T106 |
10035 |
58 |
0 |
0 |
T138 |
33323 |
201 |
0 |
0 |
T139 |
14693 |
92 |
0 |
0 |
T140 |
36190 |
312 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3814 |
0 |
0 |
T68 |
3458 |
8 |
0 |
0 |
T69 |
4677 |
21 |
0 |
0 |
T82 |
10643 |
118 |
0 |
0 |
T83 |
5662 |
15 |
0 |
0 |
T100 |
14626 |
101 |
0 |
0 |
T104 |
6586 |
24 |
0 |
0 |
T106 |
10035 |
94 |
0 |
0 |
T138 |
33323 |
355 |
0 |
0 |
T139 |
14693 |
58 |
0 |
0 |
T140 |
36190 |
206 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4083 |
0 |
0 |
T68 |
3458 |
16 |
0 |
0 |
T69 |
4677 |
9 |
0 |
0 |
T82 |
10643 |
71 |
0 |
0 |
T83 |
5662 |
9 |
0 |
0 |
T100 |
14626 |
92 |
0 |
0 |
T104 |
6586 |
59 |
0 |
0 |
T106 |
10035 |
55 |
0 |
0 |
T138 |
33323 |
251 |
0 |
0 |
T139 |
14693 |
14 |
0 |
0 |
T140 |
36190 |
320 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3917 |
0 |
0 |
T68 |
3458 |
6 |
0 |
0 |
T69 |
4677 |
4 |
0 |
0 |
T82 |
10643 |
68 |
0 |
0 |
T83 |
5662 |
53 |
0 |
0 |
T100 |
14626 |
107 |
0 |
0 |
T104 |
6586 |
21 |
0 |
0 |
T106 |
10035 |
18 |
0 |
0 |
T138 |
33323 |
330 |
0 |
0 |
T139 |
14693 |
45 |
0 |
0 |
T140 |
36190 |
211 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3832 |
0 |
0 |
T68 |
3458 |
11 |
0 |
0 |
T69 |
4677 |
15 |
0 |
0 |
T82 |
10643 |
128 |
0 |
0 |
T83 |
5662 |
8 |
0 |
0 |
T100 |
14626 |
74 |
0 |
0 |
T104 |
6586 |
22 |
0 |
0 |
T106 |
10035 |
78 |
0 |
0 |
T138 |
33323 |
208 |
0 |
0 |
T139 |
14693 |
3 |
0 |
0 |
T140 |
36190 |
328 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3741 |
0 |
0 |
T68 |
3458 |
1 |
0 |
0 |
T69 |
4677 |
10 |
0 |
0 |
T82 |
10643 |
15 |
0 |
0 |
T83 |
5662 |
56 |
0 |
0 |
T100 |
14626 |
71 |
0 |
0 |
T104 |
6586 |
57 |
0 |
0 |
T106 |
10035 |
72 |
0 |
0 |
T138 |
33323 |
263 |
0 |
0 |
T139 |
14693 |
33 |
0 |
0 |
T140 |
36190 |
316 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4209 |
0 |
0 |
T68 |
3458 |
11 |
0 |
0 |
T69 |
4677 |
10 |
0 |
0 |
T82 |
10643 |
58 |
0 |
0 |
T83 |
5662 |
28 |
0 |
0 |
T100 |
14626 |
79 |
0 |
0 |
T104 |
6586 |
38 |
0 |
0 |
T106 |
10035 |
39 |
0 |
0 |
T138 |
33323 |
335 |
0 |
0 |
T139 |
14693 |
27 |
0 |
0 |
T140 |
36190 |
247 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
4004 |
0 |
0 |
T68 |
3458 |
3 |
0 |
0 |
T69 |
4677 |
16 |
0 |
0 |
T82 |
10643 |
15 |
0 |
0 |
T83 |
5662 |
72 |
0 |
0 |
T88 |
21770 |
4 |
0 |
0 |
T100 |
14626 |
92 |
0 |
0 |
T104 |
6586 |
21 |
0 |
0 |
T106 |
10035 |
86 |
0 |
0 |
T138 |
33323 |
259 |
0 |
0 |
T139 |
14693 |
59 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3865 |
0 |
0 |
T68 |
3458 |
4 |
0 |
0 |
T69 |
4677 |
11 |
0 |
0 |
T82 |
10643 |
42 |
0 |
0 |
T83 |
5662 |
17 |
0 |
0 |
T100 |
14626 |
136 |
0 |
0 |
T104 |
6586 |
42 |
0 |
0 |
T106 |
10035 |
28 |
0 |
0 |
T138 |
33323 |
236 |
0 |
0 |
T139 |
14693 |
71 |
0 |
0 |
T140 |
36190 |
327 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1632 |
0 |
0 |
T68 |
3458 |
15 |
0 |
0 |
T69 |
4677 |
10 |
0 |
0 |
T82 |
10643 |
18 |
0 |
0 |
T83 |
5662 |
1 |
0 |
0 |
T100 |
14626 |
18 |
0 |
0 |
T104 |
6586 |
13 |
0 |
0 |
T106 |
10035 |
14 |
0 |
0 |
T138 |
33323 |
57 |
0 |
0 |
T139 |
14693 |
47 |
0 |
0 |
T140 |
36190 |
60 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1788 |
0 |
0 |
T68 |
3458 |
4 |
0 |
0 |
T69 |
4677 |
14 |
0 |
0 |
T82 |
10643 |
27 |
0 |
0 |
T83 |
5662 |
13 |
0 |
0 |
T100 |
14626 |
45 |
0 |
0 |
T104 |
6586 |
1 |
0 |
0 |
T106 |
10035 |
10 |
0 |
0 |
T138 |
33323 |
82 |
0 |
0 |
T139 |
14693 |
16 |
0 |
0 |
T140 |
36190 |
38 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1839 |
0 |
0 |
T68 |
3458 |
1 |
0 |
0 |
T69 |
4677 |
5 |
0 |
0 |
T82 |
10643 |
21 |
0 |
0 |
T83 |
5662 |
10 |
0 |
0 |
T100 |
14626 |
28 |
0 |
0 |
T104 |
6586 |
7 |
0 |
0 |
T106 |
10035 |
2 |
0 |
0 |
T138 |
33323 |
53 |
0 |
0 |
T139 |
14693 |
50 |
0 |
0 |
T140 |
36190 |
75 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1618 |
0 |
0 |
T68 |
3458 |
8 |
0 |
0 |
T69 |
4677 |
9 |
0 |
0 |
T82 |
10643 |
24 |
0 |
0 |
T83 |
5662 |
2 |
0 |
0 |
T100 |
14626 |
21 |
0 |
0 |
T104 |
6586 |
2 |
0 |
0 |
T106 |
10035 |
13 |
0 |
0 |
T138 |
33323 |
53 |
0 |
0 |
T139 |
14693 |
14 |
0 |
0 |
T140 |
36190 |
49 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
2116 |
0 |
0 |
T68 |
3458 |
7 |
0 |
0 |
T69 |
4677 |
15 |
0 |
0 |
T82 |
10643 |
19 |
0 |
0 |
T83 |
5662 |
20 |
0 |
0 |
T100 |
14626 |
25 |
0 |
0 |
T104 |
6586 |
2 |
0 |
0 |
T106 |
10035 |
23 |
0 |
0 |
T138 |
33323 |
95 |
0 |
0 |
T139 |
14693 |
56 |
0 |
0 |
T140 |
36190 |
138 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
3777 |
0 |
0 |
T11 |
626097 |
27 |
0 |
0 |
T12 |
29398 |
0 |
0 |
0 |
T13 |
465576 |
0 |
0 |
0 |
T14 |
364052 |
0 |
0 |
0 |
T15 |
1426 |
0 |
0 |
0 |
T27 |
104294 |
0 |
0 |
0 |
T34 |
0 |
22 |
0 |
0 |
T35 |
0 |
14 |
0 |
0 |
T36 |
0 |
17 |
0 |
0 |
T56 |
5886 |
0 |
0 |
0 |
T65 |
0 |
35 |
0 |
0 |
T136 |
1396 |
0 |
0 |
0 |
T137 |
28719 |
0 |
0 |
0 |
T142 |
0 |
39 |
0 |
0 |
T143 |
0 |
11 |
0 |
0 |
T144 |
0 |
71 |
0 |
0 |
T145 |
0 |
42 |
0 |
0 |
T146 |
0 |
33 |
0 |
0 |
T147 |
17711 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1808 |
0 |
0 |
T68 |
3458 |
10 |
0 |
0 |
T69 |
4677 |
5 |
0 |
0 |
T82 |
10643 |
17 |
0 |
0 |
T100 |
14626 |
28 |
0 |
0 |
T104 |
6586 |
1 |
0 |
0 |
T138 |
33323 |
62 |
0 |
0 |
T139 |
14693 |
22 |
0 |
0 |
T140 |
36190 |
59 |
0 |
0 |
T141 |
9780 |
16 |
0 |
0 |
T148 |
10485 |
25 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1857 |
0 |
0 |
T68 |
3458 |
11 |
0 |
0 |
T69 |
4677 |
23 |
0 |
0 |
T82 |
10643 |
21 |
0 |
0 |
T83 |
5662 |
10 |
0 |
0 |
T100 |
14626 |
34 |
0 |
0 |
T104 |
6586 |
1 |
0 |
0 |
T106 |
10035 |
15 |
0 |
0 |
T138 |
33323 |
70 |
0 |
0 |
T139 |
14693 |
49 |
0 |
0 |
T140 |
36190 |
46 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1586 |
0 |
0 |
T68 |
3458 |
12 |
0 |
0 |
T69 |
4677 |
9 |
0 |
0 |
T82 |
10643 |
14 |
0 |
0 |
T83 |
5662 |
6 |
0 |
0 |
T88 |
21770 |
1 |
0 |
0 |
T100 |
14626 |
23 |
0 |
0 |
T104 |
6586 |
2 |
0 |
0 |
T106 |
10035 |
8 |
0 |
0 |
T138 |
33323 |
36 |
0 |
0 |
T139 |
14693 |
33 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1500 |
0 |
0 |
T68 |
3458 |
5 |
0 |
0 |
T69 |
4677 |
16 |
0 |
0 |
T82 |
10643 |
13 |
0 |
0 |
T83 |
5662 |
10 |
0 |
0 |
T100 |
14626 |
18 |
0 |
0 |
T104 |
6586 |
7 |
0 |
0 |
T138 |
33323 |
18 |
0 |
0 |
T139 |
14693 |
34 |
0 |
0 |
T140 |
36190 |
51 |
0 |
0 |
T141 |
9780 |
6 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1554 |
0 |
0 |
T68 |
3458 |
7 |
0 |
0 |
T69 |
4677 |
11 |
0 |
0 |
T82 |
10643 |
11 |
0 |
0 |
T83 |
5662 |
9 |
0 |
0 |
T100 |
14626 |
31 |
0 |
0 |
T104 |
6586 |
2 |
0 |
0 |
T106 |
10035 |
4 |
0 |
0 |
T138 |
33323 |
40 |
0 |
0 |
T139 |
14693 |
30 |
0 |
0 |
T140 |
36190 |
45 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1677 |
0 |
0 |
T68 |
3458 |
7 |
0 |
0 |
T69 |
4677 |
4 |
0 |
0 |
T82 |
10643 |
14 |
0 |
0 |
T83 |
5662 |
5 |
0 |
0 |
T100 |
14626 |
37 |
0 |
0 |
T104 |
6586 |
10 |
0 |
0 |
T106 |
10035 |
5 |
0 |
0 |
T138 |
33323 |
42 |
0 |
0 |
T139 |
14693 |
61 |
0 |
0 |
T140 |
36190 |
35 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
2063 |
0 |
0 |
T68 |
3458 |
4 |
0 |
0 |
T69 |
4677 |
13 |
0 |
0 |
T82 |
10643 |
24 |
0 |
0 |
T83 |
5662 |
4 |
0 |
0 |
T100 |
14626 |
31 |
0 |
0 |
T104 |
6586 |
7 |
0 |
0 |
T106 |
10035 |
7 |
0 |
0 |
T138 |
33323 |
59 |
0 |
0 |
T139 |
14693 |
63 |
0 |
0 |
T140 |
36190 |
83 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1566 |
0 |
0 |
T68 |
3458 |
5 |
0 |
0 |
T69 |
4677 |
10 |
0 |
0 |
T82 |
10643 |
16 |
0 |
0 |
T83 |
5662 |
8 |
0 |
0 |
T100 |
14626 |
28 |
0 |
0 |
T106 |
10035 |
8 |
0 |
0 |
T138 |
33323 |
38 |
0 |
0 |
T139 |
14693 |
31 |
0 |
0 |
T140 |
36190 |
25 |
0 |
0 |
T141 |
9780 |
5 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
2348 |
0 |
0 |
T69 |
4677 |
15 |
0 |
0 |
T82 |
10643 |
30 |
0 |
0 |
T83 |
5662 |
8 |
0 |
0 |
T100 |
14626 |
33 |
0 |
0 |
T104 |
6586 |
17 |
0 |
0 |
T106 |
10035 |
8 |
0 |
0 |
T138 |
33323 |
162 |
0 |
0 |
T139 |
14693 |
2 |
0 |
0 |
T140 |
36190 |
97 |
0 |
0 |
T141 |
9780 |
6 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1736 |
0 |
0 |
T68 |
3458 |
3 |
0 |
0 |
T69 |
4677 |
6 |
0 |
0 |
T82 |
10643 |
19 |
0 |
0 |
T83 |
5662 |
2 |
0 |
0 |
T88 |
21770 |
4 |
0 |
0 |
T100 |
14626 |
29 |
0 |
0 |
T104 |
6586 |
3 |
0 |
0 |
T106 |
10035 |
3 |
0 |
0 |
T138 |
33323 |
54 |
0 |
0 |
T139 |
14693 |
50 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1568 |
0 |
0 |
T68 |
3458 |
9 |
0 |
0 |
T69 |
4677 |
22 |
0 |
0 |
T82 |
10643 |
8 |
0 |
0 |
T83 |
5662 |
7 |
0 |
0 |
T100 |
14626 |
22 |
0 |
0 |
T106 |
10035 |
9 |
0 |
0 |
T138 |
33323 |
34 |
0 |
0 |
T139 |
14693 |
4 |
0 |
0 |
T140 |
36190 |
38 |
0 |
0 |
T141 |
9780 |
3 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1670 |
0 |
0 |
T68 |
3458 |
4 |
0 |
0 |
T69 |
4677 |
6 |
0 |
0 |
T83 |
5662 |
14 |
0 |
0 |
T88 |
21770 |
1 |
0 |
0 |
T100 |
14626 |
18 |
0 |
0 |
T106 |
10035 |
4 |
0 |
0 |
T138 |
33323 |
48 |
0 |
0 |
T139 |
14693 |
48 |
0 |
0 |
T140 |
36190 |
31 |
0 |
0 |
T148 |
10485 |
17 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1741 |
0 |
0 |
T68 |
3458 |
11 |
0 |
0 |
T69 |
4677 |
11 |
0 |
0 |
T82 |
10643 |
13 |
0 |
0 |
T83 |
5662 |
9 |
0 |
0 |
T100 |
14626 |
29 |
0 |
0 |
T106 |
10035 |
10 |
0 |
0 |
T138 |
33323 |
36 |
0 |
0 |
T139 |
14693 |
76 |
0 |
0 |
T140 |
36190 |
38 |
0 |
0 |
T141 |
9780 |
12 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1659 |
0 |
0 |
T68 |
3458 |
11 |
0 |
0 |
T69 |
4677 |
6 |
0 |
0 |
T82 |
10643 |
14 |
0 |
0 |
T83 |
5662 |
8 |
0 |
0 |
T100 |
14626 |
28 |
0 |
0 |
T106 |
10035 |
13 |
0 |
0 |
T138 |
33323 |
65 |
0 |
0 |
T139 |
14693 |
65 |
0 |
0 |
T140 |
36190 |
26 |
0 |
0 |
T141 |
9780 |
8 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1585 |
0 |
0 |
T68 |
3458 |
10 |
0 |
0 |
T69 |
4677 |
12 |
0 |
0 |
T82 |
10643 |
8 |
0 |
0 |
T83 |
5662 |
4 |
0 |
0 |
T100 |
14626 |
32 |
0 |
0 |
T104 |
6586 |
7 |
0 |
0 |
T106 |
10035 |
3 |
0 |
0 |
T138 |
33323 |
35 |
0 |
0 |
T139 |
14693 |
63 |
0 |
0 |
T140 |
36190 |
29 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
414477099 |
1572 |
0 |
0 |
T68 |
3458 |
6 |
0 |
0 |
T69 |
4677 |
16 |
0 |
0 |
T82 |
10643 |
17 |
0 |
0 |
T83 |
5662 |
9 |
0 |
0 |
T100 |
14626 |
20 |
0 |
0 |
T106 |
10035 |
3 |
0 |
0 |
T138 |
33323 |
45 |
0 |
0 |
T139 |
14693 |
29 |
0 |
0 |
T140 |
36190 |
35 |
0 |
0 |
T141 |
9780 |
7 |
0 |
0 |