Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3509123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3896547

1

T1

4

T2

23763

T3

3177

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4182631	1			T1	1		T2	34645		T3	2670
values[0x0]	1610385	1			T1	3		T2	12213		T3	1506
values[0x1]	1612654	1			T1	5		T2	12171		T3	1548

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2491674	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4913996

1

T1

5

T2

34723

T3

3846

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	47351	1			T2	219		T3	16		T4	13
valid_sources[0x01]	29701	1			T2	276		T3	32		T4	22
valid_sources[0x02]	27293	1			T2	317		T3	20		T4	17
valid_sources[0x03]	28741	1			T2	191		T3	22		T4	16
valid_sources[0x04]	26004	1			T2	227		T3	23		T4	7
valid_sources[0x05]	26169	1			T2	242		T3	21		T4	18
valid_sources[0x06]	29175	1			T2	322		T3	25		T4	20
valid_sources[0x07]	97035	1			T2	221		T3	26		T4	26
valid_sources[0x08]	27182	1			T2	233		T3	27		T4	10
valid_sources[0x09]	29494	1			T2	293		T3	25		T4	20
valid_sources[0x0a]	27129	1			T2	170		T3	18		T4	24
valid_sources[0x0b]	27277	1			T2	199		T3	22		T4	21
valid_sources[0x0c]	29489	1			T2	219		T3	13		T4	8
valid_sources[0x0d]	30041	1			T2	203		T3	23		T4	10
valid_sources[0x0e]	26721	1			T2	284		T3	21		T4	28
valid_sources[0x0f]	30057	1			T2	187		T3	20		T4	20
valid_sources[0x10]	33378	1			T2	211		T3	22		T4	28
valid_sources[0x11]	28054	1			T2	184		T3	21		T4	6
valid_sources[0x12]	27703	1			T2	107		T3	26		T4	12
valid_sources[0x13]	31432	1			T2	218		T3	30		T4	25
valid_sources[0x14]	27030	1			T2	290		T3	27		T4	15
valid_sources[0x15]	28094	1			T2	205		T3	26		T4	6
valid_sources[0x16]	28218	1			T2	193		T3	25		T4	30
valid_sources[0x17]	26574	1			T2	247		T3	16		T4	20
valid_sources[0x18]	27174	1			T2	216		T3	15		T4	32
valid_sources[0x19]	26317	1			T2	157		T3	20		T4	15
valid_sources[0x1a]	29553	1			T2	298		T3	23		T4	22
valid_sources[0x1b]	27929	1			T2	191		T3	23		T4	21
valid_sources[0x1c]	28694	1			T2	252		T3	13		T4	18
valid_sources[0x1d]	28750	1			T2	285		T3	16		T4	16
valid_sources[0x1e]	27000	1			T2	125		T3	26		T4	16
valid_sources[0x1f]	31813	1			T2	239		T3	31		T4	16
valid_sources[0x20]	27871	1			T1	1		T2	285		T3	13
valid_sources[0x21]	28474	1			T1	1		T2	250		T3	18
valid_sources[0x22]	26173	1			T2	158		T3	18		T4	11
valid_sources[0x23]	27869	1			T2	234		T3	22		T4	13
valid_sources[0x24]	25378	1			T2	355		T3	28		T4	38
valid_sources[0x25]	27792	1			T1	1		T2	291		T3	20
valid_sources[0x26]	26335	1			T2	228		T3	22		T4	36
valid_sources[0x27]	28671	1			T2	264		T3	28		T4	10
valid_sources[0x28]	29038	1			T2	260		T3	24		T4	10
valid_sources[0x29]	24744	1			T2	219		T3	30		T4	10
valid_sources[0x2a]	28758	1			T2	189		T3	22		T4	19
valid_sources[0x2b]	26750	1			T2	194		T3	27		T4	25
valid_sources[0x2c]	28789	1			T1	1		T2	240		T3	18
valid_sources[0x2d]	32687	1			T2	267		T3	24		T4	12
valid_sources[0x2e]	27020	1			T1	1		T2	201		T3	19
valid_sources[0x2f]	29893	1			T2	118		T3	16		T4	20
valid_sources[0x30]	28814	1			T2	227		T3	29		T4	13
valid_sources[0x31]	27560	1			T2	300		T3	12		T4	17
valid_sources[0x32]	26921	1			T2	283		T3	21		T4	23
valid_sources[0x33]	25685	1			T2	207		T3	24		T4	22
valid_sources[0x34]	68560	1			T2	335		T3	26		T4	19
valid_sources[0x35]	27456	1			T2	248		T3	24		T4	18
valid_sources[0x36]	29914	1			T2	237		T3	19		T4	21
valid_sources[0x37]	28428	1			T2	309		T3	22		T4	27
valid_sources[0x38]	27545	1			T2	313		T3	18		T4	9
valid_sources[0x39]	28834	1			T2	254		T3	18		T4	17
valid_sources[0x3a]	28369	1			T2	222		T3	14		T4	10
valid_sources[0x3b]	26833	1			T2	180		T3	19		T4	18
valid_sources[0x3c]	27654	1			T2	234		T3	23		T4	20
valid_sources[0x3d]	26408	1			T2	237		T3	16		T4	22
valid_sources[0x3e]	26689	1			T2	291		T3	18		T4	19
valid_sources[0x3f]	26104	1			T2	118		T3	19		T4	34
valid_sources[0x40]	28704	1			T2	270		T3	25		T4	28
valid_sources[0x41]	32651	1			T2	344		T3	22		T4	12
valid_sources[0x42]	31654	1			T2	167		T3	23		T4	14
valid_sources[0x43]	27344	1			T2	299		T3	15		T4	8
valid_sources[0x44]	26372	1			T2	227		T3	18		T4	13
valid_sources[0x45]	28264	1			T2	181		T3	24		T4	22
valid_sources[0x46]	26194	1			T2	299		T3	14		T4	20
valid_sources[0x47]	26307	1			T2	188		T3	31		T4	21
valid_sources[0x48]	27893	1			T2	289		T3	19		T4	29
valid_sources[0x49]	27528	1			T2	162		T3	19		T4	17
valid_sources[0x4a]	30675	1			T2	189		T3	14		T4	25
valid_sources[0x4b]	26760	1			T2	253		T3	19		T4	20
valid_sources[0x4c]	29388	1			T2	184		T3	25		T4	8
valid_sources[0x4d]	25615	1			T2	126		T3	24		T4	12
valid_sources[0x4e]	27353	1			T2	270		T3	20		T4	24
valid_sources[0x4f]	31137	1			T2	157		T3	22		T4	8
valid_sources[0x50]	26706	1			T2	240		T3	29		T4	30
valid_sources[0x51]	26466	1			T1	2		T2	251		T3	28
valid_sources[0x52]	25623	1			T2	184		T3	19		T4	15
valid_sources[0x53]	28791	1			T2	158		T3	16		T4	21
valid_sources[0x54]	26925	1			T2	224		T3	17		T4	27
valid_sources[0x55]	27998	1			T2	308		T3	16		T4	12
valid_sources[0x56]	26928	1			T2	162		T3	26		T4	10
valid_sources[0x57]	27261	1			T2	280		T3	28		T4	10
valid_sources[0x58]	27099	1			T2	294		T3	20		T4	23
valid_sources[0x59]	26703	1			T2	236		T3	23		T4	17
valid_sources[0x5a]	25322	1			T2	176		T3	20		T4	24
valid_sources[0x5b]	31164	1			T2	367		T3	20		T4	8
valid_sources[0x5c]	30373	1			T2	300		T3	24		T4	22
valid_sources[0x5d]	29078	1			T2	238		T3	13		T4	13
valid_sources[0x5e]	29980	1			T2	143		T3	18		T4	28
valid_sources[0x5f]	27902	1			T2	250		T3	19		T4	16
valid_sources[0x60]	25206	1			T2	115		T3	18		T4	17
valid_sources[0x61]	27828	1			T2	154		T3	25		T4	21
valid_sources[0x62]	26737	1			T2	231		T3	19		T4	21
valid_sources[0x63]	30502	1			T2	175		T3	22		T4	16
valid_sources[0x64]	32164	1			T2	316		T3	15		T4	21
valid_sources[0x65]	27689	1			T2	200		T3	19		T4	23
valid_sources[0x66]	31794	1			T2	227		T3	26		T4	19
valid_sources[0x67]	25497	1			T2	200		T3	25		T4	12
valid_sources[0x68]	32845	1			T2	305		T3	32		T4	24
valid_sources[0x69]	26598	1			T2	297		T3	23		T4	21
valid_sources[0x6a]	27071	1			T2	172		T3	15		T4	15
valid_sources[0x6b]	25669	1			T2	287		T3	24		T4	13
valid_sources[0x6c]	26803	1			T2	254		T3	35		T4	3
valid_sources[0x6d]	26674	1			T2	197		T3	22		T4	11
valid_sources[0x6e]	57838	1			T2	206		T3	16		T4	14
valid_sources[0x6f]	27074	1			T2	201		T3	16		T4	22
valid_sources[0x70]	24981	1			T2	241		T3	27		T4	13
valid_sources[0x71]	25478	1			T2	192		T3	24		T4	19
valid_sources[0x72]	25498	1			T2	176		T3	16		T4	13
valid_sources[0x73]	27699	1			T2	183		T3	25		T4	19
valid_sources[0x74]	27463	1			T2	184		T3	21		T4	24
valid_sources[0x75]	27653	1			T2	219		T3	29		T4	5
valid_sources[0x76]	28383	1			T2	253		T3	27		T4	10
valid_sources[0x77]	28671	1			T2	241		T3	21		T4	17
valid_sources[0x78]	27786	1			T2	135		T3	24		T4	18
valid_sources[0x79]	28988	1			T2	372		T3	18		T4	20
valid_sources[0x7a]	27653	1			T2	206		T3	31		T4	10
valid_sources[0x7b]	26406	1			T2	229		T3	22		T4	22
valid_sources[0x7c]	26064	1			T2	225		T3	17		T4	16
valid_sources[0x7d]	29332	1			T1	1		T2	214		T3	23
valid_sources[0x7e]	26951	1			T2	172		T3	23		T4	26
valid_sources[0x7f]	27218	1			T2	300		T3	24		T4	29
valid_sources[0x80]	24995	1			T2	347		T3	22		T4	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1002783

1

T1

1

T2

2840

T3

842

values[0x0]

all_enables

biggest_size

1458847

1

T1

2

T2

10584

T3

1182

values[0x1]

all_enables

biggest_size

1434917

1

T1

1

T2

10339

T3

1153