Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3523353

1

T1

5

T2

35266

T3

2547

full_word

3895352

1

T1

4

T2

23763

T3

3177

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7418265	1			T1	9		T2	59029		T3	5724
auto[TlIntgErrCmd]	140	1			T86	7		T89	8		T90	12
auto[TlIntgErrData]	143	1			T86	12		T89	9		T90	11
auto[TlIntgErrBoth]	157	1			T86	11		T89	13		T90	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4183226

1

T1

1

T2

34645

T3

2670

auto[1]

3235479

1

T1

8

T2

24384

T3

3054

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3180184	1			T2	31805		T3	1828		T4	2578
auto[TlIntgErrNone]	partial	auto[1]	342769	1			T1	5		T2	3461		T3	719
auto[TlIntgErrNone]	full_word	auto[0]	1002839	1			T1	1		T2	2840		T3	842
auto[TlIntgErrNone]	full_word	auto[1]	2892473	1			T1	3		T2	20923		T3	2335
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T86	4		T89	3		T90	4
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T86	3		T89	5		T90	7
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T173	1		T174	1		T175	2
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T90	1		T107	2		T176	2
auto[TlIntgErrData]	partial	auto[0]	65	1			T86	4		T89	2		T90	6
auto[TlIntgErrData]	partial	auto[1]	63	1			T86	5		T89	5		T90	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T86	2		T89	2		T107	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T86	1		T107	1		T171	2
auto[TlIntgErrBoth]	partial	auto[0]	63	1			T86	3		T89	5		T90	3
auto[TlIntgErrBoth]	partial	auto[1]	85	1			T86	7		T89	7		T90	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T90	2		T171	1		T177	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T86	1		T89	1		T175	1