Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372991443	2481723	0	0
DepthKnown_A	372991443	372858172	0	0
RvalidKnown_A	372991443	372858172	0	0
WreadyKnown_A	372991443	372858172	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	2481723	0	0
T2	278506	12474	0	0
T3	155652	1663	0	0
T4	240310	0	0	0
T5	1041	0	0	0
T6	145957	1663	0	0
T7	4277	0	0	0
T8	843864	7511	0	0
T9	771319	13320	0	0
T10	352173	14139	0	0
T11	1683	0	0	0
T12	0	2174	0	0
T13	0	1671	0	0
T14	0	1663	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372991443	2774616	0	0
DepthKnown_A	372991443	372858172	0	0
RvalidKnown_A	372991443	372858172	0	0
WreadyKnown_A	372991443	372858172	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	2774616	0	0
T2	278506	7488	0	0
T3	155652	832	0	0
T4	240310	0	0	0
T5	1041	0	0	0
T6	145957	832	0	0
T7	4277	0	0	0
T8	843864	7337	0	0
T9	771319	17476	0	0
T10	352173	9984	0	0
T11	1683	0	0	0
T12	0	1088	0	0
T13	0	840	0	0
T14	0	832	0	0
T15	0	3714	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372991443	162588	0	0
DepthKnown_A	372991443	372858172	0	0
RvalidKnown_A	372991443	372858172	0	0
WreadyKnown_A	372991443	372858172	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	162588	0	0
T2	278506	858	0	0
T3	155652	722	0	0
T4	240310	373	0	0
T5	1041	0	0	0
T6	145957	0	0	0
T7	4277	0	0	0
T8	843864	166	0	0
T9	771319	1149	0	0
T10	352173	1135	0	0
T11	1683	0	0	0
T16	0	1344	0	0
T26	0	172	0	0
T34	0	408	0	0
T41	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372991443	387477	0	0
DepthKnown_A	372991443	372858172	0	0
RvalidKnown_A	372991443	372858172	0	0
WreadyKnown_A	372991443	372858172	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	387477	0	0
T2	278506	857	0	0
T3	155652	3249	0	0
T4	240310	1605	0	0
T5	1041	0	0	0
T6	145957	0	0	0
T7	4277	0	0	0
T8	843864	765	0	0
T9	771319	4783	0	0
T10	352173	1135	0	0
T11	1683	0	0	0
T16	0	1344	0	0
T26	0	178	0	0
T34	0	408	0	0
T41	0	355	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372991443	6020804	0	0
DepthKnown_A	372991443	372858172	0	0
RvalidKnown_A	372991443	372858172	0	0
WreadyKnown_A	372991443	372858172	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	6020804	0	0
T1	1319	9	0	0
T2	278506	50967	0	0
T3	155652	4804	0	0
T4	240310	4455	0	0
T5	1041	79	0	0
T6	145957	260	0	0
T7	4277	188	0	0
T8	843864	8557	0	0
T9	771319	19095	0	0
T10	352173	9175	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372991443	12637848	0	0
DepthKnown_A	372991443	372858172	0	0
RvalidKnown_A	372991443	372858172	0	0
WreadyKnown_A	372991443	372858172	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	12637848	0	0
T1	1319	9	0	0
T2	278506	50684	0	0
T3	155652	19049	0	0
T4	240310	18903	0	0
T5	1041	79	0	0
T6	145957	989	0	0
T7	4277	188	0	0
T8	843864	33320	0	0
T9	771319	69441	0	0
T10	352173	9090	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372991443	372858172	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0