Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	624646974	496282652	0	0
CheckNGreaterZero_A	2775	2775	0	0
GntImpliesReady_A	624646974	3065814	0	0
GntImpliesValid_A	624646974	3065814	0	0
GrantKnown_A	624646974	496282652	0	0
IdxKnown_A	624646974	496282652	0	0
IndexIsCorrect_A	624646974	3065814	0	0
LockArbDecision_A	624646974	0	0	0
NoReadyValidNoGrant_A	624646974	0	0	0
ReadyAndValidImplyGrant_A	624646974	3065814	0	0
ReqAndReadyImplyGrant_A	624646974	3065814	0	0
ReqImpliesValid_A	624646974	3065814	0	0
ReqStaysHighUntilGranted0_M	624646974	0	0	0
RoundRobin_A	624646974	5	0	925
ValidKnown_A	624646974	496282652	0	0
gen_data_port_assertion.DataFlow_A	624646974	3065814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	496282652	0	0
T1	1319	1252	0	0
T2	1083320	671814	0	0
T3	446194	297554	0	0
T4	356858	294850	0	0
T5	1041	966	0	0
T6	238437	192103	0	0
T7	6357	5263	0	0
T8	1673716	1256691	0	0
T9	2266709	1510526	0	0
T10	2267283	1301327	0	0
T12	63240	31620	0	0
T13	411810	204944	0	0
T14	0	52048	0	0
T15	0	16788	0	0
T16	0	305944	0	0
T26	0	33264	0	0
T29	0	121240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2775	2775	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	3065814	0	0
T2	1083320	14587	0	0
T3	446194	6489	0	0
T4	356858	3140	0	0
T5	1041	0	0	0
T6	238437	832	0	0
T7	6357	57	0	0
T8	1673716	5746	0	0
T9	2266709	18421	0	0
T10	2267283	20484	0	0
T11	1683	0	0	0
T12	63240	1088	0	0
T13	411810	832	0	0
T16	0	7039	0	0
T26	0	963	0	0
T34	0	2200	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	3065814	0	0
T2	1083320	14587	0	0
T3	446194	6489	0	0
T4	356858	3140	0	0
T5	1041	0	0	0
T6	238437	832	0	0
T7	6357	57	0	0
T8	1673716	5746	0	0
T9	2266709	18421	0	0
T10	2267283	20484	0	0
T11	1683	0	0	0
T12	63240	1088	0	0
T13	411810	832	0	0
T16	0	7039	0	0
T26	0	963	0	0
T34	0	2200	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	496282652	0	0
T1	1319	1252	0	0
T2	1083320	671814	0	0
T3	446194	297554	0	0
T4	356858	294850	0	0
T5	1041	966	0	0
T6	238437	192103	0	0
T7	6357	5263	0	0
T8	1673716	1256691	0	0
T9	2266709	1510526	0	0
T10	2267283	1301327	0	0
T12	63240	31620	0	0
T13	411810	204944	0	0
T14	0	52048	0	0
T15	0	16788	0	0
T16	0	305944	0	0
T26	0	33264	0	0
T29	0	121240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	496282652	0	0
T1	1319	1252	0	0
T2	1083320	671814	0	0
T3	446194	297554	0	0
T4	356858	294850	0	0
T5	1041	966	0	0
T6	238437	192103	0	0
T7	6357	5263	0	0
T8	1673716	1256691	0	0
T9	2266709	1510526	0	0
T10	2267283	1301327	0	0
T12	63240	31620	0	0
T13	411810	204944	0	0
T14	0	52048	0	0
T15	0	16788	0	0
T16	0	305944	0	0
T26	0	33264	0	0
T29	0	121240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	3065814	0	0
T2	1083320	14587	0	0
T3	446194	6489	0	0
T4	356858	3140	0	0
T5	1041	0	0	0
T6	238437	832	0	0
T7	6357	57	0	0
T8	1673716	5746	0	0
T9	2266709	18421	0	0
T10	2267283	20484	0	0
T11	1683	0	0	0
T12	63240	1088	0	0
T13	411810	832	0	0
T16	0	7039	0	0
T26	0	963	0	0
T34	0	2200	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	3065814	0	0
T2	1083320	14587	0	0
T3	446194	6489	0	0
T4	356858	3140	0	0
T5	1041	0	0	0
T6	238437	832	0	0
T7	6357	57	0	0
T8	1673716	5746	0	0
T9	2266709	18421	0	0
T10	2267283	20484	0	0
T11	1683	0	0	0
T12	63240	1088	0	0
T13	411810	832	0	0
T16	0	7039	0	0
T26	0	963	0	0
T34	0	2200	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	3065814	0	0
T2	1083320	14587	0	0
T3	446194	6489	0	0
T4	356858	3140	0	0
T5	1041	0	0	0
T6	238437	832	0	0
T7	6357	57	0	0
T8	1673716	5746	0	0
T9	2266709	18421	0	0
T10	2267283	20484	0	0
T11	1683	0	0	0
T12	63240	1088	0	0
T13	411810	832	0	0
T16	0	7039	0	0
T26	0	963	0	0
T34	0	2200	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	3065814	0	0
T2	1083320	14587	0	0
T3	446194	6489	0	0
T4	356858	3140	0	0
T5	1041	0	0	0
T6	238437	832	0	0
T7	6357	57	0	0
T8	1673716	5746	0	0
T9	2266709	18421	0	0
T10	2267283	20484	0	0
T11	1683	0	0	0
T12	63240	1088	0	0
T13	411810	832	0	0
T16	0	7039	0	0
T26	0	963	0	0
T34	0	2200	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	5	0	925
T16	440045	1	0	1
T23	1165	0	0	1
T24	190440	0	0	1
T25	19853	0	0	1
T26	500576	0	0	1
T27	93553	0	0	1
T28	2161	0	0	1
T33	393794	0	0	1
T34	186212	0	0	1
T35	11005	0	0	1
T36	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	496282652	0	0
T1	1319	1252	0	0
T2	1083320	671814	0	0
T3	446194	297554	0	0
T4	356858	294850	0	0
T5	1041	966	0	0
T6	238437	192103	0	0
T7	6357	5263	0	0
T8	1673716	1256691	0	0
T9	2266709	1510526	0	0
T10	2267283	1301327	0	0
T12	63240	31620	0	0
T13	411810	204944	0	0
T14	0	52048	0	0
T15	0	16788	0	0
T16	0	305944	0	0
T26	0	33264	0	0
T29	0	121240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	624646974	3065814	0	0
T2	1083320	14587	0	0
T3	446194	6489	0	0
T4	356858	3140	0	0
T5	1041	0	0	0
T6	238437	832	0	0
T7	6357	57	0	0
T8	1673716	5746	0	0
T9	2266709	18421	0	0
T10	2267283	20484	0	0
T11	1683	0	0	0
T12	63240	1088	0	0
T13	411810	832	0	0
T16	0	7039	0	0
T26	0	963	0	0
T34	0	2200	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	126947674	29455064	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	126947674	665392	0	0
GntImpliesValid_A	126947674	665392	0	0
GrantKnown_A	126947674	29455064	0	0
IdxKnown_A	126947674	29455064	0	0
IndexIsCorrect_A	126947674	665392	0	0
LockArbDecision_A	126947674	0	0	0
NoReadyValidNoGrant_A	126947674	0	0	0
ReadyAndValidImplyGrant_A	126947674	665392	0	0
ReqAndReadyImplyGrant_A	126947674	665392	0	0
ReqImpliesValid_A	126947674	665392	0	0
ReqStaysHighUntilGranted0_M	126947674	0	0	0
RoundRobin_A	126947674	0	0	0
ValidKnown_A	126947674	29455064	0	0
gen_data_port_assertion.DataFlow_A	126947674	665392	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	29455064	0	0
T2	402407	104488	0	0
T3	145271	124776	0	0
T4	58274	54616	0	0
T6	46240	0	0	0
T7	1040	1040	0	0
T8	414926	24544	0	0
T9	747695	255104	0	0
T10	957555	387520	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	305944	0	0
T26	0	33264	0	0
T29	0	121240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	665392	0	0
T2	402407	4440	0	0
T3	145271	3076	0	0
T4	58274	2136	0	0
T6	46240	0	0	0
T7	1040	29	0	0
T8	414926	660	0	0
T9	747695	6014	0	0
T10	957555	4838	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	4071	0	0
T26	0	828	0	0
T34	0	2200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	665392	0	0
T2	402407	4440	0	0
T3	145271	3076	0	0
T4	58274	2136	0	0
T6	46240	0	0	0
T7	1040	29	0	0
T8	414926	660	0	0
T9	747695	6014	0	0
T10	957555	4838	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	4071	0	0
T26	0	828	0	0
T34	0	2200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	29455064	0	0
T2	402407	104488	0	0
T3	145271	124776	0	0
T4	58274	54616	0	0
T6	46240	0	0	0
T7	1040	1040	0	0
T8	414926	24544	0	0
T9	747695	255104	0	0
T10	957555	387520	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	305944	0	0
T26	0	33264	0	0
T29	0	121240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	29455064	0	0
T2	402407	104488	0	0
T3	145271	124776	0	0
T4	58274	54616	0	0
T6	46240	0	0	0
T7	1040	1040	0	0
T8	414926	24544	0	0
T9	747695	255104	0	0
T10	957555	387520	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	305944	0	0
T26	0	33264	0	0
T29	0	121240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	665392	0	0
T2	402407	4440	0	0
T3	145271	3076	0	0
T4	58274	2136	0	0
T6	46240	0	0	0
T7	1040	29	0	0
T8	414926	660	0	0
T9	747695	6014	0	0
T10	957555	4838	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	4071	0	0
T26	0	828	0	0
T34	0	2200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	665392	0	0
T2	402407	4440	0	0
T3	145271	3076	0	0
T4	58274	2136	0	0
T6	46240	0	0	0
T7	1040	29	0	0
T8	414926	660	0	0
T9	747695	6014	0	0
T10	957555	4838	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	4071	0	0
T26	0	828	0	0
T34	0	2200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	665392	0	0
T2	402407	4440	0	0
T3	145271	3076	0	0
T4	58274	2136	0	0
T6	46240	0	0	0
T7	1040	29	0	0
T8	414926	660	0	0
T9	747695	6014	0	0
T10	957555	4838	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	4071	0	0
T26	0	828	0	0
T34	0	2200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	665392	0	0
T2	402407	4440	0	0
T3	145271	3076	0	0
T4	58274	2136	0	0
T6	46240	0	0	0
T7	1040	29	0	0
T8	414926	660	0	0
T9	747695	6014	0	0
T10	957555	4838	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	4071	0	0
T26	0	828	0	0
T34	0	2200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	29455064	0	0
T2	402407	104488	0	0
T3	145271	124776	0	0
T4	58274	54616	0	0
T6	46240	0	0	0
T7	1040	1040	0	0
T8	414926	24544	0	0
T9	747695	255104	0	0
T10	957555	387520	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	305944	0	0
T26	0	33264	0	0
T29	0	121240	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	665392	0	0
T2	402407	4440	0	0
T3	145271	3076	0	0
T4	58274	2136	0	0
T6	46240	0	0	0
T7	1040	29	0	0
T8	414926	660	0	0
T9	747695	6014	0	0
T10	957555	4838	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	4071	0	0
T26	0	828	0	0
T34	0	2200	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	126947674	96161950	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	126947674	419504	0	0
GntImpliesValid_A	126947674	419504	0	0
GrantKnown_A	126947674	96161950	0	0
IdxKnown_A	126947674	96161950	0	0
IndexIsCorrect_A	126947674	419504	0	0
LockArbDecision_A	126947674	0	0	0
NoReadyValidNoGrant_A	126947674	0	0	0
ReadyAndValidImplyGrant_A	126947674	419504	0	0
ReqAndReadyImplyGrant_A	126947674	419504	0	0
ReqImpliesValid_A	126947674	419504	0	0
ReqStaysHighUntilGranted0_M	126947674	0	0	0
RoundRobin_A	126947674	0	0	0
ValidKnown_A	126947674	96161950	0	0
gen_data_port_assertion.DataFlow_A	126947674	419504	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	96161950	0	0
T2	402407	288829	0	0
T3	145271	17210	0	0
T4	58274	0	0	0
T6	46240	46240	0	0
T7	1040	0	0	0
T8	414926	388338	0	0
T9	747695	484153	0	0
T10	957555	561716	0	0
T12	31620	31620	0	0
T13	205905	204944	0	0
T14	0	52048	0	0
T15	0	16788	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	419504	0	0
T2	402407	533	0	0
T3	145271	1034	0	0
T4	58274	0	0	0
T6	46240	0	0	0
T7	1040	0	0	0
T8	414926	520	0	0
T9	747695	925	0	0
T10	957555	2964	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	2968	0	0
T26	0	135	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	419504	0	0
T2	402407	533	0	0
T3	145271	1034	0	0
T4	58274	0	0	0
T6	46240	0	0	0
T7	1040	0	0	0
T8	414926	520	0	0
T9	747695	925	0	0
T10	957555	2964	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	2968	0	0
T26	0	135	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	96161950	0	0
T2	402407	288829	0	0
T3	145271	17210	0	0
T4	58274	0	0	0
T6	46240	46240	0	0
T7	1040	0	0	0
T8	414926	388338	0	0
T9	747695	484153	0	0
T10	957555	561716	0	0
T12	31620	31620	0	0
T13	205905	204944	0	0
T14	0	52048	0	0
T15	0	16788	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	96161950	0	0
T2	402407	288829	0	0
T3	145271	17210	0	0
T4	58274	0	0	0
T6	46240	46240	0	0
T7	1040	0	0	0
T8	414926	388338	0	0
T9	747695	484153	0	0
T10	957555	561716	0	0
T12	31620	31620	0	0
T13	205905	204944	0	0
T14	0	52048	0	0
T15	0	16788	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	419504	0	0
T2	402407	533	0	0
T3	145271	1034	0	0
T4	58274	0	0	0
T6	46240	0	0	0
T7	1040	0	0	0
T8	414926	520	0	0
T9	747695	925	0	0
T10	957555	2964	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	2968	0	0
T26	0	135	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	419504	0	0
T2	402407	533	0	0
T3	145271	1034	0	0
T4	58274	0	0	0
T6	46240	0	0	0
T7	1040	0	0	0
T8	414926	520	0	0
T9	747695	925	0	0
T10	957555	2964	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	2968	0	0
T26	0	135	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	419504	0	0
T2	402407	533	0	0
T3	145271	1034	0	0
T4	58274	0	0	0
T6	46240	0	0	0
T7	1040	0	0	0
T8	414926	520	0	0
T9	747695	925	0	0
T10	957555	2964	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	2968	0	0
T26	0	135	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	419504	0	0
T2	402407	533	0	0
T3	145271	1034	0	0
T4	58274	0	0	0
T6	46240	0	0	0
T7	1040	0	0	0
T8	414926	520	0	0
T9	747695	925	0	0
T10	957555	2964	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	2968	0	0
T26	0	135	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	96161950	0	0
T2	402407	288829	0	0
T3	145271	17210	0	0
T4	58274	0	0	0
T6	46240	46240	0	0
T7	1040	0	0	0
T8	414926	388338	0	0
T9	747695	484153	0	0
T10	957555	561716	0	0
T12	31620	31620	0	0
T13	205905	204944	0	0
T14	0	52048	0	0
T15	0	16788	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126947674	419504	0	0
T2	402407	533	0	0
T3	145271	1034	0	0
T4	58274	0	0	0
T6	46240	0	0	0
T7	1040	0	0	0
T8	414926	520	0	0
T9	747695	925	0	0
T10	957555	2964	0	0
T12	31620	0	0	0
T13	205905	0	0	0
T16	0	2968	0	0
T26	0	135	0	0
T41	0	3146	0	0
T42	0	2117	0	0
T43	0	3	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	370751626	370665638	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	370751626	1980918	0	0
GntImpliesValid_A	370751626	1980918	0	0
GrantKnown_A	370751626	370665638	0	0
IdxKnown_A	370751626	370665638	0	0
IndexIsCorrect_A	370751626	1980918	0	0
LockArbDecision_A	370751626	0	0	0
NoReadyValidNoGrant_A	370751626	0	0	0
ReadyAndValidImplyGrant_A	370751626	1980918	0	0
ReqAndReadyImplyGrant_A	370751626	1980918	0	0
ReqImpliesValid_A	370751626	1980918	0	0
ReqStaysHighUntilGranted0_M	370751626	0	0	0
RoundRobin_A	370751626	5	0	925
ValidKnown_A	370751626	370665638	0	0
gen_data_port_assertion.DataFlow_A	370751626	1980918	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	370665638	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	1980918	0	0
T2	278506	9614	0	0
T3	155652	2379	0	0
T4	240310	1004	0	0
T5	1041	0	0	0
T6	145957	832	0	0
T7	4277	28	0	0
T8	843864	4566	0	0
T9	771319	11482	0	0
T10	352173	12682	0	0
T11	1683	0	0	0
T12	0	1088	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	1980918	0	0
T2	278506	9614	0	0
T3	155652	2379	0	0
T4	240310	1004	0	0
T5	1041	0	0	0
T6	145957	832	0	0
T7	4277	28	0	0
T8	843864	4566	0	0
T9	771319	11482	0	0
T10	352173	12682	0	0
T11	1683	0	0	0
T12	0	1088	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	370665638	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	370665638	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	1980918	0	0
T2	278506	9614	0	0
T3	155652	2379	0	0
T4	240310	1004	0	0
T5	1041	0	0	0
T6	145957	832	0	0
T7	4277	28	0	0
T8	843864	4566	0	0
T9	771319	11482	0	0
T10	352173	12682	0	0
T11	1683	0	0	0
T12	0	1088	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	1980918	0	0
T2	278506	9614	0	0
T3	155652	2379	0	0
T4	240310	1004	0	0
T5	1041	0	0	0
T6	145957	832	0	0
T7	4277	28	0	0
T8	843864	4566	0	0
T9	771319	11482	0	0
T10	352173	12682	0	0
T11	1683	0	0	0
T12	0	1088	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	1980918	0	0
T2	278506	9614	0	0
T3	155652	2379	0	0
T4	240310	1004	0	0
T5	1041	0	0	0
T6	145957	832	0	0
T7	4277	28	0	0
T8	843864	4566	0	0
T9	771319	11482	0	0
T10	352173	12682	0	0
T11	1683	0	0	0
T12	0	1088	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	1980918	0	0
T2	278506	9614	0	0
T3	155652	2379	0	0
T4	240310	1004	0	0
T5	1041	0	0	0
T6	145957	832	0	0
T7	4277	28	0	0
T8	843864	4566	0	0
T9	771319	11482	0	0
T10	352173	12682	0	0
T11	1683	0	0	0
T12	0	1088	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	5	0	925
T16	440045	1	0	1
T23	1165	0	0	1
T24	190440	0	0	1
T25	19853	0	0	1
T26	500576	0	0	1
T27	93553	0	0	1
T28	2161	0	0	1
T33	393794	0	0	1
T34	186212	0	0	1
T35	11005	0	0	1
T36	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	370665638	0	0
T1	1319	1252	0	0
T2	278506	278497	0	0
T3	155652	155568	0	0
T4	240310	240234	0	0
T5	1041	966	0	0
T6	145957	145863	0	0
T7	4277	4223	0	0
T8	843864	843809	0	0
T9	771319	771269	0	0
T10	352173	352091	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370751626	1980918	0	0
T2	278506	9614	0	0
T3	155652	2379	0	0
T4	240310	1004	0	0
T5	1041	0	0	0
T6	145957	832	0	0
T7	4277	28	0	0
T8	843864	4566	0	0
T9	771319	11482	0	0
T10	352173	12682	0	0
T11	1683	0	0	0
T12	0	1088	0	0
T13	0	832	0	0